TW389984B - Inter-metal dielectric process made by O3-TEOS - Google Patents

Abstract

The inter-metal dielectrics (IMD) made of O3-TEOS is usually used in sub-micron semiconductor process. Combination of PECVD oxide underlayer/SACVD O3TEOS is generally used. However, the gate filling ability of such method does not meet the requirement for quarter micrometer process technology. Therefore, this invention provides a method for forming an inter-metal dielectric layer to improve its gap filling ability. A PECVD oxide/O3TEOS layer is formed on a substrate and interconnections. An argon-sputter etching back is performed and a spacer is formed on the sidewall of the interconnections, thereby modifying the profile of the interconnections. Then, a PECVD oxide underlayer/O3TEOS oxide is deposited and an inter-metal dielectric layer with good gap-filling ability is achieved.

Description

V. Description of the invention (1) The present invention relates to the manufacture of semiconductor integrated circuits, and in particular to an improved process for the metal interlayer dielectric layer (IMD) mainly composed of 0_T EOS oxide, to improve its gap filling. The capability is suitable for the manufacture of finer size integrated circuit components. In recent years, with the development of semiconductor integrated circuit manufacturing technology, the number of components contained in wafers has continued to increase, and the size of components has continued to shrink with the increase in the degree of accumulation. Required interconnect cables. In order to meet the new requirements, the design of two or more layers of metal wires has gradually become a way that many integrated circuits must adopt. In particular, some products with more complex functions, such as microprocessors, etc., even require four layers or Five or more layers of metal wires can make each component work as it should. Therefore, the process of multi-level interconnects has become one of the important technologies indispensable in today's semiconductor processes. In the process of multiple interconnected wires, although the components need to be connected to each other by means of interconnected wires, the interconnected wires cannot be directly contacted to cause a short circuit. They must be isolated by an insulating layer, which is generally called metal interlayer dielectric Layer (IMD), among which oxidized, nitrided, and TEOS oxides are the most commonly used dielectric materials. However, after the semiconductor process entered the field of half-micron line width dimensions, due to the poor gap-filling ability of the above-mentioned dielectric materials, they could not provide the required insulation properties. Therefore, many improved process technologies have emerged, including sub-normal pressure vapor deposition ( 〇3_TE〇s oxide layer formed by the SACVJ)) program has been researched and proved to have good step coverage properties. 'It is conducive to filling the shrinking wire gap, so it is currently

V. Description of the Invention (2) One of the technologies often used to produce metal interlayer dielectric (IMD) on the production line. However, although the 03_te0s oxide layer formed by the subatmospheric pressure vapor deposition process has better gap-filling properties, its deposition rate will vary greatly depending on the substrate material ', which not only affects the efficiency of manufacturing 'And cause problems such as poor quality of the oxide layer and uneven surface. Therefore, in the general process, the combination of PECVD silicon oxide underlayer / SACVD 03-TE0S oxide layer is used to cover the surface of the interconnecting wires and the substrate with a silicon oxide underlayer to facilitate the subsequent uniform deposition of the 03_TEOS oxide layer to form a metal interlayer dielectric. Floor. Hereinafter, the manufacturing process of this combination will be described with reference to FIGS. 1A to 1D. First, "as shown in 1A", a semiconductor substrate f0 is provided, for example, a silicon wafer on which a desired semiconductor element is formed. For simplicity, it is represented by a flat substrate 10 only. A diffusion barrier layer 11, a metal layer 12, and an anti-reflection layer 13 are sequentially formed on the substrate 10. For example, 'a titanium nitride (TiN) layer 11 is deposited first, then a copper aluminum (AlCu) alloy layer 12 is deposited, and then another titanium nitride layer 13 is deposited. Next, a photoresist layer 14 is applied, and a lithography imaging procedure is performed to define a wire pattern. Please refer to FIG. 1B for the steps of defining the structure of the interconnecting wires. Using the pattern of the photoresist layer 14 as a mask, the anti-reflection layer 13, the metal layer 12, and the diffusion barrier layer 11 are sequentially etched to form a layer such as The interconnecting wire structure M shown in the figure. Then, the photoresist layer 14 is removed by an appropriate solution or a dry etching process. Next, a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a thin

C: \ ProgramFiles \ Patent \ 0503-3787-E. Ptd page 5 V. Description of the invention (3) The silicon oxide layer 15 serves as an underlayer, and has a structure as shown in FIG. 1C. Next, please refer to FIG. 1D 'perform an atmospheric pressure chemical vapor deposition (SACVD) procedure to form a 03_TEOs oxide layer 16 overlying the surface of the above-mentioned oxide dream layer 15 and fill in the interconnect structure μ In the gap, a metal interlayer dielectric layer is formed together as shown in the figure to provide the insulation effect of the interconnecting conductor structure M from another metal layer (not shown) above. Among them, because the silicon oxide underlayer 15 was intentionally formed previously, the 〇3_TE〇S oxide layer 〖6 does not have the problem of uneven deposition rate during deposition, which helps to improve the filling capacity of the team. However, as the design size of semiconductor integrated circuits continues to shrink, the 0a-TEOS oxide layer 16 in the interconnect gap still inevitably generates holes 17 due to the limitation of step coverage, especially when the process technology This situation will worsen when entering the field of one-quarter micron or even finer size. The gap-filling capability of the above-mentioned combination of PECVD silicon oxide underlayer / SACVD 03-TE0S oxide layer is no longer sufficient. Among them, since the pores 17 are located in a region 'close to the surface of the 0s-TEOS oxide layer 16', in the subsequent chemical mechanical polishing (CMp) process of planarization, it is easy to expose the pores 17 and cause slurry (Slurry) Flow into it and cause subsequent particle contamination 'even when other metal layers grow at high temperatures due to thermal expansion. Therefore, in order to adapt to the manufacturing process of finer-size components, it is necessary to further improve the gap filling capability of the interlayer dielectric layer, and to improve the problem of the holes exposed by the interlayer dielectric layer due to the grinding process. ΗΗΙΗΗΙΓ C: \ Program Files \ Patent \ 0503-3787-E.ptd page 6 '5. Description of the invention (4) One object of the present invention is to provide a metal interlayer dielectric layer mainly composed of 〇3_teos oxide. The improved manufacturing process improves the filling capacity of the interconnect line and reduces the size of the holes generated. Another object of the present invention is to provide an improved manufacturing process of < 〇3_TE〇S oxide-based metal interlayer dielectric layer, which can move the holes generated in the gap between interconnect wires downward to avoid exposure due to grinding treatment. The problem. In order to achieve the above object, the present invention proposes an improved process for forming a metal interlayer dielectric layer to improve its gap filling capability. First, a PECVD silicon oxide / 〇3-TEOS oxide stack is formed on the substrate and the surface of the interconnect wire. 'Then perform an argon spatter etch back process to leave the spacers on the side walls of the interconnect wires' to relax the lateral profile of the interconnect wires; then cover a PECVD silicon oxide substrate and a 〇3-TEOS oxide layer 'is to complete the production of a metal interlayer dielectric layer with good gap filling ability. Among them, the 'holes generated in the gap area of the 〇3_TEOS oxide layer' will be smaller than those produced by the conventional process; and if the processing time of the argon spattering process that forms the gap wall is deliberately increased, the The formation of a depression 'on the semiconductor substrate between the interconnecting wires can further move the holes generated in the 〇3_TE〇s oxide layer downward to avoid subsequent exposure due to the grinding process. In detail, the present invention proposes a method for fabricating a metal interlayer dielectric layer based on 03-TE0S oxide to improve its gap-filling capability. The method includes the following steps: a semiconductor substrate is formed above There are a plurality of interconnected wires; a plasma-enhanced chemical vapor deposition and an atmospheric chemical vapor deposition process are successively performed to form a silicon oxide / compound layer, covering the exposed surfaces of the interconnected wires and the semiconductor substrate; One

C: \ ProgramFiles \ Patent \ 0503-3787-E. Ptd page 7

Ar sputter process to etch back the above silicon oxide / 〇3_te〇s compound stack, so that the part left on the side wall of the interconnect wire forms a gap wall (_spaCer); another plasma is used to strengthen the chemical gas Phase deposition process to form: a silicon oxide underlayer covering the exposed surfaces of interconnect wires, spacers, and semiconductor substrates; a nitrogen plasma treatment to increase the density of the silicon oxide underlayer; and another atmospheric chemical gas Phase deposition process to form a thick layer of 03-TE0S oxide, fill gaps of interconnect wires and cover the surface of the bottom layer of silicon oxide to complete the fabrication of the interlayer dielectric layer. According to a preferred embodiment of the present invention, the diffusion barrier layer is a TiN layer, the metal layer is an aluminum-copper alloy (41 (: 11) layer, and the anti-reflection layer is another titanium nitride layer. In addition, the above-mentioned silicon oxide / 〇3_TE〇s oxide stack 'is composed of 1000 angstrom silicon oxide and 1000 angstrom 〇3_TE〇s oxide', and the thickness of the bottom layer of silicon oxide is about In order to make the above-mentioned object, features and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with the accompanying drawings as follows: Brief descriptions 1A to 1D are a series of cross-sectional views for illustrating a manufacturing process of a metal interlayer dielectric layer of a conventional pecvd oxidation underlayer / SAC VD 03-TE0S oxide combination; and 2A to 2C are A series of cross-sectional views are used to illustrate the manufacturing process according to a preferred embodiment of the improved method of the present invention. First, as shown in FIG. 2A, a semiconductor substrate 20 is provided, such as

C: \ Program Files \ Patent \ 0503-3787-E.ptd page 8 V. Description of the invention (6) --- It is a silicon wafer with the required semiconductor components formed on it. Here again, to simplify the process See, only expressed as a flat substrate 20. A diffusion barrier layer 21, a metal layer 22, and an anti-reflection layer 23 are sequentially formed on the substrate 20. For example, a titanium nitride (1 < 10 layer 21 is deposited first, then a copper aluminum (AlCu) alloy layer 22 is deposited, and then another titanium nitride layer 23 is deposited. Then, a lithography imaging and etching process is performed, In order to define the interconnected wire structure M as shown in the figure, a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a silicon oxide layer having a thickness of, for example, 100 angstroms, followed by Another atmospheric pressure chemical vapor deposition (SACVD) procedure is performed to form a 03-TEOS oxide layer having a thickness of, for example, 1000 angstroms, thereby forming an interconnecting conductor structure M and the exposed surface of the semiconductor substrate 20 together to form a Silicon oxide / (^ — ^ ⑽ oxide stack 2 4. Please refer to FIG. 2B, and perform an Ar sputter procedure to etch back the above silicon oxide / 〇3-TEOS oxide stack 24 Until the semiconductor substrate 20 is exposed, a portion left on the sidewall of the interconnecting conductor structure μ forms a gap wall 24a with a thickness of about 2000 Angstroms. This can relax the side profile of the interconnecting conductor structure M for the benefit of subsequent The deposition of dielectric layers After the wall 24a, the argon spattering process can be continued for a period of time, and the appropriate depression I formed on the semiconductor substrate 20 between the interconnecting conductor structures M will help to make the position of the holes of the subsequent interlayer dielectric layer Move down to avoid the problem of exposure due to the grinding process. Then, as shown in Figure 2C, a plasma enhanced chemical vapor deposition process is performed to interconnect the conductor structure M, the spacer 24a, and the substrate 20 dew

C: \ Program Files \ Patent \ 0503-3787-E.ptd page 9 V. Description of the invention (7) A thin silicon oxide underlayer 25 is formed on the surface, and its thickness is, for example, 1000 angstroms. Then, an atmospheric pressure chemical vapor deposition process is performed to form an Os-TEOS oxide layer 26 overlying the surface of the above-mentioned silicon oxide underlayer 25 and fill the gaps of the interconnecting conductor structure M together to form as shown in 圚The metal interlayer dielectric layer 'provides the insulation effect of the interconnecting wire structure M from another metal layer (not shown) above. In addition, in order to increase the nucleation density of the silicon oxide underlayer 25, a nitrogen plasma treatment process can be added between the two deposition processes, which will be more beneficial for the deposition of the 03-TE0S oxide layer 26. Comparing the improved process and the conventional technology of the present invention, the following advantages can be clearly found: First, 'because the present invention first creates a gap wall 2 4 a on the side wall of the interconnected wire structure jj', it can not only relax its side profile, but also partially fill it. The 'full interconnect gap' helps to improve the step coverage of subsequent dielectric layers. Secondly, before the 03-TE0S oxide layer 26 is deposited, a nitrogen plasma treatment process is performed to increase the nucleation density of the silicon oxide underlayer 25, which also helps to improve the gap filling ability of the 03-TE0S oxide layer 26, so that The holes 27 are smaller than those skilled in the art. In addition, due to the deliberate increase of the time of the argon sputtering process, the formation of a suitable depression I in the semiconductor substrate 20 between the conductor structures M also helps to move the position of the above-mentioned hole 27 downward to avoid the occurrence of polishing treatment. And exposed problems. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouches without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application

C: \ PrQgramFiles \ Patent \ 0503-3787-E.ptd page 10

Claims (1)

6 'Application and " --- Manufacturing You 1-a kind of 〇3_TE〇S oxide-based metal interlayer dielectric layer (IMD) = method' 'to improve its gap filling (gap_filling) capabilities, the method includes The following steps: Provide a semiconductor substrate with a plurality of interconnecting wires formed thereon; successively perform a plasma enhanced chemical vapor deposition (PECVD) and a normal pressure chemical vapor deposition (SACVD) procedure to form silicon oxide / 〇 3_te ^ ^ compound stack, covering the interconnected wires and the exposed surface of the semiconductor substrate; performing an Ar sputter procedure to etch back the silicon oxide / C ^ -TEOS oxide stack, Forming a spacer on the side wall of the interconnecting wire; performing another plasma enhanced chemical vapor deposition process to form a silicon oxide underlayer covering the interconnecting wire, the The spacer and the exposed surface of the semiconductor substrate; a nitrogen plasma treatment is performed to increase the nucleation density of the silicon oxide underlayer; and another atmospheric pressure chemical vapor deposition process is performed to form a 03-TE0S oxide A thick layer is filled in the gaps of the interconnecting wires and covers the surface of the bottom layer of the silicon oxide to complete the fabrication of the metal interlayer dielectric layer. 2. As described in item 1 of the scope of patent application-a method for manufacturing a metal oxide interlayer dielectric layer (IMD) of 〇3_TE〇s oxide, wherein the line width of the interconnecting wires is about a quarter of a micron. Or finer size. 3. As described in item 1 of the scope of patent application-a kind of 〇3_11 £ 〇5 oxide is the main M IHH C: \ ProgramFiles \ Patent \ 0503-3787-E.ptd page 11 389 ^ 84 A method for manufacturing an interlayer dielectric layer (IMD), wherein the steps of forming the interconnecting wires include: 'sequentially forming a diffusion barrier layer, a metal layer, and an anti-reflection layer on the substrate surface; coating; A photoresist layer is formed on the surface of the antireflection layer, and a conductive pattern is defined by a lithography imaging program; the photoresist layer is used as a mask to sequentially etch the antireflection layer, the metal layer, and the diffusion resistance A barrier layer to form an interconnecting wire structure; and removing the photoresist layer. 4. A method for manufacturing a metal interlayer dielectric layer (IMD), which is based on oxide 3 as described in item 3 of the scope of patent application, wherein the diffusion barrier layer is a titanium nitride (TiN) layer, and The metal layer is an aluminum-copper alloy "A1Cu" layer, and the anti-reflection layer is another titanium nitride (TiN) layer. 5. A method for fabricating a 03-TE0S oxide-based metal interlayer dielectric layer (IMD) as described in item 1 of the scope of the patent application, wherein the oxide / 〇3 TEOS oxide stack is composed of 100%. Angstrom silicon oxide and 1000 Angstrom te〇s oxide "6. As described in the first patent application scope, a _3_TE〇s oxide-based = metal interlayer dielectric layer ⑽) manufacturing method , Wherein the argon reduction stroke forms outside the gap wall, and further forms a depression on the half-body base between the interconnecting wires. A method for manufacturing a metal interlayer dielectric layer (IMD), which is mainly based on the first item of the patent scope, and whose thickness is about 1,000 angstroms. Bn C: \ Program Files \ Patent \ 0503-3787-E.ptd page 12