TW388178B - On-screen display device - Google Patents

Abstract

An on-screen display device for displaying OSD information on an OSD background portion which is selectively filled with either an half tone video image or a background raster of a specific color selected by a user, or which is filled by superimposing the half tone video image and the half tone background raster selected by the user. Thee mixing and amplifying circuits are provided respectively for each of R/G/B channels. Each of the three mixing and amplifying circuits receives a video signal and an OSD signal of respective channel, mixes the video signal and the OSD signal according to a video selection signal and an OSD selection signal, amplifies a mixed signal, and outputs an amplified image signal to a display. A selection signal generating circuit receives OSD signals for R/G/B channels, a video/OSD switching signal, a half tone signal, and OSD control signals generates and outputs the OSD selection signal and the video selection signal. When the video/OSD switching signal instructs an OSD output opertaion. And the half tone signal intructs a half tone output operation, the selection signal generating circuit outputs the video selection signal and the OSD selection signal such that a half tone OSD background raster is displayed with a half tone video image in a predetermined OSD window.

Description

Printed by the Central Bureau of Standards and Jujube of the Ministry of Economic Affairs, printed by the Shellfish Consumer Cooperative Λ7 _____B7 V. Description of the Invention (!) —] Invention Vision 1. Field of the Invention The present invention relates to a display device, and particularly to a video preamplifier circuit for combining on a screen Display signal to video signal and enlarge the combined result on the display device. Applications of such on-screen display devices are based on Korean Patent Applications Nos. 98-5019, 98-13126, and 98-30385, and are described herein for reference. 2. Description of related technologies For example, monitors or LCD monitors used in computers often need to display information such as text on video images through an on-screen display (OSD). Some examples of OSD information include contrast or convergence and the title of the item currently being adjusted, which does not appear on the screen when the user attempts to adjust the contrast or convergence of the monitor. The mixing of OSD information and video signals is performed in the video preamplifier integrated circuit (1C). When the text is to be displayed on the screen through the OSD, the text needs to be emphasized, so it is easy to distinguish it from the video image. You can use the shadow method to add shadows to the edges of the text or the border method to emphasize the outline of the text to emphasize the text. In another method of emphasizing text, the 0SD window can be formed on the screen ’so only text is displayed when the video signal is intercepted in the window area. Figure 25 shows an example of the OSD text displayed on the screen of the OSD window area. In this 〇SD window area, the background image is shaped as monochrome and the OSD text is displayed on the background glory. The OSD grating that typically forms the background is fixed to black or blue. At the same time, when the OSD window is formed on the screen, the video signal is completely intercepted in the window area. 'The image quality is significantly degraded' because the original video image is based on the Chinese national standard (CNS) A4ML 彳 Μ 210X 297 male fj '( (Please read the caution page on the back first).

* 1T-line it ·· .. -4- Α7 Η 7 V. Description of the Invention (2) 'It is partially obscured by the background of the OSD. In some recent display devices, by reducing the video signal gain by half, instead of completely capturing the video signal in the window area, the half-tone video image is displayed on the background of the OSD. In this case, the OSD text is displayed at half-tone. On the image. However, the video preamplifier integrated circuit (1C) that can display halftone images in the OSD window usually does not support the operation mode of selectively filling the background portion of the OSD video by using halftone images or a background raster other than white. Thus, in the conventional OSD window generating device of the video preamplifier 1C, the background portion of the SD window can be filled with a specific color OSD background raster or a halftone video image with a white background raster according to 1C. In addition, in an OSD device that fills the OSD background portion with a specific-color OSD raster, the color of the CLSE background barrier is fixed to one color and cannot be changed to another. Therefore, consumers of video preamplifiers such as monitor manufacturers can only implement the operation modes provided by the purchased 1C, and cannot implement other operation modes like 1 (:. In other words, the monitor manufacturer It is necessary to purchase another IC to change the method of displaying the OSD window.

I. Summary of the Invention Printed by the Central Bureau of Standards, Shellfish Consumer Cooperative Co., Ltd.-(Chu Xian read the note on 16. to write this page) In order to solve the aforementioned problems, the object of the present invention is to provide an on-screen display device for The OSD information is displayed on the background portion of the OSD, which is optionally filled with a halftone video image or a specific color background raster selected by the user or an overlapped halftone video image and a halftone background raster selected by the user. Another object of the present invention is to provide an on-screen display of multiple OSD windows and borrow > fill with halftone video images or users. This paper size is applicable to China National Standards (CNS) Λ4 Regulations Μ 2 丨Printed by the Central Bureau of Standards, B Industrial Consumer Cooperatives, ^ 7 B7 V. Description of the Invention (3) 'The background raster of a specific color selected, or the half-tone video image and the half-tone background raster selected by the user are superimposed to fill the complex numbers, respectively. OSD windows. In the on-screen device according to the present invention, in order to achieve the foregoing object, three mixing and amplifying circuits are provided for the R / G / B path, respectively. Each of the three mixing and amplifying circuits can receive video signals and OSD signals of individual channels, mix the video signals and OSD signals according to the video selection signals and the OSD selection signals, amplify the mixed signals, and output the amplified image signals to the display. The selection signal generating circuit receives and outputs OSD signals, video / OSD switching signals, halftone signals, and OSD control signals to the R / G / B channels, and outputs OSD selection signals and video selection signals. When the video / OSD switching signal instructs the OSD output operation and the halftone signal instructs the halftone output operation, the selection signal generating circuit outputs the video selection signal and the OSD selection signal, so the halftone OSD background raster display and a halftone video image are attached to the predetermined OSD window. According to one aspect of the present invention, the selection signal generating circuit is implemented using a logic gate. In the selection signal generation circuit, only when the video / OSD switching signal instructs the OSD output operation, the halftone signal instructs the halftone operation, and the OSD signal has a predetermined logical combination, the halftone display signal generator can generate an excited halftone display. signal. The inverter inverts the video / OSD switching signal and outputs the video modal signal. It is only activated when the video signal is output. The attenuator attenuates the halftone display signal to half. The adder adds the video modal signal to the attenuator output and outputs the addition result as a video selection signal and an OSD selection signal.

I This paper size applies the Chinese National Standard (CNS) to the standard (210X297 male i) --------- install I (Please read the precautions on the back first to write this page

1T -6- Employees of the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Affairs Cooperative Cooperatives Λ7 H7 V. Description of the Invention (4) According to another aspect of the present invention, the selection signal generating circuit is implemented using a transistor and a passive element. In the selection signal generating circuit, the video / OSD switching unit receives the video / OSD switching signal, and generates at least one switching signal according to the video / OSD switching signal. The OSD raster selector adjusts the swing range of the R / G / B OSD signal to determine whether the adjusted R / G / B OSD signal of each level is at the first logical level or the second logical level. When the R / G / B OSD signal A raster selection signal is output when corresponding to a predetermined logic level combination (which is determined according to the OSD control signal). The halftone signal generator receives the switching signal and the raster selection signal from the video / OSD switching unit and the OSD raster selector, respectively, and generates an OSD selection signal and a video selection signal. According to the on-screen device of the present invention, in order to achieve any of the foregoing objectives, the on-screen display device forms a first predetermined number of OSD windows to display images, and displays halftone OSD information and video information on the first predetermined number of OSD windows. The second predetermined number of OSD windows. Three hybrid and amplifier circuits are provided for the R / G / B channels respectively. Each of the three mixing and amplifying circuits receives video signals and OSD signals of individual channels, mixes the video signals and OSD signals according to the video selection signals and the OSD selection signals, amplifies the mixed signals, and outputs the amplified image signals to the display. The selection signal generating circuit receives the OSD signal of the R / G / B channel, the video / OSD switching signal, the halftone signal, and the OSD control signal of the second predetermined number of OSD windows, and generates and outputs the OSD selection signal and the video selection. signal. When the video / OSD switching signal instructs the OSD output operation and the halftone signal instructs the halftone output operation, the selection signal generating circuit of the video signal outputs the video selection signal and the OSD selection signal, so the halftone OSD background raster is a halftone video copy The paper size is applicable to China National Standards (CNS) Λ Ί Regulations (210x297'i ># ·) (Please read the precautions on the back before ^ This page-installation

， 1T -7- Printed by the Central Bureau of Standards, Ministry of Economic Affairs, B Industrial Cooperative Cooperative Λ7 H7 5. Description of Invention (5) The image is displayed in the second predetermined number of OSD windows. In a preferred embodiment, the video selection signal and the OSD selection signal are the same video / OSD selection signal. Each of the mixing and amplifying circuits only amplifies a video signal and outputs an amplified video signal when the video / OSD selection signal is at a first logic level, and outputs only an amplified OSD signal when the video / OSD selection signal is at a second logic level. OSD signal. Each of the mixing and amplifying circuits mixes the video signal and the OSD signal when the video / OSD selection signal is at an intermediate logic level to output an amplified mixed signal. According to an aspect of the present invention, the selection signal generating circuit is implemented using a logic gate. In the on-screen display device, the gated signal generating unit generates a gated signal, which is only activated when the video / OSD switching signal instructs the OSD output operation and the halftone signal instructs the halftone operation. The first OSD decision unit receives the gate control signal, the OSD signal of the R / G / B channel, and the OSD control signal of the first window, and generates a first window discrimination signal. The signal is only corresponding to the first window of the OSD signal. Only when the first predetermined combination of OSD control signals are activated, and the gate control signal is activated. The second OSD determination unit receives the gate control signal, the OSD signal of the R / G / B channel, and the OSD control signal of the second window, and generates a second window discrimination signal. Only the OSD signal has a signal corresponding to the second window. The second predetermined combination of the OSD control signal and the gate control signal are activated when they are activated. The OR gate performs an OR operation on the first window discrimination signal and the second window discrimination signal. The attenuator receives the output of the OR gate and the output of the attenuated OR gate is in half. The inverter receives and inverts the video / OSD switching signal, and generates a video modal signal that is excited only when the video signal is to be output. The adder adds the output of the attenuator to the video modal signal. This paper size applies to the Chinese national standard (0 milk) / \ 4 size (21 (^ 297 male and female)) (Please read the precautions on the back page first.)

、 1T A7 H7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) and output the addition result as the video / 0SD selection signal. According to another aspect of the present invention, the selection signal generating circuit is implemented using a transistor and a passive element. In the selection signal generating circuit, the OSD raster selector receives the SD signal of the R / G / B channel, the control signal of the first and second views, and generates at least a raster selection signal. The signal is only the 0sd signal. It is enabled only when there is a logical combination of the SD control signal corresponding to the first window or the OSD control signal corresponding to the first window. The halftone signal generator receives the raster selection signal, the video / OSD switching signal and the halftone signal, and when the video / OSD switching signal is instructed, the SD output operation and the halftone signal instruct the halftone output operation and at least one raster selection signal is caused. Intermediate video / OSD selection signals are generated only when enabled. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing objects and advantages of the present invention will be apparent from the description of the preferred specific examples with reference to the drawings. In the drawings: FIG. 1 is a friend of a specific example of a display device on a screen according to the present invention Figure 2. Figure 2 shows the video signal and the background raster of DD in the Qs public window at halftone output time interval, and the color of the OSD background raster of the device in Figure 1 according to 〇SD_; Figure 1 is a detailed block diagram of the hybrid and amplifying circuit Dongyi in Figure 1; Figure 4 is a circuit diagram of a specific example of the circuit for selecting signal generation in Figure 1-Figures 5A to 5E-are waveform diagrams shown in Figure 4 The circuit outputs signals according to the input signal; This paper size applies the Chinese National Standard (CNS). (21〇x297 public wear --------- installation-•-r (Please read the note on the back first) Please fill in this page again.) Line • I 1 · -9- Λ7 H7 V. Description of the invention (7) Figure 6 is the block 另一 of another specific example of the selection signal of f 鞞 in 1 鞞; 1 Please read the back first Attention Sun Ben! The 7th circle is the circuit diagram of the video / OSD switching unit in Fig. 6; A to 8C are line diagrams showing the output signal of the video 70SD switching unit in response to the detection signal in FIG. 7; FIG. 9 is the circuit diagram of the OSD grating selector in FIG. 6; The circuit diagram of the OSD halftone signal generator; 11A 彖 丄 1 公 # is the waveform 圊 shows the simulation results of the implementation of the on-screen display device integrated circuit chip in accordance with the specific example of Fig. 6; Fig. 1 shows the result according to the present invention The square circle of another specific example of the display device on the firefighting reference; the figure shows the table, the video signal. The OSD background light phase k can be displayed in halftone in the first OSD window, and the twelfth device The color of the OSD background raster according to 〇SP ~ control signal; Figure 14 is a detailed block of the mixing and amplifying circuit of Figure 12; if / Figure 15 is a circuit diagram of a specific example of the selection signal generating circuit of Figure 12; Figures 16A to 16J printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economics are waveforms that are better than those shown in the circuit shown in Figure 15. The output signal should be the input signal; Figure 17 is another specific example of the selection signal generating circuit. This is a variation of the circuit in Figure 15; Figure 18 Figure 12 shows the square circle of another specific example of the selection signal generating circuit in Figure 12; i "19 圊 is the circuit diagram of the video / 0SD switching unit in Figure 18; this paper size applies Chinese National Standards (CNS) to regulate Dry (210X297) -10- Printed by the Central Bureau of Standardization, Shellfish Consumer Cooperative, A7 11? V. Description of the invention (8) The? 0A to 20C pictures are shown on the video / OSD switch sheet in Fig. 19 The output signal of the element in response to the input signal; Figure 21 圊 is the circuit diagram of the interface buffer of Figure 18; Figures 22A and 22B are the circuit diagrams of the OSD grating selector of Figure 18; Figure 23 is Figure 18 Circuit diagram of the round OSD half-color predicate signal generator; Figures 24A to 24C are shown as the waveform 1 killing indicator. According to the simulation results of the flag display circuit chip on the screen shown in Figure 6 of Youshi; the 21st screen shows the f screen. For example, the screen and the top—QSD text is displayed on the background part of the OSD window with ##, and the video signal of the window is intercepted according to the conventional technology; Figure 26 is an example of the display screen, and Yu Rongbei Tu according to the screen of Figure 1 Specific examples of display devices "video information and QSD grating Halftone display also has a single OSD window; and an example of the display screen in Figure 7 is shown on the screen. According to the specific example of the display device on the screen in Figure 12, the video data and the OSD raster are displayed in two OSD windows in halftone. . Description of a preferred specific example On-screen display device implementing a single OSD window Referring to FIG. 1, the on-screen display device includes a selection signal generating circuit 1 and individual mixed and amplified signals 3, 4 and 5 of the R / G / B channel. The selection signal generating circuit 1 receives the OSD signals R_OSD, G_OSD and B OSD relative to the R / G / B path, the video / OSD switching signal V / 0_SWITCH, the halftone signal HT and the OSD control signal HSO and HS1. Standards (CNS) Λ4ϋί 梠 (210X29 " 7 public garbage) --------- ^ 装 — • ·-(Please read the precautions on the back before this page, 1T -11-B7 V. Description of the invention (9), and generate and output the video / 〇SD selection signal according to the received signal. The i〇SD signal R_〇SD, G-OSD and B_OSD in the input signal are separated by i OSD controller (not shown in the figure) Input. The video / OSD switching signal V / 0_SWITCH indicates the OSD modal operation, which is input by the OSD controller. The video / OSD switching signal V / 0_SWITCH is in the "high" order in the OSD mode and in the non-OSD mode. Low "level. The halftone signal HT is indicated by an external microcontroller (not shown) whether the video signal is displayed in halftone. When the halftone signal HT is at the" high "level and the OSD signals R_OSD 'G_OSD and B_OSD have predetermined When the logic is combined, the video signal is displayed in halftones. The OSD control signals HS0 and HS1 enable the manufacturer of the monitor or liquid crystal display (LCD) to choose a predetermined OSD background and background raster, thereby displaying the background screen with the OSD window with the selected color. The predetermined color of the background screen of the OSD window is manufactured by the manufacturer The display device program planning and control signals HS0 and HS1 are input by the microcontroller according to the program planning. Figure 2 shows that according to the OSD control signals HS0 and HS1, the video signals are input in the OSD window in halftone with the OSD background raster, and the OSD Background raster color. Printed by the Central Bureau of Consumer Affairs and Industry Cooperative Cooperatives ^ If HS0 and HS1 are "low" and "low" levels, the video signal and OSD background raster can be at OSD signal R_OSD, G_OSD and B_OSD at "low" "Low" and "Low" levels are output in halftone. In this example, the OSD background raster color is black. At this time, if the halftone signal HT is excited, the video signal and the OSD background raster are output in halftone. But if The halftone signal HT is not excited, so the OSD background screen is filled with the OSD background raster only. This paper size applies the Chinese National Standards (CNS} / V) Regulation 彳 210X297 ^^) A7 Η 7 (10) If HS0 and HS1 are at the "low" and "high" stages, respectively, when the OSD signal R_OSD, G_OSDAB_OSD is at "low, ',,' low" and, high ,, and OSD When the background raster is blue, the video signal and OSD background raster can be output in halftone. If HS0 and HS1 are in the "high" and "low" stages, respectively, when the OSD signals 11_080, 0_080 and B-OSD are in the "low", "high" and "low" stages and the OSD background raster is green, the video signal is And OSD background raster can be output in halftones. If HS0 and HS1 are at "high" and "high" levels, then when the OSD signal R_OSD, G_OSDAB_OSD is at "low", "high" and "high" levels, and the OSD background raster is indigo In color, the video signal and the OSD background raster can be output in halftone. Each of the mixing and amplifying circuits 3, 4 and 5 receives the video signal% signal of the individual channel, and selects the signal ^ V / 0_SEL according to the video / OSD to mix and amplify the video signal. And OSD signals, and output mixed signals. Figure 3 shows the details of one of the mixing and amplifying circuits 3, 4 and 5 of Figure 1. The video signal selector 7 receives the video / OSD selection signal V / 0_SEL through an input terminal, And receiving the video signal through another input terminal. When the video / 0SD selection signal V / 0-SEL is in the “high” stage, the video signal selector 7 outputs the received video signal to the amplifier 9. But when the video / 0SD selection signal V / 0_SEL is at "low" "" Stage, the video signal selector 7 does not output the video signal. When the video / 0SD selection signal V / 0_SEL is in the "middle" stage, the video signal selector 7 attenuates the received video signal in half and outputs the attenuated signal To the amplifier 9. The OSD signal selector 8 receives the video through the input terminal / OSD selection letter The paper size is applicable to China National Standards (CNS) Λ4 Regulations (210 × 297ϋ) Please read the precautions on the back before this page-binding. Printed by the Central Bureau of Standards, Shellfish Consumer Cooperatives-13- Λ7 ____ ^ H7 — * " * · * ^ One "-— — ^^ ―— _ ^^ ΜΙΐυ_Ι _ ^ __ ^ _ 5. Description of the Invention (11) --------- 3 pack 丨 (Please read the precautions on the back before buying V / 0_SEL and receiving the OSD signal through the other input terminal. When the video / OSD selection signal V / 0_SEL is at "low" In the "" stage, the 0SD signal selector 8 outputs the received OSD signal to the amplifier 9. However, when the video / OSD selection signal V / 0_SEL is in the "high" stage, the 0SD signal selector 8 does not output the 0SD signal. 0SD signal selector 8 when video / OSD selection signal V / 0_SEL is at the middle stage Subtract the received OSD signal to the half and output the attenuated signal to the amplifier 9 »The amplifier 9 receives the video signal and the OSD signal selectively output by the video signal selector 7 and the OSD signal selector 8 respectively, and mixes and amplifies these Signal and output amplified signal to display drive unit such as cathode ray tube

I or LCD driver electron gun (not shown). -¼ An example of the 26th display screen. On the screen, according to the specific example of the display device on the screen in Figure 1, the video information and the OSD raster are displayed in a single OSD window in halftones. In the screen shown in Fig. 26, a halftone background raster is displayed in the background together with a halftone video signal. OSD text with a different color from the background part then appears on the background part. Figure 4 shows a specific example of the selection signal generation circuit of the first frame. The selection signal generation circuit includes AND gates 10, and the first to fourth SD determination units 12 are printed by the Consumers' Cooperative of the Central Bureau of Standards, 20, 28. And 36, OR gate 46, attenuator 48, inverter 50 and adder 52. AND gate 10 receives halftone HT and video / OSD switching signal V / 0_SWITCH and performs AND operation. Therefore, AND gate 10 is only for halftone signals HT and video / OSD switching signal V / 0_SWITCH are at, and “High” is output only when the order is high. This paper size is applicable to the Chinese national standard (CNS) Λ4 ^ Grid (210x2 ^ 7 公 #) -14- The Central Bureau of Standards of the People's Republic of China printed the button A7 贝 7 _____ V. Description of the invention (12) The output of the AND gate 10 is in the first to fourth SD decision circuits 12, 20, 28 and 36 as the gate control signals In other words, only when the AND gate 10 outputs "high", the AND operation results of the other input signals of the AND gates 18, 26, 34, and 44 of the first to fourth 0SD decision circuits 12, 20, 28, and 36 are transmitted to OR gate 46. When the AND gate 10 outputs "low" order, the first to fourth OSD decision circuits 12, 20, 28 The AND gates 18, 26, 34, and 44 of the 36 output "low" and the OR gate 46 outputs "low". The OR gate 46 performs an OR operation on the outputs of the first to fourth OSD decision circuits 12, 20, 28, and 36 β The attenuator 48 attenuates the output half of the OR gate 46 and the output attenuated signal. The inverter 50 inverts the video / OSD switching signal V / 0_SWITCH and outputs the inverted signal. The adder 52 converts the output of the attenuator 48 The signal is added to the output signal of the inverter 50 and the output addition result is given to the mixing and amplifying circuits 3, 4 and 5 as the video / OSD selection signal V / 0_SEL. Figures 5A to 5E are shown in the circuit shown in Figure 4. The output signal of the input signal. Further details of the operation of the selection signal generating circuit of the fourth frame will be described later with reference to FIGS. 5A to 5E. The time interval 60, 64, 68, and 72 'due to the video / OSD switching signal V / 0_SWITCH is in the "low" stage, so the video modal operation is performed. At this time, the AND gate 10 outputs the "low" stage, and the OR gate 46 outputs the "low" stage. However, the inverter 50 outputs "high". Therefore, the adder 52 Output "high" level video / OSD selection signal 乂 / 0_8ug 1 ^ »Mix and amplify circuits 3, 4 5 in response to the "high" order video / OSD selection signal V / 〇_SEL are amplified and output only the R / G / B video signals.

--------------- IT ------ 0.., 'Ί: (Please read the precautions on the back of this page first) I This paper size applies Chinese national standards ( CNS) (2ΙΟΧ 297 ^ ί)) Printed by the Central Bureau of quasi-Ministry of the Ministry of Commerce and Industry B Cooperative Cooperatives »Λ7 ___ ___ B7 V. Description of the invention (π) — 'Time interval 62 and 70' due to video / 〇SD switching signal v / 0—swnrcH is at the “high” level and therefore performs 0SD modal operations. Because the halftone signal HT is in the low, low, and high levels, the AND gate 10 outputs the low, high, and low levels 46 and the corresponding 46 outputs "low". Inverter 47 outputs "Low". In this way, adder 52 outputs "Low" order video / OSD selection signal V / O-SEL. Leying ,, low, and order video / 〇SD selection signal V / O SEL, The mixing and amplifying circuits 3, 4 and 5 in FIG. 1 only output OSD signals. Thus, only OSD information is displayed on the screen. SD information includes OSD text information and a background screen. The background screen has 〇81) as defined by the control signals HS0 and HS1. Specific color. In the time interval units 66 and 74, the video / 0sD switching signal V / 0_SWITCH is at the "high" level to indicate the OSD operation mode, and the halftone signal HT is at the "high level". In this case, the video signal And 〇SD backprint raster are displayed in halftone on the background screen of the OSD window, which will be detailed later. It is assumed that HS0 is in the "low" order and HS1 is in the "low" order. In this case, since the OSD control signals HS0 and HS1 are both in the "low" stage, the inverting OR gate 16 of the first OSD decision circuit 12 outputs "high". However, the gates 22, 32, and 42 output "low" Therefore, the outputs of the second to fourth OSD decision circuits 20, 28, and 36 are "low" and passivated. In the first OSD decision circuit 12, the inverting OR gate 14 is only based on the OSD signals R_OSD, G_OSD, and B_OSD. "High" is output only when the level is "Low". Therefore, only when the OSD signals R_OSD, G_OSD and B_OSD are at the "low" level, the AND gate 18 outputs, and the 'high' 'and the OR gate 46 output "high". The attenuator 50 attenuates the output of the OR gate 46 to the half and outputs the "medium" order signal. The inverter 47 inverts the video / OSD switching signal V / 0_SWITCH and outputs "low". Addition This paper size applies the Chinese National Standard (CNS) Λ4 gauge (210X297) 棼 (Please read the note on the back ^^ item on this page-install ·

1T .¼ Printed by the Consumers' Cooperative of the Central Bureau of Standards of the People's Republic of China A7 B7 V. Description of the Invention (14) The device 48 adds the output of the attenuator 50 to the output of the inverter 47, and outputs “medium” video / OSD Select signal V / 0_SEL. Therefore, when the OSD signals R_OSD, 0_080 and 8_080 are at the "low" level, that is, only at time intervals "B1" and "B2", the black halftone OSD background screen raster is displayed together with the halftone video information. Assume as As shown in Figure 5C, HS0 is in the "low" stage and HS1 is in the "high" stage. In this case, because the gates 16, 30, and 42 output "low", the first, third, and fourth OSD decision circuits 12 , 28, and 36 output "low" and are passivated. In the second OSD decision circuit 20, only when the OSD signal G_OSD is in the "high" stage and the OSD signals R_OSD and B_OSD are in the "low" stage, the AND gate 26 The output "High" and the OR gate 46 correspond to the output "High". The attenuator 50 attenuates the output of the OR gate 46 to the half and outputs the "medium" order signal. At this time, the inverter 47 inverts the video / OSD switching signal V / 0_SWITCH and outputs "low". The adder 48 adds the output of the attenuator 50 to the output of the inverter 47, and outputs "medium" order video / video / OSD selection signal V / O-SEL V / 0-SEL. Therefore, when the OSD signal G-OSD is in the "high" order and the OSD signal scales 080 and 8_080 are in the "low" order, that is, only in the time interval "C 1" and "C2", the blue halftone OSD background screen raster is displayed together with the halftone video information. It is assumed that HS0 is at the "high" level and HS1 is at the "low" level, as shown in Figure 5D. In this example, because the outputs of the gates 16, 22, and 42 are "low", the outputs of the first, second, and fourth OSD decision circuits 12, 20, and 36 are "low" and passivated. In the third OSD determination circuit 28, the AND gate 34 outputs "high" only when the OSD signal B_OSD is in the "high" stage and the OSD signals R_OSD and G_OSD are in the "low" stage. At this time, the OR gate 46 outputs "high". Therefore, when the paper size of the OSD signal is in accordance with the Chinese National Standard (CNS) Λ4 Regulation ft (210 × 297 ^^) (Please read the precautions on the back ^^-This page. Installation. 、 1Τ Line-17- A7 1Π ________ V. Description of the Invention (15) When B_OSD is at the "high," level, and the SD signal R_OSD & G_OSD is at the "low" level, that is, only at the time intervals "D1" and "D2", the green halftone OSD background screen The grating is displayed together with the halftone video information. Assume that HS0 is at "high", and HS1 is at "high". In this case, because of the output of gates 16, 24, and 32, low, the first and the first The second and third 0SD decision circuits 12, 20, and 28 output, "Low" and are passivated. In the fourth OSD decision circuit 36, only when the 0SD signal R_OSD is at, 'Low,', and the OSD signal G_OSD & B_OSD At the "high" level, the AND gate 44 outputs "high". At this time, the OR gate 46 outputs "high". Therefore, only when the OSD signal 11_080 is at the 'low' stage, and the OSD signal G_OSDAB_OSD is at the "high" stage. Time, that is, only at the time interval "E1" and "Έ2", indigo blue halftone OSD background screen raster Halftone information display. As mentioned above, according to this specific example, any OSD raster (time interval 62 and 70) selected from one of multiple OSD rasters with different colors can be borrowed, or a halftone OSD background of a specific color can be borrowed. The screen raster together with the halftone video information displays the OSD background screen in the OSD display area (time intervals 66 and 74). The " 'Ministry of Standards and Technology Bureau of the People's Republic of China's Consumer Cooperatives Co., Ltd. Printing 52 Figure 6 shows the selection signal generating circuit of Figure 1 Referring to the sixth example, the selection signal generating circuit 100 includes a video / OSD switching unit 110, an OSD raster selector 120, and an OSD halftone signal generator 130. At the same time, the mixing and amplification circuits 3, 4, and 5 are combined in the first Figure 6. The video / OSD switching unit 11 receives the video / OSD switching signal V / 0_SWITCH and generates and outputs the first and second switching signals SW1 and SW2. The video / OSD switching unit 11 generates and outputs the reference voltage REPV for It determines the rank of the video / OSD selection signal V / OSEL. This paper size is applicable to the Chinese National Standard (CNS) Λ4 Regulation 彳 210X2 ^^ -18- Printed by the Central Bureau of Standards, Ministry of Consumer Affairs, B Industrial Consumer Cooperative, A7 Η 7 5. hair Explanation (16) The OSD raster selector 120 adjusts the swing range of the RGB OSD signal and outputs the raster selection signal RSV at a specific OSD signal output timing (which is determined by the OSD control signals HS0 and HS1 of the OSD operation mode), so it is selected One of many OSD gratings. The OSD halftone signal generator 130 generates and outputs a video / OSD selection signal V / 0_SEL according to the switching signals SW1 and SW2 and the OSD control signals HS0 and HS1 when the halftone signal HT indicates a halftone video output. To assist the reader in understanding this specific example, the signals shown in Figures 6 and 7 to 10 are summarized below. 〇 Video / OSD switching signal V / 0_SWITCH: TTL level signal for switching between 0V and 5. 〇 The first switching signal SW1: relative to the video / OSD switching signal V / 0_SWITCH is in a negative phase and swings between 5.1V and 6V. 〇 Reference voltage RERV1: It is at the middle level of the swing range of the first switching signal SW1. 〇 Second switching signal SW2: Relative to the video / OSD switching signal V / 0_SWITCH is in a negative phase and swings between 4.35V and 5.25V. 〇 Reference voltage REPV: is at the middle level of the swing range of the first switching signal SW2. o OSD control signal HS1: Control G_OSD to select 0SD background raster and switch between 0.IV and 2.IV. 〇 OSD control signal HS0: Control B_OSD to select 0SD background raster and switch between 0.IV and 2.IV. 0 Grating selection signal RSV: Under the specific combination of OSD signals, the basic paper size applies the Chinese National Standard (CNS) Λ4 ^ Μ 21〇 × 297 ':. ≫] ί) (Please read the precautions on the back before ^ this page • Ding line -19- (2) Yinju A7 H7, the Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs, V. 5. Description of the invention (17) According to the excitation of the OSD control signals HSO and HS1, a certain OSD background grating was selected. Tone signal HT: Switch between 0 · ΐν and 3.1V and be in the "high" order in halftone operation mode. 〇Mode control signal HT-RS: OSD can be enabled in the OSD operation mode at 1.01V Grating selector, and OSD grating selector that can be used in non-OSD operation mode at 0V. 〇Select reference voltage BS2: Reference signal that determines the order of the OSD control signals HSO and HS1. Figure 7 shows the video of Figure 6 Further details of the / OSD switching unit 110. Referring to Figure 7, transistor Q1 ^ Q2 contains a comparator to restrict the video / OSD switching signal V / 0_SWITCH to a certain range. Video / OSD switching signal V / 0_S WITCH input transistor Q1 base. Transistors R1 and R2 and transistors Q3 and Q4 are formed by the following formula 1. The first reference current Iref, 1 is represented, so the reference voltage VA represented by the following formula 2 is provided to the base of the transistor Q2.

Iref-, = (VCc-2Vbe) / (Rl + R2) (1)

Va ^ Vcc-I ^., · R1 In this specific example, the reference voltage 乂 4 is 2.8V. Transistors Q5 and Q6 include comparators to restrict the swing range of the video / OSD switching signal V / 0_SWITCH to a certain range. The resistors R5, R6, R7, and R8 and the transistors Q12 and Q13 form a second reference current Iref, 2 represented by the following formula 3, so the reference voltage 乂 represented by the following formula 4; ^ is supplied to the base of the transistor Q6. This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 male and female) Please read-read the back side. Rebinding -20- Printed by the Central Standards Bureau of the Ministry of Economic Affairs, only printed by AFC & 7 5 Description of the invention (18) ~

Iref, 2 = (Vcc-3 Vbe) / (R5 + R6 + R7 + R8) (3)

Vb = Vcc-Iref, 2 · (R5 + R6) (4) In this specific example, the reference voltage 乂 8 is 1.5V ^ the second reference current jf ^ is repeated to the transistor Zhao qi4 by using a current mirror including transistors Q12 and Q13 , Q15, Q16 and Q17 collectors. When the video / OSD switching signal V / 0_SWITCH is at ', high, and high, transistor Q1 is turned off but transistor Q2 is turned on. The potential of the node 112 is about 3.6V ', which is higher than the reference voltage VA by 1Vbe. The potential of the node 112 is supplied to the base of the transistor Q5. At this time, the transistor Q5 is turned on but the transistor ^ 6 is turned off. Therefore, the collector current of the transistor Q7 having the same amplitude as the second reference current Iref, 2 flows through the transistor Q5. The potential of the node 114 is expressed by the following formula 5, and has a value of 5.IV ', which is output as the first switching signal swi. SW1 = Vcc-R4 + Iref> 2- Vbe,-Vbe. 9- R3- Iref, 2 (5) At the same time, when the video / OSD switching signal V / 〇-SWITCH is at, low, step, transistor Q1 Is turned on but transistor || Q2 is turned off. The potential of the node 112 drops to turn off the transistor Q5 and the transistor Q6. Therefore, very little current flows through the transistor Q5 'and the collector current of the transistor Q7 flows through the transistor Q6. The potential of the node 114 at the time is the first switching signal sw 丨 expressed by the following formula 6 and having a value of 6V »SWl = Vcc.R4Mref > 2-Vbe > 11-Vbc > 9 (6) The aforementioned first switching signal SW1 responds to the video / 〇SD switching signal V / 0—SWITCH switches between 5.1V and 6V. The amplitude of the other switching signal SW2 is "below" Vbe, g lower than the amplitude of the first switching signal SW1. Therefore, the second switch signal sw2 has the same paper size as the first switch letter (CNS) 210 (210 × 207ϋ7 (please read the note on the back before this page). Order 21-Λ7 Η 7 V. Description of the invention (19) SW1 has the same phase and switches between 4.35V and 5.25V. In terms of it, the video / OSD switching unit in Figure 7 generates and outputs two reference voltages REPV1 and REDV. The reference voltage RERV1 is based on Equation 7 below and has The value is 5.55V. REFV1 = Vcc-R5 * Iref, 2-Vbe, n-Vbe, 9-R4 * Iref, 2 (7) The reference voltage REPV has a magnitude of Vbe, 10 lower than the reference voltage RERV1. Figures 8A to 8C The line diagram shows the output signal according to the input signal of the circuit in Figure 7. As shown in Figure 8A, when the TTL-level video / OSD switching signal V / 0_SWITCH is input, the first switching signal SW1 is for video / OSD switching The reverse phase of the signal V / 0_SWITCH is between 5.1V and 6V. The reference voltage REPV1 is at the middle level of the swing range of the first switching signal SW1. The second switching signal SW2 has the same phase as the first switching signal SW1 and Switch between 4.35V and 5.25V. The reference voltage REPV is based on the second switching signal S The middle level of the swing range of W2. Fig. 9 shows the details of the OSD raster selector 120 in Fig. 6. Printed by the Central Standards Bureau of Shelley Consumer Cooperatives. OSD raster selector 120 includes a level adjustment circuit 122 and a comparison circuit 124. The level adjustment circuit 122 adjusts the swing range of the OSD signals R-OSD, G-OSD and B_OSD, and provides the level-adjusted OSD signal to the comparison circuit 124. The comparison circuit 124 outputs the raster selection signal RSV of the OSD window. Only when the specific logic combination of the OSD signal is input according to the OSD control signals HS0 and HS1. In the level adjustment circuit 122, the resistors R11 and R12 form a third reference current Iref, 3, and divide the power supply voltage Vcc, so the voltage Vc Supply transistor Q23 This paper is in accordance with Chinese National Standards (CNS). \ 4 gauge (210X2 ^ 7cm) -22- A7 _________H7 __________ 5. Description of the invention (20) Base Q. Comparison of transistor Q22 and Q23 R OSD Adjust the swing range of R_OSD with the voltage Vc 俾. According to the comparison result, the collector voltage of transistor Q21 changes, and it is supplied to the comparison circuit 124 as the SD signal R_OSD 'after the level adjustment. After the adjustment signal 〇sd R_OSD 'of the "low" and "high" is determined by the order system, in this specific embodiment have values of 1.6V and 3.6V. R_OSD '("Low ,,) = R_〇SD (" Low ,,) + Vbe. 22 + Vbe, 21 (8) R-OSD, ("_") = R12 · Iref, 3 + Vbe 23 + Vbe, 2ι resistors R13 and R14 form the fourth reference current Iref, 4 and the divided power supply voltage Vcc 'so voltage VD is supplied to the base of transistor Q40. Transistors Q26 and Q27 compare G_OSD with voltage VD and adjust G_OSD The swing range. According to the comparison result, the collector voltage of transistor Q25 changes and is supplied to comparison circuit 124 as the level-adjusted 0sQ signal g_〇SD. The level-adjusted OSD signal G_OSD 'is between 2.9V and 3.7V. The swing range. The resistors R15 and R16 form the fifth reference current Iref, 5 and the divided power supply voltage Vcc, so the voltage VE is supplied to the base of the transistor Q31. Comparing the transistors Q30 and Q31, B_SD and voltage VE 俾 adjust Swing range. According to the comparison result, the collector voltage of transistor Q29 changes and is supplied to comparison circuit 124 as the level-adjusted 0sd signal B_OSD. The level-adjusted OSD signal B OSD is in the range of 2.9V to 3.7V The emitter voltage of transistor Q24 is lVbe higher than voltage vc, and it is output to comparison circuit 124 as R. Channel OSD reference signal R_〇SD_ref. The emitter voltage of transistor Q28 is 1Vbe 'higher than voltage VD and output to comparison circuit 124 as the G channel OSD reference signal 0_080-ref. The emitter voltage ratio of transistor Q32 is output to The comparison circuit 124 is used as the B-channel OSD reference. This paper standard is applicable to the Chinese National Standard (CNS) Λ4Ίϊί > (ίΓ (210X2 ^ ΙΊ — — Please read the precautions on the back first. — Install I on this page 丨 The Bureau of Central Standards of the Ministry of Economic Affairs Pui Gong Consumer Cooperatives printed -23- Pui Gong F Cooperatives printed by the Central Standards Bureau of the Ministry of Economic Affairs __Η 7__ V. Description of the invention (21) Signal B_OSD_ref. The operation of the comparison circuit 124 is based on the OSD halftone signal in Figure 6. The modal control signal HT_RS is generated by the circuit 130. When the modal control signal HT_RS is at the "high" level, the transistors Q33, Q34 and Q35 provide current and the comparison circuit 124 operates. When the modal control signal HT_RS is at In the "low" stage, the transistors Q33, Q34 and Q35 are passivated and the comparison circuit 124 is not activated. The following description assumes that the modal control signal HT_RS is in the "high" stage. Transistors Q36 and Q37 and transistors Q38 and Q3 The 9-comparison comparator compares the OSD control signals HS1 and HS0 with the reference voltage BS2 from the halftone signal reference circuit 130, and controls the operation of the comparator based on the comparison result. The comparator includes a pair of transistors Q40 and Q41, Q42 and Q43. , Q44 and Q45, Q46 and Q47, and Q48 and Q49. The five comparators include paired transistors Q40 and Q41, Q42 and Q43, Q44 and Q45, Q46 and Q47, and Q48 and Q49. Compare the OSD signals R_OSD ', G_OSD' and B_OSD 'with OSD reference after adjustment. The voltages R_OSD_ref, G_OSD_ref and B_OSD_ref, and the raster selection signal RSV is output according to the comparison result. Therefore, the active-low signal grating selection signal RSV is enabled or disabled according to the OSD control signals HS1 and HS2. As detailed later, the video / OSD selection signal V / 0_SEL is at the “high” level when the raster selection signal RS V is de-energized to “high”, but the video / OSD selection signal V / 0-SEL is at the raster selection signal RSV. When enabled, the logic state of the halftone signal HT is at the “low” or “medium” level. It is assumed that HS0 is in the "low" order and HS1 is in the "low" order. In this case, transistor Q36 is passivated but transistor Q37 is excited. Β and transistor Q38 This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 ^^) (Jing first read the precautions on the back and then this page)

• 1T -line. »1 / • 24- Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 ____ 117__________V. Description of the invention (22) Passive but the transistor Q39 is excited. Therefore, the pair of transistors Q4〇 and Q41, Q44 and Q45, Q48 and Q49 act only so that the signal scales-080 ', G_0SD1b_0SD' are tied to the low, high, and high order grating selection signals Rsv. For the "low" order. Therefore, a black OSD background raster is selected. It is assumed that HSO is in the "low" order and HS1 is in the "high" order. In this case, transistor Q36 is passivated but transistor Q39 is excited. Therefore, the pair of transistor Q40 and Q41, 42 and Q43, Q48 and Q49 operate. Thus, only when the signal R_OSD ^ q_OSD is at the high, low, and order and the signal B_OSD 'is at the "high" order, the grating selection signal RSV is excited. Therefore, in this example, the blue OSD background raster is selected. It is assumed that HSO is in the "high" order and HS1 is in the "low" order. In this case, transistor Q36 is passivated but transistor Q37 is excited. Transistor Q38 is excited but transistor Q39 is passivated. Act on the transistors Q40 and Q41, Q44 and Q45 and Q46 and Q47 in this example. So only when the signals R_OSD, AB_OSD are tied to, 'low ,, and B_OSD' are tied to "high", the grating is selected The signal RSV is only excited. Therefore, the green OSD background grating is selected in this example. It is assumed that HSO is in the 'high' order and HS1 is in the 'high' order. In this case, transistor Q36 is excited but transistor Q37 is passivated. Transistor Q38 is excited but transistor Q39 is passivated. Therefore, the pair of transistors Q40 and Q41, Q42 and Q43, and Q46 and Q47 operate. Thus, only when the signal R_OSD ′ is at the “low” level and the signal EG_0SD1B_0SD ’is at the“ high ”level, the grating selection signal RSV is excited. Therefore, in this example, an indigo blue SD background grating was selected. This paper size applies the Chinese National Standard (CNS) Λ4 specification (210 × 2ϋΐ (Γί (please read the precautions on the back and then this page) —)} / -m- .¼. -25- Λ7 Η 7 V. Description of the invention ( 23 FIG. 10 shows the details of the OSD halftone signal generator 130 in FIG. 6. The OSD halftone signal generator 130 in FIG. 10 includes a modal control signal generating circuit 132, an output signal generating circuit 136, and a reference signal generating circuit 138. »The modal control signal generating circuit 132 receives the halftone signal HT and the second switching signal SW2, generates a modal control signal HT_RS, and outputs this signal to the OSD raster selector 120 in Fig. 9. The output signal generating circuit 136 receives the raster selection Signal RSV and signal SW2-2Vbe, which is 2Vbe lower than the second switching signal SW2, and generates and outputs a video / OSD selection signal V / O-SEL. The reference signal generating circuit 138 generates a plurality of reference voltages, and provides this The signal is provided to the modal control signal generating circuit 132 and the output signal generating circuit 136 «and the reference signal generating circuit. The circuit 138 generates a reference voltage BS2 and outputs this signal to the OSD grating selector 120 of Fig. 9. Reference In the signal generating circuit 138, the resistors R25, R26, R27, and R28 are connected in series with the transistor Q72 to divide the power supply voltage Vcc. Therefore, a predetermined voltage is supplied to the base of the transistor Q61, and a constant current flows through the transistor Q61. The pole of Q70 is biased at a constant level, so a certain reference current Iref, 6 flows through the transistors Q70 and Q71. The current is repeated through various transistors such as transistor 68. In the modal control signal generating circuit 132, Transistors Q53 and Q54 include a comparator. The second switching signal is used to reduce the signal 2Vbe through the transistors Q55 and Q56. SW2-2Vbe is applied to the base of transistor Q53. The halftone signal HT with a level of 3.1V in the halftone mode is Transistor Q51 is lowered by 1Vbe, and transistor Q52 is raised by 1Vbe, and is applied to the base of transistor Q54. Therefore, this paper can be applied to Chinese National Standard (CNS) Λ4Α) ί 怙 (210/297 ^ ¾ Please read first The note on the back page 4 is printed by the central ministry of the Ministry of Civil Engineering and Industry of China__B7 Consumer Cooperatives Co., Ltd. 26- A7 —_______ Η 7 V. Description of the Invention (24), — The half-tone signal HT is applied to the base of transistor Q54. When the second switching signal SW2 When the "high" level indicates the video interval, the transistor Q53 is excited but the transistor Q54 is passivated. So little current flows through the transistor Q60 and the resistor R22, and the modal control signal HT-RS is about 0V. " Low,, order. When the second switching signal SW2 is at ,, low, 'order and indicates the SD interval, the transistor Q53 is purified but the transistor Q54 is excited. In this way, some current flows through the transistor q60 and the resistor 1122. In the current mirror of the transistor Q57 and Q58 combination, the transistor Q58 supplies approximately three times the current than the transistor Q57. Therefore, the amplitude of the modal control signal HT_RS at this time is represented by the following Equation 9 and is at 1.0 °, high ', and order. HT_RS = 3Iref, 6 · R25 + Vbe, 6〇 (9) In the output signal generating circuit 136 of the Central Standards Bureau of the Ministry of Standards and Industry of China, the output signal generating circuit 136, the transistors Q62 and Q63 include comparators. The signal having the same level as the halftone signal HT is applied to the base of the transistor Q62. The signal SW2-2Vbe, which is 2Vbe lower than the second switching signal, is applied to the base of transistor Q62. Transistor Q62 is only activated when the half-tone signal HT is at the high level and the second switching signal SW2 is at the low level, and the buffer including the transistors Q64 and Q65 is actuated. It has a reference voltage RERV1 A voltage of equal amplitude is applied to the base of the transistor Q69 and transmitted through the resistors R23 and Q24 as the video / OSD selection signal v / 0_SEL. At this time, the current output through the RSV signal to the OSD grating selector 120 in FIG. 9 can be Ignore. Therefore, the video / OSD selection signal V / 0_SEL has a level equal to the reference voltage REDV1. When the second switching signal SW2 is at a high level and indicates the video interval, the second switching signal SW2 input includes transistors Q66 and Q67 Buffer, and output through transistor Q69 and resistors R23 and R24 as video / OSD selection signal V / 0_SEL »This paper size applies Chinese National Standard (CNS) Λ4 rule (210X297 ^ 1 -27- 7 7 Λ Η The final winner of the Jujube Bureau®; Industrial and Consumer Cooperatives Co., Ltd. 5. Description of the invention (25) In Figure 10, the buffers 133, 134, and 135 enable the OSD by buffering the OSD control signals HS1 and HS2 and the halftone signal HT. Negative current of control signals HS1 and HS2 The load is minimized "and the buffered signals HS1 'and HS2' are used to replace the OSD control signals HS1 and HS2 of the OSD raster selector 120 in Fig. 9. However, in the previous description, the buffered signals HS1 'and HS2' are It is written as the OSD control signals HS1 and HS2 for convenience. Figures 11A to 11C are waveform diagrams showing the simulation results of the integrated circuit chip of the on-screen display device implemented according to this embodiment. Figure 11A shows the video / OSD switching signal The waveform of V / 0_SWITCH. Figure 11B shows the waveform of the video / OSD selection signal V / 0_SEL. Figure 11C shows the output signal of the mixing and amplification circuit for any channel. In the simulations of Figures 11A to 11C, it is assumed The halftone signal HT is excited at time intervals 82 to 88 and passivated at time intervals 90 to 96. The interval 82 is divided into two sub-intervals 82a and 82b, where according to the OSD control signals HS0 and HS1 (not shown in the figure), The video / OSD selection signal V / 0_SEL has different levels from each other. At interval 82a, the video / OSD selection signal V / 0_SEL is at the "low" level, and no signal is output by the mixing and amplification circuit. At interval 82b, the video / OSD Selection signal V / 0 _SEL has the same level as the reference voltage REPV. So half-tone video signals are output with half-tone OSD signals. The operation of interval 86 is the same as interval 82. At time intervals 84, 88, 92, and 96 (this is the video output time interval), only output The video signal is independent of the halftone signal HT. At an interval of 90, the video / OSD selection signal V / O-SEL is at the "low" level, and only the OSD signal is output by the mixing and amplifying circuit. The calculation at the interval 94 is the same as the interval 90 »This paper size applies the Chinese National Standard (CNS) Λ4 specification (2 丨 (Please read the precautions behind and then fill in this page) ij -1 ° Γ -28 Λ7 Η 7 V. Description of the invention (26) As mentioned above, according to this specific example, the OSD function can be implemented by selecting one of various color OSD rasters or the OSD background screen can be displayed by a halftone video signal together with the halftone OSD signal. Implementation of a multi-OSD window Fig. 12 of the on-screen display device is a block diagram of another specific example of the on-screen display device according to the present invention, which implements two OSD windows. Referring to the figure, the on-screen display device includes a selection signal generating circuit 201 and R / G The individual mixing and amplifying circuits of the / B channel 3, 4 and 5. The selection signal generating circuit 201 receives the 0SD signal R_OSD relative to the R / G / B channel, (^ -OSD and B_OSD, video / OSD switching signal V / 0_SWITCH, The halftone signal HT and OSD control signals HS0 and HS1, and the video / 0SD selection signal V / 0_SEL are generated and output according to the received signals. Among the input signals, the OSD signals R_OSD, G_OSD & B_OSD are controlled by individual OSD controllers (in the figure) not (Indicated) input. The video / OSD switching signal V / 0_SWITCH indicates that the OSD modal operation is input by the OSD controller. The video / OSD switching signal V / 0_SWITCH is in the "high" order and the non-OSD mode in the OSD mode. “Low” level. The halftone signal HT is input by an external microcontroller (not shown in the figure) and indicates whether the video signal is displayed in halftone. When the halftone signal HT is in the “high” level and the OSD signal R— When the OSD, G_OSD & B_OSD has a predetermined logic combination, the video signal is displayed in halftones, which will be described in detail later. OSD control signals HS1 to HS6 enable the monitor or liquid crystal display (LCD) manufacturer to select a predetermined OSD background raster and display The paper size with the selected color is applicable to the Chinese National Standard (CNS) Λ4 gauge (210X297). Please read the note of 1¾ first, and then print it by the Central Standards Bureau of the Ministry of Standards and Industry. Standard Bureau employee consumer cooperatives print Λ7 H? V. Description of the invention (27) The background screen of the OSD window of color. The predetermined color of the background raster of the OSD window is planned by the display device manufacturing program, and the control signal HSO and HS1 is input by the microcontroller according to the program plan. In this specific example, at most two OSD windows can be displayed, and three OSD control signals are used for each OSD window to select one of the eight OSD background rasters. In other words, the OSD control signals HS1 to HS3 is used to select one of the eight possible OSD background rasters for the first window, and OSD control signals HS4 to HS6 are used to select one of the eight possible OSD background rasters for the second window. However, in this specific alternative, two OSD control signals may be used for each of the OSD windows to select one of four OSD background rasters. In another alternative of this specific example, three OSD windows can be displayed simultaneously. In this case, an additional OSD control signal can be provided to select a different color of the SD background raster for each window. Figure 13 shows that according to the OSD control signals HS1 to HS3, the video signal is halftoned with the OSD background raster on the first OSD. Window and OSD background raster color output time interval. If HS1 to HS3 are at the "low", "low" and "low" stages, respectively, when the 0SD video R-OSD is at, "low", "low," and "low" stage, the video signal and OSD The background raster can be output in halftone. In this example, the SD background raster is black. At this time, if the halftone signal YT is excited, the video signal and the OSD background raster are output in halftone. But if the halftone YT is not excited, , The OSD background screen is only filled with the OSD background raster.

If HS1 to HS3 are in the "low", "low" and "high" stages respectively, the video signal and OSD background raster are on the OSD signal R_OSD, G OSD and B OSD. The paper dimensions are applicable to the Chinese National Standard (CNS) A4HM 210X297. ) (Please read the note on the back #Fill this page first),-° 丁 -30- Η 7 V. Description of the invention (28) Can be halftone output when it is in the "low", "low" and "high" steps , And the OSD background raster is blue. If HS1 to HS3 are in the "low", "high" and "low" stages respectively, the video signal and the OSD background raster can be in the OSD signal R_OSD, G-OSD and B-OSD in "low", "high" and "low" The order is halftone output and the OSD background raster is green. If HS1 to HS3 are "low", "high" and "high" steps, then when the OSD signal R_OSD, G_OSD and B_OSD are at "low", At the "High" and "High" levels, the video signal and the OSD background raster can be output in halftone, and the OSD background raster is indigo.

If HS1 to HS3 are in the "high", low, and "low" stages, respectively, when the OSD signals R_OSD, G_OSD, and B-OSD are in the "high", low, and "low" stages, the video signal and OSD background raster can be output in halftones, and OSD i is printed by the Central Standards Bureau of the Ministry of Consumers. 5 ^ The background raster color is red. If HS1 to HS3 are at the "high" low and "high" levels, then When the OSD signals R_OSD, 0_080 and 6_080 are in the "high", "low" and "high" order, the video signal and the OSD background raster can be output in halftones, and the OSD background raster color is magenta. If HS1 to HS3 are in the "high", "high" and "low" stages, respectively, when the OSD signals R_OSD, G_OSD and B-OSD are in the "high", "high" and "low" stages, the video Signal and OSD background raster can be output in halftone, and OSD background raster color is yellow. If HS1 to HS3 are at the "high" high and "high" levels, respectively, when the OSD signals R_OSD and G_OSDAB_OSD are at "high", "high" and "high", the video signal and the OSD background raster can be The halftone output and the OSD background raster color are white. At the same time, the video signal uses halftone together with the OSD background raster during the output of the second window and the OSD background raster according to the OSD control signals HS4 to HS6. The paper dimensions apply to the Chinese National Standard (CNS) Λ4 规 #, (210X297) 7 A7 Η 7 V. Description of the invention (29) The color is similar to the first OSD window, and its detailed description will be deleted. In Figure 12, each of the mixing and amplifying circuits 3, 4 and 5 receives each The video signal of the channel is mixed and amplified according to the video / OSD selection signal V / 0_SEL and amplified video signal and OSD signal, and output the mixed video. Fig. 14 shows the details of one of the mixing and amplifying circuits 3, 4 and 5 in Fig. 12. Because the circuit shown in Figure 15 is the same as the circuit shown in Figure 3, its detailed description is deleted. Figure 27 shows an example of the screen. The screen is based on the specific example of the display device on the screen shown in Figure 12. The video information and OSD raster are based on half The tone is displayed in the two OSD windows. In the screen shown in Figure 27, the two OSD windows A1 and A2 are formed on the screen. In the first window A1, for example, a white halftone background raster is displayed on the background part together with a halftone video signal. Then, for example, Red OSD text is displayed on the background part. In the second window A2, for example, a blue halftone background raster is displayed on the background part together with a halftone video signal. Then, for example, yellow OSD text is displayed on the background part. Fig. 15 shows the 14th A specific example of the selection signal generation circuit 201 in the figure. The selection signal generation circuit includes an AND gate 210, an inverter 212, first and second OSD background screen determination units 214 and 230, an OR gate 242, an attenuator 244, and an inverter. 250 and adder 252. Printed by the Central Bureau of Standards Monthly Consumer Cooperatives --1---I j--i II---- ----- I— I Iτί. Γ (Please read 1A first · Notes on the back, please fill in this page again) AND gate 210 receives the video / 0SD switching signal V / O-SWITCH of halftone signal HT and performs AND operation. Therefore, AND gate 210 is only used for halftone signal HT and video / OSD Switching signal V / 0_SWITCH is "high" "High" is output only at the first step. The output of the AND gate 210 is used as the gate control signal in the first and second OSD background screen decision units 214 and 230. In other words, only the output of the AND gate 210 applies the Chinese national standard (CNS) for this paper size Λ4 Regulations (210X297 Public Welfare) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 _ Η 7_______ 5. When the description of the invention (30) is “high”, it is sent only at the AND gates 226a to 226h of the first OSD background screen decision unit 214 The logical operation results of the 0SD signals R_0SD, 0_080 and 8_080 and the OSD control signals HS1 to HS6 are provided to the OR gate 228. The AND gates 238a and 23 8b of the second OSD background screen decision unit 230 transmit the logical operation results of the OSD signals * R_OSD, G_OSD & B_OSD and OSD control signals HS1 to HS6 to the OR gate 240. When the AND gate 210 outputs "low", the AND gates 226a to 226h and 238a and 238b output "low", and the first and second background screen determination units 214 and 230 also output "low". In the first OSD background screen determination unit 214, the inverters 215, 216, and 217 respectively receive and invert the OSD signals 11_080, G_OSD & B_OSD, and output the inverted OSD signals. Inverters 220, 221, and 222 respectively receive and invert OSD control signals S1 to HS3, and output OSD control signals after inversion. The AND gates 218a to 218h receive the R_OSD signal or the inverted R_OSD signal, the G_OSD signal and the inverted 2G_OSD signal, and the B_OSD signal or the inverted iB_OSD signal, and perform an AND operation on the received signal. The AND gates 224a to 224h receive the OSD control signal HS1 or the inverted OSD control signal / HS1, the OSD control signal HS2 or the inverted OSD control signal / HS2, and the OSD control signal HS3 or the inverted OSD control signal / HS3 performs an AND operation on the received signal. Each of the AND gates 226a to 226h receives an output from a corresponding one of the AND gates 218a to 218h, an output from a corresponding one of the AND gates 224a to 224h, and an output of the AND gate 210 and performs an AND operation. The OR gate 228 receives the outputs of the AND gates 224a to 224h and performs an OR operation. In the first OSD background screen determination unit 230, inverters 233, 234 This paper size is applicable to the Chinese national standard (CNS) A4ML station (210X297) (Please read the precautions on the back before filling this page)

Printed by the Consumer Cooperative of the Central Bureau of Standards and Labor of the Ministry of Labor Λ7 B7 V. Description of the Invention (31) and 235 receive and reverse the SOD control signals HS4 to HS6, respectively, and output the inverted OSD control signals. The AND gates 232a to 232h receive the R_OSD signal or the inverted R_〇SD signal ’G_OSD signal or the inverted G-OSD signal, and the B_OSD signal or the inverted 2B_0SD signal and perform an AND operation. The AND gates 236a to 236h receive the OSD control signal HS4 or the inverted OSD control signal / HS4, the OSD control signal HS5 or the inverted OSD control signal / HS5, and the OSD control signal HS6 or the inverted OSD control signal / The HS6 performs an AND operation on the received signal. Each of the AND gates 238a to 238h receives an output from a corresponding one of the AND gates 232a to 232h, an output from a corresponding one of the AND gates 234a to 234h, and an output of the AND gate 210 and performs an AND operation. The OR gate 240 receives the outputs of the AND gates 238a to 238h and performs an OR operation. The OR gate 242 performs an OR operation on the outputs of the first and second background screen determination units 214 and 230. The attenuator 244 attenuates the output of the OR gate 242 to half and the output attenuated signal. The adder 246 adds the output signal of the attenuator 244 to the output signal of the inverter 212 and outputs the addition result as the video / OSD selection signal V / 0_SEL. Figures 16A to 16J show the output signal of the circuit shown in circle 15 in response to the input signal. The operation of the selection signal generating circuit of Fig. 15 will be described with reference to 16A to 16J. ; When the video / OSD switching signal V / 0_SWITCH is at the “low” level (intervals 250 and 254), the AND gate 210 outputs “low”. In this way, the first and second OSD background screen decision units 214 and 230 output "low". As a result, the OR gate 242 and the inverter 244 output "low". However, the inverter 212 outputs "high". Therefore, the paper size of the adder 246 applies to the Chinese national standard (CNS > A4 Regulations (2 丨 OX 297) #) (Please read the precautions on the back first # Fill this page)

Printed by the Central Bureau of Standards of the People's Republic of China, only printed by the consumer cooperative A7 Η 7 V. Description of the invention (32) Output "high" level video / OSD selection signal V / 0_SEL. The mixing and amplifying circuits 3, 4 and 5 respond to the “high” level video / OSD selection signal V / 0_SEL, respectively, and output only R / G / B video signals. Secondly assume that the video / OSD switching signal V / 0_SWITCH is at the "high" level to indicate the OSD operation mode, and the halftone signal HT is at the "low" level (interval 252) »In this example, the AND gate 210 outputs" low " And the attenuator 244 outputs "low". The inverter 212 outputs "low". Therefore, the adder 246 outputs "low, low-level, video / OSD selection signal V / 0_SEL. The video / OSD selection signal V / 0_SEL is supplied to the video signal selection unit and the OSD signal selection unit of the mixing and amplification circuits 3 and 4 as the OSD selection. Signal 0_SEL and video selection signal V_SEL. Each of the mixing and amplifying circuits 3, 4 and 5 intercepts the R / G / B video signal, and responds to the "low" order video / OSD selection signal Tsui V / 0_SEL only amplifies and outputs the OSD signal. Therefore, the 0SD information is displayed including OSD text information and the background screen. Secondly, it is assumed that the video / OSD switching signal V / 0_SWITCH indicates the OSD operation mode at the “high” level, and the halftone HT is at the “high” level (the interval is 256). In this case, the video signal and the OSD background raster are displayed in halftone on the background screen of the OSD window, which will be detailed later. When HS1 = “Low”, HS2 = “Low” and HS3 = “Low”, the AND gate Of the 224a to 224h, only the AND gate 224h outputs "High", and the AND gates 224a to 224g output "Low". Thus, the AND gates 226a to 226g output "Low". Only when the OSD signal R_OSD, G_OSDAB_OSD are respectively ,, low ,,, "low," and "low," order At this time, AND gate 218h and AND gate 226h output "High '". Therefore, the first OSD background screen determination unit 214 outputs "High". At this time, the attenuator 244 attenuates the signal and output of the OR gate “medium” order. The adder 246 receives the output of the attenuator 244 ---; ---; ----- install-(Please read the precautions on the back before filling this page)

、 1T i_ This paper size is in accordance with Chinese National Standard (CNS) 210X297 cm> Printed by the Central Consumers' Bureau of the Ministry of Economic Affairs and Consumer Cooperatives " A7 __B7 V. Description of the invention (33) and output "medium" video / OSD switching signal V / O SWITCH. In response, the medium and high-order video / OSD switching signals V / 0_SWITCH, and the corresponding counterparts of the mixing and amplifying circuits 3, 4 and 5 attenuating the R / G / B video signals are the halved and output attenuated signals. Each of the mixing and amplifying circuits 3, 4 and 5 attenuates the corresponding OSD signal to half and outputs the attenuated signal. In this way, the black halftone OSD background screen raster is displayed along with the halftone video information. When HS 1 = "Low", HS2 = "Low" and HS3 = "High," only the AND gate 224g of the AND gates 224a to 224h outputs "High", and the AND gates 224a to 224f and 224h output "Low" In this way, the AND gates 226a to 226f and 226h output "low". It also means that when the OSD signals R_OSD, G_OSD and B_OSD are in the "low", "low" and "high" stages, the AND gate 218g outputs "High" and AND gate 226g outputs "High". Therefore, the first SD background pen screen determination unit 214 outputs "High". At this time, the attenuator 244 attenuates the signal and output of the “OR” stage of the OR gate. The adder 246 receives the output of the attenuator 244 and outputs the "medium" order video / OSD selection signal V / 〇_SEL. In response to the "medium" level video / OSD selection signal V / 0_SEL, each of the mixing and amplifying circuits 3, 4 and 5 attenuates the R / G / B video signal to half, and outputs the attenuated video signal. Each of the mixing and amplifying circuits 3, 4 and 5 attenuates the corresponding SD signal to half and outputs the attenuated OSD signal. In this way, a blue halftone OSD background screen raster is displayed along with halftone video information. When the OSD signal has other combinations, the circuit of Fig. 6 operates in a similar manner. The second bsD background screen determination unit 230 operates similarly to the first OSD background screen determination unit 214. Therefore, the detailed description of the calculation of the second OSD background screen determination unit 230 is deleted. This paper size is applicable to China National Standards (CNS) Λ4 specifications (210x2 < m >#) (Please read the precautions on the back before filling this page): Binding & Binding A 7 H7 V. Description of the Invention (34) The 16G diagram shows the video / OSD selection signal V / 0_SEL when the OSD control signals HS1 to HS6 are in the "high", "high", "high", "low", "low" and "high" stages, respectively. When the video / OSD switching signal V / 0_SWITCH is at "high," and the OSD operation mode is indicated, and the halftone signal HT is at "high," the AND gate 210 outputs "low". As a result, the attenuator 244 outputs "low" ". The inverter 212 also outputs" Low ". The first OSD background screen determination unit 214 is only available in the OSD signal & R_OSD, 0_080 and Ug_080 at the" high "," high "and" high "steps (interval 60) only output "High". The second OSD background screen determination unit 230 outputs "high" 'only when the OSD signals R_OSD, 0_080 and 3_080 are at the "low",' 'low "and" high "steps (interval 62).

Therefore, the video / OSD selection signal V / 0_SEL is at the “middle” level at intervals of 60 and 62. So when the OSD signals R_0? D 'G-OSD and B-OSD are at the "high ,,,,, high" and "high" levels, that is, when the white first OSD background screen signal is input, mix | and zoom in Circuits 3, 4 and 5 output attenuated R / G / B ΐ video signals and attenuated OSD signals. When the OSD signals R_OSD'G_OSD and 8_08〇 are at the “low low” and “high” levels, that is, when the blue second OSD background screen signal is input, the output of the mixing and amplification circuits 3, 4 and 5 is attenuated. R / G / B video signal and attenuated 0SD signal. Printed by the Ministry of Consumers ’Central Standardization Bureau, Shellfish Consumer Cooperative, as mentioned above, according to this specific example, a 20SD window can be formed with the screen. The OSD background screen is only It can be displayed in an individual SD window by one of the multi-colors of the 0SD raster (interval 252), or by a halftone video signal and a halftone 080 background screen display (interval 256). In terms of it, on the screen using the invention In the monitor or liquid crystal display of the display, the background raster colors and 0SD characters of the first and second 0SD1 windows are made by the monitor or liquid crystal display. The paper size is applicable to the Chinese National Standard (CNS) Λ4 gauge (210X 2) ) .37- B7 V. Description of the invention (M) Program planning decision of the manufacturer "Figure 17 shows the alternative specific example of the selection signal generating circuit of Figure 15. In the specific example of Figure 17, the AND gate 210 output gate Control signal is not input AND Gates 227a to 227h 'and an additional AND gate 243 are provided. Therefore, AND gates 227a to 227h include two input gates. AND. Gate 243 performs an AND operation on the output of OR gate 242 and the gate control signal. Attenuator 244 receives the output of AND gate 243 And attenuate the received signal to half. Since the circuit operation in Fig. 17 is similar to the circuit operation in Fig. 15, its detailed description is deleted. Fig. 18 shows another specific example of the selection signal generating circuit in Fig. 12. Refer to this figure. 'Selection signal generation circuit 201 includes video / OSD switching unit 300 and interface buffer 310' OSD raster selector 320 and OSD half-color Qin tone signal generator 330. At the same time, 'mixing and amplifying circuits 3, 4 and 5 are combined in the first Figure 18. The video / OSD switching unit 300 receives the video / OSD switching signal V / 0_SWITCH and generates and outputs first and second switching signals swi and SW2. The video / OSD switching unit 300 generates and outputs a reference voltage REPV for Determining the rank of video / OSD selection signal V / 0_SEL "The interface buffer 310, which is used by the central government sample bureau staff consumer cooperative printing and printing company, receives the OSD control signal and half-color through the inter-chip (IIC) bus The signal HT buffers the received signal and outputs the buffered signals HS1 'to HS6' and HT '. The OSD raster selector 320 adjusts the swing range of the RGB OSD signal, and outputs the raster selection signals RAS1 and RAS2 at a specific OSD signal k input timing, The timing is based on the OSD control signals HS0 and HS1 of the operating mode of the OSD. -38- This paper size is applicable to China National Standards (CNS) Λ4l (2l0x29h > 满). Indium Bismuth A7 »7________________ V. Description of the Invention (36) 'Therefore, one of a plurality of ODSD gratings is selected for each of the first and second OSD windows. The OSD halftone signal generator 330 generates and outputs the video / 〇SD selection signal V / 0_SEL according to the switching signals SW1 and SW2 and the OSD control signals HS0 and HS1 when the halftone signal HT indicates halftone video output. In this specific example, the signals shown by circles 18 and 19 to 23 are summarized below. 〇Video / 〇SD switching signal v / O SWITCH: TTL level signal that switches between 0V and 5. 〇First switching signal SW1: Relative to the video / 〇SD switching signal V / O-SWITCH is in a negative phase and swings between 5.1V and 6V. 〇 Reference voltage RERV1: It is at the middle level of the swing range of the first switching signal SW1. »0 Second switching signal SW2: Relative to the video / OSD switching signal V / 0-SWITCH has a negative phase and swings between 4.35V and 5.25V. ° Reference_REFV: It is at the middle level of the swing range of the first switching signal SW2. o OSD control signal HS1: Control R_OSD to select the OSD background raster of the first OSD window and switch between .iv and 2.IV.

SD control signal HS2: controls g_OSD to select the OSD background raster of the first OSD window and switch between 0.1 v and 2.IV. 〇 SD control signal HS3: Control B_SD to select the OSD background raster of the first OSD window and switch between 0.1 v and 2.IV. 〇OSD control signal HS4: Control r_〇sd to select the OSD background raster of the second OSD window and switch between 0.1 v and 2.1 V "This paper size is applicable to the Chinese National Architecture (CNS) Λ4 grid (210X297 Public V7 (Please read the precautions before filling in this page) [Package ·

* 1T Printed by the Central Bureau of Consumer Affairs, Central Bureau of Industry and Commerce, B Industrial Consumer Cooperative, A7, B7 V. Description of the invention (37) 0 OSD control signal HS5: Control G_SD and select the OSD background raster of the second OSD window and be between ο. Switch between ιν and 21v "〇 OSD control signal HS6: Control b_OSD and select the 080 background raster of the second OSD window and switch between 0.1 \ ^ and 2.1 '^. 〇 Grating selection signal RAS1: It is excited under a specific combination of OSD signals according to the OD control signals HSO and HS1, so a certain OSD background raster is selected for the first OSS window. 〇 Raster selection signal RAS2: It is excited under a specific combination of OSD signals according to the OD control signals HSO and HS1, so a certain OSD background raster is selected for the second OD window. 〇 Halftone signal HT: Switch between 0.IV and 3.IV and be in the "high" order when the halftone operation mode is used. 〇 Modal control signal HT_RS: Enable OSD grating selector at 0.902V in OSD operation mode, and disable OSD grating selector at 0V in non-Osd operation mode. 〇 Inverted halftone signal HT_I: It has a negative phase relative to the halftone signal HT and switches between 0V and 1.26V. 0 Select reference voltage BS1: The reference signal used to bias the interface buffer is 1.197V. 〇Select the reference voltage BS2: to determine the level of the OSD control signals HS0 and HS1 as reference signals and at 1.624V »Select the reference voltage BS2: to determine the level of the level-adjusted halftone signal HT 'and generate an inverted halftone signal HT_I The reference signal is at 1.65V. '' This paper size applies the Chinese national standard (CNS > Λ4 specification (210 × 297 male adhesive 40- (#Read the note on the back ^ al · item before filling out this page) --0 丁 A7 __B7 V. Description of the invention (38) Fig. 19 is an example of a circuit circle of the video / OSD switching unit 300 of Fig. 18, and 20A to 20C. An example of an output signal of the video / OSD switching unit shown in Fig. 19 is shown in Fig. 19. Because of the video of Fig. 18, The structure and operation of the / OSD switching unit are similar to the circuit of Fig. 7, so its detailed description is deleted. Fig. 21 shows the details of the interface buffer 310 around the 18th. The halftone signal HT is input to the base of the transistor Q101. The transistor The rank of the emitter voltage of Qi〇i is 1Vbe lower than the rank of the halftone signal HT, 1 () 1 is the base of the transistor Q102. The rank is 1 Vbe higher than the base voltage of the transistor qi〇2, ι〇 2 The transistor Q101's emitter voltage output is used as a buffered halftone signal HT '"because the voltage between the base and the emitter of the transistor Q101 Vbe 10 is equal to the range between the base and the emitter of the transistor Q101 The voltage is 1 vbe, and the amplitude is 102. Therefore, the buffered halftone 笮, HT, is related to the input halftone. The level of the signal HT is the same. However, the buffered halftone signal HT 'has a greater current driving capability than the input halftone signal HT. The OSD control signal HS1 printed by the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is an input transistor Q103 The base of the buffer. The buffered OSD control signal HS1 has the same level as the OSD control signal HSI1 and has a higher current drive capability. It is a buffered halftone signal ht, which is output by the transistor Q104 in the same way. The pole wheels are output. 0sd control signals HS2 to HS6 are input to the bases of the transistor Q105, Q107, Q109, Q111, and Q113. After buffering with the same level as the OSD control signals HS2 to HS6 and a higher current drive capability The OSD control signals HS2, to HS6 'are output via the emitters of the transistors Q106, Q108, Q110, QH2, and Q114. The "buffered halftone signal (HT,)" is referred to below as, the halftone signal This paper size is applicable to China National Building Standard (CNS) A4ML 梠 (210X297 public place Γ -41-printed by the Central Standards Bureau of the Ministry of Standardization, Shellfish Consumer Cooperatives, Λ7 H7, V. Description of Invention (39) (HT ') ". "Buffered OSD control signals (HS1 'to HS6')" is simply referred to as "OSD control signals (HS1 'to HS6')". Transistors Q115 and Q116 include comparators. The halftone signal HT 'is applied to transistor Q115 The third bias BS3 output from the OSD halftone signal generating unit 330 is applied to the base of the transistor Q116. When the halftone signal HT 'is higher than the third bias BS3, the collector voltage of the transistor Q115 is at the "low" level. When the halftone signal HT 'is smaller than the third bias BS3, the collector voltage of the transistor Q115 is in the "high" order. The collector voltage of the transistor Q115 is the inverted halftone signal HT_I and is output to the OSD grating selector 320. In this specific example, the inverted halftone signal HT_I is switched between 0V and 1.26V. Figures 22A and 22B show details of the OSD raster selector 320 in the ninth circle. 22A and 22B, the OSD raster selector 320 includes a level adjustment circuit 322, a first comparison circuit 324, a bias circuit 326, and a second comparison circuit 328. The level adjustment circuit 322 adjusts the swing ranges of the OSD signals R_OSD, G_OSD & B_OSD, and provides the level-adjusted OSD signals to the first and second comparison circuits 324 and 328. The first comparison circuit 324 outputs the first raster selection signal RAS1 of the first OSD window, which is only activated when a specific logical combination of the OSD signals is input according to the OSD control signals HS1 'to HS3'. The second comparison circuit 328 outputs the second raster selection signal RAS2 of the second OSD window, which is only activated when a specific logic combination of the 0SD signal is inputted according to the 0SD control signals HS4 'to HS6'. I level adjustment circuit _ · 322, resistors R31 and R32 and two diodes The paper size is applicable to China National Standards (CNS) station (210X297) * »ί Please read the precautions on the back before this page ) Installation, 1T " -42- A7 H7 V. Description of the invention (40) The transistor is connected to form a seventh reference current Iref, 7 and divides the power supply voltage Vcc, so the voltage Vc is supplied to the base of the transistor Q123. Transistor Q122 and Q123 compare 11_080 and voltage Vc 俾 to adjust the swing range of R_OSD. According to the comparison result, the collector voltage of the transistor Q121 changes and is supplied to the comparison circuit 324 as the OSD signal R_OSD 'after the level adjustment. The "low" and "high" levels of the OSD signal R_OSD 'after the level adjustment are determined by the following formulas, and in this specific example have values of 1.6V and 3.6V, respectively. R_OSD '("Low") = R_OSD ("Low") + Vbe, 122 + Vbe, 121 (10) R_OSD, ("High") = R12 · Iref, 7 + Vbe, 123 + Vbe, m resistors R33 and R34 and two diodes connect the transistor to form an eighth reference current Iref, 8 and divide the power supply voltage Vcc, so the voltage VD is supplied to the base of the transistor Q140. Transistors Q126 and Q127 compare G_OSD and voltage VD 俾 to adjust the swing range of 0_080. According to the comparison result, the collector voltage of the transistor Q125 is changed and supplied to the comparison circuit 324 as the OSD signal G_OSD after the level adjustment. The OSD signal G-OSD after level adjustment is swinging in the range of 1.6V to 3.6V. Printed by the Central Standards Bureau of the Ministry of Work of the People ’s Republic of China, the resistor R35 uses R36 and two diodes to connect the transistor to form the ninth reference current Iref, 9 and the divided power supply voltage Vcc, so the voltage Ve is supplied to the base of the transistor Q131. Transistors Q130 and Q131 compare B_OSD and voltage VE 俾 to adjust the swing range of B_OSD. According to the comparison result, the collector voltage of transistor Q129 changes and is supplied to comparison circuit 324 as the level-adjusted signal B_OSD, and the level-adjusted OSD signal B_OSD swings in the range of 1.6V to 3.6V. Transistor Q124's emitter voltage is 1Vbe higher than voltage Vc and output to the paper standard applicable to Chinese national standards (called Na (employee shoulder _43. A7 B7 V. Description of the invention (41)) Beige Consumer Cooperative Co., Ltd. ’s first and second comparison circuits 324 and 328 serve as the R path. SD reference p number R_OSD_ref. The emitter voltage of transistor Q128 is 1λ higher than the voltage ^ and it is rotated to the first and second comparisons. The circuits 324 and 328 serve as the G-channel SD reference signal G_OSD_ref. The emitter voltage of transistor Q132 is 1 vb higher than the voltage ve and is output to the first and second comparison circuits 324 and 328 as the B-channel OSD reference signal B_OSD_ref. First comparison The operation of the circuit 324 is controlled by the modal control signal HT_RS output by the 0SD halftone signal generating circuit 330. When the modal control signal HT_RS is in the "high" order, the transistors Q133, Q134, and Q135 output current, so the comparison circuit 324 When the modal control signal HT_RS is at the "low" level, the transistors Q133, Q134, and Q135 are passivated and the comparison circuit 324 is not activated. The bias circuit 326 provides a voltage relative to the first and second comparison circuits 324 and 324. Bias of 328. Electric The transistor R37 and R38, the diode Q155 and the resistor R39 form the tenth reference current Iief. When the inverse halftone signal HT_I is at, 'high ,, the transistor Q154 forms a bypass current path' Therefore, the tenth reference current Iref, 1Q has a higher value than that when the inverse halftone signal HT_I is in the “low” order. The first grating selection signal RS1, which is the voltage of the node 400, is expressed by the following formula.

RAS1 = Vcc-R37Iref, 10-2Vbe. IR

(ID When the halftone signal HT is in the "low" order and indicates non-half. In the case of modal operation, the inverse halftone signal HTj is in the "high" order. Therefore, the tenth reference current Iref. Has a large value, And the current IR40 flowing through the resistor R40 becomes 0. This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210 × 297 male 筇 -44-Please read the note on the back first

pi i I Order Μ Printed by the Central Bureau of Standards of the Ministry of Industry, only printed by the consumer cooperative A7 H7 ___ V. Description of the invention (42)

. At this time, the first raster selection signal RAS1 has a low value of 2.5V in this specific example. When the halftone signal HT is in the "high" order to indicate the halftone modal operation, the OSD control signals HS1 to HS3 and the OSD signals are used. R_OSD, G_OSD & B_OSD, the first raster selection signal RS1 has an amplitude of 4.88V or 3.5V. Details later. The first comparison circuit 324 includes three comparators including transistors Q136 and Q137 ', transistors Q138 and Q139, and transistors Q140 and Q141, which compare the OSD control signals HS1, HS2, and HS3 with the second bias voltage BS2, and according to the comparison, The result control includes the operation of six comparators of paired transistors Q142 and Q143, Q144 and Q145, Q146 and Q147, Q148 and Q149, Q150 and Q151, and Q152 and Q153. Transistors: Compare the adjusted OSD signals R_〇SD ', G_OSD' and B_OSD for the six transistors Q142 and Q143, Q144 and Q145, Q146 and Q147, Q148 and Q149, Q150 and Q151, and Q152 and Q153. 'And OSD reference voltage R_〇SD_ref' G_OSD "ef and B_OSD_ref. According to the comparison result, the amplitude of the current 1 to 40 flowing from the node 400 to the first comparison circuit 324 changes. For example, suppose HSil '= "Low", HS2' = "Low" and HS3 '= "Low". In this example, transistors Q136, Q138, and Q140 are passivated but transistors Q137, Q139, and Q141 are excited. Therefore, the transistor operates on QH4 and Q145, Q148 and Q149, and Q152 and Q153. When at least one signal R_OSD, g_0SD 'and Ug_080' are in the "high" order, one of the transistors Q144, Q148, and Q152 receives the "high" order through the base and is excited. 》 In this way, the current ir4o flowing from the node 400 to the first comparison circuit 324 increases. At this time, the paper size of the formula 11 table applies to China National Standards (CNS) Λ4ϋ (210X2 ^^^ ~ -45-• »(Please read the precautions on the back before this page-installation ·, 1Τ -line-Α7 Η7 V. Description of the invention (43) The first grating selection signal RS1 shown in the figure is at the "low" order 3.5V. At the same time, when all the signals R_OSD ', G_OSD' and B-OSD are at,, low, 'order, by the node The IR40 current flowing from 400 to the first comparison circuit 324 is 0, and the first raster selection signal RAS1 is at a “high” level of 4.88V. Therefore, the first raster selection signal RAS1 is enabled only when the white OSD background screen is enabled. 'High' level. Therefore, OSD information can be displayed on an OSD background screen formed by a white halftone OSD raster and a halftone video signal, which will be described in detail later. When it is assumed that HS1 '= "High", HS2' = "Low" And HS3 '= "Low", the transistors Q137, Q138 and Q140 are passivated but the transistors Q136, Q139 and Q141 are excited. Therefore, the transistor acts on Q142 and Q143, Q148 and Q149, and Q152 and Q153. R OSD, tied to "low" order, signal G_OSD 'tied to "high," order 4B_0SD, tied to', high In the first order, the transistors Q142, Q148, and Q152 are excited. In this way, the current IR4q flowing from the node 400 to the first comparison circuit 324 increases. At this time, the first grating selection signal RS1 is at, low, 'order 3.5V At the same time, when the signal R_OSD 'is at the "high" level and the signal g_OSD, and B_OSD' is at the "low" level, the current IR40 is 0 and the first grating selection signal RAS1 is at "high" level 4.88V. A raster selection signal RAS1 is enabled only when the red OSD background screen is “high,”. Therefore, the OSD information can be displayed on the OSD background screen formed by the red halftone OSD raster and the halftone video signal. In detail, when the OSD control signals HS1 'to HS3' have other logic combinations, the first comparison circuit 324 operates in a similar manner. In other words, the first raster selection signal RAS1 has a low value during non-halftone modal operation 2.5V. In the half-tone modal calculation, the first raster selection signal RAS1 is only applicable to the Chinese paper standard (CNS :) eight ^ see tip (2 丨 OX2W public) in this paper scale ί · 46-Φ ( (Please read the notes on the back before this page) 0 3 Γ Printed by the Central Bureau of Standards and Quarantine, Shellfish Consumer Cooperative Λ7 Η 7 __ V. Description of the invention (44) The specific combination of OSD signals determined by the OSD control signals HS Γ to HS3 'is high during the input period. The order is 4.88V, but it is in the "low" order during the OSD signal combination different from the specific combination input. The second comparison circuit 328 operates in the same manner as the first comparison circuit 324. In other words, the current IR41 flowing through the resistor R41 and the voltage at the node 401, and the level of the second grating selection signal RS2 are changed according to the OSD control signals HS4 'to HS6' and the signals OSD_R ', OSD_G', and OSD_B '. The second raster selection signal RS2 is at a "high" level of 4.88V only when a specific OSD signal combination determined by the OSD control signals HS4 'to HS6' is input, but during the input period of an OSD signal combination different from the specific combination. At the "low" level. Fig. 23 shows the details of the OSD halftone signal generator 330 in Fig. 18. The OSD halftone signal generator 330 in Fig. 23 includes a modal control signal generating circuit 332 and an output signal generating circuit. 334 and reference signal generating circuit 336. The modal control signal generating circuit 332 receives the halftone signal HT 'and the second switching signal SW2, generates a modal control signal HT_RS, and outputs a modal

The control signal HT_RS is printed to the OSD raster selector 320 in Figs. 22A and 22B by the Central Bureau of Standards of the Ministry of Economics and Industry. The output signal generating circuit 334 receives the first and second raster selection signals RAS1 and RAS2, the first switching signal SW1, the reference voltage RERV1, and a signal SW2-2 Vbe that is 2Vbe lower than the second switching signal SW2, and generates and outputs video / OSD Select signal V / 0_SEL. The reference signal generating circuit 336 generates a plurality of reference voltages, and provides such signals to the modal control signal generating circuit 332 and the output signal generating circuit 334. Referring to the signal generation circuit 336, the paper size is applicable to China National Standards (CNS) Λ4 Regulations (210X 297) 筇 47- Λ7 H7 V. Description of the Invention (45) Generate the first to third bias voltages BS1 to BS3 'And output the first to third bias voltages to the interface buffer 310 of FIG. 21 and the 0800 raster selector 330 of the 22th and 228th circles. In the reference signal generating circuit 336, the resistors R61, R62, R63, and R64 connected in series and the transistor Q190 divide the current voltage Vcc. Therefore, the voltage level of the node 338 of a certain amplitude is supplied to the base of the transistor Q168, and some The amount of current flows through the transistor Q168. The voltage at the node 339 is supplied to the base of the transistor q 192 after the voltage between the base and the emitter of the transistor Qi7〇 is reduced. Because the base of the transistor Q192 is biased to a constant level, a predetermined reference current Iref, 7 flows through the transistors Q191 and Q192, and this current repeatedly flows through multiple transistors such as the transistor Q182 »The base of the transistor Q192 The pole voltage is output as a first bias BS1. The output of node 339 is used as the third bias BS3. The voltage of the node 340 is output as the second bias voltage BS2 after the voltage between the base and the emitter of the transistor Q193 is reduced. In the modal control signal generating circuit 332, the transistors Qi60 and Q161 constitute a comparator. The second switching signal SW2-2Vbe reduced by 2Vbe by the transistors Q162 and Q163 is applied to the base of the transistor Q160. The halftone signal ht is applied to the base of transistor Q161. The halftone signal Ητ 'has a level of 3.2V in the halftone mode. When the second switching signal SW2 is at a high, high, or high level to indicate the video interval, the transistor Q160 is excited but the transistor q 丨 6 丨 is passivated. In this way, very little current flows through the transistor Q167 and the resistor R52, and the modal control signal HT-RS is at a low order. When the second switching signal SW2 is at the low, low, and high level to indicate the OSD interval, the transistor Q160 is purified but the transistor (^ 160) is excited. In this way, the current flows through the transistor Q167 and the resistor R52 »to the transistor Q164 This paper size applies to Chinese National Standard (CNS) Λ4% #, (210X29 * 7T > Fj '----------- (Please read the note on the back before

In the current mirror of the combination of Q46 and Q165 in the current mirror of the combination of invention description (46) and Q165, the transistor 卩 165 provides a ratio of Transistor q164 has approximately 4 times the amount of current. Therefore, the amplitude of the modal control signal ht_rs is expressed by the following formula and is 0.902V in the "high" order. HTrs = 41c, 168 · R52 + VBE, 167 (12) In the output signal generating circuit 336, the transistors Q173 and Q176 and the transistor Q177 constitute a comparator. The first grating selection signal is lowered by 2vbe, and RAS1-2Vbe is applied to the base of transistor Q173. The second grating selection signal is lowered by 2Vbe 'RAS2-2Vbe is applied to the base of transistor Q177 "transistor Q173 is excited and only when the halftone signal HT' is connected to, the high order and the second switching signal SW2 are connected to The buffer of the combination of transistor Q178 and Q179 is only enabled at the "low" stage. "At this time, the reference voltage RERV1 is applied to the base of transistor Q169, which is buffered by the buffer, and it is 1Vbe2 lower than the reference voltage rEFVi. The emitter voltage output is used as the video / OSD selection signal V / 0_SEL. As a result, when the half-tone signal HT is at the "high" level and the second switching signal SW2 is at the "low" level, indicating the OSD half-tone modal operation, the video The / OSD selection signal V / 0-SEL has a voltage range that is 1Vbe lower than the reference voltage REPV1, that is, the reference voltages REPV and REVO. When printed by the Central Bureau of Standardization of the Ministry of Economic Affairs, the second switch signal SW2 is When the “low” level indicates the video interval, the first switching signal S_1 is applied to the base of transistor Q181, which is buffered by the buffer of the combination of transistors Q180 and Q181 to be output. In other words, the first switching signal SW1 is lowered at this time. 1 Vbe The emitter output of the transistor Q183 is used as the video / OSD selection signal V / 0_SEL. As a result, the video / OSD selection signal V / 0_SEL has the same amplitude as the first switching signal SW1 decreases by 1 Vbe, that is, the second Switching signal SW2. This paper size is applicable to the Chinese National Standards (CNS) Λ4 grid (2 丨 OX297) > -49-Λ7 \\ 1 V. Description of the invention (47) Figures 24A to 24C are waveform chart display basis The verification results of the integrated circuit of the device on the screen implemented in the previous specific example. Figure 24A shows the R channel output signal. Figure 24B shows the G channel output signal. Figure 24C shows the B channel output signal. Figures 24A to 24C confirm It is assumed that the OSD control signals HS1 to HS6 are set to "low", "low", "high, high", and "high" respectively, so the blue raster is used for the background screen of the first OSD window, and the white raster is used for the background of the second OSD window. Screen. Only video signals are output at time intervals 360, 364, 374, and 378. Only OSD signals are output at time intervals 362, 366, 372, and 376. Video signals and OSD signals are "medium" at time intervals 368 and 370. Order output. During these time intervals, the video image and OSD background screen input from the OSD interface (not shown) under the control of a microcontroller (not shown) are displayed in halftone. In particular, the blue background of the first OSD window The screens are displayed at intervals of 368. Such blue background screens can be identified by the OSD control signals HS1 to HS3 applied to the on-screen display according to the present invention. The white background screen of the second OSD window is 370 display. Such white background screens are identified by the OSD control signals HS4 to HS6 applied to the on-screen display according to the present invention. Although the description of the second OSD window can be displayed in the foregoing specific example, the number of OSD windows is not limited to two, but can be more. The 15 or 17 selection signal generating circuit. The number of OSD windows can be increased by increasing the number of OSD background screen decision units 214 and 230. In the selection signal generating circuit in Fig. 18, the number of OSD windows can be increased by adding the comparison circuit 324 in Fig. 22A and 22B and the paper size applicable to the Chinese National Standard (CNS) Λ4ΜΙ 彳 Μ 210X297 public light) -50- Λ7 ___ H V. Description of the invention (48) 328 and the number of grating selection signals RAS1 and RAS2 increase. The number of better OSD control signals HS1 to HS6 and the 23rd transistor Q173 and Q174 must also be increased. Even if one of the eight OSD rasters can be selected for each window in the foregoing specific example, the number of possible OSD rasters can be reduced. When the number of osd gratings is reduced, the number of OSD control signals can be reduced. As the number of possible 0SD rasters increases, the number of OSD control signals must increase. It is particularly possible that the number of gratings can be changed with respect to each window. For example, for the first window, one of the eight OSD gratings can be selected, and for the second window, one of the four OSD gratings can be selected. The display devices on the screens of the 1st and 12th circles further include a SD interface circuit for adjusting the gain of the OSD signal, so the swing range of the OSS signal is equal to the swing range of the video signal. In this example, the swing range of the OSD signal adjusted by the SD circuit is input to the mixing and amplifying circuit and the selection signal generating circuit. In the specific example in FIG. 18, the video / OSD switching unit 300 may be combined into an OSD halftone signal generating unit 330, and provided instead as another block. Printed by the Central Ministry of Economic Affairs, Central Government and Consumer Cooperatives " In the foregoing specific example, a video / OSD selection signal is commonly supplied to the video signal selector and the OSD signal selector of Fig. 5. However, the video selection signal and OSD selection signal can be supplied to the video signal selector and 〇SD signal selector. "The video information and J3SD background screen can be displayed half-tone in one of multiple 〇SD windows, while the OSD background screen can only be borrowed. 〇sd raster or video signal with perfect tone is displayed in another window. This kind of display is easy to realize by the combination of OSD control signals and has nothing to do with the background screen of OSD and the color of OSD text. The standard of this paper is applicable to the Chinese National Standard (CNS) / \ 4 regulations (210x297 male jijTy -51-printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by the Bayer Consumer Cooperative) Λ7 H7 V. Description of the invention (49) Component label comparison 1. .Select signal generation circuit generator 3-5 ... mixing and amplifying circuit 122 ... level adjustment circuit 7 ... video signal selector 124 ... comparison circuit 8 ... OSD signal selector 132 ... modal Control signal generating circuit 9 ... amplifier 136 ... output signal generating circuit 10 ... AND gate 138 ... reference signal generating circuit 12, 20, 28, 36 ... 133-5 ... buffer OSD Decision unit 201 ... selects the signal generating circuits 18, 26, 34, 44. " 210. " AND gate AND gate, 212 ... inverter 46 ... OR gate 214, 230 ... OSD background screen 48 ··· Attenuator determination unit 50 ... inverter 242 ... OR gate 5 2 ... adder 244 ... attenuator 4 7 ... inverter 250 ... inverter 60-96 ... interval 252 ... adder 16, 22, 30, 32, 42 ... gate 226a-h. &Quot; AND gate 28 ... 0SD decision circuit 228 ... · OR gate 100 ... selection signal generation circuit 238a- b " .AND Gate 110 ... Video / OSD switching order Element 240-2 ... OR gate 120 ... OSD raster selector 215-7, 220-2, 233-5 ... 130. OSD half-tone signal production inverter Please read the notes on the back first F page again.

、 1T .¼ This paper size applies Chinese National Standards (CNS) Λ4 Regulations (210X297 Gong Zheng) -52-! Λ7 H7 V. Description of the Invention (5〇) 218a-h, 224a-h, 227a-h, 232a -h, 234a-h, 236a-h, 238a-h, 243 ... AND gate 244 ... Attenuator 246... Adder 2 5 Ο-6 ... Interval 300 ... Video / OSD switching Unit 310 ... Interface buffer 320..05. Raster selector 330 ... OSD halftone signal generator 322 ... Level adjustment circuit 324 ... First comparison circuit 326 ... Bias circuit 328 ... Second comparison circuit 338-401 ... node 332 .. modal control signal generation circuit 334 .. output signal generation circuit 336 .. reference signal generation circuit 360-76 ... interval (please read the precautions on the back first) (Fill in this page again) Γ, ιτ Μ · The paper size printed by the Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs applies to Chinese National Standards (CNS) Λ4 now; (ft (210X297 public welfare) -53-

Claims (1)

Printed A8 B8 C8 D8 patent application for male workers' consumer cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 1. An on-screen display device comprising: three mixing and amplifying circuits, each supplying each R / G / B channel and each receiving individual The visual chaos signal 1 and QS & signal of the channel, mix the video signal and OSD signal peak according to the video selection signal, amplify the mixed signal, and output the amplified video signal to the display; and a selection signal generating circuit for Receiving OSD signals s ~. \ Of R / G / B channel, video / OSD switching signals, halftone signals, OSD control signals of the second predetermined number of OSD windows, and generating and outputting OSD selection signals # + Η · ί, and Video selection signal. When the video / 0SD switching signal indicates the OSD output operation and the halftone signal indicates the half-color shoulder output and operation, the selection signal generation circuit outputs the video full signal and the OSD selection signal, so the halftone OSD has a background raster. A halftone solitary image is displayed on a predetermined OSD window. 2. For example, the on-screen display device of the scope of patent application, wherein the selection $ generation circuit includes: a halftone display signal generator for generating a halftone display signal, which is only in the video / OSD switching signal _ instruction OSD The output calculation, the fur color value, the half-tone adjustment of the wearing instruction, and the OSD signal are only excited when they have a predetermined logical combination; an inverter is used to invert the video / OSD switching signal and output a video modal signal. It is excited when the video signal is output; a fader is used to attenuate the half-tone display signal to half; and an adder is used to add the video modal signal to the attenuator output. Xenon please read the note I above Order M This paper size applies to China National Standards (CNS) A4 specifications (210X297 mm) -54- Printed by A8 B8 C8 D8, Shelley Consumer Cooperatives, Central Stairway Bureau, Ministry of Economy Select Wei JiL and OSD and select i number. 3. ^ The on-screen display device in the second item of the patent application, wherein the plurality of OSD control signals include a first control signal and a second control signal. 4 As in the on-screen display device in the third item of patent application, wherein The halftone display signal generator includes: a first OSD determining circuit for controlling the second and third OSD, R OSD, G OSD and-^-— B_ The SD signal is output at the first logic level only at the second logic level. A second OSD determination circuit is used only when the first OSD signal is at the second logic level. * The second level is> The first logic level, the R_OSDLaB_OSI ^ signal is at the second logic level, and G_OS; the D signal is at the first logic level to output the first logic level; a third OSD decision circuit is used-only at the first, OSD The signal belongs to the second logic level, the second OSD control signal is at the first logic level, the R OSD and G-OSD signals are at the second logic level, and the B-OSD signal is at the first logic level. Output the first logic level; a fourth OSD decision circuit The first logic level is output only when the first and second OSD control signals are at the first level and R_OSD is at the second level. G_OSD & B_OSD signals are at the first logic level; and • ^ OR to receive The first to fourth OSJDs have decided to thin out the ^ long out and perform an OR operation. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ^ --- M ---- ^-(Please First read the note $ on the back and fill in this page) Order Ji · -55- Printed by A8, B8, C8, D8, and Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 6. Scope of patent application 5. If the screen of item 1 of the scope of patent application is applied The upper display device, wherein the selection signal generating circuit includes: a video / QSD switching unit for receiving video / QSD switching signals and generating at least one switching signal according to the video JfL / OSD switching signal; an OSD light meal selection article It is used to adjust the deafness range of the R / G / B 0SD signal, and determine whether each of the J5 is adjusted to the JR7G / B OSD signal; ^ whether the second logical level is subtracted from the first late agricultural level, and when R / G / B, OSD signal corresponds to the predetermined logic level combination determined according to the OSD control signal: Output a raster selection signal; and a halftone J-signal generator for receiving the switching signal and raster selection signal from the video / OSD switching unit and the OSD raster selector, and generating the OSD selection signal and the out-of-view selection signal. 6 For example, the display device on the screen of item 5 of the scope of patent application, wherein the video / OSD switching unit generates a reference voltage for the mixing and amplifying circuit to determine the logical level of the video selection signal and the OSD selection signal. 7. For example, the on-screen display device in the scope of application for patent, wherein the body selection signal generating circuit includes: an OSD raster selector for adjusting the R / G / B 080 signal and the range of the left swing to determine the level of each level of milk Whether the R / G / B OSD signal is at the first logic level or the second logic level, and when the R / G / B OSD signal corresponds to a predetermined logic level combination determined according to the 0 SD control signal, the output is selected first Signal; and a halftone signal generator for receiving the switching signal and the raster selection signal from the video / OSD switching unit and the OSD raster selector, the paper ruler uses the Chinese National Standard (CNS) A4 specification (210X297) (%) (Please read the note on the back before filling in this page.) --56- Central Standards Bureau of the Ministry of Economic Affairs® C Industrial Consumer Cooperative Press A8 B8 C8 D8 Patent Application Scope and Treasury OSD Tree Selection Signal and Alert Selection signal. 8. If the on-screen display device of the first patent application scope, wherein the video selection signal and the OSD selection signal are the same single video / OSD selection signal; and t each of the mixing and amplifying circuits are in the video / OSD selection product It is the second logical avoidance fish step. When only the U number is enlarged and the amplified video signal is output. I__ where each of the mixed signal and the amplifier-circuit is in the video / OSD selection signal. At the same time, only the OSD signal is amplified and the amplified OSD signal is output; and its 1F each mixing and amplifying circuit is based on the video / OSD selection signal when the logic level is mixed, and the JSv signal and the OSD signal are mixed to output the amplified signal. Mixed signal. 9. -7- «On-screen display device, including: * Three mixing and amplifying circuits, each of which supplies each R / G / B channel. And • each receives video signals and OSD signals of individual channels, according to the video selection Signal and OSD selection signal—signal mixed video signal and OSD signal, put too much signal, and output amplified video signal to the display: and 1 selection signal generation circuit to receive R / G / B and channel: ^ eSD , Signal, video / OSD switch, mouse, halftone signal, second predetermined number of OSD windows, __SD control material, and generate PSD selection signal and video selection signal, #output OSD selection 1 signal and video selection signal, Among them, when the 7QSD switching signal indicates the OSD output operation and half of it, please note it first. I The paper size of the edition applies to the Chinese National Standard (CNS) A4 (210 X 297 mm) J -57- Male Labor Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs, A8, B8, C8, D8. During the calculation, the selection signal generating circuit outputs a mid-level video selection signal, so the half-color clever video image # is displayed in a predetermined OSD window, and, where when the signal / OSO switching signal: the number instructs the OSD to output the operation and half-tone signals When instructing non-halftone operation, the selection signal generating circuit outputs a video selection signal with a disabling level and a 0 SD selection signal with an enabling level. Therefore, the OSD background raster with a predetermined color defined by the OSD control signal It is displayed in the OSD window. 10. If you request the on-screen display device in item 9 of the patent scope, wherein the video selection signal and the OS © selection signal are the same single video / OSD selection signal; and each of the mixed # amplifiers (circuits in video / 0 & The D selection signal only amplifies the video signal at the first logic level and outputs the video signal L after the A is put. Among them, the mixing and amplification circuit only amplifies the OSD signal when the video / GSD selection signal is at the second logic level. The amplified OSD signal is output; and each of the mixing and amplifying circuits is based on mixing the video signal and the OSD signal when the | il / OSD selection signal is at the middle logic level to output the amplified mixed signal. 11. An on-screen display device , Which is used to display an image to form a first predetermined number of OSD windows " and to display OSD information and video information in a second predetermined number of OSD windows in a second predetermined number of .OSD windows, including: This paper size applies to China National Standards (CNS) A4 specifications (210X297 mm) C Please read the note on the back before filling in this page > M • -58- Central Government Standards Bureau, Ministry of Economic Affairs Industrial and consumer cooperatives m8 A8 B8 C8 D8 VI. Patent application scope III Hybrid and amplifying circuits, which are seized from the video signals and OSD signals supplied to each R / G / B channel and individually selected for individual services, according to the video selection signal and OSD selection signal mixes video signal and OSD signal, amplifies the mixed signal, and outputs the enlarged image signal to the display, and a selection signal generation circuit is used to receive the 0SD signal of the R / G / B channel, and the video / OSD switch Signals, halftone signals, OSD control signals of the second predetermined number of OSD windows and generation of OSD selection ~ signals and video selection signals, and output of OSD selection signals, including Dangshi® / OSD switching signals indicating OSD When output calculation and halftone brackets indicate halftone calculation, the video signal of this selection signal generating circuit outputs the video selection value > and the OSD selection signal, so the half-tone OSD background raster is displayed on the first half of the halftone video image. Two fixed numbers-OSD window. 12. If you apply for the on-screen display device of the 11th scope of the specialty, the video selection signal and OSD selection signal: the same A video / OSD selection signal; and each of the mixing and amplifying circuits only amplifies the JfL signal and outputs the amplified video signal when the video / OSD selection signal is at the first logic level; where > the mixing and amplifying circuit is The video / OSD selection signal only amplifies the OSD signal at the second logic level and outputs the amplified OSD signal; and the mixing and amplifying circuits of each tablet are in the video and / OSD selection signals. The paper size is based on the Chinese national standard ( CNS) A4 specification (210X297 mm) (Please read the note on the back before filling in this page) Order-59- Printed on the A8 B8 C8 D8 by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs In the middle logic level, the video signal and the OSD signal are mixed and an amplified mixed signal is output. 13. The on-screen display device according to item 12 of the scope of patent application, wherein the second predetermined number of OSD windows include a first window and a second window. The on-screen display device according to item 13 of the scope of 14HP application patent, wherein the selection signal generating circuit includes: a gated signal generating unit for generating a gated signal, which is only used in video / OSD switching signal instruction 0 & D output operation And the halftone signal is excited only when the halftone and tone calculation are performed; a first OSD decision unit is used to receive the gate control signal, the OSD signal of the R / G / B channel, and the OSD control signal of the first window; A first window identification signal is generated, which is only activated when the OSD signal has a first predetermined combination of the OSD control signal corresponding to the first window and the gate control signal is activated; a second OSD decision unit is used to receive The gate control signal, the OSD signal of the R / G / B channel, and the OSD control signal of the second window, and generate the second window type signal. Only the OSD signal has a second TTSD control signal corresponding to the upper window. The predetermined combination and the gate control signal are excited only when they are excited. An OR gate is used to perform an OR operation on the first window identification signal and the second window identification signal. An attenuator is used to receive the output of the OR gate and attenuate the OR gate. Lose To half; an inverter for receiving and inverting the video / OSD switching unit and producing this paper. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the note $ on the back before filling this page) ) Order -60- Yin Ben A8 B8, Shellfish Consumer Cooperative of Central Rubbing Bureau of the Ministry of Economic Affairs _____ ^ _ ㈣Specially listed as a video modal signal, which is only sent when L video signal is waiting for rotation; and An adder uses a chirped attenuator to generate the modal signal and see the result of the addition as a video / OSD selection signal. 15.- If the on-screen display device of the 13th scope of the patent application, which is selected. 'The optional signal generating circuit includes: a gated signal generating unit for generating a gated signal, which is only excited when the oscilloscope / OSD switching signal instructs the OSD output operation and the halftone signal instructs the halftone operation; An OSD decision unit is used to receive the SD signal of the R / G / B channel? And the OSD control signal of the first window, and generate a first window identification signal. Its voice is that the OSD bee really corresponds to the first window. 〇sd control signal first A second OSD determines the thick element to receive, R / G / Bga ^ ^ osD signal, and the SD control signal of the second window, and generates a second window, the identification letter E 'its Only when the OSi > signal has a second predetermined combination corresponding to the second window $ PSD control signal; an OR gate is used to perform an OR operation on the first window identification signal and the second window identification button _ signal; An AND gate is used to perform AND operation on the output of the OR gate and the gate control signal; an attenuator is used to receive the output of the AND gate and attenuate the AND gate < output to half; an inverter is used to receive and invert the video / OSD switching Units and sizes of this paper: CNS A4 size (210X297 mm) (Please read the note on the back before filling this page) Order · C8 -------- -2! _ 、 In the lifetime of applying for a patent shed, the video mode is “money,” which is only excited when the video is waiting to be output; and the adder is used to add the output of the attenuator to the video chess signal into a round ir addition result as a video / 〇SD select signal. For example, the on-screen display device according to item 13 of the patent application scope, wherein the selection signal generating circuit includes: 10SI) the first gate selector is used to receive the 0SD signal of the R / G / B channel, and the first and second windows are 〇81 > a control signal, and generating at least one raster selection signal, the logic combination of which has an OSD control signal corresponding to the first window or a SD control signal of the first visual education is enabled; and half-tone The signal generator is used to receive the raster selection signal, the video / OSD switching signal and the halftone signal, and perform operations at the video / 0 magic ^ switching signal instruction QSD input, and the halftone signal instruction halftone output operation, and the raster selection signal. An intermediate-level video / OSD selection signal is generated only when at least one signal is enabled. 17. For example, the on-screen display device of claim 16 in the scope of patent application, wherein the QSD grating selector includes: a first comparison circuit for generating a first grating selection signal, which corresponds to the first window of the OSD signal The logic combination of the 0sd control signal is enabled; and a second comparison circuit is used to generate a second raster selection signal, which is caused when the OSD signal has a logic combination of the 0SD control signal corresponding to the second window. Yes, the size of this paper is applicable to China's National Standards (CNS) A4 (210X297 mm) (please read the note on the back and fill in pages I-βII). 62- A8 B8 C8 D8 6. The scope of patent application where the halftone signal generator is connected to the first raster selection signal or the second raster C selection signal is enabled and the Jii medium-level video / OSD selection signal is input. 18. For example, the on-screen display device of the 16th scope of the patent application, wherein the selection signal generating circuit further includes: a video / OSD switching unit for receiving a video JOSD cut signal and generating at least one switching signal, which responds to the video / OSD The switching mega-signal switching has a phase < opposite to that of the video / OSD switching signal, wherein the halftone signal generator receives a switching signal from the video / OSD switching unit. 19. For example, the on-screen display device of the scope of application for patent No. 18, wherein the video m / osa switching unit generates a #: test electronic ink, which is used by the mixing and amplification circuit to determine the level of the video / OSD selection signal. 20. The on-screen display device according to item 16 of the patent application scope, wherein the selection signal generating circuit further includes: an interface buffer for receiving and buffering the first and second windows t OSD control signals and halftone signals to improve OSD control The current drive capability of the signal and the f-tone signal, wherein the QSD grating selector receives the OSD control signal and the halftone signal whose current drive capability is improved by the interface buffer. This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) * Λ Please read the note on the back before printing on this page Order by the Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs -63-