TW382805B - Method and apparatus for synchronous memory access with separate memory banks and with memory banks divided into column independent sections - Google Patents

Abstract

A synchronous memory device is provided in which a timing and control circuit (28) receives timing and control inputs. A row address buffer (38) and row decoders (40 and 42) operate to enable rows in plural memory sections (30, 32, 34, and 36). Column decoders (58, 60, 62, and 64) operate to enable columns in each of the memory sections (respectively, 32, 36, 30 and 34). The column decoders (58, 60, 62, and 64) decode addresses received from counters (respectively 52, 54, 48, and 50), an adder (46), and a latch (56). Counters (48, 50, 52, and 54) and adder (46) allow for prefetching of data from each of the memory sections, thereby allowing for internal operation at less than the external system frequency. An output buffer (78) alternately selects data from the plural memory sections (30, 32, 34, and 36) for output in synchronism with the system clock.

Description

Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative Α7 Β7 V. Description of Invention (1) Cross-references to relevant applications

This case is a pending application for which all of the following have been assigned to Texas Instruments — Incorporated and incorporated by reference into this case: US Patent Application filed on January 1994, named " A CLOCK CONTROL CIRCUIT ARRANGEMENT " _ __________, attorney's case number TI-18272; filed on January 1994, named " METHOD AND APPARATUS FOR WRITING DATA IN A SYNCHRONOUS MEMORY " HAVING COLUMN INDEPENDENT SECTIONS AND A METHOD AND APPARATUS FOR PERFORMING WRITE MASH OPERATIONS " Patent Application No. __________, Lawyer's Case No. TI-18278; Filed in January 1994, the name is " METHOD AND APPARATUS FOR RECONFIGURING A SYNCHRONOUS MEMORY DEVICE AS AN ASYNCHRONOUS MEMORY DEVICE " Lawyer case number TI-18276; filed in January 1994, named "METHOD AND APPARATU FOR PRODUCTION TESTING OF SELF-REFRESH OPERATIONS AND A PARTICULAR APPLICATION TO SYNCHRONOUS MEMORY DEVICES", US patent application number __________, lawyer case number TI-18277; January 1994

The Japanese Patent Application No. _________ and Lawyer's Case No. Γ-18291, entitled "METHOD AND APPARATUS FOR PREVENTING INVALID OPERATING MODES AND AN APPLICATION TO SYNCHRONOUS MEMORY DEVICES", are proposed on this paper. The size of this paper applies the Chinese National Standard (CNS) Λ4 specification (210 × 297 mm) -------- 丄 / 衣 -------- Order ------ {丨 (Please read the notes on the back before filling this page) A7 _ B7 — _ V. Description of the invention (2) Technology of the invention 镅 迠 The invention summarizes the field of electronic components, especially a method and device for synchronous memory access. BACKGROUND OF THE INVENTION The basic structure of most data processing systems today includes A digital processor and random access memory. For economic reasons, random access memory (referred to as " RAM ") is often dynamic random access memory:-(dynamic random access memory, referred to as "; DRAM "). The general operating frequency of asynchronous DRAM is in the range of 33 MHz. For system clock pulse rates higher than this range, DRAM becomes a forced processor and other components waiting for memory Take the bottle 珲 〇 more expensive memory, such as static random access memory (Static random access memory (referred to as "SRAM1 '), electrically erasable programmable read-only memory" (electrically erasable programmable read-only memory & gt (Referred to as "EEPROtT"), other programmable read only memory (referred to as "PROM1 ·") and read-only memory (referred to as "ROM"), there are also similar problems. It has been suggested that synchronous dynamic random access memory (synchronous consumer cooperation with the Central Bureau of Standards of the Ministry of Economic Affairs. Printed by the agency --------- < policy-(Please read the precautions on the back before filling out this (Page) dynamic random access memory, (" SDRAM ") for better use of inherent DRAM bandwidth. With synchronous DRAM, data is clocked in and out of memory cells at a higher rate. For example, a synchronous DRAM using a pipeline structure MHz speed operation. However, the pipeline method has significant limitations that may prevent operation at speeds above 100 MHz. Using the pipeline method, the internal access path is divided into several stages. ’Each stage is (CNS) Λ4 (210x 297 cm) A7 at the edge of each clock pulse.

New data is updated. 0- After accessing the first data bit (or byte), the mother-clock pulse cycle can access the remaining bits. However, each reading is limited by the time it takes to sense and output the data. Currently, this operation takes about nanoseconds, and the pipeline method cannot do so at a speed greater than 100 MHz. Also, because of the complex timing requirements of various components, such as sense amplifiers, and inherent operating speed limitations, high-speed internal operation is often difficult and expensive in any synchronous design.

Therefore, there is a need for a synchronous memory capable of operating at high system speeds, such as up to and above 100 MHz. According to the purpose of the present invention, a synchronous memory access method and device having an individual memory bank and a memory bank divided into sections are provided, which actually eliminate or reduce various disadvantages and problems associated with the previous synchronous memory. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, T Bayong Consumer Cooperative (please read the notes on the back before filling out this page),-= * The present invention provides a memory for storing data, in which the timing and control circuit can operate the receiving bit Address and control input, one of the control input is a system clock pulse operating at the system frequency. The synchronous memory element includes a memory bank divided into a plurality of memory sections, each of which includes a memory cell array arranged in rows and columns. A row of decoders is consumed by the timing and control circuits and is operable to activate the rows in each memory segment. The one-line decoder is operable to cause the lines in each memory segment to be started simultaneously and virtually simultaneously. An output buffer is coupled to the memory bank, and actually receives data from each memory segment at the same time, and outputs data alternately from each memory segment in synchronization with the system frequency. The invention also discloses a synchronous memory element for storing data. The paper size of the package is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X 297 mm) A7 B7 " ~ ---- ------ 5 2. Description of the invention (4) Including two memory banks. This memory element includes a timing and control circuit for receiving addresses and control inputs. One of the control inputs is a system clock pulse operating at a system frequency. The two memory banks are divided into a plurality of memory sections, each of which includes an array of memory cells arranged in rows and columns. The present invention also provides a two-column decoder, a demamarizer associated with a separate memory bank for activating the columns in each associated memory segment. Similarly, the present invention provides a two-line decoder, and a decoder is associated with a different memory bank to actually simultaneously start the rows in each memory section simultaneously. Furthermore, the present invention provides an output buffer to receive data from each memory segment at the same time, and output data from each memory segment alternately in synchronization with the system frequency. The above-mentioned output buffer includes a first latch stage 'coupled to the memory sections and a second latch stage which is consumed to the first latch and is operable to output data from the memory element. Each of the latch stages is operable to access several bits of data output by all memory sectors at a time. The present invention provides a data circuit to control the second latch stage so that data from each memory sector The data is output alternately from the memory element. · Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs --------- 1 clothing-(Please read the precautions on the back before filling this page) The present invention also provides a method for accessing memory elements. Method, in which the address is received and the control is turned on, one of the control inputs is a system clock pulse operating at the system rate. Responsive to address and control inputs, predetermined columns are activated in many memory sections. Furthermore, in response to the address and control input, the scheduled actions are actually started simultaneously in each of the many memory sectors simultaneously. Then, the data is actually received from each of the memory sections at the same time, and the self-memory elements are alternately output in synchronization with the system frequency. An important technical advantage of the present invention is the memory cell array of the memory element-6-'National Standards of this Paper Standard Phase. (0 called 8-4 specification (210/297 mm)'-Central Standard of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Bureau A7 B7 V. Description of the invention (5) The columns are divided into row-independent memory sections. Actually accessing each memory section at the same time generates a prefetch operation and can output data at the system frequency. At the same time The η memory sector operates internally at a 1 / n system frequency. An important technical advantage of dividing the memory array into row-independent sectors is that the row access time is hidden by the simultaneous access of all the hundred million sectors. Another important technical advantage of the present invention is that the memory array can be divided into two independent banks. The memory array can be divided into independent banks, each of which is further divided into a row-independent memory section, which can be used to alternate between banks. To access and hide the pre-charging time of the bit line of each memory bank. Brief description of the drawings In order to fully understand the present invention and its many advantages, please refer to the following description and consider the accompanying drawings, in which the same parameters The numbers indicate the same components, in the drawings: Figure 1 illustrates a block diagram of a digital processing system including a digital processor and synchronous DRAM; Figure 2 illustrates a block diagram of a synchronous DRAM according to the purpose of the present invention; Figure 3 illustrates Figure 4 illustrates a block diagram of a specific memory cell and 1/0 circuit according to the spirit of the present invention; Figure 5 illustrates not-a synchronous DRAM according to the spirit of the present invention, which Block diagram of a specific memory segment; for synchronizing according to the purpose of the present invention, its read burst operation Figure 7 is for a synchronous DRAM according to the purpose of the present invention, which writes X burst operation (please read the precautions on the back before (Fill in this page) -0

• I- I ..--I I I i I--I Λ4 specifications (

1. Description of the invention (6) Timing chart made; Figure 8 is a timing chart for the burst operation according to the purpose of the present invention; 'Synchronous DRAM, its write / read pulses Figure 9 is for the purpose of the present invention, Timing of read / write operation_ &lt; Synchronous DRAM with automatic revocation Fig. 10 is a timing diagram for the operation of the purpose of the present invention, and out; Synchronous DRAM, whose two banks are crossed and read, Fig. 11 is for the present invention The purpose is to determine the 2 bank column cross read operation = step_, which has automatic undo. Figure 12 is for the purpose of the present invention, ^ X \ s./u, &lt; synchronous dram, which reads from a bank. And a timing diagram of a write operation to another bank; and FIG. 13 is a diagram for the purpose of the present invention, Λ 葸 <问 步 卯 AM, which has automatic undo (determining the operation of a bank writer and self-bank read operation) _; Detailed description of the invention The present invention will be discussed in conjunction with a memory element using a coffee unit. However, the concepts discussed in this case are also applicable to SRAM, EEPROM, pROM, ROM, and other memory elements. 1 Figure 1 illustrates a block diagram of a data processing system 10. The data processing system 10 includes an address sink The bus 16, the data bus 18 and the control bus 20 are connected to the digital processor 12 of the synchronous DRAM. The system clock 22 is connected to the digital processor 12 and the synchronous DRAM 14 through a lead 24. Input / output (&quot; I / O &quot; The component 26 is also connected to the digital processor 12 via buses 16, 18 and 20. The component 26 is also connected to the system clock 22 via the lead 24. The I / O component 26 may, for example, include a peripheral device such as a disc Controller, or one allowed with this week --------- * 'i clothing ------ order ------ wide (Please read the precautions on the back before filling this page) Economy The paper standard printed by the Ministry of Standards and Technology Bureau Shellfish Consumer Cooperative Co., Ltd. This paper is printed in accordance with Chinese national standards ((:! ^) 6 4 specifications (210 '/ 297) # &gt; 28 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs The inputs are listed in Table 1 below and will be discussed in conjunction with Figure 2 and the remaining figures.

A7 __; _____ B7 V. Description of the Invention (7) Device for connecting side devices. Data transfers read from or written to the synchronous DRAM 14 pass through the data bus 18. The reading and writing of data is controlled by the control signal transmitted through the control bus 20 and the address position of the wheel passed through the address bus 16. The address generally includes a row of addresses and a row of addresses. The address and control signals may be generated by the digital processor 12 or by a memory controller. The system clock 22 times the operation of the digital processor 12 and the synchronous DRAM 14. Crossing the bus ~ 16 ′ 18 ′ and 20 respectively transmit the address ‘data’ and control signals to the timing synchronous input DRAM 14 and output the data from the timing synchronous DRAM 14 regularly. Therefore, the operation of the 'synchronous DRAM 14 is synchronized with the system clock 22 and thus with the digital processor 12. Please understand that the clock number used to synchronize the timing of the DRAM 14 can be obtained from the system clock 22. For example, the digital processor I can output a clock obtained from the system clock 22 and can be used to clock the operation of the synchronous dram 14. Signal. The block diagram of Figure 1 illustrates a digital processor and a synchronous. Abdominal belly-a possible configuration. With this configuration, a significant difference in memory access can be achieved in a system using a standard isochronous tilt. The speed increases. Figure 2 is a block diagram of a synchronous DRAM 14 constructed in accordance with the purpose of the present invention. The timing and control circuit 28 receives several inputs and generates a number of internal signals for controlling and timing the synchronous DRAM circuit. Timing and Control circuit-I I.-----m! 1 -1-m I 1: 1 n — 1. T f Please read the notes on the back before filling in this page j Λ7 Β7 V. Description of the invention (8) Table 1 Input descriptions Α0-Α10 address rotation All library selection W write enable CAS row address strobe RAS column address strobe CS chip selection DQM data / output enable CLK system clock. CKE clock enable D0-D7 data input乂 / output (please first Read the notes on the back and fill out this page again.} _ _ _ 1T The Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed that the input signal CLK is a system clock that operates at the system frequency. The system frequency is the cycle rate of the CLK signal. Please understand The specific input signals listed in the table above are just examples. Other signals can be used without departing from the predetermined range of the present invention. For example, the 12-address input shown in the figure allows time-multiplexed row and column addresses to be received. You can use different numbers of address lines to allow row and column addresses to be received together. You can also use a memory element with more or less space, or use a different array of memory arrays to use more or less Also, although the 8 data lines are shown, more or less data lines can be used without departing from the predetermined scope of the present invention. The synchronous DRAM 14 can be advantageously operated in a burst mode. In the burst mode -10-This paper size is in accordance with Chinese National Standard (CNS) Λ4 specification (210 × 297 Gongchu) A7 B7 Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Data is written or read in bursts of a specific length. Within each pulse, the data is cyclically accessed every clock, thus providing high-speed synchronous operation. In a particular embodiment, the length of each burst sequence can be 2 4 or 8 accesses ', however, longer bursts can be used without departing from the invention. Therefore,' for example, using a component that rotates in or out of δ bits (one byte at a time) can Read or write L 2, 4, or 8 bytes in a burst. In this burst, each byte follows the previous byte ^ without a clock delay between them. ~ In burst operation, data can be read or written sequentially or alternately. Sequential or alternating refers to the order of the logical bit it locations accessed. The burst length and burst type (that is, sequential or alternating) are user-programmable and stored in a mode register 29 in the timing and control circuit 28. In a specific embodiment, after entering the programming mode, the burst length and burst type data can be received through the address line. The memory cell array in the synchronous DRAM is divided into two banks, bank A and bank B as shown in FIG. Furthermore, each memory bank is divided into n select sections. As shown in FIG. 2, bank A is divided into sections 30 to 32. Similarly, bank β is divided into sections 34 to 36. The present invention will be discussed in conjunction with an embodiment in which each memory bank is divided into two sections, but please understand that each memory bank can be divided into many more sections. In bank A, the rows of section 30 are not related to the rows of section 32. Therefore, each section can be accessed separately. So sections 30 and 32 are said to be "line-independent". For example, in a specific embodiment, each section contains 4,096 columns and 1,024 rows, two columns in each section are addressed by one, and the column address is addressed ', and four rows in each section are addressed by one row. Address. Therefore, in this specific example, only one line and -11-this paper is applicable _Jiaxian (CNS) Α4 specifications (2 丨 GX297) Chu --------ί -------- order ( Please read the precautions on the back before filling in this page) A 7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of Invention (10.) A row of addresses accesses 8 bits from each sector. In this embodiment, the twelve address bits are used for column addresses. One of the twelve bits selects the memory bank, and the other twelve bits select two columns in each sector. Furthermore, the nine address bits are used for the row address. One of the nine bits selects the memory section, and the other eight bits select four rows in one section. Operating synchronous DRAM 14 internally at an i / n external system frequency provides a significant advantage because higher-speed internal operations are more complex and expensive. For example, dividing bank A into sectors 30 and 32 'can read data from each sector at a half external rate, and output data from synchronous DRAM 14 at the rate of an external system clock. This is achieved by accessing a memory location from one sector and simultaneously accessing a next location from another sector. So, for example, in the case of an external system frequency of 100 MHz, when using the second sector, each sector must be operated at 50 MHz. To access the synchronous DRAM 14, regardless of whether it is read or write, enter the address A0-A11 at the address to receive the column address and latch it in the column when the rising edge of the tile signal and CL1U signal is activated in the correct way The address buffer is secured. The output of the column address buffer 38 is an internal column address. As discussed above, row and column addresses can be time multiplexed, and in certain instances, the column addresses are received first. The bank select (BANK SELECT) signal corresponding to the column address input All can be used to select the memory bank by activating the column decoders 40 and 42. The column decoder 40 decodes the column address of bank A, and the column decoder 42 decodes the column address of bank B. The BANK SELECT signal is generated by the timing and control circuit 28. In a specific embodiment, the BANK SELECT signal is generated in response to the MB input signal and the column address input All. (Please read the notes on the back before filling out this page) 袈,? Τ This paper size is applicable to China National Standard (CNS) A4 (21 () x 297g t) Economical; Printed by members of the Central Standards Bureau, Consumer Cooperation A7 _________B7 V. Description of the Invention (11.) ~~~~~ The column decoder 40 decodes the column addresses of the sector 30 and the sector 32 of the bank A, so the columns in each memory sector are activated. Similarly, the row decoder 42 decodes the row addresses of sectors 34 and 36 of bank B. In a particular embodiment, each sector of a particular bank is logically identical, and the same columns of each sector are decoded simultaneously. Please understand that individual decoders can be used for each sector of a particular bank without departing from the intended scope of the invention. -The following discusses the circuit that controls the operation of each row of a particular bank's unrelated sections. This row of decoder circuits is operable to actually start the rows in each memory segment simultaneously and simultaneously. The row address buffer 44 latches the row address received at the address input when the rising edge of the CAS signal and the CLK signal is activated in the correct manner. The output of the row address buffer 44 is an internal row address. The internal row address bits will be called CAO-CAn. For the specific embodiment in which each memory bank is divided into two sections as shown, the row address bit CA0 is used to select sections 30 and 32 of bank A and sections 34 and 36 of bank B. In embodiments where many sectors are used, more row address inputs will be required to select between sectors. For example, in the embodiment with four sectors, two rows of address bits CA0 and CA1 will be used

I Select each section. The lower-order row address bits CA1 and CA2 are input to an adder 46. Depending on the row address bit CA0 ', the adder 46 adds 1 or 0 to these lower order bits. If CA0 = 1, the adder 46 adds 1; if CA0 = 0, the adder 46 adds 0. The output of adder 46 is coupled to the inputs of counters 48 and 50. The counter 48 is connected to the sector 30 of bank A, and the counter 50 is connected to the sector of bank B. The lower order column address bits CA1 and CA2 are also directly coupled to the counters 52 and 54. Counter 52 is connected to section 32 of bank a, and counter 54 and section 36 of bank B are based on the Chinese paper standard (&lt;: ~ 5), 8 specifications (210 &gt; &lt; 297 feet) I —. 1— 1----«-1---....... 4-III— II. (Please read the notes on the back before filling out this page) A7 A7 Employees of the Central Bureau of Standards, Ministry of Economic Affairs Consumption cooperation, printed by the society B7 V. Invention description (12.) Company. In the particular embodiment in question, the lower-order row address bits input to the pulsers 48, 50, 52, and 54 directly or through the adder 46 are the row address bits CA1 and CA2. These two bits, together with the row address bit CA0, allow counting up to eight. Using the gland burst length sequence discussed in Tables 2 to 4, there is no carry or overflow bit from adder 46. Counters 48-54 load the initial row address data synchronously when the LOAD signal is activated. The LOAD signal is output by the timing and control circuit 28. After that ~ it depends on the state of the MODE signal input to each counter based on the pulse train type state stored in the mode register 29, and the counters 48-54 count in a sequential or alternating manner. Counting is controlled synchronously by a C0UNt (count) signal based on the burst data stored in the mode register 29. In operation, the COUNT signal operates at 1 / n external system class rate. The higher-order row address bits CA3-CA8 are input to the lock 'register 56 and latched when the LOAD signal is activated. The latch 56 is coupled to the row decoder 58 and ⑼. The row decoder 58 is connected to the sector 32 of bank A, and the row decoder 60 is connected to the sector 36 of bank B. The row decoder 58 is combined to the decoder 62 connected to the sector 30 of the production bank a. Similarly, the row decoder 60 is coupled to a row decoder 64 connected to the sector 34 of bank B. Each line of decoder 58_64 is coupled to an ENABLE signal. A decoder 58 is coupled to the output of the counter 52. Similarly, the column decoder 60 is coupled to the output of the counter 54. The row decoder 62 is coupled to the output of the counter 48. Similarly, when the row decoder 64 is coupled to the output of the counter 50, the BANK SEECT signal is activated when a particular embodiment of the 6-inch theory operates—a specific library. The following discussion is in conjunction with the launch of library A. Please understand that library B uses the -14-sheet scale (CNS) A4 specification {21〇 &gt; &lt; 297 mm) n I 1------ policy- — I-II-Order (please read the notes on the back before filling this page) A7 B7 Consumption cooperation between employees of the Central Standards Bureau of the Ministry of Economic Affairs. Printed by the company V. Invention description (B. Operation in a similar manner. The column decoder 40 will Decoding of fields in segments 30 and 32. When the rising edges of the CAS and CLK signals are activated, the row address buffer 44 stores the column address. This row address is the starting address and will be used to generate All other row addresses required to complete a burst operation. To achieve high-speed operation, the present invention accesses the start address from the hundreds of millions of sectors corresponding to the start address and simultaneously accesses the pulse from another sector The sequence is followed by a single address. This process is repeated until the burst is completed. Simultaneous access to more than one sector will experience the delay associated with row address decoding in parallel rather than in series, and thus hide the simultaneous access row Access time. These accesses are generally about 30 nanoseconds long. Furthermore, there are two banks, which alternate between the two banks. Take, avoid the delay associated with precharging the bit line, because one bank can be precharged when accessing another bank. Row address bits CA1 and CA2 are loaded into counter 52. Incremented by adder 46 The two bits of quantity 0 or 1 are loaded into counter 48. Row decoder 58 decodes the appropriate column in response to the addresses received through counters 48 and 52 and latch 56. To reduce redundant circuits, The row decoder 58 is produced by decoding the higher-order address bits received by the latch 56 and generates decoded higher-order factors for itself and for the row decoder 62. These higher-order factors are transmitted from the decoder 58 to the decoder 62. Therefore, the counter 52 is loaded with the initial address bit, and the counter 48 is loaded with the same bit incremented by 0 or 1 by the adder 46. If the starting row address is in sector 30 (ie, CA0 = 0) ' The adder 46 will add 0 because the sub-position (ie, CA0 = 1) is in section 32, and CA1 and CA2 are unchanged. If the address of the envy row is in section 32 (ie, CA0 = 1) ' The adder 46 will be increased by 1, because -15-this paper size is suitable for China National Standard (CNS) A4 size (210X 297 mm 1 I- -ili i (mf ^ ^^^ 1 1--— ^ n mu — ^ ϋ HH 、 一 (Please read the precautions on the back before filling out this page) A7 _____B7 V. Description of the Invention (w.) ~~~ The next position (that is, CA0 = 1) is in section 32, and CA1 and CA2 are unchanged. If the starting row address is in section 32 · (also That is, CA0 = 1), the addition 囍 will increase by 1 because the next position (that is, CAO = 〇) is in section 30, and CA1 and CA2 are incremented by 1. These initial address bits are loaded into the counters 52 and 48 when the load signal is activated, and then decoded by the decoders 58 and 62 together with the bits output by the latch 56. The latch 56 sets the bits when the LOAD signal is activated CA3- CA8 are latched. The first two addresses of a burst are accessed in this way. In the next internal loop, the COUNT signal is started, and the counters 48 and 52 count according to the state of the MODE signal. Therefore, it is the same as the internal clock frequency. Address access. Depending on the MODE signal, counters 48 and 52 will count sequentially or alternately. Counting continues in synchronization with the internal clock frequency until the burst operation is complete. The ENABLE signal will activate each row of decoders 58 and 62 during a • or write operation. »Once the burst operation is completed, the rows of decoders and column decoders will be aborted, allowing the memory section to be recharged for the next time. The logical memory space of operation 0 segments 30 and 32 is arranged so that consecutive memory locations are staggered between segments 30 and 32. For sequential access, memory locations are sequenced according to this logical arrangement. For alternate access, the memory locations are still alternately sequenced from sector 30 to sector 32 and back again, but according to an alternation routine. The following lists 2 to 4 illustrate the internal row addresses generated by the adder 46 and the counters 48 and 52 for accessing the memory locations of burst lengths 2, 4, and 8. Please understand that the memory sections 30 and 32 are accessed simultaneously, so the first and second settings are accessed simultaneously, the third and fourth, the fifth and sixth, and the first --- --A 麦 ------ Order (Please read the notes on the back before filling out this page) This paper size applies to China National Standards (CNS) (210 ^ 297 ^ 7 A7 __B7 V. Description of the invention (丨5.) The same is true for the seventh and eighth positions. Table 2 Internal row address CA0 of the sequence of burst length 2 Start 2nd order 0 -1 1 0 Alternating 0 1 1 0 Table 3 Sequence of burst length 4 central Standard Bureau employee consumer cooperative prints internal bank address CA1, CA0 starting 2nd 3rd 4 00 01 10 11 sequence 01 10 11 · 00 10 11 00 1 01 11 00 01 10 00 01 10 11 alternating 01 00 11 10 10 11 00 01 11 10 01 00 -17---------- I Packing ------- Order (Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS) A4 specification (2 丨 0X 297 mm) A7 _____B7 'Explanation of the invention (l6.) 4 Sequence of burst length 8 5 The Ministry of Economic Affairs Central Standard Bureau employee consumer cooperative prints the internal bank Addresses CA2, CA1, CA0 Start 2nd 3rd 4th 5th 6th 7th 8 000 001 010 011 100 101 110 111 001 010 011 100 101 110 111 000 010 011 100 101 110- 111 000 001 Sequence 011 100 101 110 111 000 001 010: 100 101 110 111 000 001 010 011 101 110 111 000 001 010 011 100 110 111 000 001 010 011 100 101 111 000 001 010 011 100 101 110 000 001 010 011 100 101 110 111 001 000 011 010 101 100 111 110 010 011 000 001 110 111 100 101 Alternate 011 010 001 000 111 110 101 100 100 101 110 111 000 001 * 010 011 101 100 111 110 001 000 011 010 110 111 100 101 010 011 000 001 111 110 101 100 011 010 001 000 As can be seen from the tables, the data is sequenced alternately between the memory sections 30 and 32, regardless of the burst type. The internal row address bits CA1 and CA2 shown in the tables are controlled by an adder 46 and counters 48 and 52. The first two addresses accessed during any burst period are the start address and the adder. 46 This paper size is applicable to the Chinese National Standard (CNS) M specification (2IOX 297 cm) A7 B7 V. Description of the invention ( Π. Determined. All other addresses are determined by counters 48 and 52. The internal row address bits CAO are used to determine which memory segment contains the first access location for a burst operation. Counters 48-54 and adders 46 determines the subsequent memory locations, and the two sectors are accessed simultaneously. Therefore, the CAO does not change until another burst operation is started. For clarity, the above list 2 ~ 4 indicates that the CAO is changed, and it is only an example for each memory. Take the logical order of the positions. In a specific embodiment, each row of addresses accesses 8 bits, and each internal clock cycle outputs 8 bits from each sector. Therefore, each internal clock cycle outputs a total of 16 bits The element-to-output buffer, which will be discussed below. The specific embodiment discussed includes two sections of each bank. However, many more sections are available. For embodiments with n sections Will include η-1 adder There is no adder in the nth memory segment '. The adders will add the appropriate address bits between 0 and 1, and then load the result into the associated counter. Each of the n segments will go directly from the appropriate row The address line gives its own counter through the associated adder library. The starting address determines the amount added by each adder. For example, for the starting address in memory segment χ, for l &lt; x <ri In terms of 'adders related to memory sections X to n- 丨, the consumption cooperation of the Central Standards Bureau of the Ministry of Economic Affairs will be printed and printed zero', while adders related to memory sections 1 to x-1 will It will add 1. The adder associated with the memory segment containing the starting address always adds zero. As far as the ^ memory segment is concerned, it will be initially loaded with people, and then the π bit of the -burst Figure 2 illustrates the use of η ,,,, = between the sections of the shirt. · The symbol * illustrates the synchronous response formed according to the purpose of the present invention. Its rotation / -19-Central Standard of the Ministry of Economic Affairs A7 B7 printed by the Bureau of Work and Consumer Cooperatives V. Description of the invention (丨 8.) Block diagram of the circuit of rotation. The memory area is divided into η areas Each includes m buffers. Therefore, buffers 70-72 are provided to receive output data and transfer the input data to sector 1 of banks A and B. Buffer 70 transmits internal data bit D0, and buffer 72 The transmitted data bits Dm-1 are all for sector 1. Regarding Figure 2 'buffers 70 and 72 will transmit and receive data to and from sectors 30 and 34 of banks A and B, respectively. Similarly, the buffers 74 and 76 transmit data bits D0 and Dm-1 to section n of bank A and b. In conjunction with the specific embodiment discussed in FIG. 2 'buffer 74 and 76 transmit data to regions of bank A and B Segments 32 and 36, and receive data from them. For embodiments using more than two segments per bank, each segment will provide a set of buffers. Buffers 70-76 use the BANK SELECT signal to select between banks. The data read from the synchronous DRAM 14 is output through an output buffer 78. The output buffer 78 can operate to receive data from the memory sections of a bank at the same time, and output data from the memory sections alternately in synchronization with the system frequency. The output buffer 78 is a secondary buffer that allows data to be read at an external clock frequency. The assets from each of the buffers 70-76 are latched to the first latch stage of the output buffer 78. The first latch stage includes a latch for each of the buffers 70-76. Therefore, for the m-bit and n-divided banks, there are 111 &gt; &lt; 11 latches in the first stage of the output buffer 78. In the particular embodiment in which each bank has 8 bits and two sectors, the first stage of the output buffer 78 includes 16 latches &apos; Specifically, T, the latch 80 receives data from the buffer 70, and the latch receives data from the buffer 74. Latch 84 receives data &apos; from buffer 72 and latch 86 receives data from buffer 76 &apos;. -20-CNS) Λ4 is now ((Please read the precautions on the back before filling this page)

， 1T Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7-----_______________ B7 V. Description of the Invention (19.) ~~~~ — ~-The data to be read out is latched in latch ㈣6 according to _Α_. The DL0AD1 signal is generated by the read latch control circuit 88. The readout latch control circuit 88 outputs data at a timing based on the timing and the ακ〇ϋτ signal generated by the control circuit 28. The frequency of the CUOUT signal is equal to the external system clock frequency. For the embodiment where there are two sections per memory bank, when the DLOAD1 signal is active, the DLOAD1 signal is generated at 1/2 of the external system clock frequency based on the CAS latency data stored as a code in the mode register 29. . ^ Wait ~ Time is user programmable and determines the number of clock cycles that occur between the request ^ signal and the effective output signal. The readout latch circuit 88 also generates DLOAD2k, which latches data from the first latch stage of the output buffer 78 to the first latch 鈒. The second latch stage of the output buffer 78 includes latches 90-96. The second latch stage includes one latch per latch in the first latch stage. A data switching circuit 98 selects the order in which data is output to the output data lines. For the particular embodiment where each bank is divided into two sectors, the data switching circuit 98 alternates between latches associated with each sector of the two sectors. Therefore, the data switching circuit 98 outputs its switching signal based on the CLKOUT signal and a single input, bit CA0 of the row address. CA0 selects the order in which data will be output from the two sections 30 and 32 of bank A and the sections 34 and 36 of bank B. The data switching circuit 98 will cause the data in the second latch stage associated with each memory sector to be output alternately. Once all data has been output, the first latch stage of the DL0AD2 signal is required to load new data. In the embodiment where each memory bank is divided into more than two sections, the data switching circuit 98 will receive enough input signals selected in each section for outputting data. Therefore, the actual paper size of the output buffer 78 applies to the Chinese National Standard (CNS) Λ4 specification (210 X 297 mm) f Please read the notes on the back 呗 then fill in {sf page ”'ST. Λ7 Λ7 V, B7 Description of the invention (20t) Simultaneously receive data from each memory section of a memory bank, and output data alternately from each of these memory sections in synchronization with the system frequency ο-Input the data to the synchronous DRAM 14 through the input The buffer 100 is rotated. The round-in buffer 100 includes latches 102-108. The number of latches in the input buffer 100 is the same as the number of latches in any stage of the output buffer 78. The write latch circuit 110 receives the clock signal 1 at the system frequency and the row address bit CA0 to select which of the latches 102-108 is to receive-receive the data received at the data bus at a specific time. A multiplexer 112 may also be included in the turn-out stage to periodically rotate data in or out one bit at a time in a sequential manner for appropriate applications, such as video applications. FIG. 4 illustrates a block diagram of a representative memory unit and its connection to the input / output circuit shown in FIG. 3. As shown in FIG. 4, a memory cell includes a transistor 120 and a capacitor 122 for storing electric charge. The gate of transistor 120 is connected to word line 124. Many other memory cells will also be connected to word line I24. The transistor 120 transfers charge between the capacitor 122 and the bit line 126 under the control of the word line 124. Many other memory cells are also connected to the bit lines by different transistors controlled by different word lines. Word line 124-When activated, the sense amplifier 128 senses and amplifies the charge difference between the bit line 126 and the reference bit line 130. Once the row decoder selects the bit line 126 ', it activates the gamma selection signal and turns on the bypass gate transistors 132 and 134, thereby allowing data to be output to the output buffer 138 during a read operation. The output buffer 138 corresponds to the buffers 70-76 and 78 of FIG. For the write operation, the data is received from the data bus to the buffer 7070 in the paper as shown in Figure 3. _ — m In ti-I n----χ · Take 1 ---- -· Ϊ-— —--------- 1! -I: --- I--I 1 ^ 1 HI 〆 {Please read the notes on the back first to fill in this fo staff of the Central Standards Bureau of the Ministry of Economic Affairs Consumption Cooperative Print 22-Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 ______ B7 V. Description of the Invention (2L) A ~~~~~~ and 100 corresponding input buffers 140, and then pass from the input buffer 140 Turn to drive amplifier 136. The driver amplifier 136 then drives the bit line 126 by bypassing the close-transistor 134 to write appropriate data into the memory cell. The driver amplifier 136 is a dual driver that drives a bit line or an output buffer according to a required write or read operation. FIG. 5 illustrates a specific embodiment of a bank and a sector of the synchronous DRAM 14. As shown in FIG. The particular section in question is section 30. As shown in FIG. 5, the zone-segment 30 is divided into blocks 150 and 152 β. Each block includes one-half the number of columns of the entire section 30 and can be regarded as a duplicate address space. Therefore, in a special case, each block includes 2048 columns. The row decoder 62 decodes the appropriate rows of each block and allows reading or writing by the sensing and driving circuits 154 and 156. Each of the sense and drive circuits 154 and 156 corresponds to the sense amplifier 128 and the driver amplifier 136 of FIG. 4. The data output from or input to blocks 150 and 152 passes through input and output buffers 138 and 140. For an m-bit element, m / 2 bits are read from or written to block 150, and m / 2 bits are read from or written to block 152.

I In a particular embodiment of the synchronous DRAM 14 input and output 8-bit data, the column decoder 40 will decode one column at each of blocks 150 and 152. The line decoder 62 will decode 4 lines at each block 150 and 152. Therefore, 4 bits are accessed from each of 150 and 152, and a total of 8 bits are accessed in a specific section of a bank. Please understand that the division of a specific section into two repeated blocks is merely an example, and other arrangements of the specific memory section can be used without departing from the intended scope of the present invention. For example, a memory section need not be divided into separate blocks or may be divided into more than the number shown in FIG. -23-This paper scale towel making materials (CNS) Λ4 specification (2 丨 (Please read the precautions on the back before filling this page)

1T 1. Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7. B7 V. Description of the Invention (22) Figure 6-10 is a timing chart of various operations of the synchronous DRAM 14. These timing diagrams show that there is no relationship between the input bits, data, and control signals of the synchronous DRAM 14 operation. The timing diagrams illustrate embodiments where the signals are timing at the rising edge of the clock signal. FIG. 6 illustrates the timing circle of the read burst of the synchronous DRA1 14. The specific read burst shown in the figure is the burst length 4 and the read wait time 3. Therefore, three clock cycles of data will be output after the signal is requested, and four-group data will be output. As far as an 8-bit component is concerned, each set of data will contain 8 bits. As shown in Fig. 6, the row address is received at the address inputs Α0-Α10, and is requested! ! § The signal is latched on the rising edge of the clock signal. In a specific embodiment, the address signal All of the BANR SELECT signal is high when the 11δ is required, so that the bank A is selected. Provide the column address at the address input A0-A9. When the ^ signal is required, but the f signal is not required, a read command is provided. Because the read wait time is 3, data is output after three clock cycles. As shown in the DQ data, the four sets of data a, b, c, and d occur suddenly at the clock frequency. The data is output alternately between the two sections. To prepare for the next operation, as shown by the required IKf signal, W signal, All, and ΰ! Signal, the library will pre-charge according to the undo command. FIG. 7 is a timing diagram of a burst operation with a burst length of 8. As shown in Figure 7, the receive column address is received at the address input and latched when the signal is activated. When a ^ signal and an f signal are required, a write signal is received. The data written in the column to the synchronous DRAM 14 can be received simultaneously with the write signal. This is possible with the input buffer 100 discussed in Figure 3. In this buffer-24-(Please read the precautions on the back before filling out this page)-δ version) Λ4 size (21GX297 mm) _ A7 B7 Printed by the Consumers 'Cooperative of the Central Government Bureau of the Ministry of Economic Affairs V. Invention Description (η device, which can latch the data for each sector to a separate latch. As shown in Figure 7' receive all eight groups Data, and after receiving the data, it cancels the library it has written with the undo command. Figure 8 is the timing diagram of the read-out burst, the read-out wait time 3 and the burst length 2 as shown in Figure 8. It displays the column address and latches it when the signal is requested. The write command is received at the start signal and the f signal. Because the mode register has set the program with the burst length 2, it will input ~ into two groups The data a and b are written to the synchronous DRAM 14. Secondly, the number 01 ^ 4s is required and a row address is provided in the address input, and a read command is issued. After the read waiting time of three cycles, such as data c and d As shown in the figure, a burst of one or two sets of data c and d is output. Then a cancel signal can be sent to start it. Precharging Figure 8 illustrates the start signal. When All is low, the bank to be started is Bank B. Figure 9 is the timing of the read-write burst 'with revocation cancellation, and the read wait time 3 and burst length 8 Figure β Figure 9 illustrates the operation of bank a. The read operation is completed as described in conjunction with the discussion of Figure 6, followed by a write command similar to that discussed in conjunction with Figure 7. However, for the write command, the lower address has been locked It is stored and has not changed. Because A10 is high when receiving the write command, automatic cancellation occurs. The timing and control circuit 28 in Fig. 2 therefore stops the rows of decoders when the write operation is completed. Fig. 10 is a second library Row alternate readout operation, timing diagram of readout wait time 3 and burst length 2. As shown in Figure 10, bank b is first started and provided with a column of addresses. This situation occurs when the request and All are low . Subsequently, the ® signal is activated and All is high, and bank B is activated. At address -25-This paper applies the Chinese National Standard (CNS) Λ4 Regulations ..... —II! I I.----- II— --I L ·--------D.-... Mnmn • J &quot; T 口 · &quot; (Please read first Read the notes on the back and fill in this page again.) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, A7, B7. 5. Description of the invention (24.) When the signal All is low, 01§ signal is required, and the read operation from the memory bank B is completed. In terms of readout waiting time 3 and burst length 2, the two sets of data a and b listed from the library name will be output for three cycles after the CAS is requested. Second, the address input signal All is required and provided to provide Read out the command for bank A. Therefore, after this request 01 ^ signal three cycles will suddenly send out two sets of data c and d from bank a. Second, a write command is provided for bank B. As long as the information is needed, this alternation between bank B and bank A is followed. When a read command is provided to the synchronous DRAM 14 every two clock cycles, the bank-to-bank alternate provides gap-free output of data. In general, for uninterrupted bursts of length η and fixed waiting time, each bank should receive the read command η cycle, except for the gapless output. Fig. 11 illustrates an example of a two-bank alternate read operation with automatic cancellation and a fixed 'read latency 3 and burst length 8. The operation shown in Figure II is similar to that shown in Figure 10, except that there is enough time to provide a new column address to each bank for each readout because the burst length is 8. Therefore, instead of reading from the same column of a particular memory bank as described in conjunction with FIG. 10, in FIG. Π, a new column is provided for each bank before each read from each bank. The read command shown by the request CAS signal occurs eight cycles apart because the burst length is eight. At each read operation, raise A10 to provide automatic withdrawal. This causes the timing and control circuit 28 of Fig. 2 to deactivate the appropriate list of decoders' to allow the power to be deactivated before the next read operation on the bank. Fig. 12 is a timing chart of a read operation from bank B and a write operation to bank a, a read wait time 3 and a burst length 4; As shown in FIG. 12, the read operation from library A is similar to that discussed in conjunction with FIG. 6 above. ~ ~---------- iv ------- order- ----- ^ I (Please read the notes on the back before filling out this page) This paper size applies to the Chinese National Standard (CNS) Λ4 specification (2 丨 〇X 297 Employees of the Central Standards Bureau of the Ministry of Economic Affairs, Consumer Co-operation. Print A7 ____B7 ~ ~ ~ 5. Description of the Invention (25 ·) After the read command has been issued, the RAS signal is required, and the address input All is high to start bank A. Second, the signal and f signal are required to cancel bank B . Secondly, issue a write command for bank A and write burst 4 to synchronous DRAM 14. Figure 13 shows a write burst to bank A and a read burst from bank b, with automatic cancellation and read The timing chart of waiting time 3 and burst length 4 is shown. As shown in 圏 13, 'First load the column addresses for banks a and B ~' followed by the write command for bank A. · For pulse In terms of strings, the four sets of data ad are written into the memory bank a at the beginning of the write command. When the write command signal is sent to bank A, the address signal A10 is high. The control circuit 28 will automatically cancel bank a when the write operation is completed. Then it sends out a read command with automatic undo to bank B, and because of the read wait time 3, three cycles of read length 4 after the read command ▲ Crush string. Because the address signal A10 is high when the read command is issued, the timing and control circuit 28 of FIG. 2 will cancel bank B when the read operation is completed. The present invention cooperates to receive rows and columns separately. Addresses are discussed. Please give me the answer, "You can use more address lines" to receive row and column addresses at the same time. Although the present invention has been described in detail, please understand that various changes, substitutions and changes can be made. Without deviating from the spirit and scope of the present invention as explained in the attached patent application park. -27-This paper rule New wealth 丨 materials ((Please read the precautions on the back before filling this page) Order

Claims (1)

8 8 8 A 8 c I _ &lt; t ί *---», year ^! ^ 5 D8 Xunli Jiadi Chadi M1057M; ^ qi_ROC Patent Appln. No R4J_0 ^ 7Qd · A synchronous memory element for storing data, including a certain time and control circuit, operable to receive addresses and control inputs, and generate internal control signals. One of these control inputs includes a system clock operating at the system frequency. A memory bank, including a number of memory sections, each of which includes a memory cell array arranged in rows and columns; a row of decoders, connected to the timing and control circuits described above, and can be operated to start each Columns in the memory section; a row of decoders is connected to the above timing and control circuit, and can be operated to actually start the rows in each memory section simultaneously and synchronously; and an output buffer is connected to the above memory bank The output buffer can operate to receive data from each of the above-mentioned memory sections at the same time, and output data from each of the above-mentioned memory sections alternately in synchronization with the system frequency. 2. Synchronous memory element according to item 1 of the patent application park, wherein the memory bank includes a dynamic random access memory unit. 03. Synchronous memory element according to item 1 of the patent application scope, wherein the memory bank includes two memories Section. 4. Synchronous memory element according to item 1 of the scope of patent application. Printed and amended by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. Chinese version of the application patent-Annex II—Amended Claims in Chinese-Enel II ) (Submitted on March 1998) where: .memory section (please read the notes on the back before filling this page) -a The above memory bank includes a first memory section and a first and the above line decoder includes an access to The first memory segment decoder of the first memory segment and a second memory segment decoder connected to the second memory segment. Each of the two memory segment decoders is operable in response to being received from the timing and control circuit. The address of the line, and the lines in the individual memory segments are activated. This paper is suitable for use (CNS) (210X297 mm 8 8 8 8 A 8 c I _ &lt; t ί *---», year ^! ^ 5 D8 Xunli Jiadi Chadi M1057M; ^ 气 _ 多 ROC Patent Appln. No R4J_0 ^ 7Qd Declaring a patent patent. A type of synchronous memory element for storing data, including a certain time and control circuit, operable to receive addresses and control inputs, the dragon generates internal control signals, such control inputs One includes a system clock operating at the system frequency; a memory bank including a number of memory sections, each of which includes a memory cell array arranged in rows and columns; a row of decoders connected to the timing and A control circuit, and can be operated to activate each column in each memory segment; a row of decoders is connected to the above-mentioned timing and control circuit, and can be operated to actually simultaneously start the rows in each memory segment simultaneously; and An output buffer is connected to the above memory bank. The output buffer is operable to receive data from each of the above memory sections at the same time, and output data from each of the above memory sections alternately in synchronization with the system frequency. 2 · According to the synchronous memory element of the first patent application, the above memory bank includes a dynamic random access memory unit 03. According to the synchronous memory element of the first patent scope, the above memory bank includes two memory sections. 4. Synchronous memory element according to item 1 of the scope of patent application. Printed and amended by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. Chinese version of the application patent-Annex II—Amended Claims in Chinese-Enel II ) (Submitted on March 1998) where: .memory section (please read the notes on the back before filling this page) -a The above memory bank includes a first memory section and a first and the above line decoder includes an access to The first memory segment decoder of the first memory segment and a second memory segment decoder connected to the second memory segment. Each of the two memory segment decoders is operable in response to being received from the timing and control circuit. The address of the trip, and start the trips in the individual memory sections. This paper is applicable (CNS) (210X297 mm 印 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A8 B8 ___ §__ VI. Scope of patent application 5 * The synchronous memory element according to item 4 of the patent application park, and additionally contains: a first counter connected to the above timing and control circuit, and an output connected to the first Memory segment demaser; and a second counter connected to the timing and control circuit, and an output connected to the second memory segment decoder; each of the two counters is operable to load at least part of the above row address And perform a synchronous count operation so that the first and second memory segment decoders-respectively receive output from the two counters, and simultaneously access multiple data locations from each memory segment. 6. Synchronous memory element 仵 according to item 5 of the scope of the patent application, and additionally includes-an adder connected between the first counter and the timing and control circuit, if the first memory location accessed by the row is in the first memory Segment, the reader can operate to add zero to the row address. If the first memory location for the column access is in the first-loyalty segment, then it can operate to add-to the row address. 7. The synchronous memory element according to item 丨 of the patent application scope, wherein the upper output buffer comprises: I a first latch stage connected to the above memory sections; and a second latch stage connected to To the first latch stage, and is operable to output data from the memory element; 'Each time the two latch stages access each of the operable latches, a number of bits of data from all memory sectors are accessed. Fool 8. The synchronous memory element according to item 7 of the scope of the patent application, and additionally includes-a latch control circuit, which can operate from all the data in the second latch 上述 described above. Latch-level information This paper rule is close to financial affairs ^^ (CNS) A4 ^ (21〇x297'ii &quot;) (Please read the precautions on the back before filling this page) Order 8 8 8 8 ABCD Central Standard of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives 6. The patent application scope is synchronized to the second latch level. 9. The synchronous memory element according to item 8 of the patent application, and also includes two data switching circuits, which can be operated to control the second latch stage, so that the self-memory element alternately outputs the data from each memory segment. 10. — A synchronous memory element for storing data, including: a certain time and control circuit, operable to receive the address and control the turn-in, and generate internal control signals, one of these control inputs includes a frequency-frequency A system clock for operation; a first memory bank including a plurality of memory sections, each of which includes an array of memory cells arranged in rows and columns; a second memory bank including a plurality of memory sections, etc. The memory sections each include an array of memory cells arranged in rows and columns; 'A first column decoder is connected to the above-mentioned timing friend control circuit and is operable to activate the columns in each memory section of the first memory bank. A second row of decoders connected to the timing and control circuit, and operable to activate the columns in each memory section of the second memory bank; a first row of decoders connected to the timing and control circuit, It can operate to start the rows in each memory section of the first memory at the same time. A second row decoder can be connected to the timing and control circuit. Steps in each memory section of the second memory bank are started step by step; and an output buffer is connected to the first and second memory banks, and the output buffer can operate from each of the memory banks at the same time. —Memory section connected to the paper size · (210X297mm) (Please read the precautions on the back before filling this page), 1T Central Standard of the Ministry of Economy 扃 Printed by employee consumer cooperatives A8 B8 C8 _ D8 VI. Application scope Receive data and synchronize with system frequency to output data alternately from each memory area _ segment of each memory bank. -11. The synchronous memory element according to item 10 of the scope of patent application, wherein each of the above memory banks includes a dynamic random access memory unit. 12. The synchronous memory element according to item 10 of the patent application park, wherein each of the above memory banks includes two memory sections. 13. The synchronous memory element according to item 10 of the scope of patent application, wherein:-each of the memory banks includes a first memory section and a second memory section; and each of the row decoders includes a first memory section. The first memory segment decoder of the segment and a second memory segment decoder connected to the second memory segment. The two memory segment decoders are each operable to respond to the row position received from the timing and control circuit. Address, and start the lines in the individual memory segments. 14. According to the synchronous memory element of the patent application No. 13 and including the first and second burst circuits, each of which is connected to each of the above memory banks' The two pulse train circuits each include: a first counter connected to the timing and control circuit, and an output connected to the first memory segment decoder; and a second counter connected to the timing and control circuit, and a The output is connected to the second memory segment decoder; the two counters are each operable to load at least part of the above-mentioned row addresses and perform synchronous counting operations so that the first and second memory segments are decoded. The device separately receives the output from the two counters, and stores them synchronously from each memory section. -31-This paper uses the Chinese national standard (c is called Conglin (training 297)) (Please read the notes on the back first (Fill in this page again) Order A8 Βδ C8 printed by the Employees' Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs----D8 Six 'patent for applying for patents ~ ~'-Take multiple data locations. 15. According to the patent request _ 14 The first and second pulse train circuits of the synchronous memory element of the item each include—connected to the above-mentioned first counter and timing and control circuit-like adders, if the first memory location of the access is in the first memory section The adder is operable to add zero to the row address, and if the first memory location of the column access is in the second memory section, it is operable to add one to the row address. 16. According to item 10 of the scope of patent application For a synchronous memory element, the above-mentioned output buffer includes: a first latch stage connected to the above memory section; and a second latch stage connected to the first latch stage and operable Output data from the memory element; Each of the two latch stages is operable to latch several bits of data from all memory segments. 17. According to the request, please ask for a full-time synchronous memory element of item 16 and also include-latch control The circuit is operable to latch the data from the first latch stage to the second latch stage after all the data in the second memory stage has been output from the memory element. 18. According to the patent application The synchronous memory element of item 17 further includes-a data switching circuit, which is operable to control the second latch stage, so that the self-memory element alternately outputs data from each memory segment. 19_ A kind of data storage The method of accessing the memory element includes the following steps: Receive the address and control input, one of the control inputs includes-with the system -32-this paper wave scale is used &gt; country country ^? TcNS &gt; (Please read the back Note: Please fill in this page again.) Printed on A8 B8 C8 D8 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 夂, patent application scope ~ ^ System clock for frequency operation; respond to address and control input, start Predetermined columns in many memory sections; respond to addresses and control inputs to actually start predetermined rows in many memory sections simultaneously; actually receive precious materials from each memory section simultaneously; and alternately output in synchronization with the system frequency Data received from each memory segment. 20 'According to the 19th method of the patent application park, and further including the following steps: receiving an initial row address to start the predetermined rows in each memory section; after starting the predetermined rows based on the initial row address' According to the initial row address, another row address is determined 'to synchronize the activation of the other rows in each of the self-memory sections' in order to simultaneously access multiple data locations from each memory section. 21. The method according to item 20 of the scope of patent application, wherein the memory element includes a first memory section and a second memory section, and further includes the following step I «if the first memory location to be accessed is In the first memory section, add zero to the initial row address for the first memory section; and if the first memory location for row access is in the second memory section, add one to the first memory section. The initial row address. This paper size applies to China National Standard (CNS) A4 specification (210 × 297 male thin) (Please read the precautions on the back before filling this page) Order