五、發明説明（ A7 B7 經濟部中夾標隼局貝工消費合作杜印製 發明頜M: 本發明係有關於一種靜能‘ A 〜 心隨機存取記憶體SRAM製 程，特別是指利用薄的分離複晶 Ml θ /禮以降低埋層接觸 區邊緣之溝槽之深度的製程方法。 發明背景： 靜態隨機處理記憶體（SRAM) 一般皆以雙穩離 (bistable)的電晶體為正反器（fUp_fl〇p)問住（iatched up)0或1的位準藉以儲存資料。正βI 卞正反器由兩只負載元件 和兩只電晶體所組成，另外有雨σ咨树1 _ *另兩/、#枓取存電晶體 (access transistor)以決定資料县不西山 〜貝竹疋否要由那一個電晶體 寫入或讀出。 SRAM由於不須像動態隨機處理記憶體（dram)週期 性再充電（refresh) ’不需要佔用中央處理單元的時間。 因此廣泛得使用做怏取記憶體的儲存元件。然而由於 積體電路的製程皆是朝向低功率消耗，高速，高密度 的"一低二高”潮流邁進，SRAM製程自然也不例外。為 降低成本’ SRAM的製程都是以能最緊密的方式佈局來 提咼單位密度。如此一來，在製程的一個環結中常有 造成埋層溝槽的困擾。以下我們將先介紹傳統製造4 T、 2RSRAM電晶體的問題’然後在.發明詳細說明中我們 再詳述我們的發明細節。圖一示一經以下製程步驟 之結果的橫截面圖。首先以習知技術形成墊氧化層11 0 及區域氧化層（LOC05)1 04在半導體晶圓1〇2上，接著以 -3- 本舐張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝. -訂 A7 -----— B7五、發明説明（） 經濟部中央標準局員工消費合作社印製 CVD方法形成第一複晶矽層12〇在墊氧化層11〇及區域 氧化雇104之上。此第一複晶矽層n〇的厚度约為55〇埃 左右。然後’再以罩冪層及飯刻技術定義埋層接觸區 1 2 5。之後對埋層接觸區施以離子佈植以降低電阻值。 此佈植劑量約為2.2E1 5/em2。 隨後如圖二所述，再以CVD法均勻一致性的形成一 第一複晶石夕層1 3 0 ’第二複晶矽層1 3 0的厚度約為5 5 0埃 接著以CVD法直接再形成金屬矽化層（p〇lycide) 14〇， 此金屬矽化物層140通常是選自耐火金屬（refract〇ry metal silicide)，例如鈦，鈷或鎢其中的一種之矽化物。 金屬矽化物層140厚度約為1〇〇〇埃左右， 接下來’如圖三所示’以光阻罩幕層145覆蓋在金 屬矽化物層140之第—電晶體之閘極區丨5〇。另一光阻 層146則覆蓋在第二電晶體之閘極上155(圖示中埋層接 觸區125之左邊）以及埋層接觸區125之上以定義電晶體 的位置’並曝露出第一電晶體之第一源/汲極151及第 二源/汲極1 5 2。接著，以墊氧化層i丨〇為蝕刻終止層， 以乾#刻法依序去除曝露出來的金屬矽化物層丨4〇、第 二複晶石夕層130及第—複晶矽層12〇。值得注意的是， 在圖二所示的A點處約比b點處的金屬石夕化物層i 4 〇厚 度較薄’約達550埃。由於如之前所提及為降低在本 SRAM的製程都是以最緊密的方式佈局以提高單位密 度。因此’當罩幕層】46沒有完全覆蓋^層接觸區125 時’在蚀刻過程終了，即偵測到蝕刻終止層墊氧化層n 〇 時’因為第一複晶矽層12〇和基板半導體晶圓1〇2材質 本紙張尺度it财酬家辦(CNS ) A4M,#. ( 210X 297/^t ) (請先閱讀背面之注意事項再填寫本頁)V. Description of the invention (A7 B7 The Ministry of Economic Affairs of the Ministry of Economic Affairs of the Ministry of Economic Affairs of the Ministry of Economic Affairs of the Ministry of Economic Affairs of the People ’s Republic of China. The invention of jaw M: This invention relates to a kind of static energy 'A ~ SRAM process, especially the use of thin Manufacturing method for separating complex crystal Ml θ / to reduce the depth of the trench at the edge of the buried contact area. BACKGROUND OF THE INVENTION: Static random processing memory (SRAM) generally uses bistable transistors as the front and back. The device (fUp_fl0p) asks (iatched up) the level of 0 or 1 to store data. The positive βI 卞 flip-flop is composed of two load elements and two transistors, in addition to rain sigma tree 1 _ * The other two /, # 枓 take the access transistor to determine whether the data county is not Xishan ~ Beizhu 疋 whether to be written or read by that transistor. SRAM does not need to dynamically deal with the memory (dram) Periodic recharge (refresh) 'does not need to occupy the time of the central processing unit. Therefore it is widely used as a memory storage element. However, because the integrated circuit manufacturing process is oriented towards low power consumption, high speed, high density & quot One low and two high tide Moving forward, the SRAM process is no exception. To reduce costs, SRAM processes are arranged in the most compact way to increase unit density. In this way, a ring junction in the process often causes the problem of buried trenches. In the following, we will first introduce the problem of traditional manufacturing of 4 T, 2 RSRAM transistors. Then we will detail the details of our invention in the detailed description of the invention. Figure 1 shows a cross-sectional view of the results after the following process steps. The known technology forms a pad oxide layer 11 0 and a local oxide layer (LOC05) 1 04 on a semiconductor wafer 102, and then applies the Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) at a 3--3 scale. ) (Please read the precautions on the back before filling this page) Installation.-Order A7 -----— B7 V. Description of Invention () Printed by CVD method for the first co-crystalline silicon by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs The layer 12 is over the pad oxide layer 110 and the area oxide layer 104. The thickness of this first polycrystalline silicon layer no is about 55 angstroms. Then, the buried layer contact is defined by the masking layer and the inscription technique. Area 1 2 5. Then connect the buried layer Ion implantation was applied in the area to reduce the resistance value. The implantation dose was approximately 2.2E1 5 / em2. Subsequently, as shown in FIG. 2, a first polycrystalline stone layer was uniformly and uniformly formed by CVD method 1 3 0 'The thickness of the second polycrystalline silicon layer 130 is about 550 angstroms, and then a metal silicide layer (polycide) 14 is directly formed by a CVD method. The metal silicide layer 140 is usually selected from refracting metals (refract 〇ry metal silicide), such as a silicide of titanium, cobalt or tungsten. The thickness of the metal silicide layer 140 is about 1000 angstroms. Next, as shown in FIG. 3, a photoresist mask curtain layer 145 is used to cover the gate region of the first silicide layer 140 of the metal silicide layer. . Another photoresist layer 146 covers the gate 155 of the second transistor (to the left of the buried contact region 125 in the figure) and over the buried contact region 125 to define the position of the transistor and exposes the first transistor. The first source / drain 151 and the second source / drain of the crystal 1 5 2. Next, the pad oxide layer i 丨 is used as an etching stop layer, and the exposed metal silicide layer 丨 40, the second polycrystalline stone layer 130, and the first multi-crystalline silicon layer 12 are sequentially removed by a dry etching method. . It is worth noting that the thickness of the metallized oxide layer i 4 0 at point A shown in FIG. 2 is about 550 Angstroms, which is thinner. As mentioned earlier, in order to reduce the manufacturing process in this SRAM, it is arranged in the most compact way to increase the unit density. Therefore, 'when the cover layer] 46 does not completely cover the contact layer 125' at the end of the etching process, that is, when the etch stop layer pad oxide layer n 0 is detected ', because the first polycrystalline silicon layer 12 and the substrate semiconductor Circle 102 material This paper size it financial office (CNS) A4M, #. (210X 297 / ^ t) (Please read the precautions on the back before filling this page)
五 區 此 首 體 經濟部中央標準局負工消費合作社印製 、發明説明（ 之蝕刻選擇性接近而極容易造成蝕刻過 「複晶梦層130和第-電晶體之間極的交界處 60生成。此構槽160的深度通常頗深，約為二= 右。這樣的構槽160並不易為徭而μ制# 馮1000埃左 卜勿碍设面的製程所修 常會造成中斷電流路徑的一大元兇之一，一， ， 降’而極思-新製程法來降低構槽16。的深上率因此下 發明目的及概祓· 鑒於上述之發明背景中，僂絲的Printed by the Central Standards Bureau of the Ministry of Economic Affairs, the Central Bureau of Standards and Consumers ’Cooperative of the Ministry of Economic Affairs, and the description of the invention (the etching selectivity is close and it is very easy to cause etching through the junction 60 between the polycrystalline dream layer 130 and the first transistor The depth of this structured groove 160 is usually quite deep, about two = right. Such a structured groove 160 is not easy to make. # 冯 1000 埃 左 卜 Don't interfere with the process of setting the surface will often cause interruption of the current path. One of the chief culprits, one, one, down, and think-the-new process method to reduce the depth of the groove 16. Therefore, the purpose and outline of the invention are as follows. In view of the above background of the invention,
得統的方法在形成SRAM 第一電曰曰體的源/汲極時，由於源/汲極和埋層接觸 之蝕刻終點偵測時不一致常有過度蝕刻的問題。因 提出本發明之方法予以解決。本發明之方法包括： 先，在一已形成一墊氧化層及複數個場氧化層半導 曰a圓上’形成一厚度約為IQ·!。。nm的第—複晶梦層 於墊氧化層及場氧化層之上；然後以罩幕層覆蓋在第一 複晶矽層上以定義一埋層接觸區。之後蝕刻第一複晶 石夕層以曝露出埋層接觸區；再施以離子伟植埋層接 區’佈植的劑量約lE15-lE16/cm2能量約i〇_5〇keV;; 後均勻的形成一第二複晶梦層於該第一複晶發層及 埋層接觸區；並直接沉積一金屬矽化物層於第二複晶 層上；，再覆蓋一曝露出第一電晶體的第一源/沒極區 第一源/>及極區之罩幕層圖案於金屬發化物層上。之後 以該墊氧化層為蝕刻終止層，依序蝕刻 曝露出的金 矽化物層、第二複晶矽層與第一複晶矽層。最後以 -5- 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） 觸 隨 該 矽 與 屬 稀 (請先聞讀背面之注意事項再填寫本頁)In the conventional method, when the source / drain of the first electrical body of the SRAM is formed, the problem of over-etching often occurs due to the inconsistency in the detection of the etching end point of the contact between the source / drain and the buried layer. It is solved by the method of the present invention. The method of the present invention includes: First, forming a pad oxide layer and a plurality of field oxide layer semiconductors on a circle 'a' to form a thickness of about IQ.!. . The first polycrystalline dream layer of nm is on the pad oxide layer and the field oxide layer; then, the first polycrystalline silicon layer is covered with a mask layer to define a buried contact area. After that, the first polycrystalline stone layer is etched to expose the buried layer contact area; and the ion implanted buried layer connection area is applied with a dose of about 1E15-1E16 / cm2 and an energy of about i0_50kV; Forming a second polycrystalline dream layer on the contact area between the first polycrystalline hair layer and the buried layer; and directly depositing a metal silicide layer on the second polycrystalline layer; and then covering an exposed first transistor The first source / first region / > and the mask layer of the polar region are patterned on the metal hairpin layer. Then, using the pad oxide layer as an etching stop layer, the exposed gold silicide layer, the second polycrystalline silicon layer, and the first polycrystalline silicon layer are sequentially etched. Finally, -5- this paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 mm). Touch the silicon and the rare (please read the precautions on the back before filling this page)
經濟部中央標準扃I工消費含作社印$ί A7 B7 ’ 五、發明説明（） 釋的HF或BOE潤濕，以去除剩餘的墊氧化層用以曝露 出半導體晶圓的上表面。… 根據以上所述之方法，本發明提供之方法比傳統方 法至少降低了約500埃之深度的埋層溝槽。 圖示簡單說明： 本發明的較佳實施例將於往後之文字中輔以說明圖 形做更詳細的闡述： 圖一顯示依據傳統方法，對SRAM之埋層接觸區做離子 佈植的構截面圖； 圖二顯示依據傳統方法，沉積金屬矽化物層、第二複 晶矽層的橫截面圖； 圖三顯示依據傳統方法，覆蓋一曝露出第一電晶體的 第一源/汲極區及第一源/汲極區之罩幕層圖案； 圖四顯示依據傳統方法，乾式蝕刻以形成第一電晶體 的閘極部份； 圖五顯示依據本發明之方法，形成一層薄的第一複晶 矽層並對SRAM之埋層接觸區做離子佈植的橫截面圖； 圖六顯示依據本發明之方法，沉積金屬矽化物層/第二 複晶矽層的橫截面圖； 圖七顯示依據本發明之方法，覆蓋一曝露出第一電晶 體的第一源/汲極區及第一源/汲極區之罩幕層圖案； 圖八顯示依據本發明之方法，乾式蝕刻丨以形成第一電 晶體的閘極部份，溝槽深度大為減少。 -6- 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） (請先閱讀背面之注意Ϋ碩再填寫本頁) .裝_ 丨訂 Α7 Β7 五、發明説明（） 發明詳細說明： 由;於一如發明背景所述埋層接觸區邊緣的構槽1 60常 會造成斷路的問題，因此，本發明提供一新的製程觀 念以解決習知技術的問題。本發明的方法重要觀念在 於提供一種比傳統方法明顯薄的第一複晶矽層取代厚 的第一複晶矽層以解決靜態隨機處理記憶體（SRAM)之 四電晶體、二電阻埋層接觸區邊緣的構槽問題。本發 明的細節可參考圖示來加以詳細說明。以下將詳細說 明製程的細節如下： 參考圖五的橫截面圖，在較佳實施例裡，首先在一 矽單晶基材半導體晶圓402上先形成複數個厚區域氧化 層4 0 4於此矽晶上做為元件彼此問的區隔之用。例如區 域氧化層404可經由微影和蝕刻步驟來蝕刻未被光阻罩 冪的氮化矽層、墊氧化層，在去光阻後，在氧蒸氣環 境下以熱氧化法（thermal oxidation)長FOX區404至約 30 00-8000埃。以熱磷酸鹽溶液去除剩餘的氮化矽罩幕 層，此時，墊氧化層厚約30-1 〇〇nm。接著以CVD方法 約在500-600°C下，形成一特別薄的第一複晶矽層420在 墊氡化層410及區域氧化層404之上。此複晶矽層的厚 度約僅10-100埃左右，典型值約50埃左右，再以罩幕層 及儀刻技術定義埋層接觸區（buried contact)425。然後 以磷或砷之η-型離子對埋層接觸區425做離子佈植。此 佈植劑量約為2.2E15/cm2，能量約10-50lleV。 隨後如圖六所示再以CVD法約500-600°C均勻一致性 的形成一第二複晶矽層430，第二複晶矽層430的厚度 _______·7· 本紙張尺度適用中國國家標準（CNS〉Λ4規格（210X297公釐） (諳先聞讀背面之注意事項再填寫本頁) :當 經濟部中央標準局貝工消費合作社印製The central standard of the Ministry of Economic Affairs and Industrial Consumption includes the print of the company. A7 B7 ’V. Explanation of the invention () Wetting of HF or BOE to remove the remaining pad oxide layer to expose the upper surface of the semiconductor wafer. … According to the method described above, the method provided by the present invention reduces the buried trench by a depth of at least about 500 Angstroms compared to the conventional method. Brief description of the diagram: The preferred embodiment of the present invention will be explained in more detail in the following text with explanatory graphics: Figure 1 shows the cross section of ion implantation of the SRAM buried contact area according to the traditional method FIG. 2 shows a cross-sectional view of a metal silicide layer and a second polycrystalline silicon layer deposited according to a conventional method; FIG. 3 shows a first source / drain region covered with an exposed first transistor and Pattern of the mask layer of the first source / drain region; FIG. 4 shows the gate portion of the first transistor by dry etching according to the conventional method; FIG. 5 shows the method of forming a thin first layer according to the present invention A cross-sectional view of the crystalline silicon layer and ion implantation of the SRAM buried contact area; FIG. 6 shows a cross-sectional view of a metal silicide layer / second polycrystalline silicon layer deposited according to the method of the present invention; FIG. 7 shows a basis The method of the present invention covers a pattern of a first source / drain region and a mask layer of the first source / drain region exposing the first transistor; FIG. 8 shows a dry etching process according to the present invention to form a first Gate of a transistor The trench depth is greatly reduced. -6- This paper size applies to Chinese National Standards (CNS) Λ4 specifications (210X297 mm) (Please read the note on the back before filling in this page). Equipment_ 丨 Order Α7 Β7 V. Description of the invention () Detailed description of the invention : As described in the background of the invention, the trenches 160 at the edge of the buried layer contact area often cause the problem of disconnection. Therefore, the present invention provides a new process concept to solve the problems of the conventional technology. The important concept of the method of the present invention is to provide a first polycrystalline silicon layer which is significantly thinner than the traditional method to replace the thick first polycrystalline silicon layer to solve the contact between the four transistors and the two resistance buried layers of the static random processing memory (SRAM). Grooving at the edge of the area. The details of the present invention can be described in detail with reference to the drawings. The details of the manufacturing process will be described as follows: Referring to the cross-sectional view of FIG. 5, in a preferred embodiment, a plurality of thick region oxide layers 4 0 4 are first formed on a silicon single crystal substrate semiconductor wafer 402 first. Silicon is used as a separation between components. For example, the regional oxide layer 404 can be etched through the photolithography and etching steps to etch the silicon nitride layer and pad oxide layer that are not masked by the photoresist. After the photoresist is removed, the area oxide layer is grown by thermal oxidation in an oxygen vapor environment. FOX zone 404 to about 300-8000 Angstroms. The remaining silicon nitride mask layer was removed with a hot phosphate solution. At this time, the pad oxide layer was about 30-100 nm thick. Then, a particularly thin first polycrystalline silicon layer 420 is formed on the padding layer 410 and the region oxide layer 404 by a CVD method at about 500-600 ° C. The thickness of this polycrystalline silicon layer is only about 10-100 angstroms, and the typical value is about 50 angstroms. The buried contact layer 425 is defined by the mask layer and the engraving technique. Then, the n-type ion of phosphorus or arsenic is used to implant the buried layer contact region 425. The implantation dose is about 2.2E15 / cm2, and the energy is about 10-50lleV. Then as shown in Figure 6, a second polycrystalline silicon layer 430 is formed uniformly and uniformly by CVD at about 500-600 ° C. The thickness of the second polycrystalline silicon layer 430 is _______7. This paper is applicable to China Standard (CNS> Λ4 specification (210X297 mm) (谙 Please read the precautions on the back before filling out this page): Printed by the Shelling Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs
經濟部中央標準局負工消費合作社印製 A7 ___5Z__ 五、發明説明（） 約為900-1200埃左右，典型值為1050埃。接著以CVD法 直銼#形成厚度約800-1200埃左右，典型值為1000埃之 金屬石夕化物層（p〇lycide)440，此金屬石夕化物層440，係 選自耐火金屬（refractory .. metal silicide)例如欽，钻或 嫣等其中的一種之金屬石夕化物，其中以鶴之金屬梦化 物最常被使用。當然金屬矽化物層也可用鍍較厚的第 二複晶矽層430再以CVD或濺鍍的方式沉積鈦，鈷或鎢 等金屬再施以一至二段式退火約在7〇〇-l〇〇〇〇c下以形成 金屬矽化層440。 接下來，如圖七所示以光阻罩幕層445覆蓋在金屬矽 化物層440之第一電晶體之閘極區450上，另一光阻層 44 6則覆蓋在第二電晶體之閘極上45 5(圖示中埋層接觸 區42 5之左邊，第二電晶體之閘極的側視圖）以及埋層接 觸區425之上以定義電晶體的位置，並曝露出第一電晶 體之第一源/汲極451及第二源/汲極452。接著以乾式钱 刻法例如純化學方式的電漿蝕刻法或兼具物理與化學 方式的反應氣體離子，通入如HBr、Cl2、CF4、〇2及CHF3 等為餘刻劑之蝕刻方法’以墊氧化層4丨〇為蝕刻終止 層’依序去除曝露出來的金屬矽化物層440、第二複晶 矽層43 0及第一複晶矽層420。最後再以稀釋的HF或Β〇Ε 去除剩餘的墊氧化層110。這樣可以減少乾蝕刻所造成 的離子損傷。值得注意的是，在圖七所示的A點處（在 埋層接觸區的邊緣）的第一複晶矽層4 3 〇丨厚度（接近丨〇 5 〇 埃左右）和B點處的第一複晶矽層43 0(厚度約丨丨〇〇埃）接 近。因此，僅管第一複晶矽層430和基板半導體晶圓4〇2 ____—---------- -8- 本紙張尺度適用中國國家檩準(CNS ) Λ4規格（210X 297公兹) ----- (請先閱讀背面之注意事項再填寫本頁) 裝. A7 B7 五、發明説明（ 材質蝕刻選擇性接近，且罩幕層446沒有完全覆蓋埋層 接觸έ 425的情況下’在傳統製程中蝕刻過程極容易過 度蝕刻的情形將不致於發生。理由是，由於終點偵測 在Β點到達時’ Α點處縱使有構槽4 6 0產生，構槽4 6 〇的 深度也將大為減少（約至少可比傳統製程減少约5〇〇埃左 右）。這樣的淺構槽460就很容易為後面的製程所修補。 自然，良率因此可大為提升。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之申請專利範圍；凡其它未脫離本發明户斤 揭示之精神下所完成之等效改變或修飾，均應包含& 下述之申請專利範圍内。 0'. J--------裝-- (諳先聞讀背面之注土愿事项再填"本頁j 訂 .__ 經濟部中央標準局員工消費合作社印掣 -9- 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐）Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives A7 ___5Z__ 5. Description of the invention () is about 900-1200 Angstroms, with a typical value of 1050 Angstroms. Then, a CVD method is used to form a metal oxide layer 440 with a thickness of about 800-1200 Angstroms, a typical value of 1000 Angstroms. This metal oxide layer 440 is selected from refractory metals. (metal silicide) For example, one of the metal silicides of Chin, Diamond, or Yan, among which the metal dreams of cranes are most commonly used. Of course, the metal silicide layer can also be plated with a thicker second polycrystalline silicon layer 430, and then titanium, cobalt, or tungsten is deposited by CVD or sputtering, and then annealed in one or two stages at about 700-1 00c to form a metal silicide layer 440. Next, as shown in FIG. 7, a photoresist mask curtain layer 445 covers the gate region 450 of the first transistor of the metal silicide layer 440, and another photoresist layer 44 6 covers the gate of the second transistor. Above the electrode 45 5 (left side of the buried contact region 425 in the figure, the side view of the gate of the second transistor) and above the buried contact region 425 to define the position of the transistor, and expose the first transistor. The first source / drain 451 and the second source / drain 452. Next, dry etching method such as plasma etching method of pure chemical method or reactive gas ions with both physical and chemical methods is used to pass in etching methods such as HBr, Cl2, CF4, 〇2 and CHF3. The pad oxide layer 4 is an etch stop layer, and the exposed metal silicide layer 440, the second polycrystalline silicon layer 430, and the first polycrystalline silicon layer 420 are sequentially removed. Finally, the remaining pad oxide layer 110 is removed with diluted HF or BOE. This reduces ionic damage caused by dry etching. It is worth noting that the thickness of the first polycrystalline silicon layer at point A (at the edge of the buried layer contact area) shown in FIG. A polycrystalline silicon layer 43 0 (thickness of about 丨 丨 00 angstroms) is close. Therefore, only the first polycrystalline silicon layer 430 and the substrate semiconductor wafer 4 0 2 ____ —---------- -8- This paper size is applicable to China National Standard (CNS) Λ4 specification (210X 297 Copies) ----- (Please read the precautions on the back before filling out this page) Pack. A7 B7 V. Description of the invention (materials have similar etching selectivity, and the cover layer 446 does not completely cover the buried contact layer 425) In the case of 'the etching process is extremely easy to over-etch in the traditional process will not occur. The reason is that because the end point detection is reached at point B', even if there are structured grooves 4 6 0, structured grooves 4 6 〇 The depth of the silicon wafer will also be greatly reduced (about at least about 500 Angstroms less than the traditional process). Such a shallow groove 460 can be easily repaired by subsequent processes. Naturally, the yield can be greatly improved. The description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit of the present invention should include & Within the scope of the patent application mentioned above. 0 '. J -------- 装-(谙 先Note soil would like to read back issues of the refill " j page book .__ Ministry of Economic Affairs Bureau of Standards employees consumer cooperatives and India catch -9- this paper scale applicable Chinese National Standard (CNS) Λ4 size (210X297 mm)