i、發明説明（1 ) A7 B7 經濟部中央標準局員工消費合作社印裝 本發明係關於半導體積體電路之製造。本發明尤可以 動態隨機存取記憶體（DRAM)裝置之記億單元構造加以舉 例說明，然而，須知本發明具有更廣範圍之適用性。舉例 而言，本發明可應用於其他半導體裝置之製造，諸如特殊 應用積體電路（ASICs)、微處理器（MICROS)、其他記憶 裝置等》 在DRAM裝置之製作方面，各DRAM記億單元之記憶 存儲容量（storage capacity) —直存在著問題，在 DRAM記憶單元中，存儲容量係指可存儲於一下電容器電 極與一上電容器電極間之介電材料中之最大電荷量。此存 儲容量係與此等電容電極間之電容器介電體表面積成比 例。因此，較大的電容器表面積對應於較大的存儲容量。 用於256 Kbit DRAM之低密度DRAM記憶單元係使 用大約與電晶體閘極相同之水平空間平面中所建構之平面 電容器構造設計。此等電容器構造係形成以覆於電晶體閘 極與場氧化隔離區域間所限空間區域內之電晶體源/汲極區 域上。此等平面電容器構造可有效提供足夠之存儲容量予 此等低密度DRAM記憶單元。然而，當DRAM記憶單元之 尺寸因較高密度之裝置而變小時，於此較小記億單元尺寸 內具足夠存儲容量之電容器構造之設計漸趨困難。 用以增加此等較髙密度DRAM記憶單元之記憶體存儲 容量之一種技術爲堆疊式電容器。該堆疊式電容器使其電 容器構造形成於該場效電晶體閘極之“上方”’而非與該 2 本紙浪尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） ---.--^---Λ-- (請先閏讀背面之注意事項再填寫本頁) 、1Τ A7 __B7五、發明説明（2 ) 經濟部中央標準局員工消費合作社印製 閘極相同之空間平面中。因此，該堆疊式電容器乃藉由將 電容器構造製造於該場效電晶體閘極之上方而增加其電容 器表面積。然而，此種電容器型式所受之限制爲製程上之 困難。事實上，該堆叠式電容器構造使DRAM記憶單元具 有極其複雜之凹凸形勢（topography)。此極爲複雜之凹 凸形勢造成製造技術上之困難，而導致較長之交貨時間、 較低之裝置產率，以及較髙之裝置成本。 另一種被提出以增加高密度DRAM記憶單元記憶存儲 容量之技術爲溝式電容器（trench capacitor)。該溝式 電容器之構造係形成於該DRAM記憶單元井區中之凹陷區 域或”溝道”內。該溝道界定有經選擇之寬度與深度。該溝 道更包含一溝道側壁，藉此來界定下電容器電極。覆於該 溝道側壁上者係該電容器介電層。覆於此電容器介電層上 之導電塡充材料界定出該上電容器電極。隨著電容器表面 積之增大可得漸增之電容器存儲。 較大之電容器表面係與空間上較深或較寬之溝道設計 有關。該溝道寬度因每一記憶單元之基板表面積有限而基 本上無法增大。於是，該溝道必須藉由較深溝道之製造而 增大。然而，此較深之溝渠往往因其髙縱橫比而不易準確 地製作。另一方面之限制爲因與此溝道設計相關之較大接 面面積而可能存在”軟誤差"之問題。又一方面之限制爲製 造下電容電極時之側壁摻雜常影響電容器介電層之品質。 (請先閱讀背面之注意事項再填寫本頁) 裝. 、νβ 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 五、發明説明（3) A7 B7 經濟部中央標準局員工消費合作社印製 由上述可知，一種易於製造、節省成本且可靠之髙密 度記憶單元構造常爲吾人所需求者。 本發明係提供一種DRAM積體電路裝置之電容器改良 技術，包括一種方法及一種構造在內。此經改良之電容器 不需形成較深之溝道即可具備較大之表面積。 在一特殊實施例中，本發明提供一種動態隨機存取記 憶體（DRAM)積體電路。此DRAM積體電路具有一包含凹 陷區域之半導體基板。該凹陷區域具有自底面延伸之垂直 邊側。一包含有源/汲極區域之場效電晶體提供於鄰接於該 凹陷區域處。該DRAM積體電路更包含一覆於該凹陷區域 上之絕緣層。另提供一覆於該絕緣層上、位於一部分場效 電晶體上方之下電容器板。此下電容器板係連接於源極/漏 極區域。該DRAM積體電路更包含一覆於該下電容器板上 之電容器介電體，及一覆於該介電層之上電容器板。該下 電容器板、電容器介電體及上電容器板界定出該電容器構 造。 在另一實施例中，提供一種形成動態隨機存取記憶體 積體電路元件之電容器構造之方法。此方法包括提供一半 導體基板，以及於該基板中形成一凹陷區域。此凹區域具 有自一底面延伸之垂直邊側。該方法亦包括一經界定以覆 於該凹陷區域上之絕緣層。所提供之又一步驟係形成一鄰 接於該凹陷區域之源/汲極區域。該方法包括形成一覆於 該絕緣層上、位於一部分場效電晶體上之下電器容板。此 (請先閱讀背面之注意事項再填寫本頁) 裝. 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 ___B7 五、發明説明（4 ) 下電容器板係連接至該源/汲極區域。該方法更包括形成 一覆於該下電容器板上之電容器介電體，以及形成一覆於 該介電層上之上電容器板。該下電容器板、電容器介電體 及上電容器板界定出該電容器構造。 本案之又一實施例中包含一動態隨機存取記憶體積體 電路之位元線構造。此位元線構造具有一包含凹陷區域之 半導體基板。此凹陷區域具有自一底面延伸之垂直邊側。 一場效應電晶體經界定以鄰接於該凹陷區域。一絕緣層係 界定以覆於該凹陷區域上，而一導體則界定於該凹陷區域 內。此導體連接至該源/汲極區域，並界定出一位元線。 另一特殊實施例包含於一動態隨機存取記憶體積體電 路中形成一位元線構造之方法。此方法包括提供一半導體 基板、以及於該半導體基板中形成一凹陷區域。此凹陷區 域具有自底面延伸之垂直邊側。該方法更包括形成一經界 定以覆於該凹陷區域上之絕緣層，以及形成一鄰接於該凹 陷區域之場效應電晶體之步驟。一導體被界定於該凹陷區 域內。此導體連接至該源/汲極區域，並界定出一位元 線。 本發明係在已知製造技術之背景下達成這些優點者。 然而，參照後文之詳細說明及附圖後，應可更明瞭本發明 之特性及優點。 第1圖係根據本發明DRAM積體電路元件之簡單斷面 圖。 5 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） n I !.. I *1±^- - I.-= - II— ----- - U3 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局®C工消費合作社印製 A7 B7 五、發明説明（5 ) 第2圖係第1圖之DRAM位兀線構造之簡略斷面圖； 第3圖係第2圖位元線構造之另一斷面圖； 第4圖係第1圖之DRAM的簡略頂視圖；及 第5〜14圖係用來說明根據本發明的DRAM積體電路 元件之簡略製造方法。 [特定實施例之說明] I .動態隨機存取記憶體裝置構造 第1圖係本發明DRAM積體電路裝置10之簡略斷面 圖。本裝置單純爲說明而例示者，因而不應將申請專利範 圍限定於此裝置。大體而言，該DRAM裝置10包含複數個 記憶單元區域12、一覆蓋介電層14、一頂金屬化層（top metallization layer)16、一鈍化層17及其他元件。該 記憶單元區域可使用習知CMOS處理技術等來製作。 各記億單元區域I2皆界定於一P型井區域22內，一場 效電晶體18界定於此P型井區域22內。該場效電晶體係一 N型通道金屣氧化物半導體（MOS)裝置，其包含一閘極電 極54。該閘極電極54(稱爲字線；word line)，覆蓋於一 薄閘極介電層52上。側壁（sidewall)56係界定爲鄰接於 閘極54側。覆於該閛極54上者係一蓋氧化層（cap 0Xide 1 a y e r ) 5 8 。一中間層介電體（i n t e r -1 a y e r dielectric)60係形成以覆於該蓋氧化物層58上，亦形成 以覆於部分之源/汲極區域38,46上。每一源/汲極面域 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再.填寫本頁) 裝· A7 ----------B7 五、發明説明（6 ) 經濟部中央標準局員工消費合作社印製 均包含一 N -型LDD區域42,48及一N+型源/汲極區域 40,5〇。如所示者，N +型源/汲極區域40係連接至一溝道 電容器（t r e n c h c a p a c i t 〇 r ) 2 0，亦界定於該p型井區域 2 2內。 此溝道電容器可作爲一種記憶存儲裝置使用，用以存 儲位於下電容器板26與上電容器板28間之電容介電體30中 之電荷，此電容介電體可爲任何適合的絕緣材料，諸如二 氧化矽、氮化矽等。該電容介電體較佳爲一包含二氧化 矽、氮化矽及二氧化矽之夾層，其爲習知之氧化物一氮化 物一氧化物（〇xide-on-nitride-on-oxide;〇NO)。當 然，依其適用性亦可使用其他介電材料之組合。 該下電容器板26係界定於該場效電晶體18上方，並界 定以覆於一絕緣層24上，覆蓋溝道底部3 2及邊側3 4。此絕 緣層之厚度係經選擇而足以使該P型井區域與下電容器板 26隔離。髙品質之二氧化矽材料可用作此絕緣層以達絕緣 目的。然而，該絕緣層自該溝道邊側34之上部36除去，以 提供該下電容器板26與該N +型源/汲極區域40間之電性 接觸。 該下電容器板可爲任何適合的導體層。該下電容器板 較佳爲於形成過程中摻雜（in-situ d〇Ped)N型雜質（例 如磷等）之複晶矽層。該下電容器板亦可製成包含多重金 屬層、矽化物層及其組合等之夾層構造。在另一實施例 中，該下電容器板係利用一具紋理或粗糙之複晶矽層製 7 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝·i. Description of the invention (1) A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs This invention relates to the manufacture of semiconductor integrated circuits. The present invention can be exemplified by the structure of a memory cell of a dynamic random access memory (DRAM) device. However, it should be noted that the present invention has a wider range of applicability. For example, the present invention can be applied to the manufacture of other semiconductor devices, such as special application integrated circuits (ASICs), microprocessors (MICROS), other memory devices, etc. In the production of DRAM devices, Storage capacity — There is always a problem. In DRAM memory cells, storage capacity refers to the maximum amount of charge that can be stored in the dielectric material between the lower capacitor electrode and the upper capacitor electrode. This storage capacity is proportional to the surface area of the capacitor dielectric between these capacitor electrodes. Therefore, a larger capacitor surface area corresponds to a larger storage capacity. The low-density DRAM memory cell for 256 Kbit DRAM is designed using a planar capacitor structure constructed in a horizontal space plane approximately the same as a transistor gate. These capacitor structures are formed so as to cover the transistor source / drain region within a limited space region between the transistor gate and the field oxidation isolation region. These planar capacitor structures can effectively provide sufficient storage capacity for these low-density DRAM memory cells. However, as the size of DRAM memory cells becomes smaller due to higher-density devices, the design of capacitor structures with sufficient storage capacity within this smaller memory cell size becomes increasingly difficult. One technique used to increase the memory storage capacity of these higher density DRAM memory cells is stacked capacitors. The stacked capacitor has its capacitor structure formed "above" the field-effect transistor gate, rather than the two paper wave scales that conform to the Chinese National Standard (CNS) A4 specification (210X297 mm) ---.-- ^ --- Λ-- (Please read the notes on the back before filling out this page), 1T A7 __B7 V. Description of the invention (2) Printed on the same space plane by the staff consumer cooperative of the Central Standard Bureau of the Ministry of Economic Affairs. Therefore, the stacked capacitor has its capacitor surface area increased by fabricating the capacitor structure above the field effect transistor gate. However, this type of capacitor is limited by manufacturing difficulties. In fact, this stacked capacitor structure gives DRAM memory cells extremely complex topography. This extremely complicated concave-convex situation causes difficulties in manufacturing technology, which results in longer delivery times, lower device yields, and higher device costs. Another technique proposed to increase the memory storage capacity of a high-density DRAM memory cell is a trench capacitor. The trench capacitor is formed in a recessed area or "channel" in the well area of the DRAM memory cell. The channel defines a selected width and depth. The trench further includes a trench sidewall to define a lower capacitor electrode. Covering the trench sidewall is the capacitor dielectric layer. A conductive charge material overlying the capacitor dielectric layer defines the upper capacitor electrode. As the capacitor surface area increases, more capacitor storage can be obtained. Larger capacitor surfaces are related to deeper or wider channel designs in space. The channel width is basically unable to increase due to the limited surface area of the substrate of each memory cell. Therefore, the channel must be enlarged by manufacturing a deeper channel. However, this deep trench is often difficult to make accurately because of its aspect ratio. The limitation on the other hand is that there may be "soft errors" due to the large junction area associated with this channel design. Another limitation is that the side wall doping when manufacturing the lower capacitor electrode often affects the capacitor dielectric The quality of the layer. (Please read the precautions on the back before filling this page).. Νβ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm). 5. Description of the invention (3) A7 B7 Ministry of Economic Affairs Printed by the Consumer Standards Cooperative of the Central Bureau of Standards, it can be known from the above that an easy-to-manufacture, cost-saving, and reliable structure of a 髙 density memory cell is often required by us. The present invention provides a capacitor improvement technology for a DRAM integrated circuit device, including a The method and a structure are included. The improved capacitor can have a larger surface area without forming a deeper channel. In a special embodiment, the present invention provides a dynamic random access memory (DRAM) integrated body Circuit. This DRAM integrated circuit has a semiconductor substrate including a recessed area. The recessed area has a vertical side extending from the bottom surface. A field-effect transistor in the source / drain region is provided adjacent to the recessed region. The DRAM integrated circuit further includes an insulating layer overlying the recessed region. An additional layer overlying the insulating layer is provided in a portion of the field The capacitor plate above and below the effect transistor. The capacitor plate is connected to the source / drain region. The DRAM integrated circuit further includes a capacitor dielectric on the lower capacitor plate, and a capacitor on the dielectric plate. Capacitor layer above the electrical layer. The lower capacitor plate, capacitor dielectric, and upper capacitor plate define the capacitor structure. In another embodiment, a method for forming a capacitor structure for forming a dynamic random access memory volume circuit element is provided. The method includes providing a semiconductor substrate and forming a recessed area in the substrate. The recessed area has a vertical side extending from a bottom surface. The method also includes an insulating layer defined to cover the recessed area. A further step provided is forming a source / drain region adjacent to the recessed region. The method includes forming a field effect overlying the insulating layer over a portion Crystal upper and lower electrical capacitor plates. This (please read the precautions on the back before filling this page). This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm). Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Print A7 ___B7 V. Description of the invention (4) The lower capacitor plate is connected to the source / drain region. The method further includes forming a capacitor dielectric on the lower capacitor plate, and forming a capacitor dielectric on the lower capacitor plate. The upper capacitor plate is above the electrical layer. The lower capacitor plate, the capacitor dielectric, and the upper capacitor plate define the capacitor structure. Another embodiment of the present case includes a bit line structure of a dynamic random access memory volume circuit. The bit line structure has a semiconductor substrate including a recessed area. The recessed area has a vertical side extending from a bottom surface. A field effect transistor is defined to abut the recessed area. An insulating layer is defined to cover the recessed area, and a conductor is defined in the recessed area. This conductor is connected to the source / drain region and defines a bit line. Another special embodiment includes a method of forming a bit line structure in a dynamic random access memory volume circuit. The method includes providing a semiconductor substrate and forming a recessed region in the semiconductor substrate. This recessed area has a vertical side extending from the bottom surface. The method further includes the steps of forming an insulating layer defined to cover the recessed area, and forming a field effect transistor adjacent to the recessed area. A conductor is defined in the recessed area. This conductor is connected to the source / drain region and defines a single bit line. The present invention achieves these advantages in the context of known manufacturing techniques. However, the features and advantages of the present invention should be more clearly understood by referring to the detailed description and the accompanying drawings. Fig. 1 is a simple cross-sectional view of a DRAM integrated circuit element according to the present invention. 5 This paper size applies the Chinese National Standard (CNS) Α4 specification (210 × 297 mm) n I! .. I * 1 ± ^--I .- =-II— ------U3 (Please read the Note: Please fill in this page again.) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs® C Industrial Consumer Cooperative A7 B7. 5. Description of the invention (5) Figure 2 is a simplified cross-sectional view of the structure of the DRAM bus line in Figure 1; Figure 4 is another cross-sectional view of the bit line structure of Figure 2; Figure 4 is a schematic top view of the DRAM of Figure 1; and Figures 5-14 are used to illustrate the DRAM integrated circuit components according to the present invention Simplified manufacturing method. [Explanation of Specific Embodiment] I. Structure of Dynamic Random Access Memory Device FIG. 1 is a schematic cross-sectional view of a DRAM integrated circuit device 10 of the present invention. This device is for illustration only, so the scope of patent application should not be limited to this device. Generally speaking, the DRAM device 10 includes a plurality of memory cell regions 12, a cover dielectric layer 14, a top metallization layer 16, a passivation layer 17, and other components. The memory cell region can be fabricated using a conventional CMOS processing technique or the like. Each of the 100 million unit regions I2 is defined in a P-type well region 22, and a field effect transistor 18 is defined in this P-type well region 22. The field-effect transistor system is an N-channel gold oxide semiconductor (MOS) device, which includes a gate electrode 54. The gate electrode 54 (referred to as a word line) covers a thin gate dielectric layer 52. A side wall 56 is defined adjacent to the gate 54 side. Covering the pole 54 is a cap oxide layer (cap 0Xide 1 a y e r) 5 8. An interlayer dielectric 60 is formed to cover the cap oxide layer 58 and is also formed to cover part of the source / drain regions 38,46. 6 paper size per source / drain area Applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling in this page) Installation · A7 ------- --- B7 V. Description of the invention (6) The printing of the employee consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs includes an N-type LDD region 42,48 and an N + -type source / drain region 40,50. As shown, the N + -type source / drain region 40 is connected to a channel capacitor (trr n c h c a p a c i t 0 r) 2 0, which is also defined within the p-well region 2 2. This trench capacitor can be used as a memory storage device to store the charge in a capacitor dielectric 30 located between the lower capacitor plate 26 and the upper capacitor plate 28. The capacitor dielectric can be any suitable insulating material such as Silicon dioxide, silicon nitride, etc. The capacitor dielectric is preferably an interlayer including silicon dioxide, silicon nitride, and silicon dioxide, which is a conventional oxide-nitride-on-oxide; 〇NO ). Of course, other combinations of dielectric materials may be used depending on their applicability. The lower capacitor plate 26 is defined above the field effect transistor 18 and is defined to cover an insulating layer 24 to cover the bottom 32 and sides 34 of the channel. The thickness of this insulating layer is selected to isolate the P-well region from the lower capacitor plate 26. High-quality silicon dioxide materials can be used as this insulation layer for insulation purposes. However, the insulating layer is removed from the upper portion 36 of the channel side 34 to provide electrical contact between the lower capacitor plate 26 and the N + type source / drain region 40. The lower capacitor plate may be any suitable conductive layer. The lower capacitor plate is preferably a polycrystalline silicon layer doped with in-situ doped N-type impurities (such as phosphorus) during the formation process. The lower capacitor plate can also be made into a sandwich structure including multiple metal layers, silicide layers and combinations thereof. In another embodiment, the lower capacitor plate is made of a textured or rough polycrystalline silicon layer. 7 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back first) (Fill in this page again)
*1T __B7 五、發明説明（7 ) 成。此具紋理之複晶矽層（不似平滑之複晶矽層般）具有 小突起，以藉此增加電容器之有效表面積。如所示者，該 下電容器板自溝道底部32上之絕緣層延伸，覆於溝道邊側 34上之絕緣層上，接觸該源/汲極區域40，並延伸於該中 間層介電體60上方，覆於該場效電晶體18之上。 該上電容器板28係界定以覆於該電容介電體30上。此 上電容器板係自該溝道絕緣層底部32延伸，並延伸以覆於 覆蓋該下電容器板之電容介電層上。該上電容器板亦較佳 由於形成過程中摻雜N型雜質之複晶矽層所製成。另一個 可選擇者，該上電容器板亦可製成包含多重金屬層、矽化 物層及其組合等之夾層構造。另一實施例係使用一種由具 紋理或粗糙複晶矽層所製成之上電容器板。此具紋理之複 晶矽層（不似平滑之複晶矽層般）具有小突起，以藉此增 加電容器之有效表面積。 如所示者，本案之包含下電容器板26、電容介電體 30、及上電容器板28之溝道電容器構造，自該溝道底部32 延伸，沿其邊側34延伸，且延伸經該場效電晶體18上方。 因此，可製得基本上比習知電容器構造更長之溝道電容器 構造。 經濟部中央標準局員工消費合作社印製 本案之溝道電容器係被設計成可增加電容而沒有習知 溝道構造之缺失；習知溝道構造往往不易前後一貫地製作 在某深度以上。例如，使用〇.25#m之設計規則時，溝道 深度範圍係自大約8,〇〇〇至大約12,000A，而以大約 8 本紙張尺度適用中國國家標準（CN'S ) A4規格（210 X 297公釐） A7 ___B7五、發明説明（8 ) 經濟部中央標準局員工消費合作社印製 10,000 A爲宜。就位元線及絕緣區而言，該溝道寬度約爲 2，500A。就電容器而言，該溝道寬度約在4,000 A之範圍 左右。此溝道構造設有一下電容器板。此電容器板之厚度 範圍爲大約1，〇〇〇至大約1，400A，而以大約1，200A爲宜。 必須注意的是，一部分之下電容器板係界定以覆於該場效 電晶體以及溝道邊側上。 第2圖係第1圖中DRAM之位元線構造的簡化斷面圖。 本案之位元線構造僅係一說明示例，而不應將申請專利範 圍限定於此。該斷面圖200係包含：P型井區域22及閘極電 極54(或字線）。一位元線204係形成於具有邊側與底部之 溝道201中。此溝道具有一絕緣層，此絕緣層包含一底絕 緣層部分2 0 3及一邊側絕緣層部分2 02，覆蓋其周圍。此絕 緣層係用以隔離位元線與P型井區域22。如所示者，該位 元線係以垂直於該字線54之方式形成，且用來連接於鄰近 該位元線之每一電晶體源/汲極區域。 尤其，該位元線係連接於該場效電晶體18之源/汲極 區域46。此連接係透過該邊側絕緣層部分202中之接點開 口 207而達成。換言之，一部分之邊側絕緣層於位元線形 成前除去，並形成一用於使該源/汲極區域46與該位元線 204接觸之接點開口。如使用0.25#m設計規則（design rule)，則該接點開口寬度係在大約2000至大約2800 A之 範圍，而以大約2200人爲宜。這種接點開口之深度係在大 約2200至2800 A之範圍，而以大約2500 A爲宜。 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁)* 1T __B7 5. Description of the invention (7). This textured polycrystalline silicon layer (unlike a smooth polycrystalline silicon layer) has small protrusions to increase the effective surface area of the capacitor. As shown, the lower capacitor plate extends from the insulating layer on the bottom 32 of the channel, overlies the insulating layer on the side 34 of the channel, contacts the source / drain region 40, and extends over the intermediate dielectric Above the body 60, the field effect transistor 18 is covered. The upper capacitor plate 28 is defined to cover the capacitor dielectric body 30. The upper capacitor plate extends from the bottom 32 of the channel insulation layer and extends to cover the capacitor dielectric layer covering the lower capacitor plate. The upper capacitor plate is also preferably made of a polycrystalline silicon layer doped with N-type impurities during formation. Alternatively, the upper capacitor plate may be made into a sandwich structure including multiple metal layers, silicide layers, and combinations thereof. Another embodiment uses an upper capacitor plate made of a textured or rough polycrystalline silicon layer. This textured polycrystalline silicon layer (unlike a smooth polycrystalline silicon layer) has small protrusions to increase the effective surface area of the capacitor. As shown, the trench capacitor structure of the present case, which includes the lower capacitor plate 26, the capacitor dielectric 30, and the upper capacitor plate 28, extends from the bottom 32 of the channel, extends along its side 34, and extends through the field Above the effect transistor 18. Therefore, a trench capacitor structure substantially longer than the conventional capacitor structure can be obtained. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economics The trench capacitor in this case is designed to increase capacitance without the lack of the conventional trench structure; the conventional trench structure is often difficult to consistently produce above a certain depth. For example, when the design rule of 0.25 # m is used, the channel depth ranges from about 8,000 to about 12,000A, and the Chinese National Standard (CN'S) A4 specification (210 X 297) is applied at about 8 paper sizes. (Mm) A7 ___B7 V. Description of the invention (8) It is advisable for the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs to print 10,000 A. In terms of bit lines and insulating regions, the channel width is approximately 2,500A. For capacitors, this channel width is in the range of about 4,000 A. This trench structure is provided with a lower capacitor plate. The thickness of this capacitor plate ranges from about 1,000 to about 1,400 A, and preferably about 1,200 A. It must be noted that a part of the lower capacitor plate is defined to cover the field effect transistor and the channel side. Fig. 2 is a simplified sectional view of the bit line structure of the DRAM in Fig. 1. The bit line structure in this case is only an illustrative example, and the scope of patent application should not be limited to this. The sectional view 200 includes a P-well region 22 and a gate electrode 54 (or word line). A bit line 204 is formed in a channel 201 having sides and a bottom. The trench has an insulating layer. The insulating layer includes a bottom insulating layer portion 203 and a side insulating layer portion 202, covering the periphery thereof. This insulating layer is used to isolate the bit line from the P-well region 22. As shown, the bit line is formed perpendicular to the word line 54 and is used to connect to each transistor source / drain region adjacent to the bit line. In particular, the bit line is connected to the source / drain region 46 of the field effect transistor 18. This connection is achieved through a contact opening 207 in the side insulating layer portion 202. In other words, a part of the side insulating layer is removed before the bit line is formed, and a contact opening for contacting the source / drain region 46 with the bit line 204 is formed. If a design rule of 0.25 # m is used, the opening width of the contact is in the range of about 2000 to about 2800 A, and preferably about 2200 people. The depth of this contact opening is in the range of about 2200 to 2800 A, and preferably about 2500 A. 9 This paper size applies to China National Standard (CNS) A4 (210X 297mm) (Please read the precautions on the back before filling this page)
五、發明説明（9 ) A7 B7 經濟部中央標準局員工消費合作社印製 該位元線係由一導體材料所製成。該位元線較佳爲一 於形成過程中摻雜N型雜質（例如磷等）之複晶矽層。另 外，該位元線亦可藉沈積複晶矽層及由POC13之擴散行重 度摻雜或藉退火行離子佈植而製成。該位元線受該溝道寬 度及溝道深度所限制。對應於該溝道深度者爲該位元線厚 度，其具有大約1000A之頂部絕緣部分及約500A之底部絕 緣部分。當然，該位元線更可由不同尺寸之其他材料（諸 如Poly cide或多種材料之組合）而製成。 覆於該位元線上者係一頂部絕緣層部分205。此頂部 絕緣部分205係用以隔離該位元線，使之避免覆於諸如閘 極電極等裝置元件上。包含該頂部絕緣層部分205、邊側 絕緣層部分2 0 2及底部絕緣層部分2 0 3之絕緣層部分，係界 定以環繞該位元線之周圍，用以大致上使該位元線與被界 定以環繞該構道周圍之P型井區域及其他裝置元件隔離。如 所示者，該頂部絕緣層205係連接於該邊側絕緣層部分 202，而該邊側絕緣層部分202則連接於底絕緣層部分 2 0 3 « 第3圖係第2圖位元線構造之另一斷面圖300。此斷面 圖係用以舉例說明該位元線2 0 4經由接點開口 2 0 7，與該源 /汲極區域46間之連接。如所示者，該接點開口 207使該 位元線2 0 4可連接至N +型源/汲極區域50。此N+型源/ 汲極區域提供比鄰接之區域更低之電阻，因此， 有助於電荷之傳送，其中該電荷係代表由記億單元之源/ 10 本紙張尺度適用少國國家標準（CNS ) Α4規格（2丨0X297公釐） (請先Μ讀背面之注意事項再填寫本頁V. Description of the invention (9) A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs This bit line is made of a conductive material. The bit line is preferably a polycrystalline silicon layer doped with N-type impurities (such as phosphorus) during the formation process. In addition, the bit line can be made by depositing a polycrystalline silicon layer and heavily doped by a diffusion line of POC13 or by ion implantation by annealing. The bit line is limited by the channel width and channel depth. Corresponding to the depth of the channel is the thickness of the bit line, which has a top insulating portion of about 1000 A and a bottom insulating portion of about 500 A. Of course, the bit line can be made of other materials with different sizes (such as Poly cide or a combination of multiple materials). Overlying the bit line is a top insulating layer portion 205. The top insulating portion 205 is used to isolate the bit line from being covered on a device element such as a gate electrode. An insulating layer portion including the top insulating layer portion 205, the side insulating layer portion 202, and the bottom insulating layer portion 203 is defined to surround the bit line to substantially make the bit line and It is defined to isolate the P-well area and other device elements surrounding the tunnel. As shown, the top insulating layer 205 is connected to the side insulating layer portion 202, and the side insulating layer portion 202 is connected to the bottom insulating layer portion 2 0 3 «Figure 3 is the second bit line Structure of another section view 300. This cross-sectional diagram is used to illustrate the connection between the bit line 204 and the source / drain region 46 through the contact opening 2 07. As shown, the contact opening 207 allows the bit line 204 to be connected to the N + -type source / drain region 50. This N + -type source / drain region provides lower resistance than adjacent regions, and therefore facilitates the transfer of charge, where the charge is represented by the source of billion units / 10 paper standards are applicable to few national standards (CNS) Α4 specification (2 丨 0X297 mm) (Please read the precautions on the back before filling in this page
*1T 妒！ A7 ___B7 五、發明説明（10 ) 經濟部中央標準局員工消費合作社印裝 汲極區域46發至該位元線2〇4之信號。該位元線204與源 /汲極區域46間之連接發生於此N +型源/汲極區域50處》 鄰接於該接點開口 2〇7者係該頂部絕緣層部分205及邊 側絕緣層部分2〇2A。此頂部絕緣層部分2 0 5及邊側絕緣層 部份2 02 A，係分別連接於彼此相接之邊側絕緣層部分202 及底部絕緣層部分。此種絕緣層部分之組合使位元線2(M 與鄰接之裝置元件隔離，但使該位元線2 0 4與該電晶體之 源/汲極區域46相連接。每一DRAM記憶單元均具有此種 位元線連接方式。 第4圖係本案DRAM積體電構造之簡化頂視圖400。此 頂視圖僅係一說明示例，而不應將申請專利範1限定於 此。該頂視圖顯示一具有Y方向及X方向之矩電極 54於X方向上延伸，經界定以覆於P型阱 經縱 向界定於Y方向上之每一下電容器電極2 6^^成於該閘 極5 。複數個位元線204於Y方向上之閘極54下 方垂直於該閘極電極54。每一位元線均包含 複2 0 7，使該位元線連接至該場效電晶體之個別 源/汲極區域。 Π·動態隨機存取記憶體製造技術 將本發明之全部製造方法槪述如下。 (1) 提供一半導體基板； (2) 光罩1 :在該半導體基板內形成Ρ型井； 11 本紙張尺度適用中國國家標準（CNS) Α4規格（210χ297公釐） (請先閲讀背面之注意事項再填{"本頁)* 1T Envy! A7 ___B7 V. Description of the invention (10) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, the signal from the drain region 46 to the bit line 204. The connection between the bit line 204 and the source / drain region 46 occurs at the N + -type source / drain region 50. Adjacent to the contact opening 207 is the top insulating layer portion 205 and the side-to-side insulation Layer part 202A. The top insulating layer portion 205 and the side insulating layer portion 2 02 A are respectively connected to the side insulating layer portion 202 and the bottom insulating layer portion which are in contact with each other. This combination of insulating layer portions isolates bit line 2 (M from adjacent device elements, but connects the bit line 204 to the source / drain region 46 of the transistor. Each DRAM memory cell has It has such a bit line connection method. Figure 4 is a simplified top view 400 of the DRAM integrated electrical structure of this case. This top view is only an illustrative example, and the patent application scope 1 should not be limited to this. This top view shows A moment electrode 54 having a Y direction and an X direction extends in the X direction, and is defined so as to cover each of the lower capacitor electrodes 2 6 ^^ formed in the Y direction in the P-type well. The bit line 204 is perpendicular to the gate electrode 54 below the gate 54 in the Y direction. Each bit line contains a complex 2 0 7 so that the bit line is connected to an individual source / sink of the field effect transistor. Polar area. Π · Dynamic random access memory manufacturing technology describes the entire manufacturing method of the present invention as follows: (1) providing a semiconductor substrate; (2) photomask 1: forming a P-well in the semiconductor substrate; 11 This paper size applies to China National Standard (CNS) A4 (210x297 mm) (please first Note read back surface of the refill {" page)
經濟部中央標準局員工消費合作社印製 A7 --- -B7___ 五、發明説明（11) (3) 光罩2 :在該半導體基板內形成N型井； (4) 形成一包含塾層氧化物（pad oxide)層及氮化政 層之保護層； (5) 光罩3 :形成主動區（active area)以界定溝道區 域； (6) 形成溝道區域； (7) 形成溝道側壁及底部氧化層； (8) 光罩4 :界定位元線接點，及除去光阻劑； (9) 沈積形成過程中摻雜之複晶矽以塡充溝道區域； (10) 回蝕形成過程中摻雜之複晶矽，以使形成過程中 摻雜之複晶矽保持於溝道內； (11) 光罩5 :界定非位元線溝道區域，並除去非位元 線溝道區域中之形成過程中摻雜之複晶矽； (12) 氧化位元線溝道區域內之形成過程中摻雜之複晶 矽； (13) 光罩6 :光罩P型通道區域及植入通道停止區域 (channel stop region)直到該溝道底部； (14) 沈積硼磷矽酸鹽玻璃（BPSG)以塡滿該非位元線 溝道區域中之溝道區域； (15) 從該主動區除去該保護層； (16)進行全面性臨限植入（blanket threshold implant); 12 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---^---r---扣衣------II------r. (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（12 ) (17) 光罩7 :屛蔽N型井區域，並植入P型雜質於該記 憶單元區域（或P型井區域）中以調節臨限電壓； (18) 形成閘極氧化物層； (19) 形成接雜的閘極複晶砂層或Polycide(或jjoly- 1)； (20) 光罩8 :界定閘極複晶矽層以形成閘極電極； (21) 光罩9 :界定N型輕度摻雜汲極（LDD)區域並植 入N型雜質； (2 2 )光罩1 0 :界定P型L D D區域並植入P型雜質； (23)於複晶矽閘極電極之邊側上形成側壁隔片 (sidewall spacer); (24) 光罩11 :界定N +型源/汲極區域並植入N +型雜 質； (25) 光罩12 :界定P +型源/汲極區域並植入P +型雜 質； (26) 光罩13 :以光阻劑覆蓋位元線區域及字線區域， 界定電容器區域； (27) 除去溝道電容區域中之BPSG，並除去光阻劑； (28) 沈積中間複晶矽氧化物層： (29) 光罩14 :界定電容器單元接點區域並蝕刻； (30) 沈積poly-2層並接雜； (31) 光罩15 :界定poly-2層，以形成一下電容器電 極； 13 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0>< 297公釐） n n I - n m II n m I I—- m ! -I I- i - —I m T - 、T (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 --------^___ 五、發明説明（I3 ) (32) 形成單元電容器介電體； (33) 沈積poly-3層並摻雜（或於形成期間摻雜之 P〇ly-3之沉積）； (34) 光罩16 :界定P〇ly-3層，以形成一上電容器電 極； (35) 沈積BPSG/NSG(無摻雜矽酸鹽玻璃），並流整 (flow); (36) 光罩17 :界定BPSG/NSG層中之接點圖樣； (37) 濺射第一金靥層； (38) 光罩18 :界定第一金屬層； (39) 沈積中間金屬氧化物（inter-metal oxide); (40) 光罩19 :界定通道（via)圖樣； (41) 濺射第二金屬層； (42) 光罩20 :界定第二金屬層； (43) 沈積鈍化層及聚醯亞胺塗層； (44)光罩21 :界定打線區（pad region)及熔絲 (fuse)開口區域； (45) 聚醯亞胺熟化（cure); (46) 蝕刻鈍化層以界定打線區；及 (47) 燒結。 此等步驟提供一具有一淺溝道及堆疊電容器板之改良 電容器。每一電容器板均界定於該溝道中、於該場效電晶 體之閘極電極部分上方。因此，達成一較大的電容表面 14 本紙張尺度適用中國國家標準（CNS ) A4規格（210X25»7公釐） ^ τ 4衣 、1Tr (請先閱讀背面之注意事項再填寫本頁) B7 五、發明説明（l4) 積，從而可改善存儲容量。本發明亦提供界定於該溝道中 之位元線結構。此位元線構造係在未使用習知技術之複雜 構形下，連接於各源/汲極區域。此等步驟也純爲說明而 例示者，因而申請專利範圍不應受限於此。以下，參照附 圖說明本方法。 第5〜14圖係顯示本發明DRAM積體電路裝置之簡略 製造方法。本方法純爲說明而例示者，因而申請專利範圍 不應受限於此，該方法係以提供一半導體基板11開始，如 第5圖所說明者。該基板可爲任何適於製造本案積體電路裝 置用之晶圓。舉例而言，由該晶圓著手進行DRAM記憶裝 置之互補金屬氧化物半導體（CMOS)裝置之製造技術。但 依其特殊應用性而可使用其他製造技術。 一光阻光罩係經界定以覆於該半導體基板之上表面 上，以形成P型井區域22。此等P型井區域22係藉由植入 含有P型材料之雜質至該基板中而形成者。P型雜質包括硼 等。該光阻光罩利用習知技術除去。接著，N型通道裝置 可形成於P型井區域中。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) N型井亦可界定於該半導體基板內。尤其，一光阻光 罩形成以覆於該半導體基板之P型井區域上。利用一植入步 驟形成該半導體基板內之該N型井區域。N型雜質包括如 磷、砷等材料。該光阻光罩利用習知技術除去。接著，P型 逋道裝置可形成於N型井區域中。 15 本纸伕尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 ____B7五、發明説明（l5) 經濟部中央標準局員工消費合作社印製 介電層組合501，係界定以覆於該基板上，以形成一 保護層，如第5圖所示。亦即，將該保護層當做一光罩層使 用。此保護層包含一墊層氧化物層503及一覆於上方之氮 化矽層505。該墊層氧化物層厚度爲200至300A。該氮化 矽層爲1200〜1800 A厚。該氮化矽層505亦可自由包含另 一覆於上方之二氧化矽層（未示出）。此等層經規畫以界定 複數個溝道區域，包括一電容器溝道20及一位元線溝道 201，如第6圖所示。 該電容器溝道20及位元線溝道201之形成係以一乾蝕 刻技術達成。乾蝕刻技術之一實例可包括反應性離子蝕刻 (reactive ion etching)、電浆餓刻（plasma etching) 等。較諸習知之電容器深溝而言，該溝道較佳更淺，因而 較易前後一貫地製造。如使用〇.25#m設計規則，則該電 容器溝道深度範圍係從約0.8至約1.2#m間，而以大約 1.0#m爲宜。該溝道同時具有0.4#m之寬度。如使用同 一設計規則，則該位元線溝道深度可與該電容器溝道相 當，在約0.8至約1.2/zm之範圔間，而以大約以l.〇#m爲 宜。此溝道同時具有〇.25#m之寬度。當然，各溝道之深 度與寬度係依其應用而定。 —介電隔離材料層係界定於每一包含電容器溝道20與 位元線溝道201之溝道中，如第7圖所示•尤其，該電容器 溝道20包含一覆於該溝道底部32及溝道邊側34上之介電層 24。該位元線溝道201具有分別覆於該溝道邊側及底部上 16 本紙張尺度適用中國國家標準（CN'S ) A4規格（210X 297公釐） (請先閱讀背面之.注意事項再填寫本頁)Printed by A7 --- -B7 ___ of the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the Invention (11) (3) Photomask 2: Form an N-type well in the semiconductor substrate; (4) Form an oxide containing hafnium layer (Pad oxide) layer and protective layer of nitrided layer; (5) Photomask 3: forming an active area to define a channel area; (6) forming a channel area; (7) forming a channel sidewall and Bottom oxide layer; (8) Photomask 4: boundary element line contacts, and remove photoresist; (9) doped polycrystalline silicon fills the channel region during the deposition process; (10) etchback formation Doped polycrystalline silicon during the process to keep the doped polycrystalline silicon in the channel during the formation process; (11) Photomask 5: Define the non-bit line channel region and remove the non-bit line channel Doped polycrystalline silicon during formation in the region; (12) Doped polycrystalline silicon during formation in the oxidation bit line channel region; (13) Photomask 6: photomask P-type channel region and Enter the channel stop region until the bottom of the channel; (14) deposit borophosphosilicate glass (BPSG) to fill the trench in the non-bit line channel region Area; (15) remove the protective layer from the active area; (16) perform blanket threshold implant; 12 this paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm)- -^ --- r --- Fashion clothes ------ II ------ r. (Please read the notes on the back before filling out this page) Printed by A7, Consumers Cooperative of the Central Bureau of Standards B7 V. Description of the invention (12) (17) Photomask 7: Shield the N-type well area and implant P-type impurities in the memory cell area (or P-type well area) to adjust the threshold voltage; (18) Forming a gate oxide layer; (19) forming a doped gate polycrystalline sand layer or Polycide (or jjoly-1); (20) photomask 8: defining a gate polycrystalline silicon layer to form a gate electrode; (21) ) Photomask 9: Define N-type lightly doped drain (LDD) region and implant N-type impurities; (2 2) Photomask 10: Define P-type LDD region and implant P-type impurities; (23) In Sidewall spacers are formed on the sides of the polycrystalline silicon gate electrode; (24) Photomask 11: Define an N + -type source / drain region and implant N + -type impurities; (25) Photomask 12: Define and implant P + -type source / drain regions Impurities; (26) Photomask 13: Cover bit line area and word line area with photoresist to define capacitor area; (27) Remove BPSG in channel capacitance area and remove photoresist; (28) middle of deposition Polycrystalline silicon oxide layer: (29) Photomask 14: Define the contact area of the capacitor unit and etch; (30) Deposit a poly-2 layer and dope; (31) Photomask 15: Define a poly-2 layer to form Lower capacitor electrode; 13 This paper size applies Chinese National Standard (CNS) A4 specification (2 丨 0 > < 297 mm) nn I-nm II nm II —- m! -I I- i-—I m T- 、 T (Please read the notes on the back before filling in this page) A7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs -------- ^ ___ 5. Description of the Invention (I3) (32) Forming the unit capacitor Electric body; (33) depositing poly-3 layer and doping (or doping of Poli-3 during the formation); (34) photomask 16: defining Poli-3 layer to form a layer Capacitor electrode; (35) Deposition BPSG / NSG (Undoped Silicate Glass) and flow; (36) Photomask 17: Define the contact pattern in the BPSG / NSG layer; (37) Sputtering First gold Layer; (38) photomask 18: defining the first metal layer; (39) depositing an inter-metal oxide; (40) photomask 19: defining a via pattern; (41) sputtering Two metal layers; (42) photomask 20: defining a second metal layer; (43) depositing a passivation layer and a polyimide coating; (44) photomask 21: defining a pad region and a fuse (fuse ) Open area; (45) polyimide cure; (46) etch the passivation layer to define the wire bonding area; and (47) sinter. These steps provide an improved capacitor having a shallow trench and a stacked capacitor plate. Each capacitor plate is defined in the channel, above the gate electrode portion of the field effect transistor. Therefore, a larger capacitor surface is achieved. 14 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X25 »7mm) ^ τ 4 clothing, 1Tr (please read the precautions on the back before filling this page) B7 5 2. Description of the Invention (14), which can improve the storage capacity. The present invention also provides a bit line structure defined in the channel. This bit line structure is connected to each source / drain region without a complicated configuration using conventional techniques. These steps are purely for illustration and illustration, so the scope of patent application should not be limited to this. Hereinafter, this method will be described with reference to the drawings. Figures 5 to 14 show a simplified manufacturing method of the DRAM integrated circuit device of the present invention. This method is purely for illustration and illustration, so the scope of patent application should not be limited to this. The method starts with providing a semiconductor substrate 11 as illustrated in FIG. 5. The substrate may be any wafer suitable for manufacturing the integrated circuit device of the present case. For example, the wafer starts with manufacturing technology of complementary metal oxide semiconductor (CMOS) devices for DRAM memory devices. However, other manufacturing techniques can be used depending on their particular applicability. A photoresist mask is defined to cover the upper surface of the semiconductor substrate to form a P-well region 22. These P-type well regions 22 are formed by implanting impurities containing a P-type material into the substrate. P-type impurities include boron and the like. The photoresist mask is removed using conventional techniques. Next, an N-type channel device may be formed in the P-well region. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling this page) N-type wells can also be defined in the semiconductor substrate. In particular, a photoresist mask is formed to cover the P-well region of the semiconductor substrate. An implantation step is used to form the N-well region in the semiconductor substrate. N-type impurities include materials such as phosphorus and arsenic. The photoresist mask is removed using conventional techniques. Then, a P-type tunnel device may be formed in the N-type well region. 15 This paper scale is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) A7 ____B7 V. Description of invention (l5) The dielectric layer combination 501 printed by the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is defined to cover the A protective layer is formed on the substrate, as shown in FIG. 5. That is, the protective layer is used as a photomask layer. The protective layer includes a pad oxide layer 503 and a silicon nitride layer 505 overlying the protective layer. The underlayer oxide layer has a thickness of 200 to 300A. The silicon nitride layer is 1200 to 1800 A thick. The silicon nitride layer 505 may also include another silicon dioxide layer (not shown) overlying the silicon nitride layer 505. These layers are planned to define a plurality of channel regions, including a capacitor channel 20 and a bit line channel 201, as shown in FIG. The capacitor channel 20 and the bit line channel 201 are formed by a dry etching technique. An example of the dry etching technique may include reactive ion etching, plasma etching, and the like. This trench is better and shallower than conventional deep trenches for capacitors, and is therefore easier to manufacture consistently. If a design rule of 0.25 # m is used, the depth of the capacitor channel ranges from about 0.8 to about 1.2 # m, and preferably about 1.0 # m. The channel also has a width of 0.4 # m. If the same design rule is used, the depth of the bit line channel can be equivalent to that of the capacitor channel, in the range of about 0.8 to about 1.2 / zm, and preferably about 1.0 # m. This channel also has a width of 0.25 # m. Of course, the depth and width of each channel depends on its application. —The dielectric isolation material layer is defined in each of the channels including the capacitor channel 20 and the bit line channel 201, as shown in FIG. 7. In particular, the capacitor channel 20 includes a channel 32 that covers the bottom 32 of the channel. And a dielectric layer 24 on the channel side 34. The bit line channel 201 has 16 paper covering the sides and bottom of the channel, respectively. This paper size is applicable to the Chinese National Standard (CN'S) A4 specification (210X 297 mm) (Please read the notes on the back before filling in this. page)
經濟部中央標準局員工消費合作社印製 A7 _____B7 五、發明説明（托） 之邊側介電層部分2 0 2及底部介電層部分2 0 3。此等溝道較 佳經矽之熱氧化而爲一氧化層所覆蓋。此氧化層具有一足 以將其覆蓋構造與基板及其他裝置元件隔離之厚度•該氧 化層較佳具有一自約400至約600 A範圍之厚度，而以大約 5 0 0 A爲宜。該溝道亦可藉化學氣相沉積法（CVD)或其他適 合的技術而沈積塗佈上一氧化物層或多重介電層。當然， 該介電層材料及其厚度係依其應用性而定。 形成於該等位元線溝道中之介電層中位元線接點，係 利用光罩及蝕刻技術而加以界定。此等位元線接點係界定 爲覆於該溝道邊側上之介電層中之接點開口 207 »在使用 一氧化物介電層之實施例方面，該等接點開口係藉由以光 阻劑塗覆包含溝道之基板之上表面而製得。在塗覆後進行 規畫光阻圓案以形成覆於該等接點上之外露區域，以及濕 蝕刻該外露區域以形成該位元線接點開口之步驟。每一此 等位元線接點開口爲〇.25/zm寬及3000 A深。然後，使用 習知技術除去該光阻。在稍後之處理步驟期間，該接點開 口提供一通道（via)構造，以將該位元線連接至每一場效電 晶體之源/汲極區域。 接著，使用形成過程中摻雜之複晶矽塡充層801塡充 此等溝道，如第8圖所示。使該於形成過程中摻雜之複晶矽 層進行重度摻雜，以提供一特定之導電係數。此摻雜較佳 爲例如使用磷之N型摻雜，且在約2Χ102()至約6X10^原 子/ cm3之濃度範圍內’而以4Xl〇2fl原子/cm3爲宜。在該 17 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） _ 裝— I 訂------髮 (請先閱讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（17 ) 位元線溝道中，該摻雜複晶矽層塡滿該接點開口並覆於該 基板表面上而形成。此基板表面將形成該場效電晶體之源 /汲極區域。 於形成過程中摻雜之複晶矽層上方部分係藉一蝕刻步 驟除去。此蝕刻步驟亦除去一些於形成過程中摻雜之溝道 中複晶矽層。該複晶矽之頂面較佳距該矽基板之頂面大約 1000A。此蝕刻步驟之實例包括電漿蝕刻、反應性離子蝕 刻等。 將該於形成過程中摻雜之複晶矽從該等非位元線溝道 區域除去。亦即，將該於形成過程中摻雜之複晶矽從該電 容器溝道，而非該位元線溝道，除去。在一實施例中，此 摻雜複晶矽之移除*係藉由以光阻劑塗覆該基板之頂面， 再使覆於該電容器溝道上之區域外露而發生。接著以一蝕 刻步驟將該摻雜之多晶矽由此等電容器溝道中除去。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 當除去形成過程中摻雜之複晶矽時，每一電容器溝道 則變空，而絕緣層仍存在。該電容器溝道係利用一塡料材 料塡充。此塡料材料應易於使用、具有良好之屛蔽特性， 並可於稍後之處理步驟期間可選擇性地被除去者。在一實 施例中，利用BPSG 901塡充此等溝道，如第9圖所示。 當然，視其應用性，也可使用其他材料。 該位元線溝道中之於形成過程中摻雜之複晶矽上方部 分2 05，係藉熱處理而氧化，如第9圖所示。此複晶矽層係 暴露於高溫及一氧化化合物，例如氧，水等。該形成過程 18 本紙張又度適用中國國家標準（CNS ) A4規格（210X297公釐） 五、發明説明（18) A7 B7 經濟部中央標隼局員工消費合作社印製 中摻雜層之熱處理使複晶矽轉化成一具有絕緣性質之二氧 化矽層。此二氧化矽層具有大約400至約600 A範圍間之厚 度，而以大約500 A爲宜。此厚度必須足以使該位元線與覆 於上方之裝置元件隔離。當然，也可使用其他技術（例如 CVD等）來形成此二氧化矽層。 然後，於該基板中形成通道停止區域。在一實施例 中，進行P型通道區域之光罩步驟及通道停止區域之佈植步 驟。該植入步驟較佳發生至一對應於該溝道底部之深度。 該通道停止佈植係使用例如磷等之N型佈植· 將該保護層從該主動區域中除去，如進一步於第9圖中 所示者。該保護層包含二氧化矽及氮化矽。可使用乾蝕刻 技術或濕蝕刻，例如磷酸等，將該氮化矽層除去。覆於該 基板上之二氧化矽必須選擇性地除去，以避免傷害到該基 板》在一實施例中，使用氫氟酸溶液等來選擇性地除去該 二氧化矽。當然，視其應用性，可使用其他技術。 將該CMOS過程典型化之N型通道MOS裝置及P型通 道PMOS裝置，係分別形成至該P型井區域及N型井區域 上。DRAM記憶單元係界定在該P型并區域中。此等裝置 之製造係利用下述步驟而進行。 接著對該基板之整個表面進行臨限佈植（threshold implant) »此佈植係經進行以全面性地將N型雜質同時覆 於P型及N型井區域上。在一實施例中，該N型雜質包含 磷、砷等。 19 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -------^----裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 A7 B7 五、發明説明（I9) 一光阻光罩係界定以覆於N型井區域上以便植入P型雜 質，例如硼。此P型植入步驟，係用來設定每一記憶單元中 N型通道裝置之臨限電壓。該佈植係視閘極氧化物層之厚 度而定。另外，亦可於N型雜質之前，先行植入P型雜質。 一閘極氧化物層52係形成以覆於該P型井區域之頂 面，如第10圖所示。該閘極氧化物層係一髙品質之氧化 物，且薄至足以提升該裝置之有效切換。此種閘極氧化物 層之厚度典型上在大約90 A至約110 A之範圍間，而以大約 1 0 0 A爲宜。 一覆於該氧化物層上之複晶矽層係利用一沈積步驟而 形成。該複晶矽層或P〇lycide(在複晶矽上之WSix)之厚 度範圍係在大約2500至大約3500 A間，而以大約3000 A爲 宜。同時，該複晶矽層一般以大約4X102〇至6X102(i原子 / c m 3 (較佳爲5 X 1 0 2 Q原子/ c m 3 )濃度之N型雜質摻雜。 —植入及退火之步驟用以提供N型雜質於該複晶矽中。另 外，亦可使N型雜質於複晶矽層形成時同時擴散或形成， 以減少處理步驟。就Poly cide閘極之實施例而言，可使用 並摻雜1500 A左右之較薄複晶矽，再沈積大約1000 A之 WSix。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 規畫該複晶矽層或Polycide之圖案係用以界定該複晶 矽閘極54，如第10圖所示。此等稱做字線之閘極電極經常 藉任何適當的一系列光學顯影步驟（包括上光罩、顯像、蝕 刻等）而形成。各閘極電極包含具有基本上垂直外觀之邊 20 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（20 ) 緣，但也可具有基本上非垂直之外観。該各閘極電極之確 切幾何形狀係依其應用性而定。 一全面性之佈植步驟係利用各閘極電極作爲一光罩， 將N型雜質引入一部分井中，以界定該等P型井22中之N-型LDD區域42,48。該N型雜質之劑量範圍係在大約IX 1013至5X1013原子/cm2間，而以大約3X1013原子/cm3 爲宜。進行植入之角度範圍從與通道方向正交之線起算大 於〇°之角度（較佳約30° )至大約45°間。另一可選擇 的是，屛蔽N型井區域，並對P型井區域將作N型植入，以 界定N型LDD區域。此系列步驟係用以界定記憶單元中之 N型L D D區域。 接，屛蔽P型井區域，並將P型雜質導入N型井區域 中。此等植入係用著以界定該N型井區域中之P -型LDD® 域，P-型LDD區域包含大約1X1013至5X1013原子/cm2 範圍之劑量，而以大約3 X1013原子/cm2爲宜。視其應用 性，該P·型LDD區域可使用具角度之佈植（angle implant)。 側壁隔片56係界定在各複晶矽閘極54之邊緣上。該等 側壁隔片56—般藉由沈積一介電材料層、使該層緻密化、 及除去該層之水平表面等步驟而形成。此層係由一諸如二 氧化矽、氮化矽、其組合等材料所製成》該使介電材料層 緻密化之步驟，係用以封住該複晶矽閘極54，以與覆於其 上之各層（例如二氧化矽、氮化矽、其組合等之介電材 21 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝· 、-° A7 B7 五、發明説明（21 ) 料）隔離。於該緻密化介電層上所進行之非等向蝕刻，係 用以除去形成側壁隔片之此層之水平表面。該非等向蝕刻 步驟除去介電材料之水平表面，而留下該側壁隔片。該非 等向蝕刻步驟包含諸如反應性離子蝕刻、電漿蝕刻等技 術。 各MOS裝置之源/汲極區域係藉上光罩及佈植步驟而 界定。尤其，利用一光阻光罩保護界定P型通道裝置之區 域，而使源/汲極區域外露，以爲該N型通道裝置所用。 將N +型雜質植入這些外露區域以界定該N +型源/汲極區 域40,50，如第10圖所示。此等雜質包含磷等。該N +型雜 質之劑量範圍係在大約3X101S原子/cm2至大約5X101S 原子/cm2間，而以大約4 X1015原子/cm2爲宜。進行植入 之角度範圍係從與通道方向正交之線起算約0°至約7° 間，而以大約0度爲宜》該光阻光罩係藉由習知技術除去》 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 接著，以另一光阻光罩保護該Ν型通道裝置，並使該 等源/汲極區域外露，以爲該Ρ型通道裝置所用。把Ρ +型 雜質導入該Ρ型通道裝置之源/汲極區域中》Ρ +型雜質之 劑量範圍係在大約3Χ1015至5Χ1015原子/ cm2之間，而 以大約4X1015原子/ cm2爲宜。然後，使用習知技術除去 該光阻光罩。 然後，於該基板之頂面上光罩以界定該等溝道電容器 區域上方之開口。亦即，以一光阻光罩覆蓋該位元線及字 線。將該BPSG 901從該等溝道電容器區域中除去。在一 22 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公簸） A7 -__B7 五、發明説明（22) 經濟部中央標準局員工消費合作社印繁 實施例中，以使用氫氟酸之濕鈾刻步驟選擇性地將BPSG 層由該溝道中除去，而留下該等絕緣區域24。另外，亦可 使用乾蝕刻技術以可選擇性地將BPSG層由該溝道中除 去。然後，使用習知技術除去該光阻光罩。 一覆於該閘極電極54上之中間層介電體60係以一 CVD方法形成，如第11圖所示。此中間層介電體可爲一包 含TEOS等之適合材料。該如二氧化矽等之中間層介電體 係以一諸如APCVD、PECVD、LPCVD等之技術而沈 積。當然，所使用之技術依其應用性而定。 接著進行之步驟爲，提供一覆於該包含電容器溝道之 基板頂面區域上之光阻光罩，俾形成覆於記憶單元接點區 域36上之外露區域。此等隔離區域中之記憶單元接點區域 或開口，係藉蝕刻技術來界定，如第11圖所示。此等蝕刻 技術之實例包括電漿蝕刻、反應性離子蝕刻等。另外，亦 可使用選用諸如氫氟酸作爲選擇性蝕刻劑之濕蝕刻技術。 如圖所示，各開口係供作將下電容器電極連接至該場效電 晶體源/汲極區域之用。該開口係比該基板之表面還低大 約2 0 0 0 A源/汲極區域之頂部於下一步驟前基本 上不使用一稀酸浸漬或乾蝕刻技術來淸潔該 源/汲^^域。 下一步驟係沈積一覆於該隔離區域及該源/汲極區域 之外露部分36上之下電容器電極層。該下電容器層亦提供 於該中間層介電體60之頂部1201上，藉以進一步增加電容 23 本紙悵尺度適用中國國家標準（CNS ) Α4規格（21 〇 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 A7 ___B7 五、發明説明（23) 經濟部中央標準局^C工消費合作社印製 器單元之表面積。此增加之表面積提供了電容之增加。該 下電容器層較佳由經雜質重度摻雜以降低電阻之複晶矽所 製。該雜質之引入，係視其適用性而選用多重角度佈植技 術或於形成期間摻雜。在一實施例中，該等雜質爲N型， 例如，磷等。 上光罩及蝕刻之步驟將下電容器層界定於一下電容器 電極板26內，如第12圖所示。此下電容器電極板26係透過 該接點開口 36連接至該場效電晶體源/汲極區域38。然 後，利用習知技術除去該光阻層。在製造一上覆之介電體 前，利用乾蝕刻等潔該下電容器層。 —電容器介成以覆於該下電容器板上。此電 容器介電層係用^^"儲該下電容器板及一上電容器板間之 電荷。在一實施例中，該電容器介電層爲一高品質氮化物/ 氧化物複合層。在一較佳實施例中，該電容器介電層包含 一覆於該下電容器板上之二氧化矽層、一覆於該二氧化矽 層上之氮化矽層、及另一覆於該氮化物層之二氧化矽層。 此組合層提供髙存儲容量之特性並易於製作。 完成該電容器構造之後，一上電容器層沉積以覆於該 電容器介電層上。此上電容器層可爲一經重度摻雜以降低 電阻之複晶矽層。該複晶矽層可視其適用性而選用多重角 度佈植技術或於形成期間摻雜。上光罩及蝕刻之步驟將該 上電容器層界定於一上電容器板，如第13圖所示。由該下 電容器板，該電容器介電層及該上電容器板界定出該電容 24 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（24 ) 器構造。如圖所示，一部分之電容器構造位於該場效電晶 體及該溝道上方以增加電容器表面積，藉以提供較大之電 容。 BPSG/NSG之厚層14沈積以覆於整個基板頂面上。 BPSG/NSG組合層以典型之CVD技術沈積而成。該等 BPSG/NSG層將該下方裝置構造與上方之噴鍍金屬 (metallization)隔離。使用一退火步驟以流整該 BPSG/NSG層。此等層之表面罩以光阻而界定出接點開 口。利用一蝕刻方法而形成此等接點開口。然後，利用習 知技術除去該光阻。 —第一金屬層形成以覆於這些層上，並形成於該等接 點開口中以便電連接》利用上光罩及蝕刻之步驟規畫該第 —金屬層16之圖案，如第14圖所示。一中間金靥氧化物層 17沉積以覆於該圖案形成之第一金屬層16上。此中間金屬 氧化物層以典型的CVD技術沈積。 利用習知光阻及蝕刻技術將一通道圖案（via pattern) 界定於該中間金靥氧化物層中。此通道圖案具有供第一金 屬層與第二金屬層間電接觸之開口。將此第二金靥層噴鍍 以覆於該中間金屬氧化物上，並噴鍍於該等通道中。一規 畫圖案之步驟界定出該第二金屬層。 其餘之製造步驟包括一含氮化矽層及二氧化矽層之鈍 化層之沈積。規畫該鈍化層之圖案以形成接合打線 (bonding pad)區開口與溶絲（fuse)開口。該等開口係 25 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） ^ ；---士衣-- (請先閱讀背面之注意事項再填寫本頁) ,^τ 铲 A7 B7 五、發明説明（25) 藉蝕刻技術而製成。然後使用聚醯亞胺塗覆整個表面。最 後再用一上光罩及蝕刻步驟規畫此被塗覆表面之圖案。圖 案形成後，熟化該被塗覆表面。進—步之步驟包含晶圓排 序、裝配、測試等。 以上之說明雖是特定實施例之整個詳細說明，惟可適 用各種修飾、變形構造及等效手段。例如，上述之說明雖 是以DRAM之構造爲說明之根據，惟亦可以用SRAM等來 實現本發明。 因此，不應將上述之說明及例證當做本發明範圍之限 定。本發明之範圍應由添附之申請專利範圍所界定。 m ^^^^1 n^i n^i * —^n 0¾ 、va (請先閱讀背面之注意事項再填寫本頁). Μ 經濟部中央標準局員工消費合作社印製 6 2 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐）Printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _____B7 V. The side dielectric layer part 202 and the bottom dielectric layer part 203 of the invention description (support). These channels are better covered by an oxide layer by thermal oxidation of silicon. The oxide layer has a thickness sufficient to isolate its covering structure from the substrate and other device elements. The oxide layer preferably has a thickness ranging from about 400 to about 600 A, and more preferably about 500 A. The channel can also be deposited and coated with an oxide layer or multiple dielectric layers by chemical vapor deposition (CVD) or other suitable techniques. Of course, the material of the dielectric layer and its thickness depend on its applicability. The bit line contacts of the dielectric layer formed in the bit line channels are defined using a photomask and an etching technique. These bit line contacts are defined as contact openings 207 in the dielectric layer overlying the sides of the channel. In an embodiment using an oxide dielectric layer, the contact openings are formed by It is prepared by coating the upper surface of the substrate containing the channel with a photoresist. After coating, a photoresist pattern is formed to form exposed areas overlying the contacts, and the exposed areas are wet-etched to form the bit line contact openings. Each of these bit line contact openings is 0.25 / zm wide and 3000 A deep. This photoresist is then removed using conventional techniques. During a later processing step, the contact opening provides a via structure to connect the bit line to the source / drain region of each field effect transistor. Next, these channels are filled with a polycrystalline silicon filling layer 801 doped during formation, as shown in FIG. The polycrystalline silicon layer doped during the formation process is heavily doped to provide a specific conductivity. This doping is preferably, for example, N-type doping using phosphorus, and is preferably in a concentration range of about 2 × 102 () to about 6 × 10 ^ atoms / cm3 ', and preferably 4 × 10 2 fl atoms / cm3. In these 17 paper sizes, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied. _ Packing — I Order ---- --- (Please read the precautions on the back before filling out this page) A7 B7 5 Explanation of the invention (17) In the bit line channel, the doped polycrystalline silicon layer fills the contact opening and is formed on the surface of the substrate. The source / drain region of the field effect transistor will be formed on the substrate surface. The portion above the doped polycrystalline silicon layer during the formation process is removed by an etching step. This etching step also removes some of the polycrystalline silicon layer in the channel that was doped during the formation process. The top surface of the polycrystalline silicon is preferably about 1000A from the top surface of the silicon substrate. Examples of this etching step include plasma etching, reactive ion etching, and the like. The polycrystalline silicon doped during the formation process is removed from the non-bit line channel regions. That is, the polycrystalline silicon doped during the formation process is removed from the capacitor channel instead of the bit line channel. In one embodiment, the removal of the doped polycrystalline silicon * occurs by coating the top surface of the substrate with a photoresist, and then exposing the area overlying the capacitor channel. The doped polycrystalline silicon is then removed from the capacitor channels by an etching step. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the notes on the back before filling this page). When the doped polycrystalline silicon is removed during the formation process, each capacitor channel becomes empty, and the insulation layer still exists. The capacitor channel is filled with a material. This material should be easy to use, have good shielding properties, and can be selectively removed during later processing steps. In one embodiment, these channels are filled with BPSG 901, as shown in FIG. Of course, depending on its applicability, other materials can also be used. The upper part of the bit line channel doped with polycrystalline silicon during the formation process is 205, which is oxidized by heat treatment, as shown in FIG. The polycrystalline silicon layer is exposed to high temperatures and monoxide compounds, such as oxygen and water. During the forming process, 18 papers are again applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). 5. Description of the invention (18) A7 B7. The crystalline silicon is transformed into a silicon dioxide layer having insulating properties. The silicon dioxide layer has a thickness in the range of about 400 to about 600 A, and preferably about 500 A. This thickness must be sufficient to isolate the bit line from the device elements overlying it. Of course, other techniques (such as CVD) can also be used to form the silicon dioxide layer. Then, a channel stop region is formed in the substrate. In one embodiment, a mask step of the P-type channel region and a step of implanting the channel stop region are performed. The implantation step preferably occurs to a depth corresponding to the bottom of the channel. The channel stop implantation system uses N-type implantation such as phosphorus. The protective layer is removed from the active area, as further shown in FIG. 9. The protective layer includes silicon dioxide and silicon nitride. The silicon nitride layer may be removed using a dry etching technique or a wet etching technique such as phosphoric acid. The silicon dioxide overlying the substrate must be selectively removed to avoid damaging the substrate. In one embodiment, a hydrofluoric acid solution or the like is used to selectively remove the silicon dioxide. Of course, depending on its applicability, other techniques can be used. The N-channel MOS device and the P-channel PMOS device typical of the CMOS process are formed on the P-well region and the N-well region, respectively. DRAM memory cells are defined in the P-type parallel region. These devices are manufactured using the following steps. Threshold implant is then performed on the entire surface of the substrate »This implantation system is performed to comprehensively cover the P-type and N-type well regions simultaneously. In one embodiment, the N-type impurity includes phosphorus, arsenic, and the like. 19 This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) ------- ^ ---- installed-(Please read the precautions on the back before filling this page) Order A7 B7 5. Description of the Invention (I9) A photoresist mask is defined to cover the N-type well area for implanting P-type impurities, such as boron. This P-type implantation step is used to set the threshold voltage of the N-type channel device in each memory cell. The planting system depends on the thickness of the gate oxide layer. In addition, P-type impurities may be implanted before N-type impurities. A gate oxide layer 52 is formed to cover the top surface of the P-well region, as shown in FIG. The gate oxide layer is a high-quality oxide, and is thin enough to enhance the effective switching of the device. The thickness of such a gate oxide layer is typically in the range of about 90 A to about 110 A, and preferably about 100 A. A polycrystalline silicon layer overlying the oxide layer is formed using a deposition step. The thickness of the polycrystalline silicon layer or Polycide (WSix on polycrystalline silicon) ranges from about 2500 to about 3500 A, and preferably about 3000 A. At the same time, the polycrystalline silicon layer is generally doped with N-type impurities at a concentration of about 4 × 10 2 to 6 × 102 (i atoms / cm 3 (preferably 5 × 10 2 Q atoms / cm 3)). —Implantation and annealing steps It is used to provide N-type impurities in the polycrystalline silicon. In addition, N-type impurities can also be diffused or formed at the same time as the polycrystalline silicon layer is formed, so as to reduce the processing steps. For the embodiment of the poly cide gate, the Use and dope a thinner polycrystalline silicon at about 1500 A, and deposit about 1000 A of WSix. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (Please read the precautions on the back before filling this page) Plan the polycrystalline silicon layer Or Polycide's pattern is used to define the polysilicon gate 54 as shown in Figure 10. These gate electrodes, called word lines, often use any suitable series of optical development steps (including photomask, display Image, etching, etc.). Each gate electrode includes edges with a substantially vertical appearance. 20 paper sizes are applicable to Chinese National Standards (CNS) A4 specifications (210X297 mm). Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. A7 B7 5. Description of the Invention (20) Fate, However, it can also have a substantially non-vertical outer periphery. The exact geometry of the gate electrodes depends on their applicability. A comprehensive implantation step uses each gate electrode as a mask to remove N-type impurities Introduced into some wells to define the N-type LDD regions 42,48 in these P-type wells 22. The dosage range of this N-type impurity is between about IX 1013 to 5X1013 atoms / cm2, and about 3X1013 atoms / cm3 The angle of implantation ranges from an angle greater than 0 ° (preferably about 30 °) to about 45 ° from a line orthogonal to the channel direction. Alternatively, the area of the N-well can be shielded, and N-type implantation will be performed on the P-type well region to define the N-type LDD region. This series of steps is used to define the N-type LDD region in the memory unit. Then, shield the P-type well region and introduce P-type impurities N-well region. These implants are used to define the P-type LDD® domain in the N-well region. The P-type LDD region contains a dose in the range of approximately 1X1013 to 5X1013 atoms / cm2, and at approximately 3 X1013 atom / cm2 is suitable. Depending on its applicability, the P · type LDD area can be used to angle the device (ang le implant). The sidewall spacers 56 are defined on the edges of each of the polycrystalline silicon gates 54. The sidewall spacers 56 are generally formed by depositing a layer of dielectric material, densifying the layer, and removing the layer. The surface is formed by steps such as a horizontal surface. This layer is made of a material such as silicon dioxide, silicon nitride, a combination thereof, etc. The step of densifying the dielectric material layer is used to seal the polycrystalline silicon gate The pole 54 is made of dielectric materials such as silicon dioxide, silicon nitride, combinations thereof, etc. on this layer. 21 This paper is applicable to China National Standard (CNS) A4 specification (210 × 297 mm) (please first Read the precautions on the back and fill out this page.) Installation,-° A7 B7 V. Invention Description (21) Material) Isolation. The non-isotropic etching performed on the densified dielectric layer is used to remove the horizontal surface of this layer forming the sidewall spacers. The anisotropic etching step removes the horizontal surface of the dielectric material, leaving the sidewall spacers. The anisotropic etching step includes techniques such as reactive ion etching, plasma etching, and the like. The source / drain regions of each MOS device are defined by masking and implanting steps. In particular, a photoresist mask is used to protect the area defining the P-channel device, and the source / drain region is exposed for use by the N-channel device. N + -type impurities are implanted into the exposed regions to define the N + -type source / drain regions 40,50, as shown in FIG. These impurities include phosphorus and the like. The dose range of the N + -type impurity is between about 3X101S atoms / cm2 and about 5X101S atoms / cm2, and preferably about 4X1015 atoms / cm2. The angle of implantation ranges from about 0 ° to about 7 ° from a line orthogonal to the direction of the channel, and is preferably about 0 degrees. "The photoresist mask is removed by conventional techniques." Central Standard of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperative (please read the precautions on the back before filling this page). Then, protect the N-channel device with another photoresist mask and expose the source / drain regions as the P-type. For channel installations. Introducing P + -type impurities into the source / drain region of the P-type channel device. The dosage range of P + -type impurities is between about 3 × 1015 to 5 × 1015 atoms / cm2, and preferably about 4 × 1015 atoms / cm2. The photoresist is then removed using conventional techniques. Then, a mask is formed on the top surface of the substrate to define openings above the trench capacitor regions. That is, the bit line and the word line are covered with a photoresist mask. This BPSG 901 was removed from the channel capacitor regions. In a 22-paper standard that applies the Chinese National Standard (CNS) A4 specification (210X297 male dust) A7 -__ B7 V. Description of the invention (22) In the embodiment of the Printing and Printing Cooperative of the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, The wet uranium etch step selectively removes the BPSG layer from the trench, leaving the insulating regions 24. Alternatively, dry etching techniques can be used to selectively remove the BPSG layer from the channel. The photoresist is then removed using conventional techniques. An interlayer dielectric 60 overlying the gate electrode 54 is formed by a CVD method, as shown in FIG. This interlayer dielectric may be a suitable material containing TEOS or the like. The interlayer dielectric such as silicon dioxide is deposited by a technique such as APCVD, PECVD, LPCVD, and the like. Of course, the technology used depends on its applicability. The next step is to provide a photoresist mask over the top surface area of the substrate including the capacitor channel, and form an exposed area overlying the contact area 36 of the memory cell. The contact areas or openings of the memory cells in these isolated areas are defined by etching techniques, as shown in FIG. 11. Examples of such etching techniques include plasma etching, reactive ion etching, and the like. Alternatively, a wet etching technique using, for example, hydrofluoric acid as a selective etchant may be used. As shown, each opening is used to connect the lower capacitor electrode to the field effect transistor source / drain region. The opening is about 2 0 0 A lower than the surface of the substrate. The top of the source / drain region is substantially cleaned of the source / drain region without using a dilute acid dipping or dry etching technique before the next step. . The next step is to deposit a capacitor electrode layer above and below the isolation region and the exposed portion 36 of the source / drain region. The lower capacitor layer is also provided on the top 1201 of the interlayer dielectric 60 to further increase the capacitance. 23 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 0X 297 mm). (Please read the back Note: Please fill in this page again) Pack. Order A7 ___B7 V. Description of the invention (23) Surface area of the printer unit of the Central Standards Bureau of the Ministry of Economic Affairs ^ C Industrial Consumer Cooperative. This increased surface area provides an increase in capacitance. The lower capacitor layer is preferably made of polycrystalline silicon heavily doped with impurities to reduce resistance. The introduction of this impurity is based on its applicability, using a multi-angle implant technique or doping during formation. In one embodiment, the impurities are N-type, such as phosphorus. The steps of upper mask and etching define the lower capacitor layer in the lower capacitor electrode plate 26, as shown in FIG. The lower capacitor electrode plate 26 is connected to the field effect transistor source / drain region 38 through the contact opening 36. The photoresist layer is then removed using conventional techniques. Before manufacturing an overlying dielectric, the lower capacitor layer is cleaned by dry etching or the like. -The capacitor is interposed to cover the lower capacitor plate. This capacitor dielectric layer is used to store the charge between the lower capacitor plate and an upper capacitor plate. In one embodiment, the capacitor dielectric layer is a high-quality nitride / oxide composite layer. In a preferred embodiment, the capacitor dielectric layer includes a silicon dioxide layer overlying the lower capacitor board, a silicon nitride layer overlying the silicon dioxide layer, and another overlying the nitrogen SiO2 layer. This combination layer provides the characteristics of storage capacity and is easy to make. After the capacitor structure is completed, an upper capacitor layer is deposited to cover the capacitor dielectric layer. The upper capacitor layer may be a polycrystalline silicon layer that is heavily doped to reduce resistance. Depending on its applicability, the polycrystalline silicon layer may be multi-angle implanted or doped during formation. The steps of masking and etching define the upper capacitor layer to an upper capacitor plate, as shown in FIG. 13. The capacitor is defined by the lower capacitor plate, the capacitor dielectric layer and the upper capacitor plate. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page. ) Order. Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, printed A7 B7 V. Description of Invention (24) Device structure. As shown in the figure, a part of the capacitor structure is located above the field effect transistor and the channel to increase the surface area of the capacitor, thereby providing a larger capacitance. A thick layer 14 of BPSG / NSG is deposited to cover the entire top surface of the substrate. The BPSG / NSG combination layer is deposited by a typical CVD technique. The BPSG / NSG layers isolate the underlying device structure from the metallization above. An annealing step is used to smooth the BPSG / NSG layer. The surface covers of these layers define the contact openings with photoresist. These contact openings are formed by an etching method. This photoresist is then removed using conventional techniques. —The first metal layer is formed to cover these layers and is formed in the contact openings for electrical connection. ”The pattern of the first—metal layer 16 is planned using the steps of masking and etching, as shown in FIG. Show. An intermediate gold hafnium oxide layer 17 is deposited on the first metal layer 16 formed in the pattern. This intermediate metal oxide layer is deposited using a typical CVD technique. A conventional photoresist and etching technique is used to define a via pattern in the intermediate gold hafnium oxide layer. The channel pattern has an opening for electrical contact between the first metal layer and the second metal layer. The second metal layer is spray-coated to cover the intermediate metal oxide and is spray-plated into the channels. A step of patterning defines the second metal layer. The remaining manufacturing steps include the deposition of a passivation layer containing a silicon nitride layer and a silicon dioxide layer. The pattern of the passivation layer is planned to form a bonding pad opening and a fuse opening. These openings are 25 paper sizes applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) ^; --- Shiyi-(Please read the precautions on the back before filling this page), ^ τ shovel A7 B7 V. Description of Invention (25) Made by etching technology. Polyimide was then used to coat the entire surface. Finally, a photomask and etching steps are used to plan the pattern of the coated surface. After the pattern is formed, the coated surface is cured. The further steps include wafer sequencing, assembly, and testing. Although the above description is the entire detailed description of the specific embodiment, various modifications, deformation structures, and equivalent means can be applied. For example, although the above description is based on the structure of DRAM, the present invention can also be implemented by using SRAM or the like. Therefore, the above descriptions and illustrations should not be taken as limiting the scope of the present invention. The scope of the invention should be defined by the scope of the attached patent application. m ^^^^ 1 n ^ in ^ i * — ^ n 0¾, va (Please read the notes on the back before filling out this page). Μ Printed by the Staff Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy 6 2 This paper size applies to China National Standard (CNS) Α4 specification (210 × 297 mm)