TW367590B - Integrated circuit of standard cells - Google Patents

Integrated circuit of standard cells

Info

Publication number
TW367590B
TW367590B TW086119689A TW86119689A TW367590B TW 367590 B TW367590 B TW 367590B TW 086119689 A TW086119689 A TW 086119689A TW 86119689 A TW86119689 A TW 86119689A TW 367590 B TW367590 B TW 367590B
Authority
TW
Taiwan
Prior art keywords
cells
standard
integrated circuit
standard cells
allocate
Prior art date
Application number
TW086119689A
Other languages
Chinese (zh)
Inventor
Nobuo Fudanuki
Toshikazu Sei
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW367590B publication Critical patent/TW367590B/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to a kind of integrated circuit of standard cell for basic cells of circuit mixed-loading gate array constructed by standard cells. The invention is to make easier of allocating wiring of cells and alternating circuit to achieve shortening of development time. The method is to allocate a plurality of standard cells on the chip and form the wiring area of standard rows and columns to allocate the gate array as the basic cells.
TW086119689A 1996-12-27 1997-12-24 Integrated circuit of standard cells TW367590B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35136096 1996-12-27

Publications (1)

Publication Number Publication Date
TW367590B true TW367590B (en) 1999-08-21

Family

ID=57941262

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086119689A TW367590B (en) 1996-12-27 1997-12-24 Integrated circuit of standard cells

Country Status (2)

Country Link
KR (1) KR100339909B1 (en)
TW (1) TW367590B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI502385B (en) * 2008-10-21 2015-10-01 Advanced Risc Mach Ltd Modifying integrated circuit layout

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6378550A (en) * 1986-09-22 1988-04-08 Fujitsu Ltd Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI502385B (en) * 2008-10-21 2015-10-01 Advanced Risc Mach Ltd Modifying integrated circuit layout

Also Published As

Publication number Publication date
KR19980064681A (en) 1998-10-07
KR100339909B1 (en) 2002-09-18

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees