TW357455B - High-density DRAM built-in capacitor structure and the assembly method - Google Patents

High-density DRAM built-in capacitor structure and the assembly method

Info

Publication number
TW357455B
TW357455B TW087100094A TW87100094A TW357455B TW 357455 B TW357455 B TW 357455B TW 087100094 A TW087100094 A TW 087100094A TW 87100094 A TW87100094 A TW 87100094A TW 357455 B TW357455 B TW 357455B
Authority
TW
Taiwan
Prior art keywords
forming
layer
area
silicon
implanting
Prior art date
Application number
TW087100094A
Other languages
Chinese (zh)
Inventor
Jr-Yuan Lu
Jian-Mai Sung
Original Assignee
Vanguard Int Semiconduct Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vanguard Int Semiconduct Corp filed Critical Vanguard Int Semiconduct Corp
Priority to TW087100094A priority Critical patent/TW357455B/en
Priority to JP10111621A priority patent/JPH11204759A/en
Application granted granted Critical
Publication of TW357455B publication Critical patent/TW357455B/en

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  • Semiconductor Memories (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

A method of forming DRAM built-in capacitor structure in a silicon substrate, including: forming on said silicon substrate a first photoresist implanting shade having an opening array; forming N+ doped area on the opening of said silicon substrate by means of ion implanting, being the first photoresist implanting shade preventing ion implanting in other areas on the silicon substrate; removal of said first photoresist implanting shade; forming a crystalline silicon layer on said silicon substrate; forming a P-type well array in the crystalline silicon layer on top of said N+ doped area by means of patterned second photoresist implanting shade; removal of said second photoresist implanting shade; deposition a padded oxide layer and a nitride silicon layer and forming an opening area in the field oxide insulation area in said silicon nitride layer; forming in the surrounding of the cell area said field oxide insulation area, and electrically isolate said cell area, which is aligned to said N+ doped area; one-way etching said cell area by passing through said silicon nitride layer and the P-type well in the crystalline siliocn layer to reach the N+ doped area, for forming perfroation; even selection of etching of said perforation, for removal of said N+ doped area and forming cavities in said silicon substrate; removal of said silicon nitride layer by means of etching; deposition an electrode dielectric layer on the surface of said cavity and by said perforation; deposiition a dual crystalline silicon doped between the electrodes on said cavityy surface and stuffing said perforations, forming on the dual crystalline silicon dooped layer in said cavity, said built-in capacitor anode electric contact; grinding said dual crystalline silicon doped layer by means of chemical and mechanical grinding, for completing the assembly of said built-in capacitor.
TW087100094A 1998-01-05 1998-01-05 High-density DRAM built-in capacitor structure and the assembly method TW357455B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW087100094A TW357455B (en) 1998-01-05 1998-01-05 High-density DRAM built-in capacitor structure and the assembly method
JP10111621A JPH11204759A (en) 1998-01-05 1998-04-22 Buried capacitor structure of high density dram and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW087100094A TW357455B (en) 1998-01-05 1998-01-05 High-density DRAM built-in capacitor structure and the assembly method

Publications (1)

Publication Number Publication Date
TW357455B true TW357455B (en) 1999-05-01

Family

ID=21629296

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087100094A TW357455B (en) 1998-01-05 1998-01-05 High-density DRAM built-in capacitor structure and the assembly method

Country Status (2)

Country Link
JP (1) JPH11204759A (en)
TW (1) TW357455B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6774439B2 (en) 2000-02-17 2004-08-10 Kabushiki Kaisha Toshiba Semiconductor device using fuse/anti-fuse system
US11037933B2 (en) * 2019-07-29 2021-06-15 Nanya Technology Corporation Semiconductor device with selectively formed insulating segments and method for fabricating the same

Also Published As

Publication number Publication date
JPH11204759A (en) 1999-07-30

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