TW357438B - Semiconductor manufacturing process with integrated self-aligned silicide and self-aligned contract window - Google Patents

Semiconductor manufacturing process with integrated self-aligned silicide and self-aligned contract window

Info

Publication number
TW357438B
TW357438B TW086119546A TW86119546A TW357438B TW 357438 B TW357438 B TW 357438B TW 086119546 A TW086119546 A TW 086119546A TW 86119546 A TW86119546 A TW 86119546A TW 357438 B TW357438 B TW 357438B
Authority
TW
Taiwan
Prior art keywords
forming
active area
layer
self
aligned
Prior art date
Application number
TW086119546A
Other languages
Chinese (zh)
Inventor
quan-zhong Wang
Jen-Ming Huang
Chiou-Shan You
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Priority to TW086119546A priority Critical patent/TW357438B/en
Application granted granted Critical
Publication of TW357438B publication Critical patent/TW357438B/en

Links

Landscapes

  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A semiconductor manufacturing process with integrated self-aligned silicide and self-aligned contract window, including the following steps: (a) on a substrate, separation with a shallow trench or field oxide layer a first active area and a second active area, being the first active area for forming logic circuits and the second active area for forming memory circuits; (b) forming accordingly on the substrate a gate oxide layer and a polycrystalline silicon layer; (c) forming on the second active area a silicide and a mask layer; (d) on the second active area, defining said layers for forming a polycide gate coated with a mask layer; (e) on the first active area, defining the gate oxide layer and the polycrystalline silicon layer, for forming a polycrystalline silicon gate electrode; (f) forming on the side of the gate structures a lateral wall layer; (g) forming source/drain electrode on the substrate of both sides of the gate electrode structure; (h) forming a blocking layer, coating the structure of the second active area; (i) by using a self-aligned silicide, forming silicide substance on the polycrystaline silicon gate electrode, source/drain electrode in the first active area; (j) forming the first insulator, coating the substrate; and (k) etching the insulation layer by using the blocking layer and the lateral wall layer as blocking layers and for forming on the second active area a self-aligned contact window, for exposing either the source or the drain area for contact area.
TW086119546A 1997-12-22 1997-12-22 Semiconductor manufacturing process with integrated self-aligned silicide and self-aligned contract window TW357438B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW086119546A TW357438B (en) 1997-12-22 1997-12-22 Semiconductor manufacturing process with integrated self-aligned silicide and self-aligned contract window

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086119546A TW357438B (en) 1997-12-22 1997-12-22 Semiconductor manufacturing process with integrated self-aligned silicide and self-aligned contract window

Publications (1)

Publication Number Publication Date
TW357438B true TW357438B (en) 1999-05-01

Family

ID=57940444

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086119546A TW357438B (en) 1997-12-22 1997-12-22 Semiconductor manufacturing process with integrated self-aligned silicide and self-aligned contract window

Country Status (1)

Country Link
TW (1) TW357438B (en)

Similar Documents

Publication Publication Date Title
US5492851A (en) Method for fabricating attached capacitor cells in a semiconductor device having a thin film transistor
TW347581B (en) Process for fabricating read-only memory cells
US5470776A (en) Method for fabricating stacked dynamic random access memory cell
KR940003036A (en) Method for manufacturing semiconductor device and its structure
GB2026768A (en) Process for the production of an integrated multilayer insulation storage cell
US4430791A (en) Sub-micrometer channel length field effect transistor process
WO2004019383A3 (en) Self-aligned contacts to gates
US5326989A (en) Semiconductor device having thin film transistor and method of manufacturing the same
US6136657A (en) Method for fabricating a semiconductor device having different gate oxide layers
US5510292A (en) Manufacturing method for a semiconductor device having local interconnections
KR100311954B1 (en) Manufacturing method of contact hole for doping area
JPS60113460A (en) Dynamic memory element
TW357438B (en) Semiconductor manufacturing process with integrated self-aligned silicide and self-aligned contract window
JP2000223699A (en) Fabrication of semiconductor device
US6235566B1 (en) Two-step silicidation process for fabricating a semiconductor device
US6458659B1 (en) Method of fabricating non-volatile memory devices integrated in a semiconductor substrate and organized into memory matrices
TW235370B (en) Method of fabricating semiconductor devices having electrodes comprising layers of doped tungsten disilicide
KR100372820B1 (en) Double silicon mosfet and method of manufacturing the same
KR0129984B1 (en) Semiconductor device and its manufacturing method
JPH0577175B2 (en)
KR0166856B1 (en) Method of fabricating semiconductor device
KR0165477B1 (en) Semiconductor or device wih buried of unburied type contact and fabricating method thereof
KR960013507B1 (en) Method for manufacturing sram
KR100261991B1 (en) Manufacturing method for transistor of semiconductor memory cell and its structure
JPH04245622A (en) Semiconductor device and its manufacture

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent