TW353801B - Method of forming plug in integrated circuit - Google Patents

Abstract

A method of forming a plug in an integrated circuit, which comprises the following steps: (a) forming transistors and a field oxide layer on a semiconductor substrate; (b) sequentially forming a first dielectric layer and a second dielectric layer, and forming a plug pad contact hole by using photolithography and etching techniques; (c) sequentially forming a barrier layer and a salicide layer, and etching back the salicide thereby forming a salicide plug pad; (d) forming a third dielectric layer, and producing a bitline contact hole using photolithography and etching techniques; (e) forming a salicide layer, and producing the salicide layer into bitlines using photolithography and etching techniques; (f) sequentially forming a fourth dielectric layer and a silicon nitride layer, and forming a capacitor-buried contact hole using photolithography and etching techniques; (g) forming a fifth dielectric layer, and locating the capacitors^ locations using photolithography and etching techniques; (h) sequentially forming a first silicon film, a capacitor dielectric layer and a second silicon film, and separately producing them into a storage electrode plate of capacitors, a dielectric layer and a memory cell electrode plate; (I) forming a sixth dielectric layer and forming a metallic contact hole using photolithography and etching techniques; (j) forming a tungsten plug; and (k) forming a metallic layer and forming a metallic interconnect using photolithography and etching techniques.