TW353774B - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
TW353774B
TW353774B TW086114091A TW86114091A TW353774B TW 353774 B TW353774 B TW 353774B TW 086114091 A TW086114091 A TW 086114091A TW 86114091 A TW86114091 A TW 86114091A TW 353774 B TW353774 B TW 353774B
Authority
TW
Taiwan
Prior art keywords
polarity
signal line
integrated circuit
semiconductor integrated
circuit device
Prior art date
Application number
TW086114091A
Other languages
English (en)
Inventor
Tadahiro Kuroda
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW353774B publication Critical patent/TW353774B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
TW086114091A 1996-09-30 1997-09-26 Semiconductor integrated circuit device TW353774B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8259480A JPH10107208A (ja) 1996-09-30 1996-09-30 半導体集積回路装置

Publications (1)

Publication Number Publication Date
TW353774B true TW353774B (en) 1999-03-01

Family

ID=17334669

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086114091A TW353774B (en) 1996-09-30 1997-09-26 Semiconductor integrated circuit device

Country Status (4)

Country Link
US (1) US6005265A (zh)
JP (1) JPH10107208A (zh)
KR (1) KR19980025140A (zh)
TW (1) TW353774B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864181A (en) 1993-09-15 1999-01-26 Micron Technology, Inc. Bi-level digit line architecture for high density DRAMs
US6043562A (en) * 1996-01-26 2000-03-28 Micron Technology, Inc. Digit line architecture for dynamic memory
US6072699A (en) * 1998-07-21 2000-06-06 Intel Corporation Method and apparatus for matching trace lengths of signal lines making 90°/180° turns
US6606587B1 (en) * 1999-04-14 2003-08-12 Hewlett-Packard Development Company, L.P. Method and apparatus for estimating elmore delays within circuit designs
EP1347389B1 (en) * 2002-03-19 2013-05-15 Broadcom Corporation Bus twisting scheme for equalizing coupling and low power
US6894231B2 (en) * 2002-03-19 2005-05-17 Broadcom Corporation Bus twisting scheme for distributed coupling and low power
JP4354681B2 (ja) 2002-09-13 2009-10-28 株式会社日立製作所 通信用半導体集積回路
US7139993B2 (en) * 2004-03-26 2006-11-21 Sun Microsystems, Inc. Method and apparatus for routing differential signals across a semiconductor chip
JP4492734B2 (ja) * 2008-05-29 2010-06-30 ソニー株式会社 信号処理装置、信号処理システム、および信号処理方法
JP2009302132A (ja) * 2008-06-10 2009-12-24 Toshiba Corp レイアウト設計方法及び記録媒体
US8621405B2 (en) * 2012-05-31 2013-12-31 Synopsys, Inc. Incremental elmore delay calculation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3440335B2 (ja) * 1993-08-18 2003-08-25 日本テキサス・インスツルメンツ株式会社 半導体メモリ装置
JP3158017B2 (ja) * 1994-08-15 2001-04-23 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 相互結線配列および相互結線配列用の導線を形成する方法

Also Published As

Publication number Publication date
US6005265A (en) 1999-12-21
KR19980025140A (ko) 1998-07-06
JPH10107208A (ja) 1998-04-24

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees