TW351791B - Processor having execution core sections operating at different clock rates - Google Patents

Processor having execution core sections operating at different clock rates

Info

Publication number
TW351791B
TW351791B TW086116267A TW86116267A TW351791B TW 351791 B TW351791 B TW 351791B TW 086116267 A TW086116267 A TW 086116267A TW 86116267 A TW86116267 A TW 86116267A TW 351791 B TW351791 B TW 351791B
Authority
TW
Taiwan
Prior art keywords
processor
execution core
different clock
core sections
clock rates
Prior art date
Application number
TW086116267A
Other languages
English (en)
Inventor
David J Sager
Thomas D Fletcher
Glenn J Hinton
Michael D Upton
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of TW351791B publication Critical patent/TW351791B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
  • Power Sources (AREA)
TW086116267A 1996-11-13 1997-11-03 Processor having execution core sections operating at different clock rates TW351791B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/746,606 US5828868A (en) 1996-11-13 1996-11-13 Processor having execution core sections operating at different clock rates

Publications (1)

Publication Number Publication Date
TW351791B true TW351791B (en) 1999-02-01

Family

ID=25001559

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086116267A TW351791B (en) 1996-11-13 1997-11-03 Processor having execution core sections operating at different clock rates

Country Status (6)

Country Link
US (3) US5828868A (zh)
AR (1) AR008322A1 (zh)
AU (1) AU4669297A (zh)
TW (1) TW351791B (zh)
WO (1) WO1998021641A1 (zh)
ZA (1) ZA979600B (zh)

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US5828868A (en) * 1996-11-13 1998-10-27 Intel Corporation Processor having execution core sections operating at different clock rates
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US7886164B1 (en) 2002-11-14 2011-02-08 Nvidia Corporation Processor temperature adjustment system and method
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US7165167B2 (en) * 2003-06-10 2007-01-16 Advanced Micro Devices, Inc. Load store unit with replay mechanism
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US7574611B2 (en) * 2005-11-28 2009-08-11 Atmel Corporation Command decoder for microcontroller based flash memory digital controller system
US7702885B2 (en) * 2006-03-02 2010-04-20 Atmel Corporation Firmware extendable commands including a test mode command for a microcontroller-based flash memory controller
US7414550B1 (en) 2006-06-30 2008-08-19 Nvidia Corporation Methods and systems for sample rate conversion and sample clock synchronization
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US9134782B2 (en) 2007-05-07 2015-09-15 Nvidia Corporation Maintaining optimum voltage supply to match performance of an integrated circuit
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US8370663B2 (en) 2008-02-11 2013-02-05 Nvidia Corporation Power management with dynamic frequency adjustments
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Also Published As

Publication number Publication date
WO1998021641A1 (en) 1998-05-22
AR008322A1 (es) 1999-12-29
US20120042151A1 (en) 2012-02-16
AU4669297A (en) 1998-06-03
US6216234B1 (en) 2001-04-10
US5828868A (en) 1998-10-27
ZA979600B (en) 1999-04-28

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