TW347580B - Process for forming a gate - Google Patents
Process for forming a gateInfo
- Publication number
- TW347580B TW347580B TW086115646A TW86115646A TW347580B TW 347580 B TW347580 B TW 347580B TW 086115646 A TW086115646 A TW 086115646A TW 86115646 A TW86115646 A TW 86115646A TW 347580 B TW347580 B TW 347580B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- sin
- gate
- silicon nitride
- forming
- Prior art date
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A process for producing a gate, which at least comprises the following steps: forming a conductive layer on a substrate; forming a first silicon nitride (SiN) layer on the conductive layer; etching all layers formed in the above steps thereby defining a gate; forming a second silicon nitride (SiN) layer on the gate and the surface of the substrate; and etching the second silicon nitride (SiN) layer thereby forming a spacer on the sidewall of the gate; during the etching step, the first silicon nitride (SiN) layer and the second silicon nitride (SiN) layer having different etching rates, the height of the spacer being higher than the height of the first silicon nitride (SiN) layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW086115646A TW347580B (en) | 1997-10-22 | 1997-10-22 | Process for forming a gate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW086115646A TW347580B (en) | 1997-10-22 | 1997-10-22 | Process for forming a gate |
Publications (1)
Publication Number | Publication Date |
---|---|
TW347580B true TW347580B (en) | 1998-12-11 |
Family
ID=58263991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086115646A TW347580B (en) | 1997-10-22 | 1997-10-22 | Process for forming a gate |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW347580B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE202009001980U1 (en) | 2009-03-18 | 2009-08-06 | Chen, Chien-Nan | Spectacle frame assembly and spectacle frame |
-
1997
- 1997-10-22 TW TW086115646A patent/TW347580B/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE202009001980U1 (en) | 2009-03-18 | 2009-08-06 | Chen, Chien-Nan | Spectacle frame assembly and spectacle frame |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA1247259A (en) | Method of improving silicon-on-insulator uniformity | |
EP0884774A3 (en) | Method for manufacturing a semiconductor device with an isolation trench | |
EP0406025A3 (en) | Method for fabricating a semiconductor device in which an insulating layer thereof has a uniform thickness | |
TW353797B (en) | Method of shallow trench isolation | |
TW356583B (en) | Barrier layer forming method | |
TW346664B (en) | Mixed-mode IC separated spacer structure and process for producing the same | |
TW343364B (en) | Process for producing twin gate oxide elements | |
TW346666B (en) | Process for producing dielectric layer in an integrated circuit | |
US6348414B1 (en) | Method for forming fine metal patterns by using damascene technique | |
TW347580B (en) | Process for forming a gate | |
TW339462B (en) | Vertical sidewall nitride etch process | |
TW356586B (en) | Semiconductor device having conductive layer and manufacturing method thereof | |
EP0878836A3 (en) | Planarising a semiconductor substrate | |
TW346661B (en) | A method for manufacturing a semiconductor device | |
TW360949B (en) | Dual damascene process | |
TW325583B (en) | Method of etching a polysilicon layer | |
TW336349B (en) | Process for producing IC well construction | |
TW330310B (en) | Inter-metal dielectric planarization method | |
TW429509B (en) | Manufacturing method for protection layer | |
TW290716B (en) | Method of making capacitor by etching technique | |
TW347569B (en) | Process for producing lower electrode of a capacitance | |
TW350988B (en) | Manufacturing method of forming metal layout by means of hard mask | |
TW347562B (en) | Method of plasma softetch for damaged surface of silicon substrate | |
TW337609B (en) | Process for producing tungsten plug capable of preventing disappearance of alignment mark and formation of tungsten plug recess | |
TW353794B (en) | Method of shallow trench isolation using selective liquid phase deposition of silicon oxide |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |