TW347495B - A data flow control mechanism for a bus supporting two- and three-agent transactions - Google Patents

A data flow control mechanism for a bus supporting two- and three-agent transactions

Info

Publication number
TW347495B
TW347495B TW086112178A TW86112178A TW347495B TW 347495 B TW347495 B TW 347495B TW 086112178 A TW086112178 A TW 086112178A TW 86112178 A TW86112178 A TW 86112178A TW 347495 B TW347495 B TW 347495B
Authority
TW
Taiwan
Prior art keywords
agent
data flow
flow control
control mechanism
bus
Prior art date
Application number
TW086112178A
Other languages
Chinese (zh)
Inventor
D Macwillas Peter
S Pawlowski Sterhen
V Sarangdhar Nitin
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/709,215 external-priority patent/US6405271B1/en
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of TW347495B publication Critical patent/TW347495B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A method for controlling transaction data flow, the transaction being sent out on a pipeline computer system bus, the method comprising the following steps: (a) issuing a request on a bus with a first agent; (b) providing a first instruction to the first agent by a second agent, the instruction containing the data of the second agent preparing to receive the corresponding request; and (c) placing the correspondingly requested data on a bus by the first agent corresponding to the first instruction.
TW086112178A 1996-09-06 1997-08-25 A data flow control mechanism for a bus supporting two- and three-agent transactions TW347495B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/709,215 US6405271B1 (en) 1994-09-08 1996-09-06 Data flow control mechanism for a bus supporting two-and three-agent transactions

Publications (1)

Publication Number Publication Date
TW347495B true TW347495B (en) 1998-12-11

Family

ID=24848933

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086112178A TW347495B (en) 1996-09-06 1997-08-25 A data flow control mechanism for a bus supporting two- and three-agent transactions

Country Status (3)

Country Link
AU (1) AU3587097A (en)
TW (1) TW347495B (en)
WO (1) WO1998010350A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6609171B1 (en) * 1999-12-29 2003-08-19 Intel Corporation Quad pumped bus architecture and protocol
GB2450148A (en) * 2007-06-14 2008-12-17 Advanced Risc Mach Ltd Controlling write transactions between initiators and recipients via interconnect logic

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5528764A (en) * 1992-12-24 1996-06-18 Ncr Corporation Bus system with cache snooping signals having a turnaround time between agents driving the bus for keeping the bus from floating for an extended period
US5551005A (en) * 1994-02-25 1996-08-27 Intel Corporation Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches

Also Published As

Publication number Publication date
WO1998010350A1 (en) 1998-03-12
AU3587097A (en) 1998-03-26

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees