AU3587097A - A data flow control mechanism for a bus supporting two-and three-agent transactions - Google Patents

A data flow control mechanism for a bus supporting two-and three-agent transactions

Info

Publication number
AU3587097A
AU3587097A AU35870/97A AU3587097A AU3587097A AU 3587097 A AU3587097 A AU 3587097A AU 35870/97 A AU35870/97 A AU 35870/97A AU 3587097 A AU3587097 A AU 3587097A AU 3587097 A AU3587097 A AU 3587097A
Authority
AU
Australia
Prior art keywords
flow control
control mechanism
data flow
bus supporting
agent transactions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU35870/97A
Inventor
Peter D Macwilliams
Stephen S. Pawlowski
Nitin V Sarangdhar
Gurbir Singh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/709,215 external-priority patent/US6405271B1/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU3587097A publication Critical patent/AU3587097A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU35870/97A 1996-09-06 1997-06-30 A data flow control mechanism for a bus supporting two-and three-agent transactions Abandoned AU3587097A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08709215 1996-09-06
US08/709,215 US6405271B1 (en) 1994-09-08 1996-09-06 Data flow control mechanism for a bus supporting two-and three-agent transactions
PCT/US1997/011419 WO1998010350A1 (en) 1996-09-06 1997-06-30 A data flow control mechanism for a bus supporting two-and three-agent transactions

Publications (1)

Publication Number Publication Date
AU3587097A true AU3587097A (en) 1998-03-26

Family

ID=24848933

Family Applications (1)

Application Number Title Priority Date Filing Date
AU35870/97A Abandoned AU3587097A (en) 1996-09-06 1997-06-30 A data flow control mechanism for a bus supporting two-and three-agent transactions

Country Status (3)

Country Link
AU (1) AU3587097A (en)
TW (1) TW347495B (en)
WO (1) WO1998010350A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6609171B1 (en) * 1999-12-29 2003-08-19 Intel Corporation Quad pumped bus architecture and protocol
GB2450148A (en) * 2007-06-14 2008-12-17 Advanced Risc Mach Ltd Controlling write transactions between initiators and recipients via interconnect logic

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5528764A (en) * 1992-12-24 1996-06-18 Ncr Corporation Bus system with cache snooping signals having a turnaround time between agents driving the bus for keeping the bus from floating for an extended period
US5551005A (en) * 1994-02-25 1996-08-27 Intel Corporation Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches

Also Published As

Publication number Publication date
TW347495B (en) 1998-12-11
WO1998010350A1 (en) 1998-03-12

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