TW343302B - Direct memory access controlling device - Google Patents

Direct memory access controlling device

Info

Publication number
TW343302B
TW343302B TW085116272A TW85116272A TW343302B TW 343302 B TW343302 B TW 343302B TW 085116272 A TW085116272 A TW 085116272A TW 85116272 A TW85116272 A TW 85116272A TW 343302 B TW343302 B TW 343302B
Authority
TW
Taiwan
Prior art keywords
dma
memory
memory access
transmission
data
Prior art date
Application number
TW085116272A
Other languages
Chinese (zh)
Inventor
Kim Sun-Gi
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to TW085116272A priority Critical patent/TW343302B/en
Application granted granted Critical
Publication of TW343302B publication Critical patent/TW343302B/en

Links

Abstract

A direct memory access (DMA) controlling device for DMA transmission in a computer system having a microprocessor, a source memory for storing the data to be transmitted, and a destination memory for storing the transmitted data; the DMA controlling device comprising a DMA control register for storing an instruction, which is transmitted to the DMA controlling device by the microprocessor for the DMA transmission; a DMA counter register capable of recording the number of DMA transmission; means for generating the address of the source memory during the DMA transmission; means for generating the address of the destination memory during the DMA transmission; a DMA data buffer for temporarily storing data of the source memory before the data of the source memory is transmitted to the destination memory; DMA arbitrating means for arbitrating a memory access priority upon the occurrence of each the DMA transmission cycle when the memory access request is received from at least one master intending to use one of the source and destination memories during the DMA transmission; and DMA engine controlling means for requesting the memory access priority from the DMA arbitrator, transmitting memory control signals to a master which has the memory access priority, and transmitting information regarding the DMA transmission frequency to a DMA count register.
TW085116272A 1996-12-30 1996-12-30 Direct memory access controlling device TW343302B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW085116272A TW343302B (en) 1996-12-30 1996-12-30 Direct memory access controlling device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW085116272A TW343302B (en) 1996-12-30 1996-12-30 Direct memory access controlling device

Publications (1)

Publication Number Publication Date
TW343302B true TW343302B (en) 1998-10-21

Family

ID=58263636

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085116272A TW343302B (en) 1996-12-30 1996-12-30 Direct memory access controlling device

Country Status (1)

Country Link
TW (1) TW343302B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109739785A (en) * 2018-09-20 2019-05-10 威盛电子股份有限公司 The internal connection-wire structure of multiple nucleus system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109739785A (en) * 2018-09-20 2019-05-10 威盛电子股份有限公司 The internal connection-wire structure of multiple nucleus system
CN109739785B (en) * 2018-09-20 2020-12-29 威盛电子股份有限公司 Interconnection structure of multi-core system

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees