TW335472B - Method and apparatus for transferring pixel data stored in a memory circuit - Google Patents
Method and apparatus for transferring pixel data stored in a memory circuitInfo
- Publication number
- TW335472B TW335472B TW086108053A TW86108053A TW335472B TW 335472 B TW335472 B TW 335472B TW 086108053 A TW086108053 A TW 086108053A TW 86108053 A TW86108053 A TW 86108053A TW 335472 B TW335472 B TW 335472B
- Authority
- TW
- Taiwan
- Prior art keywords
- area
- pixel data
- target
- block
- group
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Image Input (AREA)
- Controls And Circuits For Display Device (AREA)
- Image Generation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US66720796A | 1996-06-20 | 1996-06-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW335472B true TW335472B (en) | 1998-07-01 |
Family
ID=24677262
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086108053A TW335472B (en) | 1996-06-20 | 1997-06-11 | Method and apparatus for transferring pixel data stored in a memory circuit |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0814428A3 (zh) |
JP (1) | JPH10143426A (zh) |
TW (1) | TW335472B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6064408A (en) * | 1998-04-28 | 2000-05-16 | Sun Microsystems, Inc. | Method, apparatus and computer program product for eliminating edge conditions from an area image processing operations on tiled image data |
US6630936B1 (en) * | 2000-09-28 | 2003-10-07 | Intel Corporation | Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (BLT) in parallel |
JP4733138B2 (ja) * | 2006-03-31 | 2011-07-27 | パナソニック株式会社 | コマンド出力制御装置、コマンド出力制御方法およびプログラム |
KR101639574B1 (ko) * | 2009-12-30 | 2016-07-14 | 삼성전자주식회사 | 적응적 뱅크 어드레스를 제공하는 디스플레이 시스템 및 그것의 어드레스 맵핑 방법 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60147785A (ja) * | 1984-01-12 | 1985-08-03 | 株式会社アスキ− | 論理領域間デ−タ移動制御装置 |
US4808986A (en) * | 1987-02-12 | 1989-02-28 | International Business Machines Corporation | Graphics display system with memory array access |
WO1992002924A1 (en) * | 1990-08-03 | 1992-02-20 | Du Pont Pixel Systems Limited | Data-array processing system |
JP3038868B2 (ja) * | 1990-10-08 | 2000-05-08 | ソニー株式会社 | 画像データのブロック転送装置 |
-
1997
- 1997-06-11 TW TW086108053A patent/TW335472B/zh active
- 1997-06-16 EP EP97304205A patent/EP0814428A3/en not_active Withdrawn
- 1997-06-20 JP JP16476497A patent/JPH10143426A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
JPH10143426A (ja) | 1998-05-29 |
EP0814428A3 (en) | 1998-08-19 |
EP0814428A2 (en) | 1997-12-29 |
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