TW328624B - The manufacturing method for MOS with gate-side air-gap structure - Google Patents

The manufacturing method for MOS with gate-side air-gap structure

Info

Publication number
TW328624B
TW328624B TW086110021A TW86110021A TW328624B TW 328624 B TW328624 B TW 328624B TW 086110021 A TW086110021 A TW 086110021A TW 86110021 A TW86110021 A TW 86110021A TW 328624 B TW328624 B TW 328624B
Authority
TW
Taiwan
Prior art keywords
spacer
semiconductor substrate
polysilicon gate
substrate
amorphous silicon
Prior art date
Application number
TW086110021A
Other languages
Chinese (zh)
Inventor
Shye-Lin Wu
Original Assignee
Powerchip Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powerchip Semiconductor Corp filed Critical Powerchip Semiconductor Corp
Priority to TW086110021A priority Critical patent/TW328624B/en
Application granted granted Critical
Publication of TW328624B publication Critical patent/TW328624B/en

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A manufacturing method for MOS with gate-side air-gap structure includes the following steps: - Define to form polysilicon gate structure on semiconductor substrate; - Proceed 1st ion implantation on substrate to form lightly doped source and drain in substrate at both sides of polysilicon gate structure; - Form nitride spacer at sidewall of polysilicon gate structure; - Form amorphous silicon spacer at sidewall of nitride spacer; - Proceed 2nd ion implantation to semiconductor substrate, polysilicon gate and amorphous silicon spacer; - Proceed slightly annealing on substrate to form heavily doped source and drain on semiconductor substrate; - Remove nitride spacer; - Use wet oxidation process for oxidation amorphous silicon spacer to form doped oxide spacer with air-gap, and form extended doping region in semiconductor substrate under the doped oxide spacer.
TW086110021A 1997-07-15 1997-07-15 The manufacturing method for MOS with gate-side air-gap structure TW328624B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW086110021A TW328624B (en) 1997-07-15 1997-07-15 The manufacturing method for MOS with gate-side air-gap structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086110021A TW328624B (en) 1997-07-15 1997-07-15 The manufacturing method for MOS with gate-side air-gap structure

Publications (1)

Publication Number Publication Date
TW328624B true TW328624B (en) 1998-03-21

Family

ID=58262441

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086110021A TW328624B (en) 1997-07-15 1997-07-15 The manufacturing method for MOS with gate-side air-gap structure

Country Status (1)

Country Link
TW (1) TW328624B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11987876B2 (en) 2018-03-19 2024-05-21 Lam Research Corporation Chamfer-less via integration scheme
US12051589B2 (en) 2016-06-28 2024-07-30 Lam Research Corporation Tin oxide thin film spacers in semiconductor device manufacturing
US12094711B2 (en) 2017-02-17 2024-09-17 Lam Research Corporation Tin oxide films in semiconductor device manufacturing

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12051589B2 (en) 2016-06-28 2024-07-30 Lam Research Corporation Tin oxide thin film spacers in semiconductor device manufacturing
US12094711B2 (en) 2017-02-17 2024-09-17 Lam Research Corporation Tin oxide films in semiconductor device manufacturing
US11987876B2 (en) 2018-03-19 2024-05-21 Lam Research Corporation Chamfer-less via integration scheme

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees