TW328173B - The DRAM COB bit line and moat arrangement - Google Patents

The DRAM COB bit line and moat arrangement

Info

Publication number
TW328173B
TW328173B TW086103478A TW86103478A TW328173B TW 328173 B TW328173 B TW 328173B TW 086103478 A TW086103478 A TW 086103478A TW 86103478 A TW86103478 A TW 86103478A TW 328173 B TW328173 B TW 328173B
Authority
TW
Taiwan
Prior art keywords
bit line
moat
substrate
top surface
dram
Prior art date
Application number
TW086103478A
Other languages
Chinese (zh)
Inventor
Katsuyoshi Anto
Yoichi Miyai
Masayuki Moroi
Katsushi Boku
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW328173B publication Critical patent/TW328173B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

A semiconductor IC of DRAM is composed by the followings. A. A substrate has a top surface; B. The 1st insulating layer is formed on top surface of substrate to form plurality of openings through 1st insulating till top surface of substrate; Each opening is formed in arc-shaped, and bounded by top end and two leading-wires extended from top end to end; And each opening installs a moat in substrate to provide a memory cell pair, and connect a bit line connection point to memory cell located at top end, and connect storing node connection point to storing node of memory cell located at end of leading-wire; C. A conductive layer is formed on top surface of substrate to form plurality of bit lines, and each bit line is formed in wave-shaped having alternated crests and troughs. The bit line is arranged by related to moat, and each trough of bit line is located on top end of moat for covering from bit line to moat. And simultaneously the end of leading-wire is non-covered by bit line.
TW086103478A 1995-12-21 1997-03-20 The DRAM COB bit line and moat arrangement TW328173B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US904295P 1995-12-21 1995-12-21

Publications (1)

Publication Number Publication Date
TW328173B true TW328173B (en) 1998-03-11

Family

ID=49382036

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086103478A TW328173B (en) 1995-12-21 1997-03-20 The DRAM COB bit line and moat arrangement

Country Status (2)

Country Link
KR (1) KR100454373B1 (en)
TW (1) TW328173B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480602B1 (en) * 2002-06-28 2005-04-06 삼성전자주식회사 Semiconductor memory device and method for manufacturing the same
KR100706233B1 (en) 2004-10-08 2007-04-11 삼성전자주식회사 Semiconductor memory device and method of fabricating the same
US7547936B2 (en) 2004-10-08 2009-06-16 Samsung Electronics Co., Ltd. Semiconductor memory devices including offset active regions
JP2019165088A (en) * 2018-03-19 2019-09-26 東芝メモリ株式会社 Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
KR19980050069A (en) 1998-09-15
KR100454373B1 (en) 2004-12-30

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees