KR19980050069A - DRAM COB Bit Line and Mouth Configuration - Google Patents

Abstract

DRAM uses an arcuate moat 18 and wavy bit lines 28 and 30 for memory cell arrangement. Bit line contacts 20 occur at the top of the moat, and storage node contacts 22, 24 occur at the ends of the legs 40, 42 extending from this advantage. The wavy bit line has alternating ridges 32 and 36 and valleys 34 and 38. The bit line is laid on the moat such that the goal of each bit line is in contact with the layer above the top of each moat and the floor avoids the moat. The floor and valley of the bit line are offset from each other. In the half pitch pattern, the valley of one bit line lies adjacent to the floor of the next bit line. The moat is concave between the legs, and the angle between the legs is in the range of about 140 ° to 170 °. The angle between the floor and valley of the bit line is in the range of about 110 ° to 160 °. In one embodiment, the central portion 70 between the regions surrounding the storage node contacts is about 10% wider than the region surrounding the storage node contacts.

Description

DRAM COB Bit Line and Mouth Configuration

BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to semiconductor integrated circuit dynamic random access memory (DRAM) components having a bit storage capacitor (COB) disposed on a bit line, in particular reducing process steps, maintaining reliability, and providing memory cells within an array. It relates to an arcuate configuration and a wavy bit line configuration of a moat region on a memory cell, which can increase the density.

In conventional memory cells, the bit storage capacitor is located below the bit line in what is called a capacitor under bit line (CUB) memory cell configuration. In the CUB cell, the moments for each pair of memory cells were straight alongside the center bit line contact area between two storage node contact areas facing each other. These two storage nodes or capacitors were located just above the moat centered on their respective storage node contact areas. The bit line had a descending portion extending across the memory cell array above the storage node and connected to a centrally located bit line contact region at each moat. In this configuration, the bit lines were generally straight and aligned over the two storage node contacts in each moat. This was possible because the capacitor was under the bit line. The lower portion of the bit line could be connected to the bit line contact area using the space between the capacitor or storage nodes.

Newer designs have been attempted to increase the capacity of all storage node capacitors by raising the height of the capacitors centered above the storage node contact area and using the space between the capacitors. As a result of this attempt, the idea was to put a bit line under a capacitor, a COB memory cell. But there were also some new difficulties.

One difficulty is that the linear alignment of the bit lines must be moved to the side of the storage node contact area to avoid direct storage node contact plugs connecting the storage node capacitors to the storage node contacts. Another problem arises from connecting laterally spaced bit lines to bit line contacts. This connection requires either a sharp bend at the bit line, that is, a hard bend, or a separate connection pad extending from the middle of the straight line to the bit line contact. Forming hard bends results in resolution problems that make it difficult to obtain good shapes in the bend. Forming the pad requires further processing steps.

Another solution may be to move the storage node contact plug out of alignment with the bit line contacts to bend the moat to leave the bit lines straight. This has the problem that the concave curve of the moat is sharpened. This sharp curve causes excessive stress in the LOCOS insulating layer that defines the moat.

The present invention utilizes an arcuate pattern for the moat and uses regular, well-flowing wavy bit lines to increase productivity without stress in the LOCOS insulation layer defining the moat. In the present invention, both the moat and the bit line exhibit a non-linear pattern.

Each moat region is formed into an arc with one apex and two legs extending from the apex. The bit line contact is located at this vertex and the storage node contact is located at the end of this bridge. The moat area between the legs is concave and may have a radius R of 3.46 microns in one embodiment. The angle between the legs may range from about 140 ° to 170 °.

The bit lines are formed in a wavy pattern with regular floors and valleys. Depending on the observer's position, the floor may be the goal and the goal may be the floor. The important point is that the bit lines represent a regular pattern. The angle at each ridge and valley can range from about 110 ° to 160 °.

The valleys of the bit lines are arranged to overlap and overlap the moats at the vertices of each moie, ie the bit line contacts. In one embodiment, the ridges and valleys of the bit line are excreted with each other by a half pitch with the ridges of one bit line adjacent to the valleys of the next bit line.

1 is an ideal plan view of a portion of a DRAM memory cell arrangement showing moats, wordlines, and bitlines

2 is an ideal top view of one moat and two bit lines

3 is an ideal top view of the moat

4 is a plan view of a portion of a bit line

5 is a plan view of another moat the present invention

＊ Explanation of symbols for main parts of drawing

12 substrate, 14 first insulating layer, 16 opening, 18 moat, 20 bit line contact, 22, 24 storage node contact, 23 block face, 25 concave face, 26 word line, 27 1st line, 28, 30: bit line, 29: 2nd line, 32, 36: floor, 34, 38: goal

In FIG. 1, an ideal arrangement 10 of memory cells is typically formed with a plurality of arcuate openings 16 leading to the substrate 12 through a first insulating layer 14 formed in a LOCOS process. These openings 16 determine where the memory cell pairs will be fabricated. Arch openings 18 will be formed in the substrate 12 through these openings 16.

Each of the arcuate moats 18 will be formed with a bit line contact 20 and a pair of storage node contacts 22, 24. Although small circles were used to focus and focus attention on the location of the contact within the moat, in practice the entire area surrounding each of the circles would be used for each contact. Each arcuate shape of the moat 18 is represented by a block face 23 and a concave face 25. The moats are arranged in the substrate 12 to align the bit line contacts 20 almost straight along the first line 27. The moats are also arranged in the substrate 12 to align the storage node contacts 22, 24 almost straight along the second line 29.

Between each bit line contact 20 and storage node contact 22, or 24, a word line 26 travels substantially perpendicular to the first and second lines 27, 29. The word line 26 may have any curvature resulting from reducing the spacing between elements in the array, but is generally straight and travels across two word line angular moats 18. A word line 26 is formed on the first insulating layer 14, and as these word lines cross the moat, the word line moves the bit line contacts 20 to the storage node contacts 22, 24. To form a gate of a pass transistor that is electrically insulated from the circuit.

Capacitors used for storage nodes are not shown in this figure to clarify the description of the geometry of the moat and bit lines.

On the word line 26, a plurality of bit lines 28, 30 insulated from the word line by another insulating layer (not shown) are indicated by dotted lines. Although only two bit lines are shown, of course, the desired number of bit lines, word lines, and moats may be formed in the fabrication arrangement 10 of the memory cells.

The bit lines 28 and 30 are wavy, as seen from the lower part of the figure, and the floors 32 and 36 and the valleys 34 and 38 are regularly formed. In practice, each bit line is block and concave in each ridge and valley as seen from the opposite side of the bit line. The bit lines may have wavy or other desired shapes. The valleys of the bit lines 28 are such that the floors of the bit lines 30 of their moats 18 do not overlap any moat areas.

The bit line 28 is formed at the block face 23 of all the moats to which it is connected, and the bit line 30 is formed at the block face 23 of all the moats to which it is connected. By arranging the block shapes of the mou and bit lines to overlap each other, interference between the bit lines and the storage node can be avoided.

The memory cell array 10 exhibits a half pitch pattern in which the ridges 36 of the bit lines 30 are adjacent to the valleys 34 of the bit lines 28. Other pitches in which the ridges and valleys of the bit line are offset from each other may also be used. An example like this may be a quarter-pitch pattern although not shown.

Referring to FIG. 2, the ridge 36 of the bit line 30 lies closely spaced close to the concave arcuate moat 18. This allows the bit line and the moat to be electrically isolated from each other and form close to each other.

In FIG. 3, the moat 18 has an arcuate shape with a bit line contact 20 at its apex and storage node contacts 22, 24 at the ends of the legs 40, 42. The angle 44 between the legs 40, 42 may preferably range from 140 ° to 170 °. The outer edge 46 of the moat 18 is along the angle 44 and provides sufficient area around the contact to form the contacts 20, 22, 24. The moat radius R between the legs 40, 42 in the concave surface of the moat 18 may be about 3.46 microns.

In FIG. 4, the angle 48 between the floor and valley of the bit line may be between 110 ° and 160 °.

In FIG. 5, the moat 60 has a shape that can be represented by a gull winged. Areas 62 and 64 surrounding storage mode contacts 66 and 68 are generally rectangular or square. The central portion 70 of the moat 60, which includes a rectangular region 72 surrounding the bit line contacts 74, has a slightly larger area than the regions 62, 64. This provides an angle to the moat 60 while ensuring adequate space in the bit line contacts 74 to connect to any bit line (not shown). In the present embodiment, the central portion is about 10% wider than regions 62 and 64. The moats 80, 82, 84, and 86 are identical in structure and arrangement.

Thus, the mou smooth curve can be solved to solve the stress problem in the LOCOS insulating layer. The bit lines have a wavy shape to prevent the intersection of storage node contact areas and to obtain a regular pattern that can be formed while melting well during processing.

Some exemplary combinations of corresponding angles for the moat and bit lines are as follows.

As can be seen from this angle combination, a large moat angle is generally paired with a small bit line angle.

The best combination of angles is the bit line at about 140 ° and the moat at about 160 ° to 170 °.

The invention may be practiced other than as described herein. For example, the bit lines and the motes can be reduced or enlarged as desired in order to obtain a memory cell array of a desired size.

none.

Claims (9)

A. a substrate made of a semiconductor material having an upper surface; B. formed on the top surface of the substrate to form a plurality of openings on the top surface of the substrate, each of the openings being arcuate and extending from one apex and ending at the end. And forming a bit line contact for the memory cell at the apex, setting the position of the moat on the substrate for a pair of memory and storing the storage node contact for the storage node of the memory cell. A first insulating material formed at an end of the leg; And C. Formed on the upper surface of the substrate to form a plurality of bit lines, the bit lines are wavy with alternating crests and troughs, with each valley of the bit lines gathering these bit lines. 10. A semiconductor integrated circuit DRAM comprising a layer of conductive material disposed on a vertex of a moat for connection to a moat and an end of the leg disposed at a position relative to the moat so as not to be covered by the bit line. 2. The semiconductor integrated circuit DRAM of claim 1, wherein the mouts are arranged in a half-pitch pattern adjacent the ridges of one bit line. The semiconductor integrated circuit DRAM of claim 1, wherein the bit lines have a pattern in which the floors and valleys of one bit line are offset from the floors and valleys of a next bit line. The semiconductor integrated circuit DRAM of claim 1, wherein the angle between the legs of the moat is in a range from about 140 ° to 170 °, and the moat between the legs is concave with a radius R of about 3.5 microns. 2. The semiconductor integrated circuit DRAM of claim 1, wherein the ridges and valleys of one bit line are each at an angle ranging from about 110 degrees to 160 degrees. 2. The bit line of claim 1, wherein each of the moats has a block face and a concave face, and the vertices of the moat are disposed almost linearly in a plurality of lines having all concave faces on one side of the line, each bit line being a bit line. The semiconductor integrated circuit DRAM, which is disposed on the block surface of the mout to be connected. 10. The semiconductor integrated circuit of claim 1, wherein each ridge and valley of one bit line is at an angle of about 140 degrees and the angle between the legs of each moat is in the range of about 160 degrees to 170 degrees. DRAM. 10. The semiconductor integrated circuit of claim 1, wherein each moat has a central portion between the ends of the legs in a storage node contact, the central portion being wider than the moor region surrounding the storage node contact. DRAM. 8. The semiconductor integrated circuit DRAM of claim 7, wherein the central portion is about 10% wider than the moat region surrounding the storage node contacts.