TW322595B - - Google Patents

Description

32 ^ 595 A7 B7 Printed by the Employees ’Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs 5. Description of the invention (1) The present invention is applicable to the semiconductor laser circuit device, especially the optical lithography technology of the manufacturing method and the technology of etching technology ° That is, the present invention relates to the lithography technology and dry etching technology of the semiconductor manufacturing process, and particularly to the process of processing the wiring composed of high melting point gold with high accuracy and high selectivity. The wiring process and the subsequent wiring connection process are particularly effective. The optical lithography technology and etching technology commonly used in the manufacture of semiconductor ballast circuit devices use a patterned photoresist as a mask for selective etching. material. For example, when a photocatalyst is used to selectively etch a gold film formed on a concave-convex base substrate, if the light-reflecting rate of the base metal film is high when the photoresist is exposed in a puddle type, the halo effect may cause Reduce the exposure accuracy of the photoresist. There are several methods to prevent the halo caused by the reflection of light and improve the exposure accuracy, that is, the patterning accuracy of the gold film. (1) Push the anti-light sword with a light absorber on the gold film that needs to be patterned, that is, 0 ARC (Bottom Asnti-Reflection Coating) film as the anti-reflection film, and accumulate the anti-light for photosensitive on the film Agent. Then, the photoresist composed of the push-up film is exposed in a pattern. This patterning method is called the BARC method. (2) Japanese Patent Publication No. 6-1 7 6 4 or Japanese Patent Laid-Open No. 1 6 0 0 8 1 discloses a method of using a nitrogen compound as a reflection preventing film pushed on the base layer of gold film. This pattern exposure method uses a nitrogen compound as an anti-reflection film for forming aluminum and other wiring with high reflectivity. In other words, push the nitrogen compound on the processed film as the anti-reflective film, and the Chinese National Standard (CNS) A4 specification (210X297mm) is applicable to this paper standard _ 4-(Please read the precautions on the back before filling this page ) < dingsong 595 _ ^ _ V. Description of the invention (2) The anti-reflective film is used to accumulate light-sensitive photoresist. The photoresist is then exposed in a pattern. The wiring material used for 16M bit DRAM can be aluminum system. The wiring material has low resistance, and compared with the aluminum, its electrical migration resistance and corrosion resistance are very high. High melting point metals such as W or Mo. In particular, the high melting point metal is not used as a gate, but is used as a double-layer wiring or a 3-layer wiring. 0 When using wiring materials such as tungsten in high melting point gold, the reflectivity of the wiring material is lower than that of aluminum The reflectance, so the effect of halo caused by the exposure accuracy of the anti-light agent is not a problem. The inventors of the present invention have found that in order to realize the next-generation bit, for example, 64 M bit D RAM, the semiconductor manufacturing process must be more miniaturized, and the reflectance of the tungsten film, which was not a problem in the past, must also be considered. Therefore, even when patterning the wiring using high melting point metals such as W and Mo, the above-described method, for example, B A R C is used. However, the B A R C method has the following problems. Printed by the Zhengong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). The BARC method dry-etchs the anti-reflective film and uses the anti-reflective anti-reflective film as the tungsten wiring for the optical army. process. When the anti-reflection film is processed, the cutting amount of the photoresist / anti-reflection film is large. In addition, when the anti-reflective film is processed, the amount of etching in the lateral direction is large, so that the tungsten is cut and the dimensions are deviated. In the etching process of the anti-reflection film, even if the film thickness is 1000 A, it still takes about 180 seconds, and the throughput is low. The above problems are explained in more detail below. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -5-printed by the Employee Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs «. A7 B7 V. Invention description (3) Article 24 (a) ~ 24 (c) The figure shows the W wiring process using the BARC method. As shown in Fig. 24 (a), the tungsten metal film 101 for wiring is pushed onto the interlayer insulating film 100. A BARC film (antireflection film) 1 02 and a light-resistant photo-resistive film 1 0 3 are pushed on the metal film 101. After pattern exposure of the photoresist film 103 and the BARC film 102, the photoresist film 1.03 is etched by dry etching. Then, as shown in Fig. 24 (b), the BARC film 102 is etched. At this time, it is preferable to perform etching as shown by the broken line. However, the etching selectivity ratio of the BARC film 102 to the anti-light film 103 is about 1. That is, the etching speeds of the two films are approximately equal. Therefore, when the BARC film 102 is etched, the etching on the upper part of the light-resistant film 103 continues to occur, resulting in a loss of the light-resistant film h. At the same time, the side walls of the photoresist film and the BARC film are cut, that is, the size W1 deviates into the size W2. That is, the shape of the anti-reflective mask is defective. In particular, in order to prevent the loss of the anti-reflective film, when the thickness of the anti-reflective film 1 03 applied on the BARC film 102 is increased, the light-collecting margin of the anti-reflective film decreases, resulting in poor formation of the anti-reflective film. . When the tungsten film 101 is etched using the photoresist film 103 and the BARC film 102 as a photomask, the photoresist film 103 and the BARC film 102 used as an etching mask are cut. The reason is that the etching selectivity ratio of the light-resistant film 103 and the BARC film 102 to the tungsten film 101 is as low as about 2. As a result, as shown in the 24th (c), the size deviation of the tungsten wiring (W3 & W2), and the shoulder shaving phenomenon of the tungsten wiring E, the wiring cross-sectional shape becomes uneven 24. Therefore, the current density changes, and the device performance becomes uneven. The size of this paper is applicable to the Chinese National Standard (〇 奶) 84 specifications (210 father 297 mm) _6_ --- ^ J--1M ---- 1¾ ------ Subscribe ------ Media-- —-F (please read the notes on the back before filling in this page)

Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (4) When etching the anti-reflective film (BARC film) 102, the etching speed of the anti-reflective film 102 is lower than that of the upper layer. The etching speed of the layer 1 〇3 is 1 0 3. If the resistance of the upper light-resistant layer 1 〇3 is considered, the etching process conditions are limited. Therefore, the throughput of processing the photomask (anti-reflective layer / reflection prevention film) cannot be increased. On the other hand, as the flatness of the interlayer insulating film after W wiring processing is improved, it is necessary to simultaneously process wiring connection holes of different depths. For example, as a result of using CMP (Chemica 丨 Mechanical Polishing) technology to flatten the interlayer insulating film, wiring connection holes with different azimuth ratios must be formed at the same time. Regarding the dry etching technique, it is necessary to ensure that the suppression of the W cutting amount of the wire hole and the opening property of the deep hole coexist. In addition, even when excessive etching is applied to the wire hole, the hole diameter must be suppressed with high accuracy. That is, it is necessary to satisfy both the opening of a hole with a high azimuth ratio and the suppression of excessive opening of a hole with a low azimuth ratio. When wiring connection holes with different orientation ratios are formed at the same time, that is, when portions with different film thicknesses of the interlayer insulating film are simultaneously etched to form wiring connection holes, as shown in FIG. The bottom wiring material 5 2 a of the bottom of the hole 15 d2 is sufficiently enlarged to expose the edge of the opening, and over-etching of the bottom wiring 5 2 b at the bottom of the hole 15 5 di The side wall is cut off (enlarged aperture), and the alignment with the upper layer wiring is reduced and so on. That is, as shown in Figure 26, assuming that the opening size of the interlayer insulating film provided on the design of the lower wiring 14 is d, the opening (connection hole) 51 and the upper layer. The paper size is applicable to the Chinese National Standard (CNS) A4 size (210X297mm). "^ ------'- IT ------, Yiquan .._ (Please read the notes on the back before filling this page)

Part of the etching state becomes the pattern shape as shown in Fig. 27. That is, the diameter of the opening 51 is enlarged to d2> d. Therefore, the alignment with the upper layer wiring reduces the margin (i?> I? 2). Therefore, the surface portion 52c of the lower-layer wiring 14 is excessively etched. An object of the present invention is to provide a semiconductor integrated circuit device which can improve the accuracy of optical lithography of wiring composed of high-melting-point metals and the like and has low wiring resistance. Another object of the present invention is to provide a semiconductor device circuit that can improve the accuracy of optical lithography when patterning a conductive film made of high melting point gold or the like and connecting holes (through holes). Another object of the present invention is to provide a connection hole with a high azimuth ratio while ensuring the opening of a hole with a high azimuth ratio when forming connection holes with different azimuth ratios, and to suppress the removal of the base film of a hole with a low azimuth ratio and the Method for manufacturing semiconductor integrated circuit device with side walls removed. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) The other purpose of the present invention is to provide a lateral etching reaction that can occur during the processing of wiring connection holes and increase the size of the aperture A method for manufacturing a precision semiconductor integrated circuit device. The representative structure of the present invention will be described below. The present invention is a semiconductor integrated circuit device, characterized in that the upper layer of the high-melting-point metal film is a conductor layer composed of a conductor film having a reflectivity lower than that of the high-melting-point metal film, and has patterned wiring. At this time, the so-called high melting point metal means, for example, tungsten (W), titanium (T ί), and the like. The so-called low-reflectivity conductive film means that the light reflectivity is lower than the paper size below it. The Chinese National Standard (CNS) Α4 specification (210Χ297 mm) A7 B7 322595 V. The invention description (6) high melting point gold plume The conductor film is, for example, titanium nitride (TiN). The present invention is a method for manufacturing a semiconductor ball circuit device, which is characterized in that it includes: a process of forming a layered film composed of a high-melting point gold film and a low-reflectivity conductor film on a semiconductor substrate: using optical lithography technology The process of forming the first conductor layer composed of the layered man film: the process of forming the insulating film on the top of the first conductor layer: the process of forming the connection hole on the insulating film using the optical lithography technology on the top of the first conductor layer: and The process of forming the second conductor layer on the connection hole; According to the present invention, it is composed of a laminated wiring composed of a high-melting-point metal film with a low-reflectivity conductor film. The low-reflectivity conductor film uses TiN film. The TiN film has a lower reflectivity than the conventional light-absorbing film with a light-absorbing agent used for wiring patterning, and the contact selection ratio of the high-melting-point gold-tallow film at the base layer is higher than that of the light-sensitive photoresist film Etching selection ratio. Therefore, the loss of the photoresist film during patterning (dry etching) of the wiring can be suppressed, and even when there is no photoresist film, the TiN film becomes a hard mask, which can suppress the removal of the high-melting point gold film of the base layer. Therefore, it is possible to manufacture a semiconductor integrated circuit device which can improve the accuracy of dimension processing including the effective wiring width of TiN, and has wiring with a small wiring resistance. [Embodiment] Hereinafter, a semiconductor package circuit device according to an embodiment of the present invention and a method of manufacturing the same will be described with reference to a round system. The semiconductor integrated circuit of this embodiment constitutes, for example, a 64 Mbit DRAM. -This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) _ 9 _ ---- ΙΊ Ι1Ί --- ¾-- (please read the precautions on the back before filling in this page) Prototype Bureau Beigong Consumer Cooperation Du Printing A7 __B7__ printed by the WC Industrial Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy V. Description of the invention (7) [Example 1] FIG. 1 shows the memory including the semiconductor integrated circuit device of the present invention Cross-sectional view of the main parts of the body cell field and the peripheral circuit field. In the figure, M represents the memory cell area, and A represents the peripheral circuit area. The semiconductor substrate 1 is composed of, for example, a p-type silicon single crystal having a (100) crystal plane. In the memory cell area M and the memory cell area A of the semiconductor substrate 1, a common p-well 2ρ for the n MOS (FET) of the memory cell and the peripheral C MOS is formed. The p-well 2p is formed by selectively introducing boron (B) of the P-type impurity into the semiconductor substrate 1. In the peripheral circuit area A of the semiconductor substrate 1, an n well 2n for p MOS (FET) of peripheral CMOS is formed. The η well 2 η selectively introduces phosphorus (P) of the η type impurity into the semiconductor substrate 1. In order to prevent the formation of parasitic channels on the surface of the wafer 2 p, the p-type track stopper 4 p is formed in contact with the field isolation film 3 for element isolation in contact with this insulating film. The channel stop layer 4p is formed by introducing boron (B) and the like of p-type impurities through the insulating film 3 into all wells. On the η well 2 η, in order to prevent the formation of a parasitic channel on the surface of the well, an n-type channel stop layer 4 η is formed on this green film to be directly connected to the field insulating film 3. The channel stop layer 4? Is formed by introducing phosphorus (?) Of the? -Type impurity into the entire well through the field insulating film. The field insulating film 3 is made of, for example, silicon dioxide (S i 〇2) formed by selectively oxidizing a semiconductor substrate. The channel stop layer 4 ρ is located in the element surrounded by the field insulating film 3 to form the paper size. The Chinese National Standard (CNS) A4 specification (210X297mm) _ iq _ — 7 T — I r — 111 I — (please Read the precautions on the back and then fill out this page) Order A7 B7 printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (8) Field 5 p The internal part has a peak value of impurity concentration and is resistant to the alpha line The function of p + buried layer for prevention measures. Similarly, the channel stop layer 4 η has an impurity concentration peak value in the element formation area 4 η surrounded by the field insulating film 3, and has the function of the η + buried layer for countermeasures against α line resistance. In the element formation area 5 ρ within the memory cell area M, that is, the ρ-type semiconductor area, an η MOS (FET) 6 for the converter constituting the memory cell and a capacitor 11 for information storage are formed. n MO S 6 has an LDD (Lightly Doped Drain) structure, and is formed through a gate insulating film 6 c formed on the main surface of the p-type semiconductor field 5 p, and a structure formed on the gate electrode 6 b and the p-type semiconductor field 5 p One of the source and sink is composed of n-type semiconductor fields 6A1 and 6A2. The gate insulating film 6c is composed of Si02, for example. The gate electrode 6 b is made of, for example, n-type low-resistance polysilicon. A gate cap a made of, for example, CVD-S i 〇2 is coated on the upper portion of the gate 6 b. A side wall insulating film 10 composed of C V D-S i 0 2 is formed on the side of the gate electrode 6 b. A pair of n-type semiconductor fields 6 a 1 and 6 a 2 are formed by introducing phosphorus (P) into the p-type semiconductor field 5 ρ selectively. A semiconductor domain layer 6A2 in the n MOS 6 in the memory cell domain M constitutes a semiconductor domain layer in the adjacent n MOS 6 and becomes a common domain of the two memory cells. The shape of the capacitor 1 1 is a heat sink, and it is composed of a pair of electrodes for the container 1 1 a 1, 1 1 a 2, and an insulating film for the cyan container 1 1 b formed therebetween. The size of this paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) _ jj--------------- ^ 'only-(please read the notes on the back first Please fill in this page again.) Order 322595 Printed by the Ministry of Economic Affairs Bureau of Central Standards Staff Consumer Cooperative A7 B7 V. Description of invention (9) Capacitor electrode 1 1 a 1, 1 1 a 2 is made of n-type low-resistance polysilicon Pose. The insulating film 1 1 b for capacitor is made of, for example, silicon nitride (S i 3N4). One of the capacitor electrodes 1 1 a 1 is electrically connected to the semi-conductor field layer 6A2 of the n MOS 6, and the other of the capacitor electrodes 1 1 a 2 is electrically connected to the power supply wiring (not shown). The other capacitor electrode 1 1 a 2 is electrically connected to the power supply wiring (not shown). An n MOS (FET) 7 is formed on the element formation area (semiconductor area) 5p of the peripheral circuit area A, and a p MOS (FET) 8 is formed on the element formation area (semiconductor area layer) 5n. n MOS7 and p MOS8 form the peripheral circuit of the memory cell. 0 n M0S7 and p M0S8 have an LDD (Lightly Doped Drain) structure. n MOS7 is composed of a gate insulating film 7 c, a gate electrode 7 b, and a gate electrode 7 b formed on the main surface of the p-type semiconductor field 5ρ, and one of the source electrode and the sink electrode provided in the semiconductor field 5ρ is a pair of n-type semiconductor fields 7A1 , Composed of 7Α2. The n-type semiconductor domains 7Α1 and 7Α2 are formed by introducing n-type impurities such as phosphorous (P) and arsenic (A s) into the p-type semiconductor domain 5ρ selectively. The p MOS 8 is composed of a gate green film 8 c, a gate 8 b provided on the main surface of the η-type semiconductor field 5 η, and a pair of P-type source and sink provided in the semiconductor field 5b The semiconductor field is composed of 8A1 and 8A2. pMOS type 8A1, the size of this paper is in accordance with Chinese National Standard (CNS) A4 specification (210X297mm) _ 12 _ (please read the precautions on the back before filling this page)

The Central Prototype Bureau of the Ministry of Economic Affairs has printed this paper for the industrial and consumer cooperatives. The paper is suitable for the Chinese National Standard (€ Yang) 84 specifications (210 father 297 mm) _ A7 _B7_ V. Description of the invention (10) 8 A 2 series will be P The boron (B) of the type impurity is selectively introduced into the η-type semiconductor field 5 η and formed. The gate insulating films 7c, 8c are composed of S i 〇2 obtained by thermally oxidizing the surfaces of the semiconductor field 5 ρ and the semiconductor field 5 η. The gate electrode 7 b is made of, for example, n-type low-resistance polysilicon. On the one hand, the gate electrode 8 b is made of low-resistance polysilicon. A gate cap 9 made of CVD · S i 〇2 is coated on the top of the gates 7 b and 8 b, respectively. On the sides of the gate electrodes 7 b and 8 b, a side wall insulating film 10 made of CVD · S i 〇2 is formed. An interlayer insulating film (first insulating film) 12 is provided on the semiconductor substrate on which the capacitor 11, n, 036, 7, and MOS 8 are formed. The first insulating film is composed of, for example, a silicon dioxide (S i 〇2) and a layered film of BPSG (Boro-Phospho Silicate Glass) formed on the S i 〇2. A bit line 14B is formed on the first green film 12 of the memory cell area M, and the bit line is electrically connected to the n MOS 6 constituting the memory cell through a connection hole formed in the insulating film 6Α2 in the field of semiconductors. It is very difficult to directly contact the semiconductor area 6 A 2 via the deep connection hole with the bit line 1 4 B. Therefore, n-type low-resistance polysilicon 13 is buried in the connection hole. In the peripheral circuit area A, a pattern of the first conductor layer 14 is formed on the top of the first green film 12 at the same time as the formation of the bit line 14B, and is electrically connected to the n MOS through the connection hole provided in the first insulating film 7, n MOS8 each semiconductor field 7Α2, 8Α1. 13---- Ί --- Ί ------ (Please read the precautions on the back before filling in this page) Order A7 ____ B7 printed by the Crypto-Consumer Cooperative of the Central Bureau of Samples of the Ministry of Economic Affairs η) The bit line 14B and the first conductor layer 14 constitute the elements of the present invention and are formed into a TiN / W / TiN structure, that is, a titanium nitride (TiN) film 14a, tungsten is formed in sequence from below (W) Film 14b, and the uppermost titanium nitride film 14c. The lower TiN film 14a is provided to make ohmic contact with the semiconductor areas 7a2, 8a1. The film thickness is about 50 [nm] film 1 4 b is used as the main wiring material. The film thickness is about 150 [nm]. The upper TiN film 1 4 C is used as an anti-reflection film during wiring processing, and is left as part of the wiring material. The film thickness is about 50 [nm]. The line width of each bit line 1 4 b and the first conductor layer 14 is approximately 4 0 0 [nm] Ο The bit line and the first conductor layer 1 4 are formed on the first insulating film 12, An interlayer green film (second green film) planarized by, for example, CMP (Chemical Mechanical Polishing) 15. That is, the second green film 15 is composed of, for example, an overlapping film of Si02 / SOG / Si〇2 (15a, 15b, 15c), and the SOG 15b is subjected to CMP processing in its heavy barrier film. Therefore, the second insulating film 15 has a film thickness of about 400 [nm] on the memory cell area M, and has a film thickness of about 600-7 0 0 [nm] on the peripheral circuit area A. . On the second insulating film 15, SOG 1 5 b is held by S i 〇2 (15 a, 15 c) which is very stable to heat. Therefore, SOG 15 b itself is very unstable to heat (it is easy to crack due to temperature cycling). However, because it is covered by Si〇2 (15a, 15c) for thermal stability (please read the precautions on the back before filling in this page) • y order--7 · This paper size is applicable to China National Standard (CNS) A4 ( 210X297mm) · Μ-A7 B7 printed by the Uncle Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs 5. Description of the invention (12) Protect S0G1 5b, so even if S0G1 5b cracks, it will not affect the upper and lower conductor layers . In addition, since the upper conductor layer (second conductor layer 16) is in contact with the stable Si0 2 (15c), the accuracy of the processing dimension of the upper conductor layer can be improved. A plurality of second conductor layers 16 are formed on the second green film 15, and the conductor layers are electrically connected to the bit lines 1, 4 B and the first conductor layer 14 via connection holes. The second conductor layer 16 has a Ti N / AJ2 / W structure. That is, a tungsten (W) film 16a, an aluminum (Ai2) film 16b, and an uppermost titanium nitride (TiN) film 16c are formed in this order from below. The base layer W film 16 a serves as an obstacle between the upper layer Aj? Film 16 b and the first conductor layer 14 (bit line 14B), and in order to improve the coverage of the second insulating film 15 in the connection hole Former. The film thickness is about 50 [nm]. The A5 film 16 b is used as a low resistance wiring material. The film thickness is about 100 [nm]. The upper TiN film 16c is the same as the first conductor layer 14 (bit line 14B), and is used as an anti-reflection film during wiring processing, and is reserved as part of the wiring material. The thickness of the film is approximately 5'0 [nm]. An interlayer insulating film (third insulating film) 17 covering the second conductor layer 16 is formed on the second insulating film 15 above. This insulating film is the same as the second insulating film 16 and is composed of an overlapping film of S i 〇2 / SOG / S i 〇2 (16a, 16b, 16c). A plurality of third conductor layers 18 are formed on the third insulating film 17. Although not shown in the figure, the third medullary guide layer 18 is electrically connected to the second conductor layer 16 via a connection hole provided in the second insulating film 16. (Please read the precautions on the back before filling in this page). ¾ The standard of the paper wave is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) _-Supplementary A7 B7 for the year and month ) The third conductor layer 18 has the same Ti N / Aj? / W structure as the second conductor layer 16. The third green film 1'7 and the third conductor layer 18 are formed on the upper surface of the third conductor layer 18 with a thickness of about 600 [nm] S i 〇2 as a final surface stabilizing film for surface protection ( Final Passivation) 1 9. The method of manufacturing the semiconductor device circuit of the first embodiment (FIG. 1) will be described below with reference to FIGS. 2 to 19. In the figure, M represents the memory cell area, and A represents the peripheral circuit area. As shown in the second wall, the η well 2 η is formed on the main surface of the semiconductor substrate 1 composed of p-type silicon single crystal, and the P well 2 ρ ° η overcast = 2 π is formed when only the η well area is exposed After the photomask, phosphorus (P) or the like is injected into the semiconductor substrate, and then annealed to form. On the one hand, after forming a photomask in which only the ρ-well area is exposed, ρ-well 2 ρ is implanted into the semiconductor substrate with boron (B), etc., and then annealed to form _. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). Specifically, when forming ρ-well 2 ρ and η-well 2 η, self-adjusting technology using oxide film thickness ( Double-trap self-adjustment) reached (not shown). That is, the Si 3 N 4 film of the oxidation-resistant film selectively covers the main surface of the semiconductor substrate 1 on which the P well needs to be formed. Then, an ion implantation method is used to form an impurity of n-type phosphorus on the main surface of the n-well of the semiconductor substrate 1 on which the Si3N4 film is not formed to form an n-type ion implantation layer. At this time, the implantation dose is 2.0 × 1013 atoms / cm2, and the implantation energy is 12 5KeV. Then, using the Si3N4 film as a photomask, the surface of the n-type ion implantation layer is selectively oxidized to form a Si02 film on the surface. Then, without removing the S i3N4 film, use the S i 〇2 film (select the paper size applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) -16-A7 printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ___B7_ V. Description of the invention (14)

(Selective oxide film) is a photomask, and an ion implantation method is used to introduce an impurity made of P-type boron into the main surface of the P-well (the main surface of the semiconductor substrate 1 with the Si 3N4 film removed) to form a p-type ion implantation layer . At this time, the injection dose is 8. 0X1012 atoms / cm2, and the injection energy is 6 OKeV. Then, under the condition of a temperature of about 800 ° C ~ 120 ° C, the well diffusion with the annealing of ion implantation damage recovery is performed, 1 1 a p-well 2 P and an n-well 2 are formed in the semiconductor substrate 1 η. In this way, the Si02 film formed on the surface of the well is removed. Fig. 2 shows the semiconductor substrate when the Si02 film is removed. Then, as shown in FIG. 3, a field insulating film 3 is selectively formed on the main surface of the semiconductor substrate 1 on which the wells 2p, 2n are formed. The field insulating film 3 is composed of Si 0 2 with a film thickness of about 400 [nm], and is formed by the well-known LOCOS (Local Oxidation of Silicon) method. The third wall is a semiconductor substrate in a state where the oxidation-resistant photomask (Si3N4 film) used when forming the field green film 3 is removed. Then, as shown in FIG. 4, a p-type channel stop layer 4p and an n-type channel stop layer 4n are formed on the semiconductor substrate 1. First, in order to form the p-type channel stopper layer 4 ρ, a photomask covering the η well 2 η surface is selectively formed, and boron etc. are introduced into the p well 2 forming the photomask on the surface through the field insulating film 3 by ion implantation ρ · 内. At this time, the injection agent is set to 4X1 012 a t oms / cm2, and the injection energy is 18 OKeV. By implanting ions at such a high energy level, impurities can be introduced into the ρ well 2 ρ through the field insulating film 3, and the bromine peak of the impurity near the interface between the arson field insulating film 3 and the ρ well 2 ρ can be obtained by this It can prevent the formation of field-scale film 3 below the scale of the use of the Chinese National Standard (CNS) A4 specifications (210X297 mm) -17 · (please read the precautions on the back before filling this page)

Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7___ 5. The parasitic channel of the invention (is) (n-type inversion layer). The p-type channel stopper layer 4 p has an impurity degree in a p-well in which a thin S i 〇2 film 3 a without a field insulating film 3 is formed, at a position deeper than directly below the field green film 3 The spikes have the function of burying the P + layer for the so-called α-line resistance. In order to form the η-type channel stop layer 4 η, a photomask on the surface of the ρ-well 2 is selectively formed, and phosphorus or the like is introduced into the η-well 2 without a photomask on the surface through the field insulating film 3 by ion implantation within η. Then, the semiconductor substrate 1 is annealed to recover the damage that occurred during ion implantation and elongated diffusion, forming p-type and n-type channels as shown in FIG. 4 in the ρ-well 2 ρ and η-well 2η, respectively Stop layer 4ρ, 4η. Then, as shown in Figs. 5 and 6, MISFETs 6, 7, and 8 are formed on the main surface of the semiconductor substrate. Before forming the gates (gate insulating film and gate), ion implantation is used in the ρ well 2ρ, Boron and phosphorus are introduced on the surface of the η well 2η, respectively, to form a p-type and n-type element formation area 5 ρ, 5 η. In this way, the MI SFETs provided in the device formation area 5 ρ, 5 η can have the required electrical characteristics. Specifically, because of the threshold value voltage (Vt h) control, the P well 2 ρ and η well 2 η can be controlled. Surface impurity concentration. That is, the element formation area 5 ρ is an area where n MOS is formed, for example, it is formed by implanting boron ions at an implantation dose of 3.6 X 1 〇12at oms / cm2 and an implantation energy of 45 KeV. On the other hand, the element formation area 5 η is the area where the p MOS is formed. For example, an implantation dose of 4 XI OUa t oms / _cm2 and an implantation energy of 4 OKeV are formed by the phosphorus implantation method. After removing the S i 0 2 film 3 a, 3 b, as in 18-(please read the precautions on the back before filling in this page)

V. Description of the invention (16) Printed in Figure 5 of the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, as shown in Figure 5, the main surface of each component formation area 5 p, 5 n is thermally oxidized to form a structure consisting of S i 〇2 Gate insulating films 6c, 7c, 8c. The film thickness is about 12 [nm]. Then, in order to form the gate electrodes 6b, 7b, 8b on the surface of the element formation area 5p, 5n, first, an n-type low resistance polysilicon film is deposited by CVD method. The thickness of the polysilicon film is about 15 0 [nm]. Then, an insulating film made of Si0 2 is used as a cap layer by CVD or the like. The film thickness is about 200 [n m]. Then, an optical lithography technique or an etching method is used to form an insulating film and a polysilicon film pattern to form gates 6 b, 7 b, and 8 b and a gate cap layer 9. In this way, the semiconductor areas 6al, 6a2, 7al, 7a2 of the n-type MI SFET integrated in the field insulating film 3 and the gates 6b, 7b are selectively formed in the element formation area 5p. For example, the semiconductor field is formed by ion implantation. The ion implantation conditions at this time are, for example, an implantation dose of 2 X 1 0 1 3 at oms / cm2 and an implantation energy of 4 OKeV. Then, a self-integrated p-type MISFET semiconductor area 8a1, 8a 2 is selectively formed on the field-exiting green film 3 and the gate electrode 8b in the element formation area 5n. Each semiconductor field is formed by boron ion implantation. The ion implantation conditions at this time are, for example, an implantation dose of 2 X 1 0 1 3 at 0 m s / cm2, and an implantation energy of 4 5 KeV. Then, as shown in Fig. 6, side walls 10 are formed on the side surfaces of the gate electrodes 6b, 7b, 8b and the field insulating film 9. Specifically, the side wall 10 A, 10 B is formed by forming the Si 0 2 film with a thickness of 100 [nm] and anisotropically etching the SIO 2 film. (Please read the precautions on the back before filling in this page) 1 *. The size of the printed paper is in accordance with the Chinese National Standard (CNS) A4 (210X297mm) 19 Printed by the Ministry of Economic Affairs Central Falcon Bureau Shoulder Consumption Cooperative 32 ^ S9s A7 —_B7 V. Description of the invention (I7) Then, as shown in FIG. 6, side walls 10 are formed on the sides of the gate electrodes 6b, 7b, 8b and the green film 9. Specifically, the Si 0 2 film thickness is formed to a thickness of 100 [nm], and the Si 0 2 film is anisotropically etched to form sidewalls 1 OA and 1 OB. Then, the semiconductor areas 6A1, 6A2, 7A1, and 7A2 that are self-integrated into the field insulating film 9 and the side wall 1 OA are selectively formed in the element formation area 5 p. The semiconductor field 6A1, 6A2, 7A1 '7 A2 is formed using a phosphorus ion implantation method and an impurity introduction method including annealing treatment, and has a deeper and higher impurity concentration than the previously formed semiconductor field 8 a 1, 8 a 2 field. Annealing treatments for forming n-type semiconductor areas 6A1, 6A2, 7A1, 7A2, and p-type semiconductor areas 8A1, 8A2 are performed simultaneously. Then, as shown in FIG. 7, on the main surface of the semiconductor substrate (memory cell area M), a heat dissipating capacitor 11 constituting the memory cell is formed. The specific method of forming the capacitor will not be described in detail. In this embodiment, the capacitor 11 uses a heat sink type capacitor having three heat sinks, but the present invention is not limited thereto, and a crown type capacitor may also be used. Then, as shown in FIG. 8, an insulating film (first insulating film) 12 is formed on the semiconductor substrate on which the capacitor 11 is formed. The first insulating film 12 is composed of, for example, S〇2 and 8-30. The S i 〇2 film has a film thickness of about 100 0 [nm], and uses CVD (

Chemical Vapor Deposition) method. The reaction gas system used at this time is, for example, a mixed gas of SiH4 and N2〇. The successively formed BPSG (Boro-Phospho Silicate Glass) film has a large thickness (please read the precautions on the back and then fill out this page). The paper size is applicable to China National Standards (CNS) A4 specification (210X297mm) 20-Economy A7 B7 is printed by the employee consumer cooperative of the Central Bureau of Standards. V. Description of invention (18) is about 500 [nm], and it is the product of CVD method. In the reaction gas system used at this time, for example, T E 0 S (Tatraethoxysilane) gas, a mixed gas of phosphorus and boron is added. Then, in order to eliminate the severe step difference of the insulating film 12 between the memory cell area M and the peripheral circuit area A, the upper surface of the insulating film is formed as a relief surface. Therefore, after annealing the semiconductor substrate 1 to relax the insulating film 12 to 1, the surface of the insulating film 12 is etched back. Then, the semiconductor substrate 1 is annealed again. The annealing treatment is carried out in a mixed gas of 1 ^ 2 and 02. In this way, the first insulating film 12 is formed as an interlayer insulating film. Then, as shown in FIG. 9, a connection hole 1 2 a is formed in the first insulating film 12 to connect to the semiconductor field 6A2 of the n MOS 6 constituting the memory cell. This connection hole is formed by, for example, optical lithography technology and etching technology. Then, a conductive film 13 made of, for example, n-type low-low resistance polysilicon is buried in the connection hole 12a. The formation method of the conductor film 13 is as follows. First, n type low resistance polysilicon is pushed on the first insulating film 12 by CVD. The reaction gas system used at this time is a mixed gas of silane gas (S i H4) and phosphorus (PH3). Then, the polysilicon film formed by the CVD method is etched back to form a conductive film only on the connection hole 12 a, that is, a state where the polysilicon film remains. Then, as shown in FIG. 10, a connection hole 1 2 b is formed on the first insulating film 12 to connect one of the semiconductor areas 7A2 of n MOS7 constituting the peripheral circuit and one semi-conductor area 8A1 of P MOS8. The connection hole 1 2 b is made using optical lithography technology and the paper standard is applicable to the Chinese national standard (CNS> A4 specifications (210X297 mm) _ 21 (please read the precautions on the back before filling this page) H ^ Order Printed by the Ministry of Economic Affairs, Central Falcon Bureau Consumer Labor Cooperative A7 B7 V. Description of the invention (19) Etching technology is formed. Then, as shown in Figures 1 1 and 12, the bit lines 1 that constitute the memory cell circuit are formed 4 B, and the first conductor layer 14 that constitutes the peripheral circuit. The first conductor layer 14 is a characteristic element of the present invention and is manufactured by the following method. First, as shown in FIG. The main surface of the first 1 1 insulating film 12 of the hole 1 2 b is deposited with a metal film 14 a made of titanium nitride (TiN) by ion sputtering. Alternatively, it can also be pushed by ion sputtering After titanium (T i), heat treatment is performed in nitrogen (N 2) to form a Ti N film 14 a. When using this method, T i diffuses to the junction of the deposited gold-titanium film and the semiconductor field In the semiconductor field, the contact resistance can be reduced. The thickness of the TiN film 14a is approximately 50 [nm]. For example, a metal film 14 b made of tungsten (W) is formed. To this end, the W film is deposited by ion sputtering. Then, the W film is deposited by CVD. The thickness of the W film is about 150 [nm 〕. The W film made by the former ion sputtering method has the function of improving the coverage of the base layer film in the connection hole 12 b. Then, for example, the ion sputtering method is used to form a T i N film on the tungsten film 1 4 b. The formed film 1.4 c. The thickness of the Ti N film 14 c is about 50 [nm], and it is formed for the purpose of costing the invention as described later. That is, Ti N The film 14 has the function of an anti-reflection film. Then, a photoresist is coated on it, and the pattern of the photoresist is formed by optical lithography. Then, as shown in FIG. 12, it is formed by dry etching, etc. The size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) 22-(Please read the notes on the back before filling in this page) Order $ 月 日 修 止 'Supplement, A7 B7 Employee Consumption, Central Standards Bureau, Ministry of Economic Affairs Printed by the cooperative 5. Description of the invention (20) Picture of T i N film 1 4 a, 1 4 c and W film 1 4 b It is integrated with the pattern of the remaining photoresist R. Τ ί N film and W film can be etched in stages, or continuous etching, such as stage etching of TiN film and W film, first use The mixed gas of BCi ^ 3 and Cj ^ 2 dry-etchs the TiN film at a temperature of about 40 ° C. Then, the mixed gas of SF 6 and N2 is used at a temperature of about -10 ~ -3 0 ° C The W film was dry-etched at the temperature. On the one hand, when successively etching the TiN film and the W film, for example, a mixed gas of 3? 6 and 8 (: 3) is used for dry etching at a temperature of about 10 ° (:. Then, the ashing method is used only The photoresist R is removed. In this way, the bit line 14B constituting the memory cell circuit is formed, and at the same time, the first conductor layer 14 forming the peripheral circuit is formed. Then, as shown in FIG. 1 4 B and the upper surface of the first conductor layer 14 are formed with an interlayer insulating film (second insulating film) 15. The method for forming the second insulating film 15 is as follows. First, on the semiconductor substrate, the CVD method is used to derive the product from Si. 2 Insulation film 1 5 a formed by the film thickness of 2 0 0 [nm]. The reaction gas system used at this time, such as TEOS and a mixed gas of helium (He) and 〇2. Then, in the green film 1 5 a coated with eg SOG (

Spin On Glass) film 1 5 b. The film thickness is 300 [nm]. Then, the upper part of the insulating film of the double-layer structure is back-etched so that the upper surface becomes gentle. Then, on the SOG film 15b, an insulating film 15 c composed of Si0 2 is deposited by CVD. The film thickness is 200 [nm]. The reaction gases used at this time are, for example, TEOS, He and 〇2. The paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling this page)-Order- 23-A7 B7 322595 V. Description of the invention (21) Mixed gas. In order to improve the accuracy of the pattern of the upper layer wiring, for example, the upper surface of the second insulating film 15 is flattened using CMP technology. This CMP is performed on the SOG film 15 b. After flattening in this way, the accuracy of the optical lithography technology of the upper wiring can be improved, that is, the focus margin during exposure, and the shape of the photoresist pattern can be prevented from being defective. In this way, the fineness of wiring pitch and reliability can be improved. Then, as shown in FIG. 14, connection holes 15d1, 15d2 for connecting the first conductor layer 14 and the second conductor layer are formed in the second insulating film 15. Therefore, a photoresist R is applied on the second insulating film 15 to form a pattern by optical lithography. Then, using the pattern of the photoresist R as an etching mask, the second insulating film 15 located in the memory cell area M and the peripheral circuit area A is etched by dry etching, and the connection holes 15dl, 1 are formed at the same time. 5d2. The etching gas system uses a mixed gas of CF4, CHF3 and Ar. Then, as shown in FIGS. 15 and 16, a second conductor layer 16 is formed. As shown in FIG. 15, the second conductor layer 16 is formed with a ΪΙ (W) film 16 a, an aluminum (A5) film 16 b, and a titanium nitride (T i N) film on the uppermost layer from the bottom It is formed by 1 6 c, and its manufacturing method is as follows. First, for example, a gold film 16 a made of tungsten (W) is formed. In order to improve the covering characteristics of the metal film provided in the connection hole on the second insulating film 15, the metal film 16a is made by ion sputtering method Long Zhen. The film thickness is about 50 [nm]. Then, the W film was deposited by CVD. The film thickness is about 100 [n m]. Then 'use the C V D method # 稹 a metal film 16 b composed of A5. The thickness of the film is about 400 0 [nm The paper size is in accordance with Chinese National Standards (CNS & A4 specifications (210X297 mm) -24-(please read the precautions on the back and then fill out this page) H Printed on the A7 ________B7____ by the Beigong Consumer Cooperative Society of the Ministry of Industry and Technology. 5. Description of the invention (22)]. Then, in order to achieve the same purpose as the first conductor film, a gold film composed of T i N is formed by ion sputtering. 1 6 c is used as an anti-reflection film. The thickness of the film is about 50 [nm]. Then, as shown in FIG. 16, the optical lithography technique and the etching technique that form the pattern of the first conductor layer 15 are used to form the second Conductor layer 16. Then, as shown in FIG. 17, an insulating film (third insulating film) 17 is formed on the second conductor layer 16

I. The third insulating film 17 is formed in the same manner as the second insulating film 15, and is composed of an overlapping film of Si〇2 / SOG / Si〇2 (17a, 17b, 17c). At this time, since the second insulating film has been subjected to CMP to flatten the main surface of the semiconductor substrate, it is not necessary to perform CMP on the third insulating film. Although not shown in the figure, a connection hole for connecting to the second conductor layer 16 is formed in the third insulating film 17. The connection hole is formed in the same way as the connection hole of the first guide layer 14 and the second conductor layer 16. Then, as shown in FIG. 18, a third conductor layer 18 is formed. The third conductor layer 18 is formed in the same manner as the second conductor layer 16, for example. Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Then, as shown in Figure 19, a surface protective film 19 is formed and a third conductor layer 18 is coated on the umbrella conductor substrate. This surface protection film 19 is composed of, for example, S i 〇2 having a thickness of 600 [nm], and is conic by CVD method. A reaction gas system such as TEOS, a mixed gas of He and 02. The specific embodiment of the method for manufacturing the semiconductor integrated circuit device of the present invention has been described above. In this embodiment, the upper surface of the W film 1 4 b constituting the first conductor layer 14 (and the bit line 14 B) is covered with a Ti N film 14 c. Therefore, when forming the pattern of the first conductor layer 14 as shown in the twelfth image, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling this page) 25-Printed copies of the paper printed by the Central Provincial Bureau of Industry and Consumer Cooperatives of the Ministry of Economic Affairs of the People ’s Republic of China Standards (〇 阳) 84 specifications (297 mm 2) _ A7 _____ B7_- V. Invention description (23) can be produced The following functions and effects. The inventor of the present invention compared the BARC film with the TiN antireflection film. Figure 20 shows the results. The function and effect of the present invention will be described below based on the comparative data shown in Article 20. First, the reflectivity of Ti N is 30%, which is lower than that of tungsten by 60%. Therefore, it is possible to prevent the light-recording effect from occurring during the exposure of the light-resistant film (projection exposure), that is, the step (concavo-convexity) of the base film (first conductor layer 1 4) although the light-resistant agent is present because of its base The surface of the film is composed of TiN film with low reflectivity, so it can reduce the standing wave caused by chaotic reflection. In addition, the focus margin can be improved. That is, the allowable range of uneven etching resistance to uneven light film thickness can be expanded. Therefore, the processing accuracy of the photoresist R shown in Fig. 21 (a) can be improved. In Figure 21, the TiN film (14a) of the base conductor film is omitted. The etching selection ratio of the T i N anti-photo film is about 4, which is higher than that of the conventional BARC film. The etching time of T i N is about 10 seconds, which is shorter than 180 seconds of conventional BARC film processing time. Therefore, when the TiN film shown in Fig. 21 (13) is etched, the size of the light-resistant film drifts and the light loss is small, which can improve the accuracy of the T i N film 14 c. Because the processing time is short, the throughput can be increased. The etching selection ratio of T i N to 鋳 is about 5, which is higher than the etching selection ratio 2 of the photoresist film (BARC film). Therefore, as shown in FIG. 21 (c), the photoresist R and T i N film 14 c used as the etching mask of the tungsten film 14 b will not be removed by S, and the first conductor film 14 can be improved Graphical accuracy. 26-(please read the precautions on the back before filling in this page) Order Α7 Β7 Printed by Beigong Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs --- 24 V. Description of Invention () If continuous processing of W film 1 4 b and When the Ti N film is 4 c, it can be processed with only one device, so the throughput can be improved. In addition, during plasma etching, when the T N film etching is changed to the W film etching, the occurrence of the ® slurry is not cut off, so the foreign objects floating in the plasma will not adhere to the semiconductor substrate, which can reduce the foreign objects. In this embodiment, because the upper surface of the first conductor layer 14 is composed of the Ti N film 14 c, the following effects can be produced when the second green film 15 is etched. Figure 22 is a model diagram of its efficacy. First, as shown in FIG. 22, because the insulating film has a high etching selectivity to the TiN film 1 4 C, the first conductor layer 14 at the bottom of the hole is not excessively removed. That is, the Ti N film 14 c produces an etching stop. Second, as shown in FIG. 22, the ΤΝΝ exposed at the bottom of the hole reacts with the etching gas to produce a nitrogen compound 50, the nitrogen compound 50 is attached to the side wall to protect the side wall, so the diameter of the connection hole d 1 does not expand excessively. The third, because the opening d 1 of the connection hole does not expand, so the wiring connection hole 5 1 and the upper wiring 16 can be aligned according to the design 1. The width margin 1 1 is the same as this embodiment. In the example, when the first green film 12 is planarized, the azimuth ratio of the connection holes in the M-cell region M and the peripheral circuit region A is different. When the connecting holes with different azimuth ratios are simultaneously formed by the Limao etching method, the openings of the holes with high azimuth ratio must be confirmed on the one hand, and the excessive opening of the holes with low azimuth ratio must be suppressed by 3 ° The upper part is constructed by Τ ί N (please read the precautions on the back and then fill out this page) τ ', the paper size of the order is to use the Chinese National Falcon (CNS) Μ specification (210X297 mm) 27 322595 Central Sample of the Ministry of Economic Affairs The quasi-administrative staff's consumer cooperation du printing and repairing-supplement. H A7 B7 5. The invention description (25) was completed, so this problem can be solved. That is, the side wall of the connection hole can be protected and over-etching of the connection hole can be suppressed. Figure 2 3 (a) shows a schematic diagram of its effect. That is, the side wall of the connection > L can be protected and the over-etching of the connection hole can be suppressed. Therefore, in this embodiment, etching processes can be used to simultaneously form connection holes with different orientations, which can prevent an increase in the manufacturing process. The above effect can also be achieved when the second conductor layer and the third conductor layer are composed of a metal film of aluminum (Aj?) With a resistance coefficient less than TiN, W, Mo, etc. The effects of the present invention will be described below. 1>. It can improve the accuracy of optical lithography technology when forming patterns of conductive films and connecting holes made of high melting point metals. ♦ 2). It can improve the processing accuracy of the conductor film composed of high melting point metals. 3). When connecting holes with different azimuth ratios are formed, on the one hand, the opening of the holes with high azimuth ratios can be ensured, while the removal of the base film and the side walls of the holes with low azimuth ratios can be suppressed. That is, even if etching is performed on the bottom of the hole with a high aspect ratio to expose the underlying structure, the bottom of the hole with a low aspect ratio and the side wall can be prevented from being over-etched. 4). It can improve the precision of the size of the conductor film made of high melting point golden noodles and the connecting hole, and can improve the alignment margin between the connecting hole and the upper conductor film. 5). It is possible to use simultaneous etching to form insulating films of connection films with different orientation ratios, which can prevent a significant increase in the manufacturing process. (Please read the precautions on the back before filling in this page) The standard paper size is applicable to the Chinese National Standard (CNS) A4 (210 X297 mm) -28-Printed by the Ministry of Economic Affairs Central Bureau of Economics and Technology Co., Ltd. A7 ___B7______ V. Description of the invention (26) Schema: Figure 1 is a cross-sectional view of the main part of the semiconductor integrated circuit device of the embodiment of the present invention: Figure 2 is the manufacturing process of the semiconductor integrated circuit device shown in the first circle A cross-sectional view of the main part of the semiconductor substrate of the semiconductor substrate; Figure 3 is a cross-sectional view of the main part of the semiconductor substrate during the manufacturing process of the semiconductor integrated circuit device shown in Figure 1; Figure 4 is the semiconductor shown in Figure 1 The cross-sectional view of the main part of the semiconductor substrate during the manufacturing process of the integrated circuit device; FIG. 5 is the cross-sectional view of the main part of the semiconductor substrate during the manufacturing process of the semiconductor integrated circuit device shown in FIG. 1: FIG. 6 is Figure 1 shows the cross-section of the main part of the semiconductor substrate in the manufacturing process of the semiconductor integrated circuit device; Figure 7 shows the cross section of the main part of the semiconductor substrate in the manufacturing process of the semiconductor integrated circuit device shown in Figure 1 Picture: Picture 8 is the first picture The cross-sectional view of the main part of the semiconductor substrate in the manufacturing process of the conductive volume circuit device; FIG. 9 is the cross-sectional view of the main part of the semiconductor substrate in the manufacturing process of the semiconductor masher circuit device shown in FIG. 1: 0 is the cross-sectional view of the main part of the semiconductor substrate in the manufacturing process of the semiconductor masher circuit device shown in the first 囵; Sectional view of the main parts: Figure 12 shows the manufacturing of the semiconductor device circuit shown in Figure 1. This paper has been produced using the Chinese National Instruments (CNS) 84 specifications (210X297mm). 29-(please first Read the precautions on the back and fill in this page) Order A7 __B7__ printed by Beigong Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economy V. Invention description (27) Sectional view of the main parts of the semiconductor substrate in the process: Figure 13 is the first figure The cross-sectional view of the main part of the semiconductor substrate in the manufacturing process of the semiconductor masher circuit device shown: Figure 14 is the cross-sectional view of the main part of the semiconductor substrate in the manufacturing process of the semiconductor integrated circuit device shown in Figure 1: Picture 15 is the half of picture 1 The cross-sectional view of the main part of the semiconductor substrate during the manufacturing process of the conductor ball circuit device: Figure 16 is the cross-sectional view of the main part of the semiconductor substrate during the manufacturing process of the semiconductor integrated circuit device shown in Figure 1; 7 is a cross-sectional view of the main part of the semiconductor substrate in the manufacturing process of the semiconductor integrated circuit device shown in FIG. 1: FIG. 18 is a semiconductor substrate in the manufacturing process of the semiconductor integrated circuit device shown in FIG. 1 Figure 19 is a cross-sectional view of the main part of the semiconductor substrate in the manufacturing process of the semiconductor integrated circuit device shown in Figure 1: Figure 20 is a conventional BARC film and the T 丨 of the present invention Comparison chart of N reflection prevention film: Figure 2 1 (a) ~ (c) is a cross-sectional view of the etching mechanism of the conductor layer when using the present invention: Figure 2 2 囵 is the connection hole and upper layer wiring when using the present invention The pattern diagram and cross-section of the alignment width margin: Figure 23 shows the cross-section of the main part of the semiconductor device circuit device in which connection holes with different azimuth ratios are formed on the interlayer insulating film when using the present invention. 2 4 (a) ~ (c) is the guide layer etching in the conventional technology ^^ 1- In i_l In 1 ^ 1 ^^ 1 ί. Ντ «Γ (please read the precautions on the back before filling in this page) The size of the paper used for the Chinese National Standard (CNS) Α4 specification (210Χ297mm) 30-322595 A7 B7 5. Description of the invention (28) Sectional view of the mechanism: Figure 25 shows the main part of a semiconductor integrated circuit device in which connection holes with different orientation ratios are formed on the interlayer insulating film when using conventional techniques Top view: Figure 2 6 is a schematic diagram of the alignment width margin of the connection hole and the upper wiring at the design stage: Figure 2 7 is a schematic diagram of the alignment width margin of the connection hole and the upper wiring when using conventional technology And its cross-section. Printed by the Beigong Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs [Symbol Μ Semiconductor Velvet Film. Layer 0 0 6 6 a 1 6 A 2: gate η Μ 0 7 A pole 0 ρ Μ. 8 Pole pole. wall. Description】: Remember the 100 million body substrate. 5 Ρ: shape, 6 I η insulation 0 S 1 »7 c 0 S A 1 P:: P is formed in a 2 type high film ° 0 7 A •• Gate cell area. A: 2 p: ρ well 0 2 P-type channel stop layer. Semiconductor field. Within the memory cell area: n-type low-concentration semiconductor area. 7: formed on the periphery 7a1, 7a2: 2: η-type high-concentration semi-polar insulating film. 8: 8 a 1 »8 a 2: A 2: ρ-type high-degree gate insulating film. 9 Container β 1 1 a 1 Peripheral circuit area η: η lecture 0 4 η: η type 5 η: η type half of the η Μ Ο S body area. 6 6 b: n-type low-degree semiconductor in the field of gate circuits. Formed in the field of peripheral semi-semiconductors with low-degree P-type. : Insulating film. , 1 1 a 2: 3. Field barrier stop conductor area Ο A 1, conductor area 7 b: conductor area within the gate area 8 b: 1 0: for side capacitors (please read the precautions on the back before filling in this Page) This paper scale is applicable to China National Standards (CNS) A4 specifications (21〇X297 mm) 31 A7 B7 Printed by the National Standards Bureau of the Ministry of Economic Affairs, the Consumer Labor Cooperatives 5. Instructions for invention (29) Electrodes. lib: insulating film for capacitors. 12: The first insulating film. 12a, 12b: the connection hole of the first insulating film. 13: Conductor membrane. 14: The first conductor layer. 14a ~ 14c: Metal film. 15: The second insulating film. 15a ~ 15c: insulating film. 15d, 15dl, 15d2: the connection hole of the second insulating film. 16: The second conductor layer. 16a ~ 16c: metal film. 17: The third insulating film. 17a ~ 17c: insulating film. 18: The second conductor layer. 18a ~ 18c: metal film. 19: Surface protection film. 50: Nitrogen compounds. 51: connection hole. 52a, 52b: The first conductor layer composed of W is used conventionally. 52c: Over-etched part of the first conductor layer. R: Light-resistant film (mask). E: It is used to remove the chip part of the first conductor layer composed of W. S: The shoulder of the first conductor layer composed of Ti N in the upper layer of the present invention is removed. d: The opening diameter of the connection hole at the design stage. d1: opening diameter of the connection hole when using the present invention. d 2: Diameter of connection hole when using conventional technology. 1: When designing the blind section, the connection hole and the upper layer wiring are aligned with the margin. 1 1: Alignment width margin of connection hole and upper layer wiring when using the present invention. 1 2: Alignment width margin of connection hole and upper layer wiring when using conventional technology. (Please read the precautions on the back first and then fill out this page) The size of this paper is applicable to China National Standard (CNS) Α4 specification (210Χ297mm) _ 32-

Claims (1)

6. Patent application scope No. 841 1 1 554 Patent application Chinese application Patent scope amendment December, 1985 Amendment 1. A semiconductor integrated circuit device, which is characterized by including: the upper surface of the high melting point metal film by the reflectivity A first conductor layer composed of a conductor film having a reflectance lower than the high melting point gold film; an insulating film formed with a connection hole on the first conductor layer; and connected to the portion of the first conductor layer provided in the connection hole The second conductor layer. Printed and printed by the Ministry of Economic Affairs of the Ministry of Economic Affairs and Industry and Consumer Cooperatives (please read the precautions on the back before filling out this page) 2. A semiconductor integrated circuit device, which includes many memories with capacitors and M ISFET The dynamic semiconductor memory device in the memory cell field constituted by the body cell and the peripheral circuit field constituted by many M ISF ET is characterized by including: covering the memory cell field and the peripheral circuit field The first insulating film; the reflectivity of the high-melting-point metal film formed on the first-insulating film on the memory area and the first-insulating film on the peripheral circuit area, and on the high-melting point metal film Many first conductor layers composed of a conductive film of the melting point metal film; a second insulating film with connection holes formed on the first conductor layer in the area of the memory cell and peripheral circuits; The second conductor layer in the first conductor layer portion of each connection hole. 3. For the device of patent application item 1 or 2, the high melting point metal film is a tungsten film. 4. The device as claimed in item 1 or 2 of the patent application, wherein the low-reflectivity conductor film is a titanium nitride film. 5. If the device of patent application item 1 or 2, the high melting point paper size is printed in China National Standards (CNS) Α4 specification (210X297 mm). The Alpha 8 is printed by the Male Industry Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs. Β8 C8 D8 VI. Patent application The metal film is a tungsten film, and the low-reflectivity conductor film is a titanium nitride film. 6. For example, the device in the second scope of the patent application, in which the orientation ratio of the connection hole in the area of the memory cell and the connection hole in the area of the peripheral circuit are different. 7. A method for manufacturing a semiconductor integrated circuit device, characterized in that it includes: forming a first semiconductor film composed of a high melting point metal film and a conductive film having a reflectivity lower than that of the high melting point gold film 1 The process of the pattern of the conductor layer; the process of forming the insulating film on the top of the first conductor layer; the process of forming the connecting hole on the insulating film using the optical lithography technology on the top of the first conductor layer; and the formation of the second on the connecting hole Conductor layer process. 8. A method for manufacturing a semiconductor integrated circuit device, which has a memory cell field composed of many memory cells including a capacitor and M ISF ET, and is composed of many M ISF ET The dynamic semiconductor memory device in the peripheral circuit field is characterized by including: the process of forming the memory cell field in the memory cell field of the semiconductor substrate, and the process of forming the M ISF ET in the peripheral circuit field; on the main surface of the semiconductor substrate The process of forming the first insulating film covering the memory cell in the memory cell field and the MISFET in the peripheral circuit field; forming a metal film with a high melting point on the first insulating film and a reflectivity lower than high The process of laminating a film composed of a conductive film that melts the reflectivity of the metal film; the process of forming the first conductor layer for the memory cell composed of the laminated film and the first conductor layer for the peripheral circuit using optical lithography The process of forming an insulating film on the top of each first conductor layer; the process of forming the first and second connection holes on the insulating film on the top of the first conductor layer using optical lithography; On the 1st, the first paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm) _ 〇 (please read the notes on the back before filling this page). Order the Ministry of Economic Affairs Central Standards Bureau negative labor consumption cooperative printed «. A8 B8 C8 D8 VI. Patent application 2 The process of forming the second conductor layer on the connection hole respectively. 9. For the method of claim 7 or 8, the high melting point gold film is a tungsten film. 10. If the method of patent application item 7 or 8 'where the low-reflectivity conductor film is a silicon nitride film "1 1 · If the method of patent patent application item 7 or 8, where the high melting point gold film is applied The tungsten film and the low-reflectivity conductor film are titanium nitride films. 1 2. As in the method of claim 7 or 8, the aspect ratio of the connecting hole is different. 1-3. The method as claimed in item 7 or 8 of the patent application, wherein the high-melting-point gold film is a tungsten film, and the low-reflectivity conductor film is a titanium nitride film, which is continuously formed by a tungsten film and a nitride The pattern of the laminated film composed of the titanium film to form the first conductor layer "14. As in the method of claim 7 or 8, the insulating film on the first conductor layer becomes flat. 15. A semiconductor integrated circuit device, characterized in that the upper surface of the metal film with a low resistivity includes a conductor film composed of a conductive film with a resistivity greater than the resistivity of the metal film and a reflectivity less than the reflectivity of the metal film 1 Conductor layer, an insulating film forming a connection hole on the first conductor layer, and a second conductor layer connected to the portion of the first conductor layer provided in the connection hole. 16. The device as claimed in item 15 of the patent application, wherein the metal film is an aluminum film * and the low-reflectivity conductor film is a titanium nitride film. 1 7. A method for manufacturing a semiconductor integrated circuit device, which is characterized by having a semiconductor substrate (1) with a main surface prepared, and the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -3-< "Strategy-(Please read the precautions on the back before filling in this page) Order 322595 SJ C8 D8 6. The scope of patent application and the formation of the first conductor film (14b) of high melting point gold on the main surface of the aforementioned semiconductor substrate ) 'And a second conductor film (1 4 c) having a low reflectance via the first conductor film is formed on the first conductor film, and a photoresist film is formed on the second conductor film ( R), and patterning the photoresist film, and using the patterned photoresist film as a photomask, etching the second conductor film 'and etching the second conductive film as a photomask It is used to etch the aforementioned first conductor film. 18. A method for manufacturing a semiconductor integrated circuit device according to claim 17, wherein the aforementioned second conductor film is titanium nitride. 1 9. A semiconductor Integrated circuit device The manufacturing method is characterized by preparing a semiconductor substrate (1) with a main surface, and forming a high melting point of gold on the main surface of the aforementioned semiconductor substrate (please read the precautions on the back before filling this page) Ministry of Economic Affairs _ Central Diplomatic Bureau Cooperative Consumer Cooperative Printed Body Engraved Conductive Etching Path. 2. Electrician, using bulk titanium to make the accumulation of low R with bulk nitrogen as the rate, {add conductivity as the rate to cover the film half film The anti-reflective body of the film-blocking light is the guide. Let the guide be made into the shape of 9 1 CM film 1 on the film "quote, the first section, the body of the film resists the enclosing} introduction case light film Fan Qianb's physical benefits of the previous map, 41 Yuzhi's film guide secondary school 1 No. 2 into the case, please call it {述 形 第 光 图 2 Shen, film front} The description of the first legal body from C front front Front and side guide 4 Yu Ling will Ιο made ί and 1 and the second and the second system of the film described in front of the paper size of this paper is applicable to China National Standards (CNS) 8 4 specifications (210Χ297 mm) -4 -A8 B8 C8 D8 VI. Patent application range 2 1.-A method for manufacturing semiconductor device circuit, the characteristics of which are accurate A semiconductor substrate (1) having a main surface, and above the main surface of the semiconductor substrate, a wiring conductor pattern (1 4) 'and an interlayer insulating film (15) formed to cover the wiring conductor pattern are formed, and the foregoing Above the interlayer insulating film, at the stage of this planarization seen above, a plurality of different conductor films (14, 14B) are included in the aforementioned wiring conductor case, forming a through-layer insulating film that reaches the aforementioned plurality of different ones Conductor film connection holes (15dl, 15d2). 2 2. A method for manufacturing a semiconductor integrated circuit device as claimed in item 21 of the patent scope, wherein the second conductor film is titanium nitride. 23. A method for manufacturing a semiconductor integrated circuit device, characterized by having a semiconductor substrate (1) with a main surface prepared by the Ministry of Economic Affairs, Central Bureau of Standards, Labor and Consumer Cooperatives (please read the notes on the back before filling in (This page) A pair of complex MI SFETs (6, 7, 9) having a pair of semiconductor regions formed on the main surface of each of the aforementioned semiconductor substrates, formed on the main surface of the aforementioned semiconductor substrates, and through the insulating film, on the aforementioned MISFETs Above a predetermined number of MI SFETs, an information storage capacitor (11) is formed. Each capacitor is connected to the first semiconductor range in the semiconductor range of one of the aforementioned MISFETs to form a memory cell, and a 1 interlayer insulating film (12), and formed through the first interlayer insulating film, reached the predetermined number of the paper size of the above-mentioned Chinese National Standard (CNS) Α4 specifications (210X297 mm) -5-322595 Shao C8 D8 々. One of the patent application ranges MISFETs, the first connection hole (12a) of the second semiconductor range in the semiconductor range, and the first connection hole of each of these, to The connection conductor (1 3) is filled, and the connection conductor is in contact with Zen of the second semiconductor range in the semiconductor range of one of the aforementioned predetermined number of M I SF ET s, and on the aforementioned first interlayer insulating film, A first conductor film (14b) of a high-melting-point metal in contact with the connecting conductor, and a second conductor film (14c) having a low reflectance via the first conductor film are formed on the first On the conductor film, the first and second conductor films are etched to form a first wiring conductor pattern, and on the resulting substrate, a second interlayer insulating film (15) is formed, and the second interlayer insulating film is planarized On the top, at this stage of the flattening seen above, a plurality of different conductor films (14, 14B) are included in the first wiring conductor pattern to form an interlayer insulating film penetrating the second The aforementioned connection holes (15dl, 15d2) of multiple conductor films are printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ---------- not installed ------ ordered (please read the notes on the back first Please fill in this page for details.) The second wiring conductor pattern (16) electrically connected to the first wiring conductor pattern is formed on the above flat second interlayer insulating film. 24. The method for manufacturing a semiconductor integrated circuit device according to item 23 of the patent application, wherein the second conductor film is titanium nitride. 25. A semiconductor integrated circuit device, which is characterized by having a semiconductor substrate (1) with a main surface prepared, and this paper uses the Chinese National Standard (CNS) A4 specification (210X297 mm) 8 88 8 ABCD 々, apply The patent scope and the wiring conductor pattern (14) containing the first conductor film (14b) and the second conductor film (14c) formed on the first conductor film above the main surface of the aforementioned semiconductor substrate, and The first conductor film is made of a high-melting-point metal, and the second conductor film has a reflectivity lower than that of the first conductor film and a lower etching rate than the first conductor film. 26. The semiconductor integrated circuit device as claimed in item 25 of the patent scope, wherein the second conductor film is titanium nitride. 27. The semiconductor integrated circuit device of claim 25, wherein the first conductor film is tungsten, titanium or molybdenum. (Please read the precautions on the back before filling in this page) Printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. This paper scale is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210X297 mm) -7-