S2895S 0698TWF.CTC r〇C/Jonathan/002 Β7 五、發明説明（I ) 本發明是有關於靜態隨機存取記憶體（St a t i c Random Access Memory ; SRAM)的位元線上拉電路（Bit Line Pull Up Circuit)，且特別是有關於一種利用改良的擴散區結 構（Diffusion Structure)，以增加抗靜電放電 (Electro-StaticDamage ; ESD)能力的位元線上拉電路。 在積體電路的製造過程中，靜電放電事件常是導致積 體電路損壞的主因之一。在很多情況下，當靜電放電應力 加諸在某一輸出入（I/O)接腳時，由於靜電放電保護電路 中的上拉（Pull Up)或下拉（Pull Down)二極體之故，靜電 放電能量會流到電壓源匯流排（Power Bus)。因此，在發 生靜電放電事件期間，許多內在寄生元件（Internal Parasitic Devices)可能被開啓（Turn On)，而取代指定 的靜電放電保護電路。這些就是內部電路（Internal Circuit)的弱點（Weak Spots)所在，而這些弱點大抵上和 下列的因素有關： (1) 連接到VDD匯流排的n+擴散區（在電壓源匯流排間 形成一 n_+/p井型二極體）； 一 (2) 連接到Vss匯流排的p+擴散區（在電壓源匯流排間 形成一 p+/n井型二極體）； (3) —連接到VDD匯流排的n+擴散區，其與某一連接到 、55匯流排的n+擴散區鄰接（在電壓源匯流排間形成一寄生 的NPN型雙極性電晶體）；或 〇> (4) 一連接到▽⑽匯流排的p+擴散區，其與某一連接到 Vss匯流排的P+擴散區鄰接（在電壓源匯流排間形成一寄生 3 (請先閱讀背面之注意事項再填寫本頁) 、τ 經濟部中央標準局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） OC/ionathan/002 A7 B7 五、發明説明（之） 的PNP型雙極性電晶體）。 在靜電放電事件發生期間，當電壓源匯流排間的電壓 相對於Vss接地電壓被提昇時，內部電路就會被觸發。由於 內部電路多半依循最小設計準則（Minimum Design RuleS) 設計，且未適當地設計（例如接觸窗到擴散區的邊緣以及 接觸窗到閘極邊緣均需要較大的空間）以抵抗巨大的靜電 放電暫態電流（Transient Current)，因此，極容易受到 靜電放電的損害。 請參照第1圖，圖1是習知一種靜態隨機存取記憶體 * 之位元線上拉電路的佈局上視示意圖。對靜態隨機存取記 憶體而言，位元線上拉電路通常是用來將所有的位元線設 定到一共有的正電壓，以使感測放大器（Sense Amplifier) 能對感測的位元線快速響應。圖1中，位元線BL11〜BL14 被4個N型金氧半場效電晶體所控制，該些N型金氧半場 效電晶體具有一共通控制閘電位（Common Control Gate Potential)，也就是說控制閘電位VG1等於控制閘電位 VG2。左右相鄰的N型金氧半場效電晶體是共用一汲極擴 散區，而相鄰接的N型金氧半電晶體的汲極擴散區則是分 離的，例如n+擴散區15a與15b分別只被左右兩N型金氧 半電晶體共用。具有一共通控制閘電位的N型金氧半電晶 體被應用在位元線上拉電路中時，汲極擴散區須藕接到VDD 匯流排，例如n+擴散區15a與15b分別透過金屬接觸窗 η 16a、17a和16b、17b耦接到VDD匯流排，與4個Ν型金 氧半場效電晶體相結合，形成複數個n+/P井型二極體（未 4 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項存填寫本頁) "S2895S 0698TWF.CTC r〇C / Jonathan / 002 Β7 V. Description of the invention (I) The present invention relates to a bit line pull-up circuit of static random access memory (St atic Random Access Memory; SRAM) Circuit), and in particular, it relates to a bit line pull circuit that uses an improved diffusion structure (Diffusion Structure) to increase the anti-static discharge (Electro-StaticDamage; ESD) capability. In the manufacturing process of integrated circuits, electrostatic discharge events are often one of the main causes of damage to integrated circuits. In many cases, when ESD stress is applied to an input / output (I / O) pin, due to the pull-up (Pull Up) or pull-down (Pull Down) diode in the ESD protection circuit, Electrostatic discharge energy will flow to the voltage source bus (Power Bus). Therefore, during an ESD event, many internal parasitic devices (Turn On) may be turned on instead of the specified ESD protection circuit. These are the weaknesses of the internal circuit (Weak Spots), and these weaknesses are probably related to the following factors: (1) n + diffusion area connected to the VDD bus (form an n_ + between the voltage source bus) / p well-type diode); one (2) connected to the p + diffusion region of the Vss bus (forming a p + / n well-type diode between the voltage source buses); (3) — connected to the VDD bus N + diffusion region of the adjacent to a n + diffusion region connected to the 55 busbar (a parasitic NPN bipolar transistor is formed between the voltage source busbars); or 〇 > (4) a connection to ▽ ⑽The p + diffusion area of the bus bar is adjacent to a P + diffusion area connected to the Vss bus bar (a parasitic 3 is formed between the voltage source bus bars (please read the precautions on the back and fill in this page) The standard of the paper printed by the Central Standard Bureau for consumer cooperation is the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) OC / ionathan / 002 A7 B7 V. Description of the invention (PNP type bipolar transistor). During an ESD event, when the voltage between the voltage source busbars is raised relative to the Vss ground voltage, the internal circuit will be triggered. Because the internal circuits are mostly designed in accordance with the Minimum Design Rule (Minimum Design RuleS), and not properly designed (such as the contact window to the edge of the diffusion area and the contact window to the edge of the gate require a large space) to resist the huge static discharge Transient Current, therefore, it is extremely susceptible to damage by electrostatic discharge. Please refer to FIG. 1. FIG. 1 is a schematic top view of a layout of a bit line pull circuit of a conventional static random access memory *. For static random access memory, the bit line pull-up circuit is usually used to set all bit lines to a common positive voltage, so that the sense amplifier (Sense Amplifier) can sense the bit line Quick response. In FIG. 1, the bit lines BL11 to BL14 are controlled by four N-type metal oxide half-field effect transistors. The N-type metal oxide half-field effect transistors have a common control gate potential (Common Control Gate Potential), that is to say The control gate potential VG1 is equal to the control gate potential VG2. The left and right adjacent N-type metal oxide semi-field effect transistors share a drain diffusion region, while the adjacent N-type metal oxide semi-transistor transistors have separate drain diffusion regions, such as n + diffusion regions 15a and 15b, respectively Only shared by the left and right N-type metal oxide semi-transistors. When an N-type metal oxide semi-transistor with a common control gate potential is used in the bit line pull circuit, the drain diffusion region must be coupled to the VDD bus, for example, the n + diffusion regions 15a and 15b respectively pass through the metal contact window η 16a, 17a and 16b, 17b are coupled to the VDD bus, combined with four N-type metal oxide semi-field effect transistors to form a plurality of n + / P well-type diodes (CNS) A4 specification (210X297mm) (Please read the notes on the back to fill in this page) "
、tT 經濟部中央標準局員工消費合作社印製 經濟部中央標準局貝工消費合作杜印製 318958 0698TWF； DOC/Jonathan/002 ^7 B7 <.«««- ___i_______ 五、發明説明（,） 顯示）。在靜電放電事件中，如果n+/P井型二極體的崩潰 (Break Down)是由Vdd匯流排與Vss匯流排之間的暫態高電 壓所引起，那麼流經n+/P井型二極體的靜電放電電流將升 高環繞n+擴散區15a、15b邊緣之二極體接面區域的溫 度。當金屬接觸窗16a、17a; 16b、17b與n+擴散區15a、 15b邊緣的距離很小時，在金屬接觸窗16a、17a; 16b、 17b中的金屬就很容易到達融點溫度（Melting Tempe r a t u r e)，例如在擴散區間之錦-砂的最低融化溫度 約是550 t，以致產生產生鋁尖峰（Spiking)和接觸窗漏電 (Contact Leakage)現象。是故，金屬接觸窗16a ' 17a;16b、17b—般均須與n+擴散區15a、f5b的邊緣保持 一段距離，因此也就限制了汲極端之金屬接觸窗的數目。 換句話說，以此種設計，於靜電放電事件期間，流經汲極 端之金屬接觸窗的電流就容易使電路受損。 有鑑於此，本發明的主要目的就是在提供一種改良的 擴散區結構，用以形成靜態隨機存取記憶體的位元線上拉 _電路，以增加抗靜電放電的能力。_ 根據本發明之一較佳實施例，提出一種金氧半場效電 晶體之位元線上拉電路，藕接至靜態隨機存取記憶體中之 一電壓源匯流排，以增加抗靜電放電的能力；該位元線上 拉電路包括：複數個接觸窗；複數個位元線；一汲極擴散 區’透過該些接觸窗藕接至該電壓源匯流排；複數個源極 擴散區，藕接至對應的位元線；以及一閘極，以該汲極擴 散區爲中心，呈左右對稱之配置，且藕接至該閘極電壓源。 (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 0698TWF.DOC/ J〇nathan/002 A7 B7 五、發明説明（十） (請先閱讀背面之注意事項再填寫本頁) 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖是一種習知靜態隨機存取記憶體之位元線上拉 電路的佈局結構上視示意圖； 第2圖是本發明之一較佳實施例的佈局上視示意圖； 以及 第3圖是本發明之另一較佳霣施例的佈局上視示意 圖。 實施例 --1 經濟部中央標準局員工消費合作社印製 請參照第2圖，其繪示本發明之一較佳實施例，一種 靜態隨機存取記憶體的位元線上拉電路的佈局上視示意 圖。控制位元線上拉電路的N型金氧半電晶體有複數個， 對於每一個N型金氧半電晶體來說，其均具有一閘極、一 連接到VDD的n+擴散區與另一連接到一位元線的n+擴散 區。在圖2申，n+擴散區20係一區塊，含蓋4個4型金氧 半電晶體，以共同Vdd匯流排連接的n+擴散區20爲中心， 呈對稱性安置，佈局呈現左右對稱，其中汲極端的n+擴散 區20透過金屬接觸窗2.0 a、20b連接到Vdd匯流排*由追 些N型金氧半電晶體共享。該些N型金氧半電晶體的位元 線連接n+擴散區推進到薄氧化角（ThinOxideCorner )， 且每一擴散彎曲角度近似90度彎角。而源極端的n+擴散區 則分別透過金屬接觸窗連接到不同的位元線，例如n+擴散 6 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） 侧―，麵 r U,,丨丨一3!§958 0 6 9 8TWF .DOC/Jonathan/002 A7 B7 五、發明説明（5 ) 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 區20分別透過金屬接觸窗21a、21b連接到位元線BL21， 透過金屬接觸窗22a、22b連接到位元線BL22，透過金屬 接觸窗23a、23b連接到位元線BL23，透過金屬接觸窗 24a、24b連接到位元線BL24。圖2中，n+擴散區26係另 一區塊，其佈局設計與n+擴散區20相似，亦含蓋4個N型 金氧半電晶體（未全畫出），位元線BL271與BL272相當 於位元線BL21與BL22;同樣地，n+擴散區28係另一區塊， 其佈局設計與n+擴散區20相似，亦含蓋4個N型金氧半電 晶體（未全畫出），位元線BL293 - BL294相當於位元線 BL23與BL24。圖2中複晶閘極（Poly Gate ) 25不是一 直線，而是有一些近似90度彎角的轉折（turns )，爲了隔 離位元線連接n+擴散區到VDD連接n+擴散區，使佈局區域最 佳化，閘極爲多節彎摺的形狀。複晶閘極的轉折角（如圖 中箭頭C處）理想上應該爲圓形（未畫出），以避免電場 群擠效應（Electric Field Crowding Effect)的發生，並 增進靜電放電免疫力（ESD Immunity)，亦可爲一圓弧狀， 或是多邊形狀。在圖2中_，源極擴散區中之接觸窗被該轉 折角與該源極擴散區的外周圍邊緣所包圍，而且，源極擴 散區被轉折角之複晶閘極局限在主動區域的角落上。複晶 閘極折疊到兩個場氧化邊緣大約互相垂直，Vdd連接Π +擴 散區被場氧化分開；複晶線經過場氧化以連接該位元線上 拉電路的N型金氧半電晶體複數個複晶閘極，且複晶閘極, TT Ministry of Economic Affairs Central Standards Bureau employee consumer cooperatives printed by the Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperation Du Printing 318958 0698TWF; DOC / Jonathan / 002 ^ 7 B7 <. «« «-___I_______ V. Description of invention (,) display). In the electrostatic discharge event, if the breakdown of the n + / P well diode is caused by the transient high voltage between the Vdd bus and the Vss bus, then the n + / P well diode The body's electrostatic discharge current will raise the temperature of the diode junction area surrounding the edges of the n + diffusion regions 15a, 15b. When the distance between the metal contact windows 16a, 17a; 16b, 17b and the edge of the n + diffusion regions 15a, 15b is very small, the metal in the metal contact windows 16a, 17a; 16b, 17b can easily reach the melting point temperature (Melting Tempe rature) For example, the minimum melting temperature of Jin-Sand in the diffusion zone is about 550 t, so that aluminum spikes and contact leakage occur. Therefore, the metal contact windows 16a '17a; 16b, 17b generally have to maintain a distance from the edges of the n + diffusion regions 15a, f5b, thus limiting the number of metal contact windows on the drain side. In other words, with this design, during the electrostatic discharge event, the current flowing through the metal contact window of the drain terminal can easily damage the circuit. In view of this, the main purpose of the present invention is to provide an improved diffusion region structure for forming a bit line pull circuit of a static random access memory to increase the anti-static discharge capability. _ According to a preferred embodiment of the present invention, a bit-line pull-up circuit of a metal-oxide half field effect transistor is proposed, which is coupled to a voltage source bus in a static random access memory to increase the anti-static discharge capability The bit-line pull-up circuit includes: a plurality of contact windows; a plurality of bit lines; a drain diffusion area 'connected to the voltage source bus bar through the contact windows; a plurality of source diffusion areas, coupled to The corresponding bit line; and a gate electrode, with the drain diffusion area as the center, in a bilaterally symmetrical configuration, and coupled to the gate voltage source. (Please read the precautions on the back before filling in this page) The size of the revised paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) 0698TWF.DOC / J〇nathan / 002 A7 B7 V. Description of the invention (ten) ( Please read the precautions on the back before filling in this page) In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is described below in detail in conjunction with the attached drawings. The description is as follows: A brief description of the drawings: FIG. 1 is a schematic top view of a layout structure of a bit line pull circuit of a conventional static random access memory; FIG. 2 is a layout of a preferred embodiment of the present invention Schematic view; and FIG. 3 is a schematic top view of another preferred embodiment of the present invention. Embodiment--1 Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economics, please refer to FIG. 2, which illustrates a preferred embodiment of the present invention, a layout of a static random access memory bit line pull circuit schematic diagram. There are a plurality of N-type metal oxide semi-transistors controlling the pull-up circuit on the bit line. For each N-type metal oxide semi-transistor, it has a gate, an n + diffusion region connected to VDD and another connection To the n + diffusion area of the bit line. In Fig. 2, the n + diffusion region 20 is a block, which contains four 4 type metal oxide semi-transistors, and is arranged symmetrically with the n + diffusion region 20 connected by a common Vdd bus as the layout is symmetrical. The n + diffusion region 20 of the drain terminal is connected to the Vdd bus through the metal contact windows 2.0a and 20b * and is shared by the N-type metal oxide semi-transistors. The bit lines of the N-type metal oxide semi-transistors are connected to the n + diffusion region to advance to a thin oxide angle (ThinOxide Corner), and each diffusion bending angle is approximately 90 degrees. The n + diffusion area at the source terminal is connected to different bit lines through metal contact windows, for example, n + diffusion 6 This paper scale is applicable to the Chinese national standard (CNS > A4 specification (210X297 mm) side ―, surface r U, , 丨 丨 一 3! §958 0 6 9 8TWF .DOC / Jonathan / 002 A7 B7 V. Description of the invention (5) Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) The area 20 is connected to the bit line BL21 through the metal contact windows 21a, 21b, connected to the bit line BL22 through the metal contact windows 22a, 22b, connected to the bit line BL23 through the metal contact windows 23a, 23b, and connected through the metal contact windows 24a, 24b To bit line BL24. In Fig. 2, n + diffusion region 26 is another block, and its layout design is similar to n + diffusion region 20, and it also covers 4 N-type metal oxide semi-transistors (not fully drawn), bit Lines BL271 and BL272 are equivalent to bit lines BL21 and BL22; similarly, n + diffusion region 28 is another block, and its layout design is similar to n + diffusion region 20, and also includes four N-type metal oxide semi-transistors (not Full drawing), bit lines BL293-BL294 are equivalent to bit lines BL23 and BL24 The poly gate 25 in Figure 2 is not a straight line, but has some turns of approximately 90 degrees. In order to isolate the bit line from the n + diffusion area to the VDD connection n + diffusion area, the layout area Optimized, the gate electrode has a multi-section bending shape. The turning angle of the polycrystalline gate electrode (as shown by arrow C in the figure) should ideally be round (not shown) to avoid electric field crowding effect (Electric Field Crowding Effect), and enhance the ESD Immunity (ESD Immunity), can also be a circular arc, or polygonal shape. In Figure 2_, the contact window in the source diffusion area is affected by the turning angle and the source The outer peripheral edge of the polar diffusion region is surrounded by, and the source diffusion region is limited to the corner of the active area by the compound gate of the corner. The compound gate is folded until the two field oxide edges are approximately perpendicular to each other, Vdd connects + The diffusion area is separated by field oxidation; the complex crystal line undergoes field oxidation to connect to the N-type metal oxide semi-transistor of the pull-up circuit on the bit line.
•"S 25連接到複晶閘極電壓VG，平常複晶閘極電壓VG均是設 定在低態（Low)，但在位元線上拉電路工作期間，則均被 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） :.DOC/Jonathan/〇〇2 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（/7 ) 切換至高態（High丨。 根據上述的佈局安排，本發明具有以共同匯流排 連接的n+擴散區20爲對稱中心，呈對稱性安置，佈局呈對 稱性安置的閘極與凹陷的擴散區邊緣290，如此，當靜電 放電事件發生時，就能使由汲極流入的靜電放電電流均勻 的流往源極’而提高位元線上拉電路的靜電放電免疫力。 當然’這些金屬接觸窗與共同VDD連接的n+擴散區邊緣間， 仍舊維持有一很好的距離。 接著請參照第3圖，其繪示卒發明之第二較佳實施 例’一種靜態隨機存取記憶體的位元線上拉電路的佈局上 視示意圖。第3圖中之構件與圖2中相同的部份係以相同 的編號標示之，本較佳實施例中僅就差異部份做說明。其 中汲極端的n+擴散區30透過金屬接觸窗30a、30b連接到 Vdd匯流排；複晶閘極31形成一多節彎摺的形狀，並藕接 到閘極電壓源VG1，複晶閘極32藕接到閘極電壓源VG2， VG1等於VG2，常態下係設定在低態，但在位元線上拉電 路工作期間，則均被切換至高態。圖3中，對於位元線上 拉電路而言’ VDD連接n+擴散區30全部合倂在一塊，此n + 擴散區30係一完整區塊，以增加Vdd連接n+擴散區至基底 二極體（Substrate Diode )的面積；如此一來，可以降 低N型金氧半電晶體的汲極電阻，促進位元線上拉電路的 操作’同時亦改善靜電放電免疫力。 * 根據上述本發明之較佳實施例的佈局安排，^發明在 沒有增加佈局面積而卻能使佈局區域最佳化，該位元線上 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -派·• " S 25 is connected to the polycrystalline gate voltage VG. Normally the polycrystalline gate voltage VG is set to Low (Low), but during the operation of the bit line pull circuit, it is all 7 paper standards for China National Standard (CNS) A4 specification (210X297mm): .DOC / Jonathan / 〇〇2 A7 B7 Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (/ 7) Switch to high state (High 丨. According to the above The layout arrangement of the present invention has the n + diffusion region 20 connected by the common bus bar as the center of symmetry, and is arranged symmetrically. The layout of the gate is arranged symmetrically and the edge of the recessed diffusion region 290. , It can make the electrostatic discharge current flowing from the drain to the source evenly, and improve the electrostatic discharge immunity of the pull-up circuit on the bit line. Of course, between these metal contact windows and the edge of the n + diffusion area connected by the common VDD, it is still Maintain a good distance. Next, please refer to FIG. 3, which shows a schematic top view of the layout of a bit line pull circuit of a static random access memory according to the second preferred embodiment of the invention. The components in FIG. 3 that are the same as those in FIG. 2 are marked with the same numbers, and only the differences are described in this preferred embodiment. The n + diffusion region 30 of the drain terminal passes through the metal contact window 30a, 30b is connected to the Vdd bus; the polycrystalline gate 31 forms a multi-node bending shape, and is coupled to the gate voltage source VG1, and the polycrystalline gate 32 is coupled to the gate voltage source VG2, VG1 is equal to VG2, the normal state The lower system is set to the low state, but during the operation of the bit line pull circuit, they are all switched to the high state. In FIG. 3, for the bit line pull circuit, the VDD connection n + diffusion region 30 are all integrated together, this The n + diffusion region 30 is a complete block to increase the area of Vdd connecting the n + diffusion region to the substrate diode (Substrate Diode); in this way, the drain resistance of the N-type metal oxide semi-transistor can be reduced to promote the bit The operation of the pull-up circuit on the element line also improves the electrostatic discharge immunity. * According to the layout arrangement of the preferred embodiment of the present invention described above, the invention can optimize the layout area without increasing the layout area. The bit line 8 This paper standard is suitable for Chinese countries Associate (CNS) A4 size (210X297 mm) (Please read the back of the precautions to fill out this page) - faction ·
*1T* 1T
J .:七:麵賴广- 0698TWF.DOC/Jonathan/002 A7 B7 五、發明説明（Q ) 拉電路的佈局結構，能強化電路的弱點；換句話說，本發 明在沒有增加佈局面積情況之下，卻能增加接觸窗至擴散 邊緣（contact-to-diffusion-edge )與接觸窗至閘極邊 緣（contact-to-gate-edge )的距離。 雖然本發明已以一些較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 • utt —^n· · 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐）J .: Seven: Face Lai Guang-0698TWF.DOC / Jonathan / 002 A7 B7 V. Description of invention (Q) The layout structure of the pull circuit can strengthen the weakness of the circuit; in other words, the invention does not increase the layout area However, the distance from the contact window to the diffusion edge (contact-to-diffusion-edge) and the contact window to the gate edge (contact-to-gate-edge) can be increased. Although the present invention has been disclosed as the above with some preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill can make various modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of an invention shall be deemed as defined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) Printed by the Employees Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs • utt — ^ n · · 9 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm )