318278 A7 ______B7___ 五、發明説明（） 發明領述： 本發明與一種DRAM之製程有關，特别是一種自行對 準形成位元線及非破壤性形成摻雜區之製程。 發明背景： 積體電路之流程非常複雜，基本上大致可分爲晶片之 製造、積髏電路之製作與積體重路之構裝（package)將各 種耄子元件及線路縮小並製作在大小僅及2平方公分或 更小之面積上，半導體工業因爲技術的提昇而朝向將元件 之尺寸缩小邁進，兩或4層内連線之技術正普遍地應甩於 雹路之設計，目前工業界致力於發展高積集度之動懇随機 存取記懷想（dynamic random access memory ; DRAM)，從16K位元、64位元、1 M位元至16M.位元發 展’因此便宜且容量大乏DRAM便随著製程技術之改善而 向64M位元、256ΛΛ位元發展》 經濟部中央橾隼局貝工消费合作社印裂 -^n- ·1·^1 m n (请先閲讀背面之注意事項存填寫本頁) 動態随機存取記憶體（dynamic random access memory ; DRAM)是一種主要之揮發性（V0|a川之記億 體。在元件不斷缩小下，電容之表面積輿儲存之電荷數亦 不斷減小，在此情形下因α粒子造成之軟記錯及在半導體 中之穩定性變成重要之問題。在元件縮小下以提高積集度 而使電容之表面積減少，爲使電容性能不會降低之電容製 程方法舆結構是電容製程努力之方向。當動態隨機存取記 本紙浪尺度適用中困國家標準（CNS ) A4規格（210X297公釐） 經濟部中央搞準局貝工消费合作社印裝 3l8278 A7 _ B7 五、發明説明（） 憶體（dram)之缩小化時，其所能儲存資料之容量卻不能 随-之減少，因此將增進對於動態随機存取記憶體對於介電 材料之發展以及記憶胞結構之設計上之一種驅動力，此方 面主要是減少介電層之厚度、高介雹之材料及增進表面積 之電容結構。 . 而一般所謂的單一 t晶體DRAM胞（single transister DRAM cell)事實上是由一個電晶體與電容器 (capacitor)所構成的，萆容器是DRAM胞藉以儲存訊號之 心臟部份，若電容器所儲存之電荷越多，讀出放夫器在讀 取資料時受干擾之影響如α粒子所產生之軟記錯（soft errors)將大大降低t更可減低«再補充”之頻率。一般增加 t容器儲梦電荷能力方法有（1)增加介電質之介電常數， 使電容器單位面積之儲存電荷數增加；（2)減少介霆層之 厚度；（3)増加電容器之面積，使整個儲存於電容器内之 電荷數增加。 一般典型之動態随機存取記憶髖是於半導髖之基板 上製造金氧半場效t晶體（MOSFET)舆電容器i利用接觸 窗來連接電容器之電荷储存電極（storage node)舆金氧 半場效電晶雅之源極作電性之接觸。藉由電容器與源極區 之電性接觸，數位資訊儲存在電容器並藉金氧半場效電晶 體、位元線（bit line)、字語線（word line)陣列來取得電容 器之數位資料。一般之電容器可分爲堆疊式電容器 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁)318278 A7 ______B7___ V. Description of the invention () Summary of the invention: The present invention is related to a process of DRAM, especially a process of self-aligning the formation of bit lines and the formation of doped regions without soil breaking. Background of the Invention: The process of integrated circuits is very complicated, and can be roughly divided into the manufacture of chips, the manufacture of integrated circuits and the packaging of integrated circuits. The various components and circuits are reduced and manufactured in a size only In the area of 2 square centimeters or less, the semiconductor industry is moving towards reducing the size of the device due to the improvement of technology. The technology of interconnecting two or four layers is generally should be thrown into the design of the hail road. At present, the industry is committed to Development of dynamic random access memory (DRAM) with a high degree of integration, from 16K bits, 64 bits, 1 M bits to 16 M bits With the improvement of process technology, it will develop to 64M bits and 256ΛΛ bits. "The Ministry of Economic Affairs, Central Falcon Bureau Beigong Consumer Cooperative Printed-^ n- · 1 · ^ 1 mn (please read the notes on the back and fill in (This page) Dynamic random access memory (DRAM) is a main type of volatile (V0 | a Chuanzhijiyi body. Under the continuous shrinking of the device, the surface area of the capacitor and the number of stored charges are also constant Decrease in In this case, the soft memory errors caused by alpha particles and the stability in semiconductors become important issues. Under the reduction of components, the surface area of the capacitor is reduced to increase the degree of accumulation, and the capacitor manufacturing method is to prevent the performance of the capacitor from decreasing. The public structure is the direction of the capacitor manufacturing process. When the dynamic random access notebook paper wave scale is applicable to the national standard (CNS) A4 specification (210X297 mm), the Central Bureau of Economic Affairs of the Ministry of Economic Affairs, Beige Consumer Cooperative Printed 3l8278 A7 _ B7 Five 2. Description of the invention () When the memory (dram) is reduced, the capacity of the data it can store cannot be reduced with it, so it will improve the development of dielectric materials and memory cell structure for dynamic random access memory A driving force in the design, this aspect is mainly to reduce the thickness of the dielectric layer, high dielectric material and to increase the surface area of the capacitor structure. The so-called single t-crystal DRAM cell (single transister DRAM cell) is actually It is composed of a transistor and a capacitor. The container is the heart of the DRAM cell to store the signal. If the capacitor stores the charge The more, the reader will be affected by the interference when reading the data, such as the soft errors generated by the alpha particles (soft errors) will greatly reduce t and the frequency of "refill". Generally increase the t container storage dream The charge capacity methods are: (1) increase the dielectric constant of the dielectric substance to increase the number of stored charges per unit area of the capacitor; (2) reduce the thickness of the dielectric layer; (3) increase the area of the capacitor so that the entire storage in the capacitor The number of charges increases. The typical typical dynamic random access memory hip is to manufacture a metal oxide half field effect t-crystal (MOSFET) on the substrate of the semi-conducting hip and the capacitor i. The contact window is used to connect the charge storage electrode of the capacitor The source of the gold-oxygen half-field effect crystal is used for electrical contact. Through the electrical contact between the capacitor and the source region, the digital information is stored in the capacitor and the digital data of the capacitor is obtained by the metal oxide field effect transistor, bit line, and word line array. The general capacitors can be divided into stacked capacitors. The paper standard is applicable to China National Standard (CNS) Α4 specification (210X297mm) (please read the precautions on the back before filling this page)
V >π 318278 A7 B7 五、發明説明（） (stacked capacitor)及凹溝式電容器（trenched capacitor) »傳统之堆疊式慮容器增加重容之方法是增加 電容器下層電極板之厚度以增加電容器之表面積，然而增 加雹容器之下層電極板之厚度卻產生陡峭之地形地勢，導 致微影、蝕刻與薄膜沈積之不易。凹溝式電容器則以增加 半導髖基板内之深度以增加表面積，以便降低記憶元件之 平面面積之同時亦應維持相同之電容値，由於此破壤了半 導髖基板之晶體結構，容易產生漏電流（丨eakage current} ° 傳统CMOS製程中之掺雜區域之形成方法爲利用離 子植入之方式穿越閘極氧化層於基板之中形成，而此步驟 通常會破壤矽之基板，另外，爲了降低電性接觸之電阻之 離子植入有時亦會偏離對準而無法達到預期之要求。 —--J------II-- (請先閲讀背面之注意事項再填寫本頁)V > π 318278 A7 B7 5. Description of the invention () (stacked capacitor) and trenched capacitor (trenched capacitor) »The traditional method of stacking the container to increase the weight is to increase the thickness of the lower electrode plate of the capacitor to increase the capacitor The surface area, however, increasing the thickness of the electrode plate below the hail container produces a steep terrain, which makes it difficult to achieve lithography, etching and film deposition. Recessed capacitors increase the depth of the semiconducting hip substrate to increase the surface area, so as to reduce the planar area of the memory device while maintaining the same capacitance value. Because this breaks the crystal structure of the semiconducting hip substrate, it is easy to produce Leakage current (丨 eakage current) ° The formation method of doped regions in the traditional CMOS process is to use ion implantation to form through the gate oxide layer in the substrate, and this step usually breaks the silicon substrate. In addition, In order to reduce the electrical contact resistance, the ion implantation sometimes deviates from alignment and fails to meet the expected requirements. —-- J ------ II-- (Please read the precautions on the back before filling this page )
，tT f 經濟部中央梂隼局男工消费合作社印製 本紙張尺度適用中國國家梯準（CNS ) A4规格（210X297公釐〉 經濟部中央樣準局®:工消費合作社印装 318278 A7 ________B7 五、發明説明（） 發明目的及概述： 本發明之主要目的在提供一種非破壤矽基板之掺雜 區形成方法。 毒 本發明之另一目的在提供一種自行對準形成位元線 之製程。 場氧化層形成在主動區之用園作爲隔離電性之用，接 著形成閘極氧化層、閘極與絶緣遮蓋層以形成閘極電極輿 字語線。接著，一未摻雜之複晶矽層形成於閘極結構、字 語線與基板之上’定義一捧雜區之光阻，一離子植入步樣 以上述之光阻做爲軍幕穿越該部份未被光阻覆蓋之未掺 雜之複晶矽層形成汲極輿源極，而上述未被光阻覆i之複 晶梦層亦形成捧雜之複晶梦*·此步裸之僳點爲藉由上述之 步骤完成之摻雜區離子植入不會破壤基板，也就是本發明 防止基板因傳统之離子植入而被破壤，另外位元線區域輿 内連線之區域亦被同步自行野準形成。一發化轉金屬層 18接著形成於複晶矽之表面以降低複晶矽之電阻値，接 著一蝕刻技術蝕刻上述之矽化鎢金屬層與複晶梦以形成 位元線與内連線’第一介電層形成於；上述之基板、閘極結. 構、位元線與内連線之上，然後一微影與蝕刻技術用以形 成接觸孔於第一介電層之中，最後形成一電容於該第一介 電層之中上。 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210X297公釐） ----------— (請先閱讀背面之注意Ϋ項再填寫本頁) 訂 1——. •H in 318278 A7 B7 __ " ___ ~ ' " __—— 五、發明説明（） —本發明另一實施例爲同步形成DRAM記憶胞輿外圍 電路區域（periphery region)於基板之上，記憶胞區域之 閘極結構、内連線舆外面雹路區域之閘極結構、内連線可 以利用上述實施之方法同步形成。然後第一介重層同步形 成於DRAM記憶胞與外圍電路區域上，接著一光阻定義於 外困電路區域之上以曝露記憶胞區，一微影輿蝕刻技術用 以形成接觸孔於記憶胞區域之第一介電層之中。形成一電 容於第一介電層之上，去除上述之光阻。另一光阻形成於 記憶胞之上以曝露外圍電路區域，接著第二介電層形成於 上述之第一介電層之上’接著以微影與蝕刻技術蝕刻該第 一介電層舆第二介電層形成無觸孔。一金屬鎢栓形成於上 述之接觸孔中做爲電性連接，然後《習知之技術形成金屬 連線於上述之金屬鎢栓之上，最後形成第三介電層於第二 介電層與金屬連線之上，去除光阻。 (請先閲读背面之注意事項再填寫本頁) 經濟部中央梂準局貝工消费合作社印装 第第第 之。之。之。 : 明圖明圈明圈 明 發面發面發面 説 本截本截本截 單 爲之爲之爲之 簡圈上圈線®上 式 一板二語三層 圈 第基第字第梦 於 線 語 字 及 以 體 晶 電 成 形 例 施 實 及 以 體 晶 於 矽 晶 複 成 形 例 施 實 晶 複 於 廣 屬 金 鎢 化 矽 成 形 例 施 實 6 本紙張尺度適用中國鼷家揉準（CNS ) A4規格（210X297公嫠） 318278 A7 ___ B7 五、發明説明（) 笫四圈爲本發明之第一實施例形成一接觸孔於一介電層 中之截面圈。 第五圈爲本發明之第一實施例形成電容之截面圈。 第六圈爲本發明之第二實施例形成電晶髖於基板上之截 1面圈。 第七瞋爲本發明之第二實施例形成複晶矽於電晶體之截 面圈。 第八®爲本發明之第二實施例形成矽化鎢金屬層於複晶 矽層上之截面圈。 第九圈爲本發明之第二實施例蝕刻矽化鎢金屬以及複晶 矽之截面®。 第十圈爲夺發明之第二實施例形成接觸孔之截面圈。 第十一圈爲本發明之第二實施例形成内連線之截面圈。 第十二Α圈、第十二Β圈爲本發明之第三實施例同時形成 電晶體、複晶矽層以及矽化鎢金屬層於記憶胞區與外園電 路區之截面圈。 第十三A圈、第十三B圈爲本發明之第三實施例形成接觸 孔於記憶胞區之截面圈》 第十四A圖、第十四B圖爲本發明之第三實施例形成電容 於記愫胞區上之截面圈。 經濟部中央梂準局貝工消费合作社印装 ---------rt- (請先Μ讀背面之注意Ϋ項再填寫本頁) Λ 第十五A圖、第十五B圈爲本發明之第三實施例蝕刻介電 層形成接觸孔於介電層中之截面圈。 第十六A圈、第十六B圈爲本發明之第三實施例形成内連 線於外周固電路區之截面圈。 本纸張尺Α逋用中國國家標準< CNS ) Α4規格（210X297公着} i、發明説明（） 發明詳細説明： A7 B7 本發明爲一種位於位元線上之電容製程（capacitor over bit line ; CQB)，本發明之特徵之一爲摻雜區之離 子植入爲藉由穿透一未摻雜之複晶矽形成而不會造成因 掺雜時使基板受到破壞，另外亦可以同步形成位元線（bit line)之自行對準，本發明可被利用做爲下列之製程 (1)C0B動態隨機存取記憶體（DRAM)之記憶胞（2)外固區 域（periphery ;爲各記憶胞之速線或電路）（3) C0日動態 隨機存取記憶體（DRAM)之記憶胞與外固區域之同步形成 製程。 --------裝— (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 如第一圖所示，在基板2中成絶緣區域4園繞元件 區，此絶緣區域4也就是場氡化層4形成於半導體基板上 用以定義主動區與絶緣區。較佳之基板2爲晶面是<100》 之P型單晶矽，此厚之場氧化層4形成在主動區之周圍作 爲隔離電性之用，此場氧化層4由沈猜於主動元件區域之 氧化矽（氧化墊）與氮化矽層爲軍慕然後以氧化所形成，較 佳之厚度爲4000至6000埃》再以習用之溼蝕刻去除氮 化矽位障與氧化墊後半導體電晶體元件形成於主動區 域’最常用於動態随機存取記憶體之元件爲MOSFET， 此元件首先以熱氧化於溫度850至1〇〇〇 在主動區域形 成薄的閘極氧化層6，較佳之厚度爲埃。 8 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 訂 Λ 318278, TT f The printed paper size of the Male Workers ’Consumer Cooperative of the Central Bureau of Economics and Trade of the Ministry of Economic Affairs is applicable to the Chinese National Standard (CNS) A4 (210X297mm). The Central Prototype Bureau of the Ministry of Economic Affairs®: 318278 A7 _________B7 Description of the invention () Purpose and summary of the invention: The main purpose of the present invention is to provide a method for forming a doped region of a non-breaking silicon substrate. Another object of the present invention is to provide a process for self-aligned formation of bit lines. The field oxide layer is formed in the active area for isolation purposes, and then a gate oxide layer, a gate electrode and an insulating cover layer are formed to form a gate electrode word line. Then, an undoped polycrystalline silicon The layer is formed on the gate structure, the word line and the substrate 'to define a photoresist for the impurity region. An ion implantation step uses the above photoresist as the military screen to pass through the part that is not covered by the photoresist The doped polycrystalline silicon layer forms the drain electrode and the source electrode, and the above-mentioned polycrystalline dream layer that is not covered by the photoresist also forms a complex polycrystalline dream. * This step is naked by the above steps. Ion implantation in the doped area will not break the soil The board, that is, the present invention prevents the substrate from being broken by traditional ion implantation, and the bit line area and the internal connection area are also simultaneously formed by the self-alignment. A hair transfer metal layer 18 is then formed on the polycrystal The surface of the silicon is to reduce the resistance value of the polycrystalline silicon, and then an etching technique is used to etch the above tungsten silicide metal layer and the polycrystalline dream to form bit lines and interconnects. The first dielectric layer is formed on the above substrate and gate Pole junction. Structure, bit line and interconnection, then a lithography and etching technique is used to form a contact hole in the first dielectric layer, and finally form a capacitor on the first dielectric layer . This paper scale is applicable to China National Standard (CNS) Α4 specification (210X297mm) -------------- (please read the note Ϋ on the back before filling in this page) Order 1——. • H in 318278 A7 B7 __ " ___ ~ '" __—— V. Description of the invention ()-Another embodiment of the present invention is to synchronously form a DRAM memory cell and a peripheral circuit region on the substrate, the memory cell Gate structure of area, gate structure of internal connection and outside hail road area The interconnects can be formed synchronously using the method described above. Then the first dielectric layer is formed synchronously on the DRAM memory cell and the peripheral circuit area, and then a photoresist is defined on the external trapped circuit area to expose the memory cell area, a lithography The etching technique is used to form a contact hole in the first dielectric layer of the memory cell area. A capacitor is formed on the first dielectric layer to remove the above photoresist. Another photoresist is formed on the memory cell to Expose the peripheral circuit area, and then the second dielectric layer is formed on the first dielectric layer. Then, the first dielectric layer and the second dielectric layer are etched by lithography and etching techniques to form contactless holes. A metal A tungsten plug is formed in the above contact hole as an electrical connection, and then a conventional technique is used to form a metal connection on the above metal tungsten plug, and finally a third dielectric layer is formed on the second dielectric layer and the metal connection Above, remove the photoresist. (Please read the precautions on the back first and then fill out this page) Printed by the Central Bureau of Economic Affairs of the Ministry of Economic Affairs, Beigong Consumer Cooperative, No. 1st. Of it. Of it. : Ming Tu Ming Circle Ming Circle Ming Fa Ming Fa Fa Fa Fa Fa Fa said that this cut-out cut this cut-out form for the sake of simple circle upper circle line ® on the type one board second language three layer circle first base first word first dream Line language characters and examples of body crystal electroforming and body crystals on silicon crystal complex forming examples Shi Jing crystals on a wide range of gold tungsten silicon forming examples 6 This paper size is suitable for China's Yanjia (CNS) A4 specifications (210X297 public daughter) 318278 A7 ___ B7 V. Description of the invention () The fourth circle is a cross-sectional circle in which a contact hole is formed in a dielectric layer in the first embodiment of the invention. The fifth circle is a cross-sectional circle forming a capacitor in the first embodiment of the present invention. The sixth circle is the second embodiment of the present invention to form a cross-section circle of the electric crystal hip on the substrate. The seventh rule is the second embodiment of the present invention to form a cross-section ring of polycrystalline silicon on a transistor. Eighth® is the second embodiment of the present invention to form a cross-sectional ring of a tungsten silicide metal layer on a polycrystalline silicon layer. The ninth circle is the cross-section of etching the tungsten silicide metal and polycrystalline silicon in the second embodiment of the present invention. The tenth ring is a cross-sectional ring forming a contact hole according to the second embodiment of the invention. The eleventh circle is a cross-section circle forming an inner line in the second embodiment of the present invention. The twelfth A circle and the twelfth B circle are the third embodiment of the present invention, in which the cross-section circles of the transistor, the polycrystalline silicon layer and the tungsten silicide metal layer are simultaneously formed in the memory cell area and the outer garden circuit area. The thirteenth circle A and the thirteenth circle B are the third embodiment of the present invention forming a cross-sectional circle of the contact hole in the memory cell area. The fourteenth FIGS. 14 and B are the third embodiment of the present invention. The cross-section circle of the capacitor is recorded on the cell area. Printed by Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs --------- rt- (please read the note Ϋ on the back first and then fill out this page) Λ Figure 15A, Figure 15B In the third embodiment of the present invention, the dielectric layer is etched to form a cross-sectional circle of the contact hole in the dielectric layer. The sixteenth circle A and the sixteenth circle B are the third embodiment of the present invention to form a cross-section circle with an inner connecting line in the outer peripheral circuit area. This paper ruler uses the Chinese National Standard < CNS) Α4 specification (210X297 published) i. Description of the invention () Detailed description of the invention: A7 B7 The present invention is a capacitor process (capacitor over bit line) located on the bit line; CQB), one of the features of the present invention is that the ion implantation of the doped region is formed by penetrating an undoped polycrystalline silicon without causing damage to the substrate due to doping, and also can form bits simultaneously The self-alignment of the bit line, the present invention can be used as the following process (1) C0B dynamic random access memory (DRAM) memory cell (2) external solid area (periphery; for each memory cell Speed line or circuit) (3) The memory cell of the C0 dynamic random access memory (DRAM) and the external solid area are synchronized to form a manufacturing process. -------- Install — (Please read the precautions on the back first (Fill in this page again) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. As shown in the first figure, an insulating area 4 is formed in the substrate 2 to surround the element area. This insulating area 4 is the field radonized layer 4 formed on the semiconductor substrate It is used to define the active area and the insulating area. The preferred substrate 2 The crystal plane is P-type single crystal silicon of <100 ". This thick field oxide layer 4 is formed around the active area for electrical isolation. This field oxide layer 4 is composed of silicon oxide in the active device area from Shen Kuai ( Oxide pad) and the silicon nitride layer are formed by oxidation, and the thickness is preferably 4000 to 6000 Angstroms. Then, the silicon nitride barrier and the oxide pad are removed by conventional wet etching. The semiconductor transistor is formed in the active area 'The most commonly used device for dynamic random access memory is a MOSFET. This device first thermally oxidizes at a temperature of 850 to 1000 to form a thin gate oxide layer 6 in the active area, preferably with a thickness of Angstrom. The paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X297mm) Order 318318
、發明説明（ ---------Λ袈— (請先閲讀背面之注意事項再填寫本頁y 已捧雜之複晶矽層8以化學氣相沈積法沈積於基板 2、場氧化4、及閘極氧化層6之上，該複晶矽層8爲閘 極’上述之複晶矽層8之厚度爲1500至2000埃之間， 如第1闽所不絶緣層12形成於複晶矽層8之上，绝 緣層10是由具反反射性質之氛化珍形成較佳。接著以微 影與钱刻技術定義閘極氧化層6、閘極8與絶緣遮蓋層1〇 «形成閉極電極與導電結構12。導電結構12形成於場氧 化區上作爲字語線12形成於基板表面做爲在DRAM或其 他元件之電晶體一部份。絶緣側壁間隙14形成於閘極電 極之侧壁’此绝緣侧壁間隙14是以LPCVD沈積氧化矽且 以非等向性仕刻形成。 經濟部中央標準局員工消費合作社印製 接著’如第二圖所示，一未掺雜之複晶矽層16形成 於閘極結構、字語線12與基板2之上，該未掺雜之複晶 矽層16之較佳厚度爲1〇〇〇至2000埃，定義一掺雜區之 光阻，一離子植入步驟以上述之光阻做爲革幕穿越該部份 未被光阻覆蓋1之未捧雜之複晶夕層8形成没極與源極，而 上述未被光阻覆蓋之複晶矽層8亦形成摻雜之複晶發。上 迷離子摻雜之劑量爲4E15 atoms/cm2，離子植入之能量 爲40 KeV。此步骤之優點爲藉由上述之步樣完成之捧雜 區離子植入不會破壤基板，也就是本發明防止基板因傳統 之離子植入而被破壤，另外位元線區域與内連線之區域亦 被同步自行對準形成。 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） 經濟部中央榇準局負工消費合作社印製 1 A7 ________B7五、發明説明（） 參閲第三圈，一厚度1000埃之矽化鴿金屬層18接著 形成於複晶發1 6之表面以降低複晶矽之電阻値，請 四圈，一光阻20定義於矽化鎢金屬層18之上，接著―仕 刻技術独刻上述之發化為金屬層18與複晶發16以形成 位元線22輿内連線24，然後去除光阻20，該蝕刻之仕 刻劑爲HBr。第一介電層26形成於上迷之基板2、閘極 結構、位元線22輿内連線24之上，以較佳實施例而言第 一介t層26以硼磷矽玻璃形成，厚度爲4000埃。然後一 微影與蝕刻技術用以形成接觸孔28於第一介電層26之 中。 參閲第五圈，一第一導電層30形成於上述之接觸孔 (contact hole)28之中以及形成於第一介電層26之上然 後以微影與蝕刻技術用以蝕刻該第一導電層3 0做爲電容 之底部電極，該第一導電層30爲掺雜複晶矽（doped polysilicon)或是已掺雜複晶矽（in-situ doped polysilicon)形成，然後一介電質32覆蓋於該第一導電層 30之上，一般該介電質32爲氮化物/氧化物/氮化物 (0/N/0)、氮化物/氧化物（N/0)或Ta2〇5，最後第二導電 層34形成於介電質32做爲做爲電容之頂部電極完成動 態隨機存取記憶體（DRAM)之記憶胞製程。電容之底部電 極藉由接觸孔28與内連線24接觸。 (請先閲讀背面之注意事項再填寫本頁) 袈· 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公嫠） 318278 ' A7 ___________B7 五、發明説明（） 本發明之第二實施例爲利用本方法用以形成DRAM 間或其他1雹路之外圍重路區域（periphery region)，該方 法如下所述： 如第六圖所示，在基板42晶面是<100〉之P型單晶發 形成作爲隔離電性之場氧化層44 ，較佳之厚复爲4〇〇0 至6 000埃。再以熱氧化法於溫度850至1000 t；在主動區 域形成薄的閘極氧化層46，較佳之厚度爲100埃。然後 以化學氣相沈積法沈積厚度爲1 500至2000埃之間已捧 雜之複晶矽層48於基板42、場氧化44、及閘極氧化層 46之上’絶緣層50形成於複晶矽層48之上，絶緣層5〇 是由具反反射性質之氮化矽形成較佳。接著以微影與蝕刻 技術定義閘極氧化層46、閘極48與絶緣遮蓋層50以形 成閘極結構。接著以LPCVD沈積氧化矽且以非等向性钱 刻形成绝緣側壁間隙52形成於閘極之側壁。 經濟部中央橾隼局員工消費合作社印製 接著，如第七圖所示，一未掺雜之複晶矽層56形成 於閘極結構之上，該未摻雜之複晶矽層56之較佳厚度爲 1000至2000埃，接著分别以離子植入技術步驟形成p型 捧雜區域與π型摻雜區域，而進行上述之離子植入時以光 阻做爲軍幕穿越該部份未被光阻覆蓋之未摻雜之複晶矽 層56形成p與π型汲極/源極，而上述未被光阻覆蓋之複 晶矽層56亦形成摻雜之複晶矽，形成π型汲極/源極上述 離子摻雜之劑量爲4E15 atoms/cm2，離子植入之能量爲 40 KeV，形成p型汲極/源極上述離子摻雜之劑量爲3E15 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 五、發明説明（） atoms/cm2，離子植入之能量爲30 KeV。此步騍之優點 爲藉由上述之步嫌完成之摻灕區離子植入不會破壞基 板，也就是本發明防止基板因傳统之離子植入而被破壞。 參閲第八圈，一厚度1000埃之矽化鎢金屬層58接著形成 於複晶矽56之表面以降低複晶矽之電阻値。 請看第九圈，一光阻60定義於矽化鎢金屬層58之 上，接著一蝕刻技術蝕刻上述之矽化鎢金屬層58與複晶 矽56以形成内連線62，然後去除光‘阻20，該蝕刻之蝕 刻劑爲HBr。 參閲第十圈，第一介電層64形成於上述之閘極結構 與内連線62之上，以較佳實施例而言第一介電層62以硼 磷矽玻璃形成，厚度爲3 0&0埃。接著第二介電層66形成 於上述之第一介電層64之上，較佳之第二介電層66爲厚 度8000埃以SiH4$反應物形成之二氧化矽组成，接著以 微影與蝕刻技術蝕刻該第一介雹層62與第二介電層66 形成接觸孔（contact hole}67以曝露内連線62。 經濟部中央梂準局貝工消費合作社印装 參閲第十一圈，一金屬鎢栓68形成於上述之接觸孔 (con tact hoi e}67中做爲電性連接，以習知之技術形成金 屬連線70於上述之金屬鱗栓68之上，最後形成第三介電 層72形成於第二介電層66與金屬連線70之上。 12 本紙張凡度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B72. Description of the invention (--------- Λ 袈 — (Please read the precautions on the back and then fill in this page y The complex polysilicon layer 8 has been deposited on the substrate 2 by chemical vapor deposition. Oxidation 4, and on the gate oxide layer 6, the polycrystalline silicon layer 8 is a gate 'The thickness of the polycrystalline silicon layer 8 is between 1500 and 2000 angstroms, as the first insulating layer 12 is formed in On the polycrystalline silicon layer 8, the insulating layer 10 is preferably formed of an anti-reflective atmosphere. Then, the gate oxide layer 6, the gate electrode 8 and the insulating cover layer 10 are defined by photolithography and money etching techniques. «Forming a closed-electrode electrode and a conductive structure 12. The conductive structure 12 is formed on the field oxide region as the word line 12 is formed on the surface of the substrate as part of the transistor of the DRAM or other device. The insulating sidewall gap 14 is formed on the gate The side wall of the electrode 'This insulating side wall gap 14 is deposited by LPCVD silicon oxide and is formed by anisotropic etching. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Then as shown in the second figure, an undoped The doped polycrystalline silicon layer 16 is formed on the gate structure, the word line 12 and the substrate 2, and the undoped polycrystalline silicon layer 16 The preferred thickness is 1000 to 2000 angstroms, which defines a photoresist in a doped region. An ion implantation step uses the photoresist described above as a leather curtain to pass through the part that is not covered by the photoresist. The crystal layer 8 forms an electrode and a source, and the above-mentioned polycrystalline silicon layer 8 which is not covered by the photoresist also forms a doped polycrystalline hair. The dose of the upper ion doping is 4E15 atoms / cm2. The energy is 40 KeV. The advantage of this step is that the ion implantation in the impurity region completed by the above steps will not break the soil substrate, that is, the present invention prevents the substrate from being broken by traditional ion implantation. The area of the line and the area of the inner line are also aligned and formed simultaneously. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). Printed by the Ministry of Economic Affairs, Central Bureau of Prejudication and Consumer Cooperatives 1 A7 ________B7 2. Description of the invention () Refer to the third circle, a layer of 1000 Angstrom thick silicon metal layer 18 is then formed on the surface of the polycrystalline silicon 16 to reduce the resistance value of the polycrystalline silicon. Four circles, a photoresist 20 is defined as On the tungsten silicide metal layer 18, then-the official engraving technology described above The metal layer 18 and the polycrystalline hair 16 are formed to form the bit line 22 and the interconnect 24, and then the photoresist 20 is removed, and the etching agent is HBr. The first dielectric layer 26 is formed on the substrate 2 , The gate structure, the bit line 22 and the interconnect 24, in the preferred embodiment, the first dielectric layer 26 is formed of borophosphosilicate glass and has a thickness of 4000 angstroms. Then a photolithography and etching technique is used To form a contact hole 28 in the first dielectric layer 26. Referring to the fifth circle, a first conductive layer 30 is formed in the above-mentioned contact hole 28 and formed in the first dielectric layer 26 Then, lithography and etching techniques are used to etch the first conductive layer 30 as the bottom electrode of the capacitor. The first conductive layer 30 is doped polysilicon or doped polysilicon ( in-situ doped polysilicon), and then a dielectric 32 covers the first conductive layer 30, generally the dielectric 32 is nitride / oxide / nitride (0 / N / 0), nitride / Oxide (N / 0) or Ta205, and finally the second conductive layer 34 is formed on the dielectric 32 as the top electrode of the capacitor to complete the dynamic random access memory DRAM memory cell process. The bottom electrode of the capacitor contacts the interconnect 24 through the contact hole 28. (Please read the precautions on the back before filling in this page) 袈 · The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 public daughter) 318278 'A7 ___________B7 V. Description of the invention () The second embodiment of the invention In order to use this method to form a peripheral region of a DRAM or other 1 hail circuit, the method is as follows: As shown in the sixth figure, the crystal surface of the substrate 42 is a P type of < 100> The single crystal hair forms a field oxide layer 44 as an electrical isolation, and the preferred thickness is 4,000 to 6,000 angstroms. Then, a thermal oxidation method is used at a temperature of 850 to 1000 t; a thin gate oxide layer 46 is formed in the active area, preferably with a thickness of 100 angstroms. Then, a chemical vapor deposition method is used to deposit a mixed polycrystalline silicon layer 48 with a thickness between 1 500 and 2000 angstroms on the substrate 42, the field oxide 44, and the gate oxide layer 46. The insulating layer 50 is formed on the polycrystalline Above the silicon layer 48, the insulating layer 50 is preferably formed of silicon nitride with anti-reflective properties. Next, the gate oxide layer 46, the gate 48 and the insulating mask layer 50 are defined by lithography and etching techniques to form a gate structure. Next, silicon oxide is deposited by LPCVD and insulating sidewall gaps 52 are formed on the sidewalls of the gate by anisotropic etching. Printed by the Employee Consumer Cooperative of the Central Falcon Bureau of the Ministry of Economic Affairs. Then, as shown in the seventh figure, an undoped polycrystalline silicon layer 56 is formed on the gate structure. The preferred thickness is 1000 to 2000 angstroms, and then the p-type impurity region and the π-type doped region are formed by the ion implantation technology step respectively, and the photoresist is used as a military curtain to pass through this part when the above ion implantation is performed. The undoped polycrystalline silicon layer 56 covered by photoresist forms p and π-type drain / source, and the above-mentioned polycrystalline silicon layer 56 not covered by photoresist also forms doped polycrystalline silicon to form pi-type drain The dose of the above-mentioned ion doping is 4E15 atoms / cm2, and the energy of ion implantation is 40 KeV, forming a p-type drain / source. The dose of the above-mentioned ion doping is 3E15. ) A4 specification (210X297mm) A7 B7 5. Description of the invention () atoms / cm2, the energy of ion implantation is 30 KeV. The advantage of this step is that the ion implantation in the Li-doped area completed by the above steps does not damage the substrate, that is, the present invention prevents the substrate from being damaged by traditional ion implantation. Referring to the eighth circle, a tungsten silicide metal layer 58 with a thickness of 1000 angstroms is then formed on the surface of the polycrystalline silicon 56 to reduce the resistance value of the polycrystalline silicon. Please refer to the ninth circle, a photoresist 60 is defined on the tungsten silicide metal layer 58, followed by an etching technique to etch the tungsten silicide metal layer 58 and the polycrystalline silicon 56 to form the interconnect 62, and then remove the photoresist 20 The etchant for this etching is HBr. Referring to the tenth circle, the first dielectric layer 64 is formed on the gate structure and the interconnect 62 described above. In the preferred embodiment, the first dielectric layer 62 is formed of borophosphosilicate glass and has a thickness of 3 0 & 0 Angstroms. Next, a second dielectric layer 66 is formed on the above-mentioned first dielectric layer 64. Preferably, the second dielectric layer 66 is made of silicon dioxide formed with a SiH4 $ reactant with a thickness of 8000 angstroms, followed by lithography and etching Technically etch the first dielectric layer 62 and the second dielectric layer 66 to form a contact hole 67 to expose the interconnect 62. For printing and printing of the Beigong Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs, please refer to the eleventh circle. A metal tungsten plug 68 is formed in the contact hole 67 as an electrical connection, and a metal connection 70 is formed on the metal scale plug 68 by a conventional technique, and finally a third dielectric is formed The layer 72 is formed on the second dielectric layer 66 and the metal connection 70. 12 This paper is suitable for China National Standard (CNS) A4 specification (210X297mm) A7 B7
經 濟 部 中 央 搮 隼 局 % X. 五、發明説明（） 本發明另一應用爲同步形成DRAM記憶跑（第十二A 圈）與外困電路區域（periphery region)(第十二B囷）於基 板80之上，如第十二A圈輿第十二B圈所示’記憶胞區 域之閘極結構82、内連線84輿外面電路區域之閘極結構 86、内連線84可以利用上述實施之方法同步形成。 參閲第十三A圖與第十三B圖，厚度爲3000埃第一 介電層88同步形成於DRAM記憶胞（第十三A圏）與外固 電路區域（第十三B®)上’以較佳實施例而言第一介電層 88以硼磷矽玻璃形成，接著一光阻90定義於外圍電路區 域（第十三B圈）之上以曝露記憶胞（第十三A圈>區’一微 影與蝕刻技術用以形成接觸孔92於記憶胞區域之第一介 電層88之中》 參閲第十四A圖輿第十四B圈，接著第一導電層94 形成於上述之接觸孔（contact hole}92之中以及形成於第 一介電層88之上然後以微影與蝕刻技術用以蝕刻該第一 導電層94做爲電容之底部電極，該第一導電層94爲摻雜 複晶矽（doped polysilicon)或是已掺雜複晶矽（in-situ dopedpolysilicon)形成，然後一介電質96覆蓋於該第一 導電層94之上，最後第二導電層98形成於介電質96做 爲做爲電容之頂部電極，去除上述之光阻90。 參閲第十五A圖與第十五B圖，一光阻1〇〇形成於記 消 费 合 作 社 印 速用中國國家揉準(CNS >八4胁（210X297公釐)The Central Falcon Bureau of the Ministry of Economic Affairs X. V. Description of the invention () Another application of the present invention is to simultaneously form a DRAM memory run (12th circle) and a peripheral region (12th B) On the substrate 80, as shown in the twelfth A circle and twelfth B circle, the gate structure 82 of the memory cell area, the interconnection 84 and the gate structure 86 of the outer circuit area, the interconnection 84 can use the above The implemented method is formed simultaneously. Referring to Figures 13A and 13B, the first dielectric layer 88 with a thickness of 3000 Angstroms is formed on the DRAM memory cell (13th A-ring) and the external solid circuit area (13th B®) simultaneously 'In the preferred embodiment, the first dielectric layer 88 is formed of borophosphosilicate glass, and then a photoresist 90 is defined on the peripheral circuit area (13th circle B) to expose the memory cell (13th circle A) > Area 'a lithography and etching technique is used to form the contact hole 92 in the first dielectric layer 88 of the memory cell area. See FIG. 14A and circle 14B, followed by the first conductive layer 94 Formed in the above-mentioned contact hole 92 and above the first dielectric layer 88 and then used lithography and etching techniques to etch the first conductive layer 94 as the bottom electrode of the capacitor, the first The conductive layer 94 is formed of doped polysilicon or in-situ doped polysilicon, and then a dielectric 96 covers the first conductive layer 94, and finally the second conductive The layer 98 is formed on the dielectric 96 as a top electrode of the capacitor, and the photoresist 90 mentioned above is removed. Refer to FIG. 15A and FIG. Figure 15B, a photoresist 100 is formed by the Consumer Credit Cooperative Society. Printed with the Chinese National Standard (CNS > 8 4 threats (210X297mm)
經濟部中央揉準局貞工消费合作社印*. 31«278 ' A7 - -67 _^ 五'發明説明（） 憶胞（第十三A圖）之上以曝露外面電路區域（第十三日 圏），接著第二介電層102形成於上述之第一介電層88之 上’較佳之第二介電層102爲厚度8000埃以SiH4爲反麂 物形成之二氧化矽，接著以微影與蝕刻技術蝕刻該第一介 電層88與第二介電層102形成接觸孔。 . 參閲第十六A圈與第十六B圖，一金屬鎢栓1〇4形咸 於上述之接觸孔中做爲電性連接，然後以習知之技術形成 金屬連線106於上述之金屬鎢栓1〇4之上，最後形成第彡 介電層1&8形成於第二介耄層1〇2與金屬連線106之 上，去除光阻100。 本發明之實施例可以同步形成記憶胞與外面電路區 域節省成本及簡化製程，另外本發明提供一種非破壤珍基 板之摻雜區形成方法，以及一種自行對準形成位元線之製 程。 本發明以較佳實施例説明如上，而熟悉此領域技藝 者’在不脱離本發明之锖神範团内，當可作此許更動濁 姊’其專利保護範面更當視後附之申請專利範固及其等同 領域而定。 (装-------訂------ ns/fcs请背希4淡意事項鼻填寫本育>Printed by the Zhengong Consumer Cooperative of the Central Ministry of Economic Affairs of the Ministry of Economic Affairs *. 31 «278 'A7--67 _ ^ Five' Invention Description () On top of the memory cell (Figure 13A) to expose the circuit area outside (13th day)圏), and then the second dielectric layer 102 is formed on the above-mentioned first dielectric layer 88. The preferred second dielectric layer 102 is 8000 Angstroms thick silicon dioxide formed with SiH4 as an anti-curly substance, and then Shadow and etching techniques etch the first dielectric layer 88 and the second dielectric layer 102 to form contact holes. Refer to the sixteenth circle A and sixteenth figure B. A metal tungsten plug 104-shaped salt is used as an electrical connection in the above-mentioned contact hole, and then a metal wire 106 is formed on the above-mentioned metal by a conventional technique. On the tungsten plug 104, finally a first dielectric layer 1 & 8 is formed on the second dielectric layer 102 and the metal connection 106 to remove the photoresist 100. Embodiments of the present invention can simultaneously form memory cells and external circuit areas to save costs and simplify the manufacturing process. In addition, the present invention provides a method for forming a doped region of a non-breaking ground substrate and a process for forming bit lines by self-alignment. The present invention has been described above with the preferred embodiments, and those skilled in the art can use it as a permit to change the scope of the patent protection scope of the Shenshen Fan Group without departing from the present invention. The application for patents depends on the field and its equivalent. (Installed ------- ordered --- ns / fcs, please recite 4 insignificant matters, fill out this education>