TW317657B - Electrostatic discharge protection structure and manufacturing method thereof - Google Patents

Abstract

An electrostatic discharge protection structure comprises of: (1) one first conductive-type heavily doped polysilicon region, formed on one substrate surface, and connected to one power voltage; (2) one first conductive-type lightly doped region, formed under the substrate surface, and also below the polysilicon region; (3) one first conductive-type first heavily doped region, belonging to one first MOS device, formed under the substrate surface, and completely capped by the lightly doped region; (4) one first conductive-type second heavily doped region, belonging to one second MOS device, formed under the substrate surface, and with partial lightly doped region and second conductive-type doped portion in the substrate separating with the first region; (5) in which the first and second region is separated by one portion of the lightly doped region, therefore this can raise turn-on of one bipolar junction device constituted by first and second region, the portion of the lightly doped region, the second conductive-type doped portion in the substrate, so as to avoid the bipolar junction device of pre-turning on before electrostatic discharge protection device, preventing electrostatic discharge effect between the power voltage, takes effect, and the lightly doped region can contain one surface region bigger than the first heavily doped region, and decreasing flown electrostatic discharge current density when electrostatic discharges.

Description

317657 Printed A7 B7 by Beigong Consumer Cooperative of Central Bureau of Standards of Ministry of Economy V. Description of invention (1) 1 ~ This invention relates to improving the electrostatic discharge protection of semiconductor components and structures of integrated circuits, in particular to an internal electrostatic discharge protection Structure and manufacturing method. Electrostatic discharge protection is an important consideration in the design of integrated electrical circuits, especially when the size of semiconductor structures and components has been reduced to sub-micron (such as below 0.65 microns) resolution. The process of electrostatic discharge is in a very short time (often shorter than one microsecond), transferring high-potential charge to the pins of the integrated circuit wafer. Because most semiconductor integrated circuits contain metal oxide semiconductor elements such as MOSFETs, and their extremely thin gate oxide layer or lightly doped source wave region are easily damaged by electrostatic discharge. As these components shrink further, they are more likely to be injured by electrostatic discharge at a lower potential. Fig. 1 is a schematic diagram of an electrostatic discharge protection circuit 10 of an integrated circuit. The circuits 16 and 18 are used to protect the input buffer 12 from or will exert an electrostatic force on the input pad 14. When an electrostatic discharge occurs, the diode of circuit a has to co-flow most of the electrostatic discharge charge. When the polarity of the electrostatic discharge potential is negative, the diode D1 will conduct the electrostatic discharge charge to the vss line, and when the polarity of the electrostatic discharge potential is positive, the diode D2 will conduct the electrostatic discharge charge to the VDD line. The circuit 18 includes a resistor R connected in series with a grounded transistor M0. The circuit 18 has to limit the potential applied to the gate of the round buffer 12. The core friction limiting circuit 20 provides electrostatic discharge protection to the VDD and Vss power cables by transferring the electrostatic discharge charge between vDD and Vss. Most ESD protection devices are designed to be activated when a high ESD force is applied between the two pins of the integrated circuit chip. However, recent studies have noticed how to protect the power supply row of the integrated circuit chip. The paper standard of the 4 Ϊ paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210 χ29-7 -------- (please read the precautions on the back first Fill in this page).

、 1T line Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 317657 A7 B7 V. Description of the invention (2) Electrostatic discharge force between the lines. For example, the following literature reveals: DJ〇1 ^ ¥ 1 ^>% 11 · Rountree & 0. Adams, Internal Chip ESD Protection Beyond the Protection Circuit, IEEE TRANS. OF ELEC. DEV., VOL. 35, no. 12 . p.2133-38. Dec., 1988; J. LeBlanc & M. Chaine, Proximity Effects of “unused” Output Buffers on ESD Performance, IEEE IRPS PROC ·, P. 327-30 (1991). These data show that the ESD protection circuit between the VDD and Vss pins does not provide sufficient protection for the internal components of the chip. Furthermore, due to the internal device structure and the layout of each area, the chip may be damaged earlier due to the parasitic bipolar interface device that is activated earlier than the trigger of the electrostatic discharge protection circuit, which may damage the internal device. The circuits depicted in Figures 2 to 4 are taken as examples. FIG. 2 shows two adjacent internal circuits. In particular, a first circuit 22 including an NMOS transistor N1 is disposed adjacent to an NMOS transistor N2 of a second circuit 24. The plan diagram is shown in Figure 3, and the cross-sectional diagram is shown in Figure 4. Transistor N1 has a gate 30, a source 36 and a drain 38. The source electrode 36 and the drain electrode 38 are N + regions extending from the surface of the substrate 34. The transistor N2 has a gate 30 ', a source 40 and a drain 42. Like the transistor N1, the source electrode 40 and the drain electrode 42 are N + regions extending from the surface of the substrate 34. The drain 38 of the transistor N1 is connected to the VDD power supply line 32 via the contact area 28, and the source 40 of the transistor N2 is connected to the power supply line Vss 32 via the contact area 28 '. As shown in FIG. 4, the drain region 38 is relatively close to the adjacent source region 40. The N + drain region 38, N + source region 40 and the P-type substrate 34 between them are in accordance with the Chinese National Standards (CNS) A4 specification (210X297) ---------- Outfit ------ order ------ line- (please read the precautions on the back first and then fill out this page) Printed and printed 317657 A7 --------_ B7 3. Description of the invention (3 '--- into a parasitic NPN bipolar junction element 44. During electrostatic discharge, the electrostatic force may act between the Vdd power cable 32 and the V-shirt power cable 32. Because N + The drain region 38 and the source region 40 are too close, and the starting potential of the parasitic bipolar junction transistor 40 may be as low as 13 volts. The electrostatic discharge potential between the Vdd and Vss power supply lines 32 and 32 will be It is high enough to activate the parasitic junction transistor 44 and operate in the "snap-back" mode. In this way, it will cause a large amount of current and damage the components and structures of the integrated circuit. Note that the potential of the bipolar junction transistor 44 needs to be activated compared to the circuit used to protect the electrostatic discharge protection between the power cables (that is, the core clamp of Figure 1 The circuit 2〇) can handle a lower potential, so although there is an electrostatic discharge protection circuit, it is still inevitably damaged by electrostatic discharge. In some prior art, it has been proposed to widen the distance between components and structures to avoid similar parasitics Damage caused by bipolar junction components. For example, the distance between the drain region 38 and the source region 40 of transistors N1 and N2 is increased to 20 microns. However, such a waste of space on the integrated circuit chip will undoubtedly cause each egg. The structure and component density are reduced. Moreover, this design method may not completely prevent parasitic bipolar junction components from damaging the integrated circuit. Therefore, the purpose of the present invention is to overcome the disadvantages of the aforementioned conventional technologies. According to an embodiment of the present invention, a The ESD protection circuit is provided by a first conductivity type concentrated doped polycrystalline silicon region. This concentrated doped polycrystalline silicon region is deposited on a substrate surface and is connected to a power supply potential. A first conductivity type A lightly doped region is formed under the surface of the substrate and the polycrystalline silicon region. A first heavily doped region of a first conductivity type belonging to a first MOS device is formed on the surface of the substrate Below, it is included in the entire lightly doped area. It belongs to a second paper standard Tongzhou Jiashunzuzu Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back and fill in this page) Line A 7 B7 V. Description of the invention (4) A second conductivity type second heavily doped region of the MOS device is formed under the surface of the substrate and is composed of a part of lightly doped region and a second conductivity type in the substrate The impurity region is separated from the first region. Obviously, the first and second regions separated by partial light impurity regions will include the first and second regions, part of the lightly doped region and the substrate The turn-on voltage of the bipolar junction element formed by the partial regions of the two-conductivity type impurities is increased. (This bipolar junction element is actually a parasitic bipolar junction transistor. The collector is formed by the first region and the lightly mixed region. The second conductivity type part of the substrate is used as the base, and the first The two regions form their emitters.) The increase in the starting potential is due to the electrostatic discharge between the voltage and potential, to prevent the bipolar junction element from being activated before the electrostatic discharge protection element is inactive. Printed by the Employee Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs According to another embodiment of the present invention, the ESD protection structure is manufactured according to the following description. The heavily doped polycrystalline silicon region of the first conductivity type is formed on the surface of the substrate. The impurities thermally diffuse from the polycrystalline silicon into the substrate to form a lightly doped region of the first conductivity type. The first heavily doped region of the first conductivity type of the first MOS element is formed under the surface of the substrate and is completely covered by the lightly doped region. First: The first conductive type second heavily doped region of the Mos element is formed in a specific region below the surface of the substrate, so that the first and second heavily doped regions are partially lightly doped regions and part of the substrate Separated by the second conductivity type region. According to the above, the present invention proposes an electrostatic discharge protection structure and a manufacturing method thereof. This ESD protection structure is easy to manufacture with MOS compatible manufacturing process, and it can prevent the internal circuit from being damaged when ESD occurs between the power cables. This paper scale is applicable to the Chinese national frns: AW head k ¾ public yv 2 (please read the precautions on the back before filling out this page) Printed by the Ministry of Economic Affairs, Central Falcon Bureau Employee Consumer Cooperative 317657 A7 B7 V. Description of invention (5) In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, preferred embodiments are described below in conjunction with the accompanying drawings. Brief description of the drawings: Figure 1 shows a traditional electrostatic discharge protection integrated circuit; Figures 2 to 4 show the traditional internal circuit architecture with parasitic bipolar junction elements, the bipolar junction elements are static The electrostatic discharge phenomenon will still be caused under the discharge protection circuit; and FIGS. 5-12 show the manufacturing steps of the electrostatic discharge protection structure according to a preferred embodiment of the present invention. Embodiments The fabrication of an ESD protection structure according to an embodiment of the present invention is shown in FIGS. 5 to π. For the convenience of description, although the present invention is applicable to the entire CMOS device, the following will only take the formation of the electrostatic discharge protection structure of the nmOS device therein. Anyone who is familiar with this skill can also push the construction of the ESD protection structure for PMOS devices in CMOS devices according to the discussion in this article. Referring to the fifth ring, a P-type parallel region 110 and an N-type parallel region are formed in a substrate 102 by implantation or diffusion. The areas 110 and 112 may have a width of 20 microns and a depth of 1.9 microns. The p-type don-region 10 may be doped with paste ions at a concentration of about 8 × 10 16 / cm3, and the n-type don-region 112 may be doped with scale or kun ions at a concentration of about 2 × 1015 / cm3. As shown in FIG. 6, field oxide regions 114, 116, and 118 are formed on the surface of the substrate 102. The field oxides 114, 116 and 118 have to be made by the well-known local silicon oxide method (LOCOS). That is before the surface of the substrate 1〇2 (. Please read the precautions on the back before filling this page)-installed.

• 1T This paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297mm) A7 Printed and printed by the Staff Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs

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, 1T • 丨 line 317657 A7

case. This will form photoresist regions 132, 134, and 136, which correspond to the first polycrystalline silicon electrode of the first -MOS device, one of the polycrystalline silicon contacts of the first Mos device electrode, and a first: M〇 A polycrystalline silicon gate of the s device. The second layer 128 is etched with an etchant such as C6. As shown in FIG. 9, this will form the polycrystalline silicon gate 142 of the first MOS device, the polycrystalline silicon contact 144, and the polycrystalline silicon gate 146 of the first MOS device. Secondly, as shown in FIG. 9, a photoresist layer 148 is formed on the polycrystalline silicon gates 142, 146, the polycrystalline silicon contact region 144, the field oxide regions 144, 116, and 118 and the thin oxide layer 120. 148 defines surface windows 150, 152, 154, and 156 on the thin oxide layers 12 on both sides of each polycrystalline silicon gates Γ42 and 146. Next, impurities such as phosphorous ions are implanted through these windows 150, 152, 154, and 156 to form lightly doped source / drain regions 160, 162, 164, and 166 in the substrate. For example, with an energy of 70KeV, the implantation amount of 5 X 10I3 / cm2 is taken, and the source / drain regions 16〇, 162, ι64, and〗 are formed with an impurity concentration of about 5 X 10ls / cm3 and a depth of about 0. 66. The lightly doped source regions 160 and 164 and the lightly doped drain region 162 have a width of about 2.5 microns, and the lightly doped drain region 162 has a width of about 0.2 microns. As shown in Figure 10, Beigong Consumer Co., Ltd., Central Bureau of Standards, Ministry of Economic Affairs. After the photoresist layer 148 is removed, a dielectric layer 168 is formed on the polycrystalline silicon gates 142 and 146, the polycrystalline silicon contact area 144, Over field oxides 114, 116, and 118 and thin gate oxide layer 120. The dielectric layer 168 may be a silicon monoxide layer. Further, as shown in FIG. N, by anisotropic etch technique, the dielectric layer 168 is etched into the spacers 170, 172, 174, and 176 adjacent to the side surface of each polysilicon gate 142. A spacer 178 10 Printed by Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 _____B7 _ V. Description of Invention (8) It is also formed on the side of the polycrystalline silicon contact 144 and adjacent to the drain region 162. As shown in Fig. 11, by ion implantation, densely doped regions 180, 182, 184, and 186 are obtained in a square shape under the surface of the substrate. This planting can incorporate phosphorus ions of about 5 X 1015 / cm2 at 80KeV energy. Thus, concentrated doped source / drain regions 180, 182, 184, and 186 with a concentration of about 1020 / cm3 and a depth of about 0.2 microns are generated. Among them, the widths of the heavily doped source regions 180 and 184 and the densely doped drain region 186 are about 2.3 microns, and the width of the heavily doped drain region 182 is about 0.2 microns. FIG. 12 shows a structure 100 according to an embodiment of the invention. A first MOS device 210 is a MOSFET whose polycrystalline silicon gate 142 is formed on the thin oxide layer 120, its source contains source regions 180 and 160, its drain contains drain regions 162 and 182 and lightly doped The region 130, and its channel region contains a part of the p-type Dong region 110 and is laterally disposed between the source region 160 and the drain region 162 on both sides of the surface. A second MOS device 220 is a MOSFET whose polycrystalline silicon gate 146 is formed on the thin oxide layer 120, its source contains source regions 164 and 184, its drain contains drain regions 166 and 186, and its channel The region contains a part of the p-type don region 110 and is laterally disposed between the source region 164 and the non-electrode region 166 on both sides of the surface. As shown in the figure, it also includes a pre-metal dielectric 188, a polysilicon contact region 144, a source region 184, and a drain region 186, respectively. Contact 190 is connected to source region 180. Contact 192 connects to the polycrystalline contact area 144 (which is the drain contact 1820 1¾ to the VDD power cable (please refer to Figure 1 to Figure 4). Contact 194 connects the source region 184 to the Vss power cable ( (Please refer to Figure 1 to Figure 4). Contact 196 connects to the drain region 186. This paper scale is applicable to China National Standard (CNS) Α4 specification (210X297mm) (please read the precautions on the back before filling this page) Installed.-Β line Printed bags of employees ’consumer cooperatives of the Central Bureau of Standards and Economics of the Ministry of Economic Affairs 3ί7δ57 Α7 _____ Β7 5. Description of the invention (9) The ESD protection structure 10 is an integrated circuit that includes an ESD protection circuit as shown in Figure 丨Internal components. In particular, when the electrostatic discharge protection circuit of at least one power bank, such as a core clamp device, is provided to protect the electrostatic discharge effect occurring between the VDD and Vss power banks. Now consider the parasitic bipolar connection The surface element 230 has a collector including drains 162, 182, and 130 of the first MOSFET 210, a base including a p-type substrate 110 between the lightly doped region 130 and the source region 184, and an emitter Contains the source 16 of the second MOSFET 220 4 and 184. This parasitic bipolar junction element 230 is a bipolar junction transistor. The low impurity concentration of the JT Bu doped region 130 will increase the breakdown potential of the pn junction between base collectors. Among them, the breakdown of BJT 44 The potential is only 3 volts, and the breakdown potential of BJT 23〇 is increased to about 18 volts. This will prevent the parasitic BjT 230 from starting before the power supply electrostatic discharge protection element during the electrostatic discharge process (especially when the electrostatic discharge voltage When applied to the VDD and vss power banks.) It is important to note that the lightly doped region 13 is deeper than the drain regions 162 and 182. This will help reduce contact penetration due to electrostatic discharge ( Contact spiking). Especially when the N + drain region 182 is completely contained within the lightly doped region 130, the chance of a short circuit between the N + drain region 182 and the p-type dongle region 110 will be even lower. In addition, the metal contact 192 may be separated from the N + drain region by the polycrystalline silicon contact region 144. Since the metal contact 192 does not directly contact the N + drain region, the N + drain region 182 is caused by contact breakdown of the power supply potential vDD electrostatic discharge The possibility is even lower. The lightly doped region 130 occupies a considerable space, and its volume and table 12 table paper scale are applicable to the Chinese National Standard (CNS) A4 specification (2 丨 Οχ29 * / 公 楚) II --------- installed 丨· *-(Please read the notes on the back before filling this page)

、 1T line 3ί7δ57 V. Description of the invention (10 The area is larger than the volume and surface area of the Ji_polar region 182. When the bjt 230 starts to collapse, the electrostatic discharge current will spread through its larger surface area, reducing its current density In order to reduce the damage to the integrated circuit. The present invention discloses an electrostatic discharge protection structure and a method of manufacturing the same. A first conductivity type heavily doped polycrystalline silicon region is formed on a substrate surface and is connected to a power supply potential.- The first-conductivity type heavily doped region is formed below the substrate surface and the polycrystalline sand region. A first-conductivity type first concentrated exchange impurity region, which belongs to a first MOS το device, is formed under the substrate surface and completely includes In the lightly doped region, a first conductively second densely doped region, which belongs to a second Mos / 0 part, is formed under the surface of the substrate, and is part of the lightly doped region and the substrate -The part of the second conductivity type is separated from the first region. The first and second regions separated by the light-exchange region can increase the starting potential of the parasitic bi-junction junction element. The first and second areas are lightly mixed areas < And the second conductivity type part in the substrate. The increase of the starting potential can prevent the parasitic bipolar junction device from starting first during the electrostatic discharge process before the electrostatic discharge protection device acts. According to the process of the present invention, it is highly praised Miscellaneous complex eggs are formed on the surface of the substrate, and the impurities in it have to form a lightly doped area under the surface of the substrate by thermal diffusion. Central Ministry of Economic Affairs Printed by the Beige Consumer Cooperative Society Although the invention has been better The embodiments are disclosed as above, but it is not intended to limit the present invention. Anyone who is familiar with this continuation technique can make some changes and modifications within the spirit and scope of the present invention, so the scope of protection of the present invention is Subject to the definition of the scope of the attached patent application. This paper standard towel ϋ 13

Claims (1)

A8 B8 C8 D8 Amendment date 317657 No. 85108800 is applied for the patent scope printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. The scope of the patent application is amended. 1. An electrostatic discharge protection structure, including: a first conductive type densely doped polycrystalline silicon region formed on a substrate The surface is connected to a power supply potential; a lightly doped region of the first conductivity type is formed under the surface of the substrate and also below the polycrystalline silicon region; a first heavily doped region of the first conductivity type , Belonging to a first MOS device, formed under the surface of the substrate and completely covered by the lightly doped region, and a second heavily doped region of the first conductivity type, belonging to a second MOS device , Formed under the surface of the substrate, and separated from the first region by a portion of the lightly doped region and a second conductivity type doped portion of the substrate; where 'the first and second regions are affected by the A part of the lightly doped region is separated, so the first and second regions, the part of the lightly doped region, and the second conductivity type doped part in the substrate can be formed Bipolar junction components The start-up is increased so that the bipolar junction can be prevented from starting before the electrostatic discharge protection element that prevents the electrostatic discharge effect between the power supply potentials, and the lightly doped region can further include a concentration greater than the first The larger surface area of the doped area reduces the electrostatic discharge current density flowing during electrostatic discharge. 2. The structure as described in item 1 of the scope of the patent application further includes: a metal contact formed in the heavily doped polycrystalline silicon region for electrically connecting the first heavily doped region to the power source, the metal The contact is substantially separated from the first heavily doped region, so that the first densely doped region and the paper size can be reduced to use the China National Standards (CNS) A4 specification (210X297mm) (please read the notes on the back first (Fill in this page again) Printed and printed by the Employees Consumer Cooperative of the Central Bureau of Economics and Trade of the Ministry of Economic Affairs A8 B8 C8 _ — 08 VI. Application for patent specification -1 —- The possibility of short circuit of the second conductive type part of the substrate during electrostatic discharge. 3. A kind of electrostatic discharge protection structure, suitable for an integrated circuit, the integrated circuit includes a first and a second power cable, and a connected between the first and the second power cable Electrostatic discharge protection circuit; the electrostatic discharge protection structure is an internal circuit connected between the _ and the second power line, including: a concentrated doped region polycrystalline silicon region, having a first conductivity type, Formed on the surface of a substrate and connected to one of the power cables; a lightly doped region, having the first conductivity type, formed under the surface of the substrate and the polycrystalline silicon region; a first heavily doped region , Having the first conductivity type, belonging to a first MOS device, formed under the surface of the substrate and completely contained in the lightly doped region; a second heavily doped region, having the first conductivity type, belonging to a first Two MOS devices are formed under the surface of the substrate, and are separated from the first region by a portion of the lightly doped region and a doped portion of the second conductivity type in the substrate. 4. An electrostatic discharge protection structure suitable for a semiconductor structure containing a first and a second MOSFET, each of which includes: a polycrystalline silicon gate 'formed on a substrate surface; a heavily doped first A conductive type drain region is formed under the surface of the substrate; and a heavily doped first conductive type source region is formed on the surface of the substrate. 15 paper buttons are suitable for the Laijia standard (;) from the secret (210X297 Mm) " (please read the precautions on the back before filling in this page) T 7657 A8 B8 C8 D8 6. Under the scope of patent application; the ESD protection structure includes: a concentrated doped polycrystalline silicon contact area, with The first conductivity type is formed on the surface of the substrate and connected to a power supply voltage, and a lightly doped region having the first conductivity is formed under the surface of the substrate and below the polycrystalline silicon region; wherein, the MOSFETs are The source or drain region of the first MOSFET is completely contained in the lightly doped region, and the second conductive type doped portion in the substrate is used to Source of two MOSFET Isolated drain regions. 5. A method of manufacturing an electrostatic discharge protection structure, including the following steps: forming a first conductivity type concentrated doped polycrystalline silicon region on the surface of a second conductivity type portion of a substrate; The doped region diffuses into the substrate, and a lightly doped region of the first conductivity type is formed under the surface of the substrate and below the polycrystalline hair region; a first heavily doped region of the first conductivity type is formed, belonging to a first A MOS device under the surface of the substrate and completely contained in the lightly doped region; and a second heavily doped region forming the first conductivity type, belonging to a second MOS device 'located under the surface of the substrate A specific position to laterally separate the first and second regions by the lightly doped region and the second conductivity type region of the substrate. This paper uses the Chinese National Standard (CNS) A4 (210x297mm) (please read the precautions on the back and then fill out this page) T. Ordered by the Ministry of Economic Affairs, Central Bureau of Standardization, Beigong Consumer Cooperative Printed A8 B8 C8 D8 6. Patent application scope 6. The manufacturing method described in item 5 of the patent application scope further includes: forming a metal contact on the heavily doped polycrystalline silicon region, so that the heavily doped polycrystalline silicon region, the The lightly doped region and the first heavily doped region are connected to a first power supply line; and a metal contact is formed on the second heavily doped region to connect the second heavily doped region to a second power supply Flat cable; wherein, an electrostatic discharge potential must be generated through the first and second power cables. (Please read the precautions on the back before filling out this page) T, 11 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs This paper standard applies to the Chinese National Standard (CNS) A4 (210 X 297 mm)