31C328 A7 B7 經濟部中央梯準局哭工消费合作社印装 五、發明説明（) 發明領域： 本發明與一種高密度動態随機存取記憶體（dynamic random access memory ； DRAM)之電容器製程有關，特 别是一種形成堆疊式t容之氮化矽/氧化矽（Nf/O)介電層 之方法，適用於半導《工業之積體電路製作中。 發明背景： 目前工業界致力於發展高積集度之動態隨機存取記 It tt (dynamic random access memory ； DRAM)，從 16K 位元、64K位元、1M位元至16M位元發展，因此便宜且 容量大之DRAM便随著製程技術之改善而向更高位元發 展。動態随機存取記憶嫌（dynamic random access memory ; DRAM)是一種主要之揮發性（volatile)記憶 雄。在元件不斷縮小下，電容之表面積輿儲存之電荷數亦 不斷減小’在此情形下因a粒子造成之軟記错及在半導想 中之穩定性變成重要之問題。在元件墙小下以提高積集度 將使電容之表面積減少，爲使電容性能不會降低之重容製 程方法舆結構是電容製程努力之方向。一般典型之動態隨 機存取記愫體是於半導體之基板上製造金氧半場效電晶 體（MOSFET)輿電容器，利用接觸窗來連接電容器之電荷 儲存電極（storage node)與金氧半場效電晶體之源極作電 性之接觸。籍由電容器與源極區之電性接觸，數位資訊锻 (請先閱讀背面之注意Ϋ項再填寫本頁)31C328 A7 B7 Printed by the Crypto-Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs 5. Description of the invention () Field of the invention: The present invention relates to a high-density dynamic random access memory (DRAM) capacitor manufacturing process, In particular, a method of forming a stacked t-capacitor silicon nitride / silicon oxide (Nf / O) dielectric layer is suitable for manufacturing semiconductor integrated circuits. Background of the invention: At present, the industry is devoted to the development of high-integration dynamic random access memory It tt (dynamic random access memory; DRAM), which develops from 16K bits, 64K bits, 1M bits to 16M bits, so it is cheap And DRAM with large capacity will develop to higher bit with the improvement of process technology. Dynamic random access memory (DRAM) is a main type of volatile memory. As the device continues to shrink, the surface area of the capacitor and the number of stored charges continue to decrease. In this case, the soft memory errors caused by the a particles and the stability in the semiconducting concept become important issues. Under the component wall is small to increase the degree of accumulation will reduce the surface area of the capacitor, in order to make the capacitor performance does not degrade the heavy capacity process method and structure is the direction of the capacitor process. A typical dynamic random access memory device is to manufacture a metal oxide half field effect transistor (MOSFET) and a capacitor on a semiconductor substrate, and use a contact window to connect the charge storage electrode (storage node) of the capacitor and the metal oxide half field effect transistor The source is used for electrical contact. Due to the electrical contact between the capacitor and the source region, the digital information is forged (please read the note Ϋ on the back before filling this page)
X 裝. 訂 本紙张又度逍用中國國家標準（CNS ) A4規格（210X297公董） 316328 A7 B7 經濟部中央標準局貝工消费合作社印裂 五、發明説明（） 存在電容器並藉金氧半場效重晶髏、位元線（bit line)、 字锊線（word line)陣列來取得重容器之數位資料。所謂 的單一重晶體 DRAM 胞（single transister DRAM cell)事 實上是由一個DRAM雹晶鳢輿雹容器（capaCit〇r)所構成 的’電.容器是DRAM胞藉以錄存訊號之心臟部份，若電 容器所儲存之電荷越多，讀出放大器在讀取資料時受雜訊 之影響如α粒子所產生之軟記錯（soft errors)將大大降 低，更可減低"再補充"之頻率。電晶醴之源極舆電容之一 端連接，電容之另一端則與參考電位連接，因此製造 DRAM記憶胞，包含了重晶醴輿黨容之製程，一般增加電 容器儲存電荷能力方法有（1)增加介黨質之介電常數，使 電容器單位面積之儲存雹荷數增加；（2)減少介電層之厚 度；（3)增加雹容器之面積，使整個偫存於電容器内之電 荷數增加。——般平板電容器爲最常用之電容結構，爲了增 進晶圓元件之密度’ DRAM技術傾向於將尺寸缩小，因 爲尺寸之编小相對的重容面積也減少而造成電容餘存能 力之減少’電容之再捕充（refresh)^率也會增加，另外也 會造成電容亦受α粒子之干擾。 一種具有半球形晶粒之複晶矽之電容也已發表在文 獻中，如"A Capacitor-Over-Bit-Line Cell With Hemispherical-Grain Storge Node For 64Mb Drams”，Μ· Sakao etc· microelectr research laboratories, NEC Corporation).該半球形晶粒之複晶 矽是以化學氣相沈猜法於非晶形轉變至晶形之相變溫度 本紙張尺度逋用中國國家橾準（CNS〉A4規格（210X297公釐） -------：-丨+裝—— (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央梂準局貝工消费合作社印製 A7 ____B7 五、發明説明（） 下沈積。另外一種爲具有半球形晶粒複晶矽之圓柱形電 容’參閲"A New Cylindrical Capacitor Using Hemispherical Grained Si For 256 Mb Drams", H. 评3七31^661&1.,丁6(：1\01宕,〇6(：.1992,卩卩.259-262。其次， 一種皇冠形（crown shape capacitor)或中空柱狀結構 (cylindrical structure)之電容亦已被發表，然而上述之 電容型態製程非常之複雜。 傳统之電容介電質爲使用二氡化矽/氮化矽/二氧化梦 (O/N/O)或是氮化矽/二氧化矽（N/O)，一般堆疊式霄容 以厚度爲7-20nm之二氧化矽/氮化矽/二氧化梦做爲電 容介雹質之信賴度較高，但是因爲積集度之增加，爲了符 合64Mbit或更高之需求，目前爲止以N/O'比O/N/O適 合做爲重容介電質，主要是N/O有較大之等效介電常 數，因此在形成氮化矽之前必須將自然形成之二氧化珍去 除，傳统之方法爲在沈積氮化矽之前使用氫氟酸將二氡化 矽去除。參閲第一圈，以此種方法之製程在將基板1迭入 沈積氮化矽5之瀘管前仍有部份二氧化矽3形成於做爲電 容重極之複晶*夕11之上，沈積氮化矽5之後在於其上形 成二氧化矽7,最後再沈積第二複晶矽9做爲電容第二電 極，然而這些多餘之二氧化矽3將會增加氮化矽5之成核 時間，且在组成比爲SUN4形成前會產生不連續之富石夕 (silicon-rich)之成份，此現象顯然會增加等效二氡化石夕 厚度。 本紙張尺度逋用中國國家標準（CNS )八4規格（210x297公釐） (請先閲讀背面之注意事項再填寫本頁)X pack. The bound paper is used in Chinese national standard (CNS) A4 specification (210X297 company director) 316328 A7 B7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention () There are capacitors and borrow gold for half-time The digital data of the heavy container is obtained by using the array of crystal skeletons, bit lines and word lines. The so-called single-transistor DRAM cell (single transister DRAM cell) is actually composed of a DRAM hail crystal and hail container (capaCitor). The container is the heart of the DRAM cell to record the signal, if The more charge stored in the capacitor, the sense amplifier will be affected by noise when reading data, such as the soft errors generated by alpha particles (soft errors) will be greatly reduced, and the frequency of "additional" may also be reduced. The source of the transistor is connected to one end of the capacitor, and the other end of the capacitor is connected to the reference potential. Therefore, the manufacturing process of the DRAM memory cell includes the process of regenerating the capacitor and the party capacity. Generally, the method of increasing the capacitor's charge storage capacity is Increasing the dielectric constant of the dielectric substance increases the storage hail load per unit area of the capacitor; (2) reduces the thickness of the dielectric layer; (3) increases the area of the hail container, so that the charge amount stored in the entire capacitor increases . ——Generally, flat capacitors are the most commonly used capacitor structure. In order to increase the density of wafer components, DRAM technology tends to reduce the size, because the smaller the size, the smaller the recombination area is, which reduces the residual capacity of the capacitor The refresh rate will also increase, and the capacitance will also be disturbed by alpha particles. A polycrystalline silicon capacitor with hemispherical grains has also been published in the literature, such as " A Capacitor-Over-Bit-Line Cell With Hemispherical-Grain Storge Node For 64Mb Drams ”, Μ · Sakao etc · microelectr research laboratories , NEC Corporation). The polycrystalline silicon with hemispherical grains is transformed from amorphous to crystalline phase by chemical vapor deposition method. The paper size is based on the Chinese National Standard (CNS> A4 specification (210X297mm ) -------:-丨 + installed—— (Please read the notes on the back before filling in this page) Order A7 ____B7 printed by Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs Deposition. The other is a cylindrical capacitor with hemispherical grain polycrystalline silicon 'see " A New Cylindrical Capacitor Using Hemispherical Grained Si For 256 Mb Drams ", H. Comment 3/7 31 ^ 661 & 1, Ding 6 (: 1 \ 01Dang, 〇6 (:. 1992, 卩 卩 .259-262. Secondly, a crown shape capacitor or hollow cylindrical structure) has also been published, but the above Capacitive type process is very complex The traditional capacitor dielectric is silicon dioxide / silicon nitride / dream dioxide (O / N / O) or silicon nitride / silicon dioxide (N / O), which is generally stacked in thickness The reliability of 7-20nm silicon dioxide / silicon nitride / dioxide as a capacitor dielectric is higher, but because of the increase in accumulation, in order to meet the requirements of 64Mbit or higher, so far O 'ratio O / N / O is suitable as a bulk dielectric, mainly because N / O has a large equivalent dielectric constant, so the naturally formed dioxide must be removed before forming silicon nitride. Traditional The method is to use hydrofluoric acid to remove the silicon radon before depositing the silicon nitride. Refer to the first circle. In this method, there are still some parts before the substrate 1 is stacked into the lubricating tube where silicon nitride 5 is deposited. A portion of silicon dioxide 3 is formed on the polycrystal as the heavy pole of the capacitor * 11. After the deposition of silicon nitride 5, silicon dioxide 7 is formed thereon, and finally the second polycrystalline silicon 9 is deposited as the second capacitor Electrodes, however, these excess silicon dioxide 3 will increase the nucleation time of silicon nitride 5, and will produce discontinuous rich stone before the composition ratio is formed by SUN4 on-rich), this phenomenon will obviously increase the equivalent thickness of the two radon fossils. This paper uses the Chinese National Standard (CNS) 84 specifications (210x297 mm) (please read the precautions on the back before filling in this page)
，1T 經濟部中央樣準局系工消費合作杜印製 316328 A7 A7 B7 五、發明説明（） 其次，若以Ta2〇s做爲雹容之介電質時，在以pVD 或CVD形成Ta2〇s之後必須施以退火處理（armealing)以 消除因氧缺陷而造成之漏電流，但是在進行含氧環境之退 火步棵時’氧容易穿透Ta2〇s進入至複晶矽底部書極之表 面造成複晶夕底部電極之氡化，因此其介電常數 (effective permittivity)將降至小於25以下，傳统防止複 晶矽底部電極氧化之方法爲利用快速熱處理製程（RTN) 形成一 SiON薄膜於複晶矽底部電極之上以防止氧化，但 是此製程在NH3環境中以高溫處理不僅產能很低且有氩 原子穿透之問題。 發明目的及概述： 本發明之主要目的爲利用電感耦合氮電漿在形成氮 化矽/氧化矽介雹廣之前，處理複晶矽底部電極以防止其 氧化。 形成電晶體以及接觸洞之後沈積一複晶矽層於基板 之上’接著在此複晶矽層上以定義光阻之圈案，利用蝕刻 技術進行上述之複晶矽層之蝕刻，形成耄容之底部電極。 接著將複晶梦表面自然氧化之二氧化梦（native oxide)去 除。再以電感拓合氮電漿（inductively-coupled nitrogen plasma ; ICNP)將其表面氮化。反應氣體爲氮氣，此雹 感拓合氮電漿可以進入複晶矽之表面以抑制二氧化梦之 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公酱） ---------T 裝-- (請先閲讀背面之注意事項再填寫本頁) 訂 A7 B7 五、發明説明（） 自然形成（native oxide growth)並降低氣化發之成核定-遢時間。電漿之功率爲150-250W，氮氣之流量爲35至 45 seem， 氣《壓力爲400至450 mtorr，處理時問爲5 至15分鐘。 完成ICNP之處理步驟後，進行氮化矽之沈積。以較 佳實施例而言，氮化矽以低壓化學氣相沈積法沈積，接著 可以再次使用以電感耦合氮之電漿處理，電漿之功率爲 250W，氮氣之流量爲35至45 seem，氣禮壓力爲400至 450 mtorr，處理時間爲5至15分鐘。然後氧化方式形成 二氧化矽於氮化矽之上，最後以低壓化學氣相沈積 (LPCVD)法形成另一複晶矽層，此複晶矽層將作爲電容之 上層霓極。 圈式簡單説明·- 第1圖爲傳统形成電容介電層製程之截面圈。 第2图爲本發明之形成金氧半場效電晶體之截面圈》 第3固爲本發明之形成第二複晶矽層之截面圈。 第4圈爲本發明以電感耦合雩漿前處理之截面圈。 經濟部中央樣準局属工消費合作杜印製 ----------(^— ·'- (請先聞讀背面之注意事項再填寫本頁〕 C、 第5圈爲本發明形成氮化矽沈積以及利用電感耦合電漿 處理之截面圈》 第6圈本發明形成第三複晶矽之截面圈。 本紙張又度逋用中國國家標準（CNS ) A4规格（210X297公釐） A7 B7 經濟部中央橾準局員工消费合作社印裝 五、發明説明（） 發明詳細説明： 本發明爲一種可以提高動態随機存取記憶髖 (dynamic random access memory)堆疊式電容之氮化發/ 二氡化矽或Ί^2〇5介重層形成方法，本發明製程簡易且能 有效提昇電容之性能。本發明之實施例將詳細説明如下： 參閲第二圈，以一晶面爲< 1〇〇>之單晶半導髖爲基 板’如Ρ型單晶之基板2。以限區氧化製程製作一厚的場 氧化區4作爲主動區域之絶緣物，此場氧化區域4之形成 係藉由經過沈積、微影之氮化矽輿二氧化矽複合層作爲革 幕將主動區加定義，然後在含氡之環境下熱氡化，溫度 在850-1050 ·(〇間產生二氡化矽，厚度爲4000-6000埃，然 後以熱磷酸去除氡化矽，以氫氟酸去除二氡化矽，接著在 上述之P型基板上經由習知技術之製程形成金氧半場效 霣晶體，其結構包含有一二氧化矽層6形成於基板2之上 做爲閘極氧化層，此二氧化矽層一般爲利用熱氧化法形 成，製程溫度約爲850至1000 之間形成厚度約50至200 埃，當然一般昔知之技術亦可以形成此閘極氧化層6，如 化學氣相沈積法（chemical vapor deposition)，第一複晶 矽層8沈積於二氡化矽層6、場氡化層4以及基板2之上， 以一實施例而言，此第一複晶矽層8利用化學氣相沈積法 (CVD)形成，厚度約爲1500至3000埃之間，接著字語線 (wordline)lO、位元線（bitline)12、閘極結構（閘極8 (請先閲讀背面之注意事項再填寫本頁) -K裝· 訂 1- 本纸張又度逍用中國國家橾準（CNS > A4規格（210X297公釐） 經濟部中央梂準局貝工消費合作社印袈 A7 B7五、發明説明（） 與閘極氧化層6)以及側壁間隙（sidewall spacers) 14利用 昔知之技術製作’而在此非本發明之重點因此不加以詳 述。其次，爲了重晶體與黨容做電性接觸，一做爲絶緣層 之介耄層16形成於上述之閉極結構、場氧化層4以及基 板2之上，然後一接觸洞利用微影以及蝕刻製程形成於該 介電層16之中。 參閲第三圈，完成金氧半場效電晶體之製作後，接著 沈積第二複晶矽層18，厚度爲2000埃至3000埃之間， 第二複晶矽層以低壓化學氣相沈積（LPCVD)法以PH 3 、 SiH4 、N2之混合氣體利用同步摻雜（in-situ doped)形 成複晶矽層或是沈積複晶矽層後再摻雜雜質，緊接著在此 第二複晶石夕層上以定義光阻之圈案，利用蝕刻技街進行上 述之第二複晶矽層之蝕刻形成電容之底部雹極。接著沈積 氩化矽之前施以前處理程序將第二複晶矽18表面自然氧 化之二氧化矽（native oxide)去除，以較佳實施例而言可 以使用氫氟酸之清理程序。 參閲第四圈，以電感Μ合氮電漿（inductively-coupled nitorgen plasma ; ICNP)在形成氮化石夕/二氧化 矽介雹層之前處理複晶矽底重極，反應氣禮爲氮氣，此嘗 卷耦合氮重槳可以進入第二複晶矽18之表面以防止二氧 化梦之自然形成（native oxide growth)以及降低氮化發 20之成核延遲時間。以較佳之實訑例而言，電漿之功芈 本紙張尺度逍用中國困家榡準（CNS ) Α4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) η 裝· 、π 經濟部中央棣準局貝工消费合作社印製 A7 B7 五、發明説明（） 爲250W»氛氣之流量爲35至45sccm，最佳爲40sccm， 氣雔整力爲400至450 mtorr，最佳爲420 mtorr，處理 時間爲5至15分鏜。 另外亦可以使用Ta205做爲重容之介重質經過上述 之ICNP之前處理，使之複晶矽底部電極之表面含有富氮 (nitrogen rich)，因此在後續Ta2Os之退火處理時，複晶 矽底部電極不易氧化，因而可以確保介電層之等效厚度， 本發明之方法不會有氫原子穿透之問題而且製程温度較 低約爲300 eC，其次利用ICNP之方袪可以形成均勻且薄 之 SiON。 參閲第五圈，完成ICNP之處理步驟後，速行氮化矽 20之沈積，以較佳實施例而言，氮化矽20以低壓化學氣 相沈積法沈積至厚度約爲70至140埃，接著可以再次使 用以電感麵合氮之電漿（inductive coupled nitrigen plasma)處理以修補氮化矽20表面之缺陷。此步嫌亦可以 不實行’端視所需達致之目標而定。同理，以較佳之實施 例而言，t漿之功率爲250W，氮氣之流量爲35至45 seem，氣禮壓力爲400至450 mtorr，處理時間爲5至15 分鐘。然後以熱氧化方式形成二氧化矽層22於上述之氮 化矽層20之上，以最佳實施例爲在含氧環境中形成，製 程溫度爲800至950 ·(〇之間，處理時間约爲25至35分鐘。 本紙張尺度逋用中國國家標準（CNS ) Μ規格（210Χ297公釐） (請先Μ讀背面之注意Ϋ項再填寫本頁) 訂 3X6328 A7 Αν _____ B7 五、發明説明（） 如第六圈所示，以低壓化學氣相沈積（LPCVD)法以 PH 3 、SiH4 、 之混合氣體利用同步摻雜（in-situ doped)形成第三複晶矽層24，亦可沈積複晶矽層後再摻 雜雜質形成此第三複晶矽層24，此第三複晶矽層24將作 爲電容之上層電極沈積於上述二氧化矽22之上，接著以 蝕刻技術蝕刻第三複晶矽層完成電容之製作。 本發明以一較佳實施例説明如上，而熟悉此領域技藝 者，在不脱雜本發明之精神範面内，當可作些許更動濶 飾，其專利保護範圍更當視後附之申請專利範圍及其等同 領域而定。 (請先閲讀背面之注項再填寫本頁) Γ 訂 經濟部中央棣準局男工消费合作社印製 一張 -紙 本 準 搞 家 固 國 中 用 適 Μ, 1T Ministry of Economics, Central Bureau of Prospects, Industrial and Consumer Cooperation Du Printing 316328 A7 A7 B7 V. Description of the invention () Secondly, if Ta2〇s is used as the dielectric material of hail capacity, Ta2 is formed by pVD or CVD After s, an annealing treatment (armealing) must be applied to eliminate the leakage current caused by the oxygen defect, but during the annealing step in the oxygen-containing environment, oxygen can easily penetrate Ta2〇s and enter the surface of the bottom of the polycrystalline silicon. The radon of the bottom electrode of the compound crystal is reduced, so its effective permittivity will be reduced to less than 25. The traditional method for preventing the oxidation of the bottom electrode of the compound crystal silicon is to use a rapid thermal process (RTN) to form a SiON film It is above the bottom electrode of crystalline silicon to prevent oxidation, but this process at high temperature in NH3 environment not only has low productivity but also has the problem of argon atom penetration. Object and Summary of the Invention: The main object of the present invention is to use an inductively coupled nitrogen plasma to treat the bottom electrode of polycrystalline silicon to prevent its oxidation before forming the silicon nitride / silicon oxide dielectric layer. After forming transistors and contact holes, a polysilicon layer is deposited on the substrate. Then, on the polysilicon layer to define the photoresist circle, the above polysilicon layer is etched using etching technology to form a capacitance The bottom electrode. Then remove the native oxide on the surface of the compound crystal dream. The surface is then nitrided with inductively-coupled nitrogen plasma (ICNP). The reaction gas is nitrogen. This hail sensor and nitrogen plasma can enter the surface of the polycrystalline silicon to suppress the dream of dioxide dioxide. The paper size is applicable to the Chinese National Kneading Standard (CNS) A4 specification (210X297 public sauce) ------ --- T outfit-- (Please read the precautions on the back before filling in this page) Order A7 B7 V. Description of the invention () Natural formation (native oxide growth) and reduce the nucleation time of gasification. The power of the plasma is 150-250W, the flow rate of nitrogen is 35 to 45 seem, the pressure of the gas is 400 to 450 mtorr, and the processing time is 5 to 15 minutes. After the ICNP process is completed, silicon nitride is deposited. In the preferred embodiment, silicon nitride is deposited by low-pressure chemical vapor deposition, and then it can be treated again by plasma with inductively coupled nitrogen. The power of the plasma is 250W, and the flow rate of nitrogen is 35 to 45 seem. Ceremonial pressure is 400 to 450 mtorr, and processing time is 5 to 15 minutes. Then oxidize to form silicon dioxide on top of silicon nitride. Finally, another low-pressure chemical vapor deposition (LPCVD) method is used to form another polycrystalline silicon layer. This polycrystalline silicon layer will serve as the upper layer of the capacitor. Brief description of the ring type-Figure 1 is a cross-sectional ring of the traditional process of forming a capacitor dielectric layer. FIG. 2 is a cross-sectional ring of the present invention for forming a metal oxide half field effect transistor. FIG. 3 is a cross-sectional ring of the present invention for forming a second polycrystalline silicon layer. The fourth circle is a cross-section circle of the present invention pre-treated with inductively coupled magma paste. Printed by the Ministry of Economic Affairs, Central Bureau of Standards, Industrial and Consumer Cooperation ---------- (^ — · '-(please read the precautions on the back before filling out this page) C, circle 5 is the basis Invention of the formation of silicon nitride deposition and the use of inductively coupled plasma treatment of the cross-section circle "6th circle The invention forms the third polycrystalline silicon cross-section circle. This paper also uses the Chinese National Standard (CNS) A4 specification (210X297 mm ) A7 B7 Printed by the Central Consumer ’s Consumer Cooperative of the Ministry of Economic Affairs 5. Description of the invention () Detailed description of the invention: The present invention is a nitrided capacitor that can improve the dynamic random access memory hip (dynamic random access memory) stacked capacitor / The formation method of di-radonized silicon or Ί ^ 205 dense layer, the process of the present invention is simple and can effectively improve the performance of the capacitor. The embodiments of the present invention will be described in detail as follows: See the second circle, taking a crystal plane as < 1〇〇 > The single crystal semiconducting hip is the substrate 'such as the P-type single crystal substrate 2. A limited field oxidation process is used to make a thick field oxide region 4 as the active area insulator, this field oxide region 4 Formed by deposition, lithography of silicon nitride and dioxide The composite layer is used as a leather curtain to define the active area, and then thermally radonized in an environment containing radon. The temperature is between 850 and 1050. (Di-radonized silicon is produced at a temperature of 4000-6000 Angstroms, and then the radon is removed with hot phosphoric acid. Silicon dioxide, using hydrofluoric acid to remove the radon silicon, and then forming a gold-oxygen half-field effect crystal on the above-mentioned P-type substrate through a process of conventional technology. Its structure includes a silicon dioxide layer 6 formed on the substrate 2 As the gate oxide layer, the silicon dioxide layer is generally formed by thermal oxidation, the process temperature is about 850 to 1000, and the thickness is about 50 to 200 Angstroms. Of course, the conventional technology can also form this gate oxide Layer 6, such as chemical vapor deposition (chemical vapor deposition), the first polycrystalline silicon layer 8 is deposited on the two radon silicon layer 6, the field radon layer 4 and the substrate 2, in an embodiment, this The first polycrystalline silicon layer 8 is formed by chemical vapor deposition (CVD) with a thickness of about 1500 to 3000 angstroms, followed by a wordline 10, a bitline 12, and a gate structure (gate Pole 8 (Please read the precautions on the back before filling in this page) -K 装 · Order 1- This paper is used for the Chinese National Standard (CNS> A4 size (210X297mm). The Central Bureau of Economic Affairs of the Ministry of Economic Affairs, Beigong Consumer Cooperatives printed seal A7 B7 V. Description of invention () and gate oxide layer 6) and Sidewall spacers 14 are made using previously known techniques and are not the focus of the present invention and therefore will not be described in detail. Secondly, in order to make electrical contact between the heavy crystal and the party's content, a dielectric layer 16 is used as an insulating layer It is formed on the above-mentioned closed-pole structure, field oxide layer 4 and substrate 2, and then a contact hole is formed in the dielectric layer 16 using lithography and etching processes. Referring to the third circle, after the fabrication of the metal oxide half field effect transistor is completed, a second polycrystalline silicon layer 18 is deposited with a thickness between 2000 angstroms and 3000 angstroms. The second polycrystalline silicon layer is deposited by low pressure chemical vapor deposition ( LPCVD) method using in-situ doped mixed gas of PH 3, SiH4 and N2 to form a polycrystalline silicon layer or depositing a polycrystalline silicon layer and then doping with impurities, followed by the second polycrystalline stone To define the photoresist circle on the evening layer, use the etching technique to etch the second polycrystalline silicon layer to form the bottom hail electrode of the capacitor. Next, before depositing the argonized silicon, a pretreatment process is performed to remove the naturally oxidized silicon oxide on the surface of the second polycrystalline silicon 18, and in a preferred embodiment, a cleaning process of hydrofluoric acid may be used. Refer to the fourth circle, inductively-coupled nitorgen plasma (ICNP) is used to process the heavy pole of the polycrystalline silicon substrate before the formation of the nitrided silicon dioxide / silica dioxide hail layer. The reaction gas is nitrogen. The coupled nitrogen heavy paddle can enter the surface of the second polycrystalline silicon 18 to prevent the native oxide growth and reduce the nucleation delay time of the nitride 20. In terms of better practical examples, the power of the plasma is to use the paper standard of China's Sleepy Family Standard (CNS) Α4 specification (210X297mm) (please read the precautions on the back and fill in this page) η 装 装Π Printed by the Ministry of Economic Affairs, Central Bureau of Precision Industry, Beigong Consumer Cooperative A7 B7 V. Description of the invention (): 250W »The flow rate of the atmosphere is 35 to 45 sccm, the best is 40 sccm, and the air-cylinder reconditioning force is 400 to 450 mtorr, the most The best is 420 mtorr, the processing time is 5 to 15 minutes boring. In addition, Ta205 can also be used as a bulk mediator before the above ICNP pretreatment to make the surface of the bottom electrode of the polycrystalline silicon contain nitrogen rich. Therefore, in the subsequent annealing treatment of Ta2Os, the bottom of the polycrystalline silicon The electrode is not easy to be oxidized, so it can ensure the equivalent thickness of the dielectric layer. The method of the present invention does not have the problem of hydrogen atom penetration and the process temperature is low about 300 eC. SiON. Referring to the fifth circle, after completing the ICNP processing step, the rapid deposition of silicon nitride 20 is performed. In the preferred embodiment, silicon nitride 20 is deposited by low pressure chemical vapor deposition to a thickness of approximately 70 to 140 angstroms Then, the inductive coupled nitrigen plasma can be used again to repair the defects on the surface of the silicon nitride 20. This step may or may not be implemented depending on the desired goal. Similarly, in the preferred embodiment, the power of the t slurry is 250W, the flow rate of nitrogen is 35 to 45 seem, the gas pressure is 400 to 450 mtorr, and the processing time is 5 to 15 minutes. Then, a silicon dioxide layer 22 is formed on the silicon nitride layer 20 by thermal oxidation. The preferred embodiment is formed in an oxygen-containing environment. The process temperature is between 800 and 950. It takes 25 to 35 minutes. The paper size uses the Chinese National Standard (CNS) Μ specification (210Χ297mm) (please read the note Ϋ on the back before filling this page) Order 3X6328 A7 Αν _____ B7 V. Description of invention ( ) As shown in the sixth circle, the third polycrystalline silicon layer 24 is formed by a low-pressure chemical vapor deposition (LPCVD) method using a mixed gas of PH 3, SiH 4, and in-situ doped (in-situ doped). After the crystalline silicon layer is doped with impurities to form the third polycrystalline silicon layer 24, the third polycrystalline silicon layer 24 will be deposited on the silicon dioxide 22 as the upper electrode of the capacitor, and then the third complex is etched by etching technology The crystalline silicon layer completes the fabrication of the capacitor. The present invention is described above with a preferred embodiment, and those skilled in the art should be able to make some minor changes without departing from the spirit of the present invention, and its patent protection scope More attention should be paid to the scope of attached patent applications and the like . Field may be (please note the item back and then fill read this page) Γ Order Ministry of Economic Affairs Bureau of the Central Di prospective male workers printed a consumer cooperative - paper quasi-engage in home country with a solid fitness Μ