4655 經濟部中央橾準局員工消費合作社印製 A7 B7 五、發明説明（） ㈠·技術領域 本發明是有關於積體電路之f金屬連線』（Metal Interconnection)和『金屬栓 柱』（Metal Plug )的製造方法；特別是關於利用化學氣相沉積法（Chemical Vapor Deposition ; CVD)形成之金屬來形成r金屬連線』和r金屬栓柱』之方法。 (二）.發明背景 當積體謙元件不斷縮小，進入次微米技術領域時，爲了提高積體離元件的 集積密度，連線技術（Interconnection)也跟著不斷縮小，微細的金屬線條越來越不 容易形成，同時，『接觸窗』（Contact Hole)和『介層孔』（Via Hole)的階梯覆 蓋問題（Step Coverage Problem)也愈趨嚴重。例如，由於光阻對金屬蝕刻選擇比 率太高，利用微影技術與電漿蝕刻技術（Lithography and Etching)來形成0.15微 米到0.35微米之間寬度的金屬線條是非常困難的。另一方面，金屬線條越來越細 時，由於金屬線條之厚g並沒有減少，因此，金屬線條的『厚度』對金屬線條的 『寬度』的比値越來越高（High Aspect Ratio)，造成相當陡峭的地形地勢（Severe Topography)，相當不利於後續薄膜沉積和微影餓刻製程。 爲了要解決金屬線條的F厚度』對金屬線條的『寬度』的比値越來越高（High Aspect Ratio)的問題，由日本的NEC半導體公司工程師在1995年的『VLSI SYMPOSIUM』之第27—28頁提出了一種利用化學氣相沉積法（Chemical Vapor Deposition ; CVD)形成之埋層金屬（Recessed Metal)來形成『金屬連線』和『金 屬栓柱』之方法，現在簡述其方法如下列。首先，矽半導體晶圓表面（Silicon Semiconductor Wafer )形成一層介電層（Dielectric )和一層硬保護罩（Hard • Mask)，所述『硬保護罩』是作爲蝕刻終止層之用途（Etch Stop)。 接著，利用微影技術形成第一個光阻圖案（First Photoresist Pattern)，再利用 電漿鈾刻技術蝕去一部份的所述Γ硬保護罩』和所述『介電層』，以在所述『介電 層』表面形成第一個淺凹溝（First Shallow Trench)。接著，再利用另外—層微影 光罩形成第二個光阻圖案（Second Photoresist Pattern)，所述『第二個光阻圖案』 覆蓋住一部份的所述f第一個淺凹溝』’而露出一部份的所述r第一個淺凹溝』。 由於所述『硬保護罩』之鈾刻速率比所述『介電層』小很多，所以，在微影製程有 對準偏差時（Misalignment)，所述『硬保護罩』可以當作蝕刻終止層（Etch Stop)以防止所述『硬保護罩』下方之所述p介電層』被飽刻掉。 然後，利用電漿蝕刻技術繼續蝕去露出之所述『第一個淺凹溝』’一直到露出 底層金屬層（Underlying Metal)，使所述『第一個淺凹溝』成爲『第二個深凹溝』 (Second Deep Trench)。接著，去除所述F第二個光阻圖案』和所述『硬保護 H』後，再利用化學氣相沉積法形成一層金屬層，所述金屬層塡滿所述『第一個淺 凹溝』和『第二個深凹溝』。 本紙張尺度適用中國國家榡準（CNS ) Μ规格（210X297公釐） --------^ I 裝 — N -. ii. - < (請先閱讀背面之注意事項再填寫本頁) „訂 .線 經濟部中央樣準局貝工消費合作杜印製 A7 B7 五、發明説明（） 利用電漿回蝕刻技術（Plasma Etchback)或化學機械式磨光技術（Chemical Mechanical Polishing ; CMP)去除所述『第一個淺凹溝』和『第二個深凹溝』以外 區域之所述金屬層，以在所述『第一個淺凹溝』內形成金屬連線，在所述『第二個 深凹溝』內貝！I形成【金屬栓柱】。 (三).發明的簡要說明 本發明的主要目的是提供一種積體電路之F金屬連線』（Metal Interconnection)和f金屬栓柱』（Metal Plug)的製造方法，特別是關於利用化學 氣相沉積法（Chemical Vapor Deposition ; CVD)形成之金屬來形成f金屬連線』 .和11金屬栓柱』之方法。 茲說明本發明之主要製程方法如下列。 首先，在矽半導體晶圓表面（Silicon Semiconductor Wafer)形成一層第一介 電層（First Dielectrc)。所述『矽半導體晶圓』包含有場氧化層、金氧半場效電晶 體或【電容器】和【電阻器】等電性元件，而所述F金氧半場效電晶體』並含有閘 氧化層（Gate Oxide)、聞極（Gate Electrode)與源極/汲極（Source/Drain)。所 述『第一介電層』則通常是利用低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition ; LPCVD)形成之攙雜二氧化矽層（Doped Silicon Dioxide)，其 反應氣體是矽甲烷（Silane ; SiH4)或四乙基矽酸鹽（TetraEthOxySilane ; TEOS)，其厚度介於3000到8000埃之間。通常，並利用化學機械式磨光技術 (Chemical Mechanical Polishing ; CMP)來平坦化戶斤述『第一介電層』。 接著，形成一層第二介電層（Second Dielectrc)，然後，利用微影技術形成 第一個光阻圖案（First Photoresist Pattern)，以所述F第一個光阻圖案』作爲蝕刻 保護罩，利用電漿蝕刻技術蝕去所述【第二介電層】和一部份厚度的所述【第一介 電層】，以在所述『第一介電層』表面形成第一個淺凹溝（First Shallow Trench)。然後，利用光阻浸蝕技術（Resist Erosion)，側向鈾去一部份的所述 F第一個光阻圖案』以露出一部份的所述【第二介電層】，再利用電漿餓刻技術蝕 去露出之所述【第二介電層】，所述電漿蝕刻終止於所述^第一介電層J!表面，蝕 刻結束後並去除所述f第一個光阻圖案』。 接著，利用微影技術形成第二個光阻圖案（Sec〇nd Photoresist Pattern)，所 述『第二個光阻圖案』覆蓋住一部份的所述『第一個淺凹溝』和一部份的所述【第 二介電層】，而露出一部份的所述『第一個淺凹溝』和一部份的所述【第二介電 層】。然後，以所述f第二個光阻圖案』和露出一部份之所述【第二介電層】作爲 蝕刻保護罩，利用電漿蝕刻技術蝕去露出之所述【第一介電層】，所述電漿蝕刻終 止於所述『第一介電層』底層之金靥層（Underlying Metal),使所述『第一個淺凹 溝』成爲『第一個深凹溝』（First Deep Trench)。然後，去除所述『第二個光阻 圖案』和所述【第二介電層】。此時，在所述【第一介電層】表面形成所述『第一 個淺凹溝』和《第一個深凹溝j。. 本紙張尺度逋用中國国家標準（CNS〉Μ规格（21'0Χ297公釐') (請先閲讀背面之注意事項再填寫本頁) -裝- ir 314655 A7 B7 五、發明説明（） 接著，利用化學氣相沉積法（Chemical Vapor Deposition ; CVD.)形成一層 金屬層，所述金屬層包含銅、鈦、鎢、鋁和氮化鈦（Titanium Nitride)等金屬，所 述金屬層並塡滿所述F第一個淺凹溝』和®第一個深凹溝』。最後，利用電漿回蝕 刻技術（Plasma Etchback )或化學機械式磨光技術（Chemical Mechanical Polishing ; CMP)去除所述『第一個淺凹溝』和f第一個深凹溝』以外區域之所述 金屬層，以在所述"第一個淺凹溝』內形成第一金屬連線（First Metal Intoconnection)，在所述『第一個深凹溝』內則形成第一金屬栓柱（FirstMeial Plug)。 形成一層第三介電層（ThirdDielectrc)第四介電層（FourthDielectrc)，重 複運用上述方法，可形成『第二個淺凹溝』和『第二個深凹溝』，並進而在所述 『第二個淺凹溝』內形成【第二金屬連線】，在所述『第二個深凹溝』內則形成 【第二金屬栓柱】，其中，所述【第二金屬連線】係透過所述『第一金屬栓柱』跟 所述【第一金屬連線】作電性接觸。 ' (四） .圖示的簡要說明 圖一至圖十一是本發明實施例之製程剖面示意圖（Process Cross Section)。 (五） ·發明的詳細說明 以下利用積體電路之雙層金屬連線技術（Double-Level Metal Interconnection)之『介層孔』（Via Hole)來說明本發明之方法，但本發明之方法 能應用到多層金屬連線技術積體電路.(Multi-Level Metal Interconnection)。 經濟部中央標準局員工消費合作社印裳 (請先閲讀背面之注意Ϋ項再填寫本頁) 首先，在電阻値約3.5 ohm-cm、晶格方向（100)的P型矽半導體晶圓20 (Silicon Semiconductor Wafer)表面形成場氧化層，所述『場氧化層』之厚度介於 3000埃到6000埃之間，作爲隔離電性元件之用。然後，在所述『P型矽半導體晶 圓20』上形成金氧半場效電晶體，所述『金氧半場效電晶體』含有閘氧化層（Gate Oxide)、閘極（Gate Electrode)與源極/汲極（Source/Drain)。同時，在所述 『場氧化層』上也形成複晶矽（Polysilicon)或複晶矽化物（Polycide)以作爲所述 『金氧半場效電晶體』之局部連線（Local Interconnection)。所述『場氧化層』、 所述『金氧半場效電晶體』和『局部連線』均未顯示.在圖一。 參考圖—。接著，形成—層絕緣層22 (Insulator)，並在所述『絕緣層22』 上形成第一金屬連線24 (First Metal Interconnection)。所述『絕緣層22』通常是 利用化學氣相沉積法（Chemical Vapor Deposition ; CVD)形成之硼磷玻璃—膜 (BoroPhosphoSilicate Glass ; BPSG )或隣玻璃薄膜（PhosphoSilicate Glass ; PSG)，其厚度介於3000到8000埃之間，完成所述『絕緣層22』之沈積後，利 用傳統熱流整技術（Thermal Flow)使所述『絕緣層22』平坦（Planarized),所述 熱流整溫度介於850°C到950°C之間，所述熱流整時間介於1〇分鐘到40分鐘之 本纸張.尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） S14655 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） 問。也可以利用習知的化學機械式磨光技術（Chemical Mechanical Polishing ; CMP)來平坦化所述『絕緣層22』。接著，利用微影技術與電漿蝕刻技術蝕去所 述『絕緣層22』，以形成『接觸窗』（Contact Hole)，所述『接觸窗』之底部是 所述P型矽半導體晶圓20之『源極/汲極』或所述『局部連線』，後續之【金屬 栓柱】將透過所述『接觸窗』跟所述『源極/汲極』或所述『局部連線』作電性接 觸。所述『第一金屬連線24』是由鈦（Titanium)、氮化鈦（Nitride Titanium)與 鋁合金（Aluminum Alloy)構成，其中，鈦金屬位於氮化鈦之下方，並跟所述『金 氧半場效電晶體』之源極/汲極區域作電性接觸。 接著，形成一層第一介電層26 (First Dielectrc)第二介電層28 (Second Dielectrc)，其中，有利用習知的化學機械式磨光技術（Chemical Mechanical Polishing ; CMP)來平坦化所述『第一介電層26』，如圖二所示。然後，利用微 影技術形成第一個光阻圖案30 (First Photoresist Pattern)，如圖三所示。所述『第 一介電層26』通常是利用電漿增強式化學氣相沉積法（Plasma Enhanced Chemical Vapor Deposition ; PECVD)形成之二氧化矽（Silicon Dioxide)，其沉積溫度介於 300°C到400°C之間，其厚度介於3000到6000埃之間。所述『第二介電層28』 則通常是利用『電漿增強式化學氣相沉積法』形成之氮化砂（Silicon Nitride)，其 沉積溫度介於300°C到400°C之間，其厚度介於500到2000埃之間；所述『第 二介電層28』也可以是利用『電漿增強式化學氣相沉積法』形成之非晶矽 (Amorphos Silicon)。 然後，以所述『第一個光阻圖案30』作爲鈾刻保護罩（EtchMask)，利用 電漿蝕刻技術單向性的蝕去所述『第二介電層28』和一部份厚度的所述『第一介 電層26』，以在所述『第一介電層26』表面形成第一個淺凹溝31 (First Shallow Trench)，如圖四所示。對所述『第二介電層28』和所述『第一介電層26』之 『單向性的蝕刻』，可以利用磁場增強式活性離子式電漿蝕刻技術（Magnetic Enhanced Reactive Ion Etching ; MERIE)或電子迴旋共振電漿飽刻技術（Electron Cyclotron Resonance ; ECR)或傳統的活性離子式電漿触刻技術（Reactive Ion Etching ; RIE)，在次微米半導體技術領域，通常是使用8磁場增強式活性離子式 電漿蝕刻技術』，其電漿反應氣體一般是CF4、CHF3和Ar等氣體。 然後，利用光阻浸飽技術（Resist Erosion) ’將所述『第一個光阻圖案30』 浸泡於氧氣電獎中（OxygenPlasma)，以側向触去一部份的所述『第一個光阻圖案 30』，以露出一部份的所述『第二介電層28』，再利用電漿蝕刻技術單向性的蝕 去露出之所述『第二介電層28』，所述電漿蝕刻終止於所述『第一介電層26^表 而，如圖五所示，蝕刻結束後並去除所述『第一個光阻圖案30』，如圖六所示。 對所述『第二介電層28』之『單向性的蝕刻』，是利用『磁場增強式活性離子式 屯漿蝕刻技術』，其電漿反應氣體是CF4、CHF3和Ar等氣體。 接著，利用微影技術形成第二個光阻圖案34 (Second Photoresist Pattern) ’ 所述『第二個光阻圖案34』覆蓋住一部份的所述『第一個淺凹溝31』和一部份的 所述『第二介電層28』，而露出一部份的所述F第一個淺凹溝31』和一部份的所 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公釐） (請先閲讀背面之注意Ϋ項再填寫本頁) -裝· 、11 A7 B7 五、發明説明（） 述『第二介電層28』’如圖七所示。然後，以所述『第二個光阻圖案』和露出一 部份之所述『第二介電層28』作爲蝕刻保護罩，利用電漿蝕刻技術單向性的蝕去 露出之所述『第一介電層26』，所述電獎触刻終止於所述『第一介電層26』底層 之所述『第一金屬連線以』，使所述p第一個淺凹溝31』成爲『第一個深凹溝 35』（First Deep Trench)，如圖八所示。所述f第一個深凹溝35』呈『階梯型』 (Ladder Shape) ’提供了較理想的階梯覆蓋能力（step Coverage)。然後，去除 所述『第二個光阻圖案34』和所述【第二介電層】，如圖九所示，此時，在所述 F第一介電層20』表面形成所述f第一個淺凹溝31』和『第一個深凹溝35』。 對露出之所述『第二介電層28』之『單向性的蝕刻』，也是利用r磁場增強式活 性離子式電漿蝕刻技術』’其電漿反應氣體是CF4、CHF3和Ar等氣體。 參考圖十和圖十一。接著，利用化學氣相沉積法（Chemical Vapor Deposition ; CVD)形成一層金屬層38，所述『金屬層38』包含銅、鈦、鎢、銘 或氮化鈦（Titanium Nitride)等金屬，所述『金屬層38』並填滿所述f第一個淺凹 溝31』和『第一個深凹溝35』’如圖十所示。最後，利用電漿回細刻技術 (Plasma Etchback)或化學機械式磨光技術（chemical Mechanical Polishing ; CMP)去除所述f第一個淺凹溝31』和p第一個深凹溝35』以外區域之所述f金 屬層38』’以在所述『第一個淺凹溝31』內形成第二金屬連線38A (Second Metal Interconnection) ’在所述『第一個深凹溝35』內則形成第二金屬栓柱38B (Second Metal Plug)，如圖十一所示，其中，所述『第二金屬連線38A』係透過 所述F第二金屬栓柱38B』跟所述P第一金屬連線24』作電性接觸。 完成圖十一的結構後，可以再重複利用上述方法形成上一階層的『金屬連 線』和『金屬栓柱』’亦即’本發明之製程方法能應用到多層金屬連線技術積體電 路（Multi-Level Metal Interconnection)。 以上係以最佳實施例來闡述本發明，而非限制本發明，並且，熟知半導體技藝 之人士皆能明瞭，適當而作些微的改變及調整，仍將不失本發明之要義所在，亦不 脫離本發明之精神和範圍。 (請先Μ讀背面之注意事項再填寫本頁) -裝.4655 Printed A7 B7 by the Employees ’Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs 5. Description of the invention () (1) Technical field The present invention relates to the f metal connection of integrated circuits” (Metal Interconnection) and “metal studs” (Metal Plug) manufacturing method; in particular, the use of chemical vapor deposition (Chemical Vapor Deposition; CVD) metal to form r metal connection "and r metal plug" method. (2). Background of the invention When the integrated semiconductor components continue to shrink and enter the sub-micron technology field, in order to increase the accumulation density of integrated components away from the components, the connection technology (Interconnection) has also continued to shrink, and the fine metal lines are becoming less and less It is easy to form, and at the same time, the step coverage problem of "Contact Hole" and "Via Hole" becomes more and more serious. For example, due to the high selection ratio of photoresist to metal etching, it is very difficult to form metal lines with a width between 0.15 micrometers and 0.35 micrometers using lithography and plasma etching (Lithography and Etching). On the other hand, when the metal lines are getting thinner, the thickness g of the metal lines has not decreased. Therefore, the ratio of the "thickness" of the metal lines to the "width" of the metal lines is getting higher (High Aspect Ratio), Severe Topography is quite unfavorable, which is not conducive to the subsequent thin film deposition and lithography process. In order to solve the problem that the F thickness of metal lines' ratio to the "width" of metal lines is getting higher (High Aspect Ratio), engineers from Japan's NEC Semiconductor Co., Ltd. No. 27 of 1995 "VLSI SYMPOSIUM" On page 28, a method for forming a "metal connection" and a "metal stud" using a buried metal formed by chemical vapor deposition (CVD) is described. . First, a dielectric layer and a hard mask are formed on the surface of the silicon semiconductor wafer. The "hard mask" is used as an etch stop layer (Etch Stop). Next, the first photoresist pattern (First Photoresist Pattern) is formed by using lithography technology, and then a part of the Γ hard protective cover and the “dielectric layer” are etched away by plasma uranium etching technology, in order to A first shallow trench (First Shallow Trench) is formed on the surface of the "dielectric layer". Then, another layer of lithography mask is used to form a second photoresist pattern (Second Photoresist Pattern), and the "second photoresist pattern" covers a part of the f first shallow concave groove. 'And a part of the first shallow groove of r was exposed.' Because the uranium engraving rate of the "hard protective cover" is much lower than that of the "dielectric layer", the "hard protective cover" can be used as an etching stop when there is misalignment in the lithography process (Misalignment) Etch Stop layer to prevent the p-dielectric layer below the "hard protective cover" from being burnt out. Then, use plasma etching technology to continue to etch the "first shallow groove" exposed until the underlying metal layer (Underlying Metal) is exposed, so that the "first shallow groove" becomes the "second "Second Deep Trench". Next, after removing the second photoresist pattern of F "and the" hard protection H ", a metal layer is formed by chemical vapor deposition, and the metal layer is filled with the" first shallow groove "And" the second deep groove ". This paper scale is applicable to the Chinese National Standard (CNS) Μ specification (210X297mm) -------- ^ I installed — N-. Ii.-≪ (Please read the precautions on the back before filling this page ) "Order. A7 B7 of the Ministry of Economic Affairs, Central Bureau of Samples and Consumer Cooperation, Du Printed 5. V. Description of invention () Use of plasma etching technology (Plasma Etchback) or chemical mechanical polishing technology (Chemical Mechanical Polishing; CMP) Remove the metal layer in areas other than the "first shallow concave groove" and "second deep concave groove" to form a metal connection in the "first shallow concave groove", in the " The second deep groove is "Inner shell! I form a [metal stud]. (3). Brief description of the invention The main purpose of the present invention is to provide an F-metal connection of an integrated circuit" (Metal Interconnection) and f-metal The manufacturing method of "Plug" (Metal Plug), in particular, the method of using metal formed by chemical vapor deposition (Chemical Vapor Deposition; CVD) to form f-metal connection ". And 11 metal plug" method. The main process methods of the invention are as follows. First, in the silicon half A first dielectric layer (First Dielectrc) is formed on the surface of the bulk semiconductor wafer (Silicon Semiconductor Wafer). The "silicon semiconductor wafer" includes a field oxide layer, a metal oxide semi-field effect transistor or [capacitor] and [resistor] Isoelectric elements, and the F metal oxide half field effect transistor "also contains a gate oxide layer (Gate Oxide), Wen electrode (Gate Electrode) and source / drain (Source / Drain). The" first media The "electric layer" is usually a doped silicon dioxide layer (Doped Silicon Dioxide) formed by Low Pressure Chemical Vapor Deposition (LPCVD), and the reaction gas is silicon methane (Silane; SiH4) or tetraethyl Silicate (TetraEthOxySilane; TEOS), whose thickness is between 3000 and 8000 Angstroms. Usually, chemical mechanical polishing (Chemical Mechanical Polishing; CMP) is used to flatten the user's "first dielectric layer" Then, a second dielectric layer (Second Dielectrc) is formed, and then, the first photoresist pattern is formed by using lithography technology, and the first photoresist pattern F is used as an etch Engrave the protective cover, and use plasma etching technology to etch away the [second dielectric layer] and a part of the thickness of the [first dielectric layer], so as to form a A shallow groove (First Shallow Trench). Then, using a resist etching technique (Resist Erosion), a part of the first resist pattern of F is removed laterally to the uranium to expose a part of the [second dielectric layer], and then the plasma is used Etching away the exposed [second dielectric layer], the plasma etching ends at the surface of the first dielectric layer J! After the etching is completed, the first photoresist pattern is removed 』. Next, a second photoresist pattern (Second Photoresist Pattern) is formed using photolithography technology, and the "second photoresist pattern" covers a part of the "first shallow concave groove" and a part Part of the [second dielectric layer], and a part of the "first shallow groove" and a part of the [second dielectric layer] are exposed. Then, using the f second photoresist pattern "and the exposed part of the [second dielectric layer] as an etching protection cover, the plasma exposed etching technique is used to etch the exposed [first dielectric layer] ], The plasma etching ends at the bottom metal layer (Underlying Metal) of the "first dielectric layer", making the "first shallow groove" the "first deep groove" (First Deep Trench). Then, the "second photoresist pattern" and the [second dielectric layer] are removed. At this time, the "first shallow concave groove" and the "first deep concave groove j" are formed on the surface of the [first dielectric layer]. . This paper uses the Chinese National Standard (CNS> M Specification (21'0Χ297mm ') (please read the precautions on the back before filling in this page) -installed- ir 314655 A7 B7 5. Description of invention () Next, Using chemical vapor deposition (Chemical Vapor Deposition; CVD.) To form a layer of metal, the metal layer contains copper, titanium, tungsten, aluminum and titanium nitride (Titanium Nitride) and other metals, the metal layer is not full Describe the first shallow concave trench F and the first deep concave trench. Finally, use plasma etch back technology (Plasma Etchback) or chemical mechanical polishing technology (Chemical Mechanical Polishing; CMP) to remove the A shallow concave trench "and f the first deep concave trench" outside the metal layer to form a first metal connection (First Metal Intoconnection) in the "first shallow concave trench", in The first metal plug (FirstMeial Plug) is formed in the "first deep groove". A third dielectric layer (ThirdDielectrc) and a fourth dielectric layer (FourthDielectrc) are formed. The second shallow concave ditch "and" the first "Two deep concave grooves", and then a "second metal connection" is formed in the "second shallow concave groove", and a "second metal bolt" is formed in the "second deep concave groove" ], Where the [second metal connection] is to make electrical contact with the [first metal connection] through the "first metal stud". '(四). A brief illustration of the illustration Figures 1 to 11 are schematic diagrams of the process cross section (Process Cross Section) according to an embodiment of the present invention. (5) Detailed description of the invention The following uses the "interlayer" of the double-level metal interconnection technology of the integrated circuit (Double-Level Metal Interconnection) (Via Hole) to illustrate the method of the present invention, but the method of the present invention can be applied to multi-level metal interconnection technology integrated circuit. (Multi-Level Metal Interconnection.) Read the note Ϋ on the back before filling in this page) First, a field oxide layer is formed on the surface of a P-type silicon semiconductor wafer 20 (Silicon Semiconductor Wafer) with a resistance value of about 3.5 ohm-cm and a lattice direction (100). Thickness of "field oxide layer" Between 3000 Angstroms and 6000 Angstroms, it is used to isolate electrical components. Then, a metal-oxide half-field transistor is formed on the "P-type silicon semiconductor wafer 20", and the "metal-oxide half-field transistor" contains Gate Oxide, Gate Electrode and Source / Drain. At the same time, polysilicon (Polysilicon) or polysilicon (Polycide) is also formed on the "field oxide layer" as a local interconnection of the "gold oxide half field effect transistor". The "field oxide layer", the "gold oxide half field effect transistor" and the "local connection" are not shown. In Figure 1. Reference figure-. Next, an insulating layer 22 (Insulator) is formed, and a first metal interconnection 24 (First Metal Interconnection) is formed on the "insulating layer 22". The "insulating layer 22" is usually a boron phosphorous glass film (BoroPhosphoSilicate Glass; BPSG) or an adjacent glass film (PhosphoSilicate Glass; PSG) formed by chemical vapor deposition (CVD), and its thickness is between Between 3000 and 8000 angstroms, after the deposition of the "insulating layer 22" is completed, the "insulating layer 22" is flattened (Planarized) using traditional thermal flow technology (Thermal Flow), and the thermal flow temperature is between 850 ° Between C and 950 ° C, the heat flow time is between 10 minutes and 40 minutes on the original paper. The standard applies to China National Standard (CNS) Α4 specification (210X297 mm) S14655 Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative Print A7 B7 V. Description of invention () Question. The "insulating layer 22" can also be planarized using conventional chemical mechanical polishing (CMP). Next, the "insulating layer 22" is etched away by using lithography technology and plasma etching technology to form a "contact hole". The bottom of the "contact window" is the P-type silicon semiconductor wafer 20 "Source / drain" or the "local connection", the subsequent "metal stud" will follow the "source / drain" or the "local connection" through the "contact window" Make electrical contact. The "first metal connection 24" is composed of titanium (Titanium), titanium nitride (Nitride Titanium) and aluminum alloy (Aluminum Alloy), wherein the titanium metal is located below the titanium nitride, and with the "gold The source / drain regions of the oxygen half field effect transistor are in electrical contact. Next, a first dielectric layer 26 (First Dielectrc) and a second dielectric layer 28 (Second Dielectrc) are formed, in which a conventional chemical mechanical polishing technique (Chemical Mechanical Polishing; CMP) is used to planarize the "The first dielectric layer 26", as shown in Figure 2. Then, the first photoresist pattern 30 (First Photoresist Pattern) is formed using lithography technology, as shown in FIG. 3. The "first dielectric layer 26" is usually a silicon dioxide (Plasma Enhanced Chemical Vapor Deposition; PECVD) formed silicon dioxide (Silicon Dioxide), the deposition temperature is between 300 ° C to Between 400 ° C, its thickness is between 3000 and 6000 angstroms. The "second dielectric layer 28" is usually silicon nitride sand (Silicon Nitride) formed by the "plasma enhanced chemical vapor deposition method", and its deposition temperature is between 300 ° C and 400 ° C. The thickness is between 500 and 2000 angstroms; the "second dielectric layer 28" may also be an amorphous silicon (Amorphos Silicon) formed by the "plasma enhanced chemical vapor deposition method". Then, using the "first photoresist pattern 30" as a uranium etching protective cover (EtchMask), using plasma etching technology to unidirectionally etch the "second dielectric layer 28" and a part of the thickness of The "first dielectric layer 26" is to form a first shallow trench 31 (First Shallow Trench) on the surface of the "first dielectric layer 26", as shown in FIG. For the "second dielectric layer 28" and the "first dielectric layer 26" "unidirectional etching", magnetic field enhanced active ion plasma etching technology (Magnetic Enhanced Reactive Ion Etching; MERIE) or Electron Cyclotron Resonance (ECR) or traditional reactive ion plasma etching (Reactive Ion Etching; RIE). In the field of submicron semiconductor technology, 8 magnetic fields are usually used to enhance Type active ion plasma etching technology, the plasma reaction gas is generally CF4, CHF3 and Ar gas. Then, immerse the "first photoresist pattern 30" in the Oxygen Award (OxygenPlasma) using the resist erosion technique (Resist Erosion) to touch a part of the "first Photoresist pattern 30 ”to expose a part of the“ second dielectric layer 28 ”, and then use plasma etching technology to unidirectionally etch the exposed“ second dielectric layer 28 ”, the Plasma etching ends at the "first dielectric layer 26" surface, as shown in FIG. 5, and after the etching is completed, the "first photoresist pattern 30" is removed, as shown in FIG. 6. The "unidirectional etching" of the "second dielectric layer 28" uses "magnetic field enhanced active ion type plasma etching technology", and the plasma reaction gases are gases such as CF4, CHF3 and Ar. Next, a second photoresist pattern 34 (Second Photoresist Pattern) is formed by using lithography technology. The "second photoresist pattern 34" covers a part of the "first shallow groove 31" and a Part of the "second dielectric layer 28", and a part of the F first shallow concave groove 31 "and a part of the original paper size are applicable to the Chinese National Standard (CNS> A4 specifications ( 210X297mm) (please read the note Ϋ on the back before filling in this page)-Installation ·, 11 A7 B7 5. Description of the invention () The "second dielectric layer 28" 'is shown in Figure 7. Then, The "second photoresist pattern" and part of the "second dielectric layer 28" exposed as an etching protection cover, using plasma etching technology to unidirectionally etch the exposed "first dielectric" The electric layer 26 ", the electric award contact is terminated at the" first metal connection "of the bottom layer of the" first dielectric layer 26 ", so that the first shallow recess 31 of the p becomes" First Deep Trench 35 "(First Deep Trench), as shown in Figure 8. The f First Deep Trench 35 is presented as a" ladder shape " The ideal step coverage (step Coverage). Then, remove the "second photoresist pattern 34" and the [second dielectric layer], as shown in Figure 9, at this time, in the F On the surface of the first dielectric layer 20, the f first shallow concave groove 31 and the first deep concave groove 35 are formed. For the exposed "second dielectric layer 28", "unidirectional "Etching" is also the use of r magnetic field enhanced active ion plasma etching technology "" The plasma reaction gas is CF4, CHF3 and Ar and other gases. Refer to Figures 10 and 11. Then, use the chemical vapor deposition method (Chemical Vapor Deposition; CVD) to form a metal layer 38, the "metal layer 38" contains copper, titanium, tungsten, indium or titanium nitride (Titanium Nitride) and other metals, the "metal layer 38" and fill the f The first shallow concave groove 31 "and the" first deep concave groove 35 "are shown in Figure 10. Finally, the use of plasma back fine etching technology (Plasma Etchback) or chemical mechanical polishing technology (chemical Mechanical Polishing; CMP) to remove the regions other than the first shallow recess 31 and the first deep recess 35 f metal layer 38 "to form a second metal interconnection 38A (Second Metal Interconnection) in the" first shallow concave groove 31 "to form a second in the" first deep concave groove 35 " A metal plug 38B (Second Metal Plug), as shown in FIG. 11, wherein the "second metal connection 38A" is connected to the P first metal via the F second metal plug 38B " 24 ”Make electrical contact. After completing the structure of FIG. 11, the above method can be reused to form the "metal connection" and "metal stud" of the upper level. That is, the manufacturing method of the present invention can be applied to a multi-layer metal connection technology integrated circuit (Multi-Level Metal Interconnection). The above is a description of the present invention with the preferred embodiments, rather than limiting the present invention, and anyone skilled in semiconductor technology can understand that appropriate and slight changes and adjustments will still not lose the essence of the present invention, nor Departs from the spirit and scope of the present invention. (Please read the precautions on the back before filling this page)-Install.
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