TW312042B - Multi-level high density mask read only memory - Google Patents

Abstract

A nonvolatile memory device comprises of: (1) multiple memory cells, which includes one memory transistor which consist of one source/drain diffusion region, one channel region for separating source/drain diffusion region, and one gate oxide, one gate in sequence located on the channel region; (2) in which each memory transistor characteristic is determined by one selected among at least four threshold voltages, and different memory transistor has different threshold voltage; (3) in which memory transistor array consists of first-type memory transistor, whose gate is formed by first material with first function, the first material determines threshold voltage of the first-type transistor; and second-type memory transistor, whose gate is formed by second material with second function, the second material determines threshold voltage of the second-type memory transistor.

Description

3120 線 WF.DOC / 002 Μ 3120 網 WF.DOC / 002 Μ Printed by the Consumer Standardization Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Β5. Description of the invention (/) The present invention relates to the arrangement of memory transistors for data storage, and it is special It is about a non-volatile memory, such as read-only memory (ROM). Modern memory design is limited by semiconductor process technology, and to reduce the size of memory devices requires more improved process technology. The conventional read-only memory (ROM) is composed of an array of field effect transistors. Each memory cell includes a single field effect element; and each field effect transistor is formed to provide transistor characteristics. One of the two predetermined values, the selective transistor characteristic is, for example, the threshold voltage of the transistor. The implantation of impurities into the channel region of the transistor will make the transistor have a lower starting voltage, and the transistor can be opened by the voltage Vcc applied to the gate; and the transistor formed without implantation of impurities into the channel region has The higher the starting voltage, the transistor will not be opened by the voltage Vcc applied to the gate. Binary data can be stored in the memory by selectively implanting impurities into the channel area of the transistor; the channel area of the transistor has a logical "〇" that can store the impurities and the channel If no impurity is planted in the area, the logical "1" is stored. The size design of memory transistors currently implemented is limited by process technology, such as programmable read-only memory, which selectively implants impurities into the channel area of the transistor defined by the implantation mask In terms of the design size of 0.5, the process of aligning the implantation screen is not only time-consuming and error-prone, but also increases the manufacturing cost of the read-only memory, and the size of the product obtained is not originally designed. Component design considerations will also limit the extent to which conventional read-only memory can increase the amount of stored data; for example, conventional read-only memory connects the source / drain diffusion of a row of transistors with an embedded N + type line Area, this 〆- · '4' C reading first read the precautions on the back%, fill out this page) -installation- binding paper size is applicable to China National Standard (CNS) A4 specification (2 丨 OX 2W mm) 0294TWF .DOC / 002 A7 B7 __ 5. Description of the invention (>) The N + type wires used for connection become smaller and smaller as the design size decreases, so that the resistance of the N + type wires increases inevitably because of the higher concentration When the impurities are implanted to form the N + type line, it will be accompanied by diffusion of impurities into the channel area and the adjacent element area; when the resistance value of the buried N + type line increases, the resistance capacitance time constant (re si stance-capacitor time constant) increase 'makes it more time to read the data in the read-only memory. To increase the density of read-only memory storage data, many difficulties must be overcome. One of the methods proposed to improve the data storage density of _memory is to store more than two bits of data in each storage unit; this method It has been achieved by forming a transistor with one of more than three sets of predetermined values. Through transistors with different characteristics, multi-bit data can be stored in a single memory unit; although compared to the first As far as read-only memory is concerned, multi-bit read-only memory must provide a complicated circuit to read data, but in theory, by storing multi-bit data in a single memory unit, the read-only memory can be improved. Storage density. However, the storage strategy of this multi-bit read-only memory encountered many difficulties in the actual implementation of forming a multi-bit read-only memory with predetermined programmable properties to accurately write or read specific data of. An example of more than one embodiment of the memory has been proposed by Stark in US Patent No. 4,287,57. In this patent, the channel width of each memory transistor is a programmable characteristic of the memory, which changes The channel width will change the impedance or conductivity of the transistor. It can be known by applying a reference voltage to the gate of the transistor and then measuring the potential difference between the transistors, so making different channel widths can compare memory transistors. With ~ or more reference transistors, the '5 ϋ wave scale ^ use the Chinese National Standard (CNS> Μ specifications (--〆 ---- C please read the notes on the back-Μ' to fill in this page) .Installed. * 1Τ Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 3l20M WF.DOC / 002 A7 Printed by the Ministry of Economic Affairs, Central Standard Beige Consumer Cooperatives ------ B7__ V. Invention description ($) Potential difference to complete .Transistors with different channel widths can be formed by selectively forming gates of different widths on the active area on the substrate, and then forming source / drain diffusion areas that are automatically aligned to the gate to complete the different channel widths. Transistor made h. However 'this The design faces many difficulties; designing different channel widths to store data 'must produce transistors of insignificant size, so sufficient space is needed to accommodate a transistor with the largest channel width at each memory location, to A regular transistor arrangement is formed. Therefore, as mentioned above, the smallest size element will not be suitable for this method, and the read-only memory made according to the Stark patent wastes a lot of space. The difficulty in the production of the memory transistor is that the memory transistor is prone to errors on the cover screen (such as errors in the focal length), so that the width of the channel formation process will have obvious errors, so it must have sufficient tolerance In order to allow such errors; providing these tolerances limits the suitability of Stark's design to reduce the size of the device. The second implementation of multi-bit memory is U.S. Patent No. 5,386,281 by Takizawa et al. It is proposed that it is mainly to form gate oxide layers with different thicknesses on the channel region of the memory transistor to be formed, and then Selectively form a transistor on it; thereby, the thickness of the gate oxide layer of the transistor can be uniform, or the thickness of the gate electrode on one transistor channel area is half 160A and the other half is 320A. According to the patent proposed by Takizawa et al. , Can be implanted in four different degrees of impurities, namely: undoped; implanted through a gate oxide layer with a uniform thickness of 320A; implanted through a separate gate oxide layer, of which half of the oxide layer thickness is 320A, the thickness of the other half of the oxide layer is about 160A. Impurity implantation through a thicker oxide layer can reduce the implantation rate to the standard of the "Shenzhen Pass 6" (CNS) A4 specification (210X 297mm>

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Binding line 0294TWF.DOC / 002 A7 0294TWF.DOC / 002 A7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs -----------------———— V. Description of the invention (Shi) The concentration of impurities in the road area, so the implantation of the four types of impurities can be made into the channel area with the four types of concentration of impurities in the body. The channel regions with different impurity concentrations can be made with transistors with different starting voltages; the starting voltage can be detected by applying different gate voltages to the memory, which can be detected when the transistor is turned on To. However, the implementation of Takizawa's read-only memory also has many difficulties. The most important thing is to use the accurate mask automatic alignment process to form Takizawa's read-only memory, and the accurate mask automatic alignment process needs to be implemented. The two-layer structure only reads the channel area of the memory, and the size of this structure is half of ^^, so the accuracy of the automatic alignment of the mask is stricter than the process of making the memory transistor. If the memory is manufactured based on this design principle, it would be infeasible to produce a channel oxide layer mask with precise alignment to the separation as mentioned in the Takizawa patent. Therefore, Takizawa read-only memory based on this principle does not make full use of the advantages of all small-sized components. In view of this, the present invention proposes a multi-bit read-only memory element that is easier to mass-produce. The element is non-volatile and each memory element includes multiple memory cells, and each memory cell includes a memory, which has A source / drain diffusion region, a channel region separating the source / drain diffusion region, and a gate oxide layer and gate electrode covering the channel region. The nature of each memory is defined by the starting voltage, which is selected from one of at least three predetermined values, and different transistors have different starting voltages. The memory array includes a first type of memory, which includes a gate electrode composed of a first material with a first function, and the first material portion determines the starting voltage of the first transistor; and the second '7' ϋ The Zhang scale is applicable to the Chinese National Standard (CNS) Λ4 specification (2 丨 0X297mm) IU --------- installed L-^ --- set ----- line. C please read the back first Note to fill in this page} 0294TWF.DOC / 002 A7 0294TWF.DOC / 002 A7 Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs / B7 V. Invention description (夂) type memory, which contains the second function The gate electrode composed of the second material, and the second material part determines the starting voltage of the second transistor. Another feature of the present invention is to provide a non-volatile memory element including a plurality of memory cells, each memory cell includes a memory transistor, the memory transistor includes a source / drain diffusion region, and a separate source / drain The channel area of the diffusion area includes a gate oxide layer and a gate electrode covering the channel area. The nature of each memory transistor is defined by one selected from at least four starting voltage values. Different transistors have a different starting voltage value. The memory array includes a first-type memory, which includes a gate electrode composed of a first material having a first function, and the first material portion determines the starting voltage of the first transistor; and the second-type memory, It includes a gate electrode composed of a second material with a second function, and the second material portion determines the starting voltage of the second transistor. In addition, the array includes a third memory transistor with a first gate oxide thickness and a fourth memory transistor with a second gate oxide thickness. Another feature of the present invention is to provide a first column structure including a plurality of first-type transistors, each of which includes a first source / drain diffusion region and a first gate Electrodes; and a second column structure containing a plurality of second-type transistors, each second transistor includes a second source / drain diffusion region, and a second gate. The first gate of the first transistor and the second gate of the second transistor further comprise a continuous wire, wherein one of the first gate contains N-type polycrystalline silicon and the adjacent second transistor The second gate contains P-type polycrystalline silicon; at least one of the first transistors contains a gate oxide layer with a second thickness. In order to make the above and other objects, features, and advantages of the present invention clearer I. ---- ^ ----- ^ ------- ΪΤ ------ m Note on the back Η 'fill in this page) This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specifications (210Χ 297 mm) S12042 94TWF.DOC / 002 A7 B7 5. Description of the invention (cold) It is easy to understand, especially below A preferred embodiment, in conjunction with the attached drawings, will be described in detail as follows: Brief description of the drawings: FIG. 1 is a partial cross-sectional schematic diagram of a mask-type read-only memory transistor according to the present invention. Fig. 2 is another schematic sectional view of a mask-type read-only memory transistor according to the present invention. Figures 3 to 12 are schematic cross-sectional views of parts of a mask-based read-only memory manufactured according to the present invention. Embodiments Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy One of the features of the present invention is to provide a screen-type read-only memory transistor whose data is encoded by selectively programming the starting voltage of each transistor in the array , Whose size is one of three or more than three predetermined values, preferably four different starting voltages for each transistor in the array to select, so that at least 2 bits of data can be Stored in each memory unit. Multi-bit data can be stored in different transistors, for example, gate electrodes with different starting voltages can be selectively formed by materials with different properties; another technique, such as changing the thickness of the gate oxide layer of the imperfect transistor, It is possible to change the placement of the starting voltage, and other techniques that combine alternative technologies to adjust the starting voltage can also be applied. According to a preferred embodiment of the present invention, a transistor is provided, the gate electrode material is selected from one of two materials with different functional properties, and the thickness of the gate oxide layer is selected from one of the two thicknesses; Combining two kinds of gate electrode materials and two kinds of gate electrode oxygen layer thickness I, the recorder can selectively provide one of four different starting voltages, which are used to apply Chinese national standards (CNs i ^ Grid (210 X 297 mm) A7 B7 0294TWF.DOC / 002 5. Store the data in the description of invention (Q). For example, the first and highest starting voltage values can store two-bit data, 〇〇, ', Second, the lower starting voltage value can store two-bit data "01" 'The third starting voltage can store two-bit data,】 〇 ,, and the lowest starting voltage value can store two-bit data " ιι ". According to a preferred embodiment of the present invention, the data of the memory is programmed by selecting the starting voltage of the transistor; and selecting the starting voltage of the memory can, for example, select the material properties used to form the gate electrode. Or change the impurity concentration in the channel area Or change the thickness of the gate oxide layer or change the fixed charge in the gate oxide layer, or other well-known methods; however, many of these methods are not feasible in programmed memory. It is more feasible to Different materials form gate electrodes of transistors to produce transistors with different starting voltages; however, there will be more difficulties and expense to form such a memory array. Unless the multi-bit read-only memory is as it is now The single-bit read-only memory used is easy to program, otherwise the multi-bit read-only memory will not be commercially viable. The following will describe a preferred embodiment according to the present invention, which provides 1S [Bab or P _ 型 龙 复 _ crystalline silicon to form transistors has a starting voltage, these memory transistors can be mass-produced inexpensively, the method of use is as follows: The preferred embodiment uses two different The gate electrodes of transistors composed of functional materials (such as N-type and p-type polycrystalline silicon), connected to other programmed layouts, have defined at least three different starting voltages. Some roots In the embodiments of the present invention, both P-type polycrystalline silicon and N-type polycrystalline sand are used as gate electrode materials, which have different functional properties, so transistors with different starting voltages can be fabricated; gates of transistors The electrode can be selected p -----10 The paper size is suitable for China ^^ (CNS) A4 specification-'s ................. „^ L-- 1 Please read the precautions on the back first and fill out this page) The line of the Ministry of Economic Affairs, Central Standard Falcon Bureau Employee Consumer Cooperative printed five troubles Wh, N. G Λ —- -7J, f 7! If · k \ h No. 0294TWF1.DOC / 002 No. 85〗 11373 Chinese Manual Amendment Page A7 B7 Amendment Date 86.4.24 Description of Invention (Y) or N-type polycrystalline silicon printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs as a material Transistors with high or low starting voltages can easily complete the programmed work. For example, the material of the polycrystalline silicon gate electrode can be fully implanted with the first-type conductive impurities, and then a mask is formed on the predetermined programming area, and then the second-type conductive impurities are implanted into the polycrystalline silicon gate electrode. A polysilicon region partially doped with impurities of the second type conductive layer is formed. In this preferred embodiment, two different gate electrode materials are used, and the properties of the second type memory may only be changed by at least two optional starting voltage values; for example, transistors may form gate oxides with two different thicknesses One of the layers: the thicker gate oxide layer has a thickness of approximately 135 Å. Changing the thickness of the gate oxide layer between the gate electrode and the silicon substrate can generate two different starting voltages, for example, the starting voltage is 3.6V (P-type silicon substrate, the thickness of the gate oxide layer is about 300A), 26v ( b-type sand substrate 'gate oxide layer thickness of about 30〇A), 1.95V (l-type sand substrate, gate oxide layer thickness of about 135A)' 〇_95V (N-type silicon substrate, gate oxide layer thickness of about 135A), which Has been obtained from the combination of field effect transistor layout. The use of selectively doped polycrystalline silicon gate electrodes to encode read-only memory transistors is briefly described in Figure 1 'which shows the intermediate process stage of read-only memory, and it is a pile of bit read-only memory Body, only the gate electrode of the selective memory is used to complete the programming work; the single bit embodiment of the read-only memory in FIG. 1 is to program the read-only by selectively doping the gate electrode Memory. The manufacturing method of the read-only memory in FIG. 1 is: providing a P-type sand substrate 10, and forming an embedded N + type bit line array 12_ in the unit area of the substrate and the N type required by the peripheral circuit area Well area 14 and used to define Γ ¥ (Please read the note $ item on the back before filling this page)

, 1T 11 This paper standard is applicable to China National Standard (CNS specification (210X297mm) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 0294TWF.DOC / 002 _Β7 Fifth, the invention description (彳) of the unit area and the isolated peripheral circuit area Field oxide region 15; gate oxide layer 16 covers the channel region of the memory and the buried N + type bit line array 12; N type polycrystalline silicon line 20 is formed on the gate oxide layer 16 to select as Part of the gate electrode of the memory, and the P-type polycrystalline silicon wire 22 is formed as the gate electrode of the remaining memory. The starting voltage of the transistor with the N-type polycrystalline silicon electrode 20 is about 0.9 ~ 1.0V , And the starting voltage of the transistor with the P-type polycrystalline silicon electrode 22 is about 1.9V; the difference of the starting voltage is close to IV, you can control the formation of P-type or N-type polycrystalline silicon by conventional doping techniques The degree of miscellaneous quality can be achieved. The degree of programmatic difference can be detected by detecting the impedance of the memory, or detecting the situation where the transistor is activated when a reference voltage is applied to the gate electrode of the memory. As shown, when the design size is less than 0.5 read-only memory It is easy, and its operating voltage can be adjusted to a lower level, about 1.5 V. The P / N junction 24 is formed at the interface between the N-type and P-type polycrystalline silicon gate electrode lines, which makes the gate electrode non-conductive. In addition, Forming a conductor layer 26 on the N-type polycrystalline silicon gate electrode 20 and the P-type polycrystalline silicon gate electrode 22, so that an ohmic contact occurs between the N-type polycrystalline silicon and the P-type polycrystalline silicon; this N-type The layered structure formed by polycrystalline silicon, P-type polycrystalline silicon and conductive layer allows the gate electrode of the memory to be used as a word line in this type of read-only memory. The peripheral circuit basically includes NMOS transistor 30 and PMOS Both crystals 32 can be coupled to form an inverter circuit and a buffer circuit area. As shown in Figure 1, the read-only memory can be manufactured and programmed in large quantities by this method. This read-only memory is inexpensive and has Sufficient reproducibility, it can be controlled well when defining different starting voltage states. The gate oxide layer of uniform thinness is deposited on the buried N + type bit line 12 by 16; after completion,,: 12 :; The paper size is applicable to China National (CNS) A4 (210X 297mm) ~ --- please Read the notes on the back & fill in this page) Install ·. * 1 'A7 0294TWF.DOC / 002 B7 5. Description of the invention (Sichuan) Deposited polycrystalline silicon once uniformly doped with a conductive impurity (such as N-type impurities) Layer, and then form a mask on the polycrystalline silicon layer, and expose the part of the polycrystalline sand on the channel region of the potential transistor; then, implant with opposite conductive impurities (such as P-type impurities) Or diffuse into the exposed polycrystalline silicon area. After the defined mask is removed, deposit a heat-resistant metal or a heat-resistant metal silicide layer on the polycrystalline silicon layer, and then form a mask to define the character line, the upper conductive layer and the polycrystalline silicon layer It is etched, and then the manufacturing of read-only memory is completed according to the conventional method. The read-only memory defined in this way provides greater tolerance than necessary, and if it uses completely different materials to form the gate electrode of the memory, it can have more different functions; The quasi-tolerance is greater than the memory defined by conventional channel doping. In particular, this preferred embodiment utilizes selective doping techniques. Selectively provide one or another type of polycrystalline silicon with different conductive properties as the gate electrode, which can easily provide two different starting voltages; and the design of multi-bit read-only memory must provide more than two different memory transistors The initial voltage value, which is defined by alternating programming techniques, can be accomplished in many ways. For example, it can be selectively ion implanted into the channel region of the memory transistor and combined with a gate electrode containing different impurity characteristics. Provide at least four different starting voltage values; however, this step is not completely reliable, because it is difficult to provide a fixed amount of impurities for multiple implants. In addition, it is necessary to incorporate more programming techniques that can be mass-produced to dope polysilicon gates to provide different starting voltages to form a multi-bit memory. 1. Provide at least two additional starting voltage values, the choices are different _. 13 'ϋ Zhang scale is applicable to China National Standard (CNS) Λ4 specifications (210X 297 mm)-— i -------- -Install I ί .. Please read the notes on the back ^ 4 fill in this page) Order the printed version of the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs

The printed and doped gate electrode materials of the Central Standard Falcon Bureau Employee Consumer Cooperative must be the same as the gate oxide layers of different thicknesses; in recent years, many documents have published how to manufacture gate oxide layers with good definition and reproducibility , Including thickness. Changing the interval between the substrate and the gate electrode provides gate oxide layers of different thicknesses, which can change the starting voltage of the memory. In addition, this preferred embodiment is particularly selective in providing two gate oxide layers with different thicknesses and two gate electrode materials with different functions. Figure 2 shows the read-only memory as shown in Figure 1, which provides a P-type silicon substrate 10 on which a buried N + type bit line array and N-type located in the peripheral circuit area are formed The well area 14, and the field oxide area 15 separating the cell area and the peripheral circuit area; a thin gate oxide layer 40 is formed on the channel area selected as the memory transistor, and a thick gate oxide layer 42 is formed on other memories On the channel area of the transistor. The thickness of the thin gate oxide layer 40 is, for example, less than about 150A, and the thickness of the thicker gate oxide layer 42 is more than about 250A. The difference in the thickness of the gate oxide layer is mainly determined by the manufacturability and the difference in the starting voltage that can be effectively detected between different memories. N-type polycrystalline silicon electrode 44-level P-type polycrystalline silicon electrode 46 is selectively formed on the channel area of the memory to store special data in the read-only memory: the wire 48 is formed on the N-type and P-type complex On the crystalline silicon electrode, a continuous conductive path along the gate electrode is provided as the word line of the read-only memory. The peripheral circuit area includes both the OS transistor 50 and the PMOS transistor 52 to form an inverter circuit and a buffer circuit area, such as the design of a conventional read-only memory. According to this manufacturing method, a memory transistor with one of four starting voltages can be selectively formed; for example, a starting voltage value of about 3.6V can be provided (P-type silicon substrate, the thickness of the gate oxide layer is about 300A ), 2.6ν (ϋ type_14_ (please read the precautions on the back before filling in this page). The size of the paper is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) A7 B7 0294TWF1.DOC / 002 312042 V. DESCRIPTION OF THE INVENTION (丨 1) Silicon substrate, gate oxide layer thickness is about 300A), 1.95V (formed silicon substrate, gate oxide layer thickness is about 135A), 0.95V ({ijy silicon substrate, gate oxide layer) Thickness is about 135A). The highest starting voltage (3.6V) can store binary data "00", the next highest starting voltage (2.6V) can store binary data "01", and the lower starting voltage (1.95V) can Store binary data "10", the lowest starting voltage (0.95V) can store binary data "11". These different starting voltage values can be read by the sense amplifiers of the memory, and the distinguishing diagrams of the data are as described in US Patent No. 4,287,570 obtained by Stark and US Patent No. 5,386,381 obtained by Takizawa et al., The appropriate parts of these patents are incorporated in the references. The manufacturing method of the read-only memory as shown in Figure 2 is described in Figures 3-12. First, please refer to FIG. 3 to provide a P-type silicon substrate 60 on which an N-type well region 70 and a field oxide layer 72 of PMOS and NMOS are formed, and a buried N + region 74 arranged in parallel is formed on the substrate To serve as the source / drain diffusion area of the bit line and field effect transistor, and then form a relatively thick oxide layer 76 on the substrate, and then form a mask layer 78 on the oxide layer 76, and cover the predetermined Thick gate oxide layer on the channel area of the transistor, so that it will have one of two higher starting voltages in the four data storage systems; then, the oxide layer 76 is etched, leaving the selected channel area The oxide layer 77 is shown in Figure 4. Next, please refer to Figure 5 and Figure 6 'After removing the mask 78, a thin gate oxide layer 80 is formed on the remaining substrate surface by thermal oxidation, which is also formed in the transistor channel area of the peripheral circuit area The upper surface of the substrate: At this time, the memory cell area of the substrate has a thick gate oxide layer 77 and a thin gate electrode (Don first read the precautions on the back side and then fill out this page)

-* 1T line < The paper standard printed by Beigong Consumer Cooperative of Central Bureau of Standards of Ministry of Economic Affairs is applicable to China National Standard (CNS) A4 specification (21〇'〆297mm) A7 B7 0294TWF.DOC / 002 V. Description of invention () Oxide layer 80. Then, deposit a polycrystalline silicon layer 82 with a thickness of about 1000 ~ 250 OA on the thick and thin gate oxide layer, the preferred thickness of which is about 1500A, which can be known at low temperature by chemical vapor deposition Formed at about 620 ° C. The definition of N-type and P-type polycrystalline silicon gate electrodes can be completed in a single mask process. The entire polycrystalline silicon layer can be doped with first-type impurities, for example, by diffusion or comprehensive ion implantation to form a first conductivity Layer, and then form a mask to expose the surface of the polysilicon gate region doped with the opposite impurity, and then implant the impurity with opposite conductivity into the surface of the exposed polysilicon to form a surface with opposite conductivity Polycrystalline silicon electrode with sexual impurities. As shown in Section 6_ [Fu Jin, the polycrystalline silicon layer 82 is first implanted with boron fluoride, the implantation dose is about 2X1015atoms / cm2 and the implantation energy is about 50KeV, forming a p-fracture complex silicon, this The amount of doping is as suitable as possible to produce thin and thick gate oxides_the starting voltage of the memory ', which allows storage-related data to be reliably measured. To put it another way, the implanted impurity concentration must be sufficient to produce a transistor whose starting voltage is sufficiently different from that of other transistors with other starting voltage values. The programmed data can be reliably written and read out . ^ Please refer to Figure 7 and Figure 8, after the crystals are fully implanted, deposit ~, / The Ministry of Economic Affairs Central Standards Bureau employee consumer cooperative prints% layer 84 on the polycrystalline silicon layer 82, and then uses lithography imaging and etching The technology side photomask 86 is exposed on the N-type polycrystalline silicon gate area to be formed, forming the gate electrode of the field effect transistor with a lower starting voltage, and causing the strip and the P-type polycrystalline silicon gate The gate oxide layer with the same thickness of the electrode; and the N-type polycrystalline sand gate is often used, so the mask is often exposed to a predetermined percentage to form the polycrystalline silicon layer 82 of the gate oxide layer of the field effect transistor. In the soil, diffuse oxychloride phosphorus (POCh) or apply arsenic and phosphorus on 16 paper scales to the Chinese National Standard (CNS) Λ4 specification (21〇X: 297 mm) 0294TWF.DOC / 002 A7 B7 Ministry of Economic Affairs Printed by the Central Bureau of Standards 'Staff Consumer Cooperative V. Invention description (丨 T) 4X1015atoms / cm2 with an energy of 60KeV implanted into the area not covered by the mask 86, the impurity concentration forming the N-type polycrystalline silicon area must be sufficiently concentrated' The starting voltage of the manufactured memory transistor can be distinguished from the starting voltage of other memory transistors to form a multi-bit read-only memory that is easy to read and write. If the diffusion of oxygen chloride scales is used to locally dope the polycrystalline silicon layer, then an oxidation mask must be formed on the photoresist layer during the diffusion process. If arsenic or phosphorous is used, this oxidation mask is not required. Next, referring to FIG. 9, after the implantation of N-type and P-type impurities is completed, the mask 86 is removed, and the polycrystalline silicon layer includes a locally-doped N-type polycrystalline silicon layer 90 and a locally-doped P-type complex The crystalline silicon layer 92 and the P / N junction 91 are the interfaces between the adjacent P-type and N-type polycrystalline silicon layers; when the gate electrode is formed on the polycrystalline silicon layer, the P / N junction is almost impossible to conduct of. Then, referring to FIG. 10, a conductive layer 94 is formed on the polycrystalline silicon layer, which partially forms a gate electrode (character line) and connects the signal over the read-only memory to the field effect transistor gate in the array ; And the conductive layer 94 preferably has high conductivity, so that ohmic contact between N-type polycrystalline silicon and P-type polycrystalline silicon 'tungsten silicide is a preferred material for the conductive layer, and other heat-resistant metals and heat-resistant metal silicide can also Provide materials with this characteristic. Next, referring to FIG. 11, after the conductive layer 94 and the polycrystalline silicon layers 90 and 92 are etched, word lines and gate electrodes are formed, and at the same time, gates 96 of NMOS elements and gates 98 of PMOS elements are formed in the peripheral circuit area . Finally, please refer to FIG. 12, after the gates of the NMOS device and the PMos device in the peripheral circuit area are formed, the source / drain of the NMOS device and the PMOS device are formed using the conventional lightly doping drain technology . I II Pack I order! —The line is- (please read the note name on the back to fill in this page) This paper size is applicable to Chinese National Standard (CNS) Λ4 specification (210X29 * 7mm) A7 0294TWF.DOC / 002 B7 5. Description of the invention (β) Diffusion zone. Finally, a borophosphosilicate glass 100 (BPSG) is deposited to encapsulate the read-only memory, and then the contact window of the memory is formed by a conventional process to complete the manufacture of the memory. The detailed process is not the focus of the present invention. This will not be repeated here. Although the present invention has been disclosed as above in a preferred embodiment, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications within the spirit and scope of the present invention. The scope of protection of an invention shall be deemed as defined by the scope of the attached patent application. Please read the precautions on the back first and fill out this page)-Packing. Threading Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm)

Claims (1)

ABCD 312042 0294TWF.DOC / 002 VI. Patent application. The material of the conductive layer is heat-resistant metal or heat-resistant metal silicide. 6. The non-volatile memory device as described in item 1 of the patent application scope, wherein some of the first-type memories are gate oxide layers with a first thickness, and the rest are gate electrodes with a second thickness Oxide layer. 7. The non-volatile memory element as described in item 1 of the patent application, wherein the first thickness is less than 150A and the second thickness is more than 300A. 8.-Non-volatile memory device, including: a plurality of memory cells, the memory cell includes a memory transistor, the memory transistor includes a source / drain diffusion area, a separate source / drain diffusion area The channel region, and a gate oxide layer and a gate electrode are sequentially located on the channel region, wherein the characteristics of each memory transistor are determined by one of at least four predetermined threshold voltages, different The memory transistor has different starting transistors, wherein the memory transistor array includes a first type memory transistor, the gate electrode of which is formed by a first material having a first function, the first material portion Determines the starting voltage of the first type transistor; and the second type memory transistor, the gate electrode of which is formed by a second material having a second function, and the second material portion determines the second type memory transistor The starting voltage of the crystal, and among these memory transistor arrays, includes a third transistor having a first thickness gate oxide layer and a fourth transistor having a second thickness gate oxide layer. 20 The size of this paper is in accordance with the Chinese National Standard (CNS) Λ4 specification (210X 297mm): ---------- 1 --- ^ ---- 1T ----- 叫 ——, ii- (Please read the precautions on the back before filling in this page) A8 0294TWF.DOC / 002 B8 C8 D8 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. Scope of patent application 9. As described in item 8 of the scope of patent application A volatile memory device element, wherein the first memory has a gate oxide layer with a second thickness, and the second memory has a gate oxide layer with a first thickness. 10. The non-volatile memory device as described in item 8 of the patent application, wherein the first material is polycrystalline silicon. 11. The non-volatile memory device as described in item 10 of the patent application range, wherein the first material is N-type polycrystalline silicon and wherein the second material is P-type polycrystalline silicon. 12. —Memory device, including: a first row, including a plurality of first transistors, the first transistors including a first source / drain diffusion region, and a first gate; and a first Two columns, including a plurality of second transistors, the second transistor includes a second source / drain diffusion region, and a second gate, wherein the first gate of the first transistor and the second transistor The second gate of the transistor contains a continuous wire, and at least one first gate contains N-type polycrystalline silicon and its adjacent second gate contains P-type polycrystalline silicon, and at least one has a first thickness The first transistor and a second transistor with a second thickness J-^ ------, order ----- ^ I ^ '(Please read the precautions on the back before filling this page) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 21 This paper standard is applicable to the Chinese National Standard (CNS) Λ4 specifications (210X297 mm). Body elements, including: a plurality of memory units, the memory unit includes a memory Transistor, the memory transistor includes a source / drain diffusion region, a channel region separating the source / drain diffusion region, and a gate oxide layer and a gate electrode are sequentially located on the channel region, wherein each memory The characteristics of the transistor are determined by one of at least four predetermined threshold voltages. The different memory transistors have different starting transistors. The memory transistor array includes a first type memory transistor. The gate electrode of the crystal is formed by a first material having a first function, the first material portion determines the starting voltage of the first type transistor; and the second type memory transistor, the gate electrode is formed by Formed by a second material with a second function, the second material portion determines the starting voltage of the second memory transistor. 2. The non-volatile memory element as described in item 1 of the patent scope, wherein the first material and the second material are polycrystalline silicon. 3. The non-volatile memory element as described in item 1 of the patent scope, wherein the first material is N-type polycrystalline silicon and the second material is P-type polycrystalline sand. 4. The non-volatile memory device according to item 3 of the patent application scope, wherein at least one first-type memory transistor is formed adjacent to a second-type memory transistor, and one of the conductive layers is located A connecting wire structure is formed on the second-type material of the gate electrode of the one-type memory transistor. 5. The non-volatile memory element 19 as described in item 4 of the patent application is bound to the front line (please read the precautions on the back and then fill out this page). The paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 Mm)