經濟部中央樣隼局員工消費合作社印裝 309630 File I 3 961 w Γ. doc/J I m m y/002 __B7 五、發明説明（I ) 本發明是有關於一種形成淺溝渠隔離（Shallow Trench Isolation，STI )的方法，且特別是有關於—種利 用化學氣相沈積法在溝渠表面沈積一矽層，以形成無空隙 淺溝渠隔離的方法。 溝渠隔離（Trench Isolation )，在超大型積體電路 (VLSI )製作上的應用’已愈來愈普遍。例如，已被廣 泛應用在新一代記憶體製程上的金氧半導體（MOS )隔離 技術，以及應用在動態隨機存取記憶體（DRAM )的製作 上等等。前者的原理，係利用非等向性（Anisotropic )乾 蝕刻（Dry Etching )，在MOS間“挖出”一道溝渠，然 後陸續塡入絕緣物質，例如二氧化矽。而後者，其溝渠不 再做爲隔離之用，而是做爲DRAM記憶胞的電容器，使其 在不損及DRAM積集度的情況下，而增加電容器的面積。 然而，由於設計準則（Design Rule )趨於縮小化的發展， 當最小線寬僅達0.18μπι的深半次微米（Deep Sub-Half Micron )技術被開發出來時，如何增進淺溝渠隔離的溝塡 能力（Gap filling )，也變得愈來愈重要。 請參照第la〜lc圖，其繪示一種習知以次氣壓化學 氣相沈積（Sub-Atmospheric Chemical Vapor Deposition， SACVD )法形成淺溝渠隔離的方法。利用四乙基矽酸鹽 (tetra-Ethyl-Ortho-Silicate，TEOS ) /臭氧（03 )爲 主反應氣體，所形成的淺溝渠隔離具有良好的一致性 (Conformity )，是現今溝塡能力變得愈來愈困難時較佳 的選擇。 ^—叫------ck------訂------^— (請先閲讀背面之注$項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央橾準局員工消費合作ft印聚 A7 B7__ 五、發明説明（> ) 首先如第la圖所示，在一半導體基底10上，例如一 矽基底，陸續形成一墊氧化層12以及一矽氮化物層14後， 利用乾触刻以形成多數個溝渠16，並在溝渠16內形成一 薄氧化層18，例如直接以熱氧化法或沈積法來形成。接 著，如圖lb所示，利用SACVD法，其操作氣壓約爲450 torr，並以TEOS / 03爲主反應氣體，沈稹一二氧化矽層 11在矽氮化物層14上及溝渠16內，以完成該些溝渠16 的溝塡。之後，將上述元件經由密化（Densification )及 化學機械硏磨的步驟，去除矽氮化物層14上之二氧化矽層 11，以形成如圖lc之淺溝渠隔離。 雖然，以TEOS/ 03形成的淺溝渠隔離有良好的一致 性，但因 TE0S / 03 的表面敏感性（Surface Sensitivity ) 之故，將使其在不同之薄膜層表面會有不同的沈積速率， 以致溝渠內會產生空隙（Void)。又，密化步驟後，二氧化 矽層11會收縮（Shrink )約5%-10%，造成形成後之淺溝 渠隔離的品質不佳。 有鑑於此，本發明的主要目的就是在提供一種形成淺 溝渠隔離的方法，用以使溝渠內不會產生空隙。 本發明的次要目的就是在提供一種形成淺溝渠隔離的 方法，使密化後收縮的二氧化矽層得到回補。 爲達成本發明之上述目的，提出一種形成淺溝渠隔離 的方法，其包括下列步驟： a-提供一半導體基底，並在基底上依序形成一墊氧化 層及一矽氮化物層； 4 -T—----Ο------1T------A. (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） 經濟部中央樣举局員工消費合作社印裝 F |e &3❽ mv/002 A7 __E__ 五、發明説明（多） b. 定義矽氮化物層與墊氧化層，在基底上形成複數個 溝渠； c. 在溝渠內形成一薄氧化層； d. 形成一砂層； e. 形成一氧化層，使之塡滿溝渠； f. 將氧化層進行密化處理，並同時使矽層完全氧化；以 及 g. 去除該矽氮化物層上的氧化層，形成一淺薄溝渠隔 離。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下。 圖示之簡單說明： 第la〜lc圖繪示一種習知以SACVD形成淺溝渠隔離 的方法；以及 第2a〜2d圖繪示本發明之一較佳實施例，一種以 SACVD形成淺溝渠隔離的方法。 實施例 請參照第2a圖，在一半導體基底20上’例如一矽基 底，依序形成一墊氧化層22以及一矽氮化物層24。之後， 利用乾蝕刻以形成多數個溝渠26，並在溝渠26表面形成 一薄氧化層28，例如直接以熱氧化法形成。 之後請參照第2b圖，在矽氮化物層24上及溝渠26內 以低壓化學氣相沈積（LPCVD )法，沈積一矽層30 ’例 (請先聞讀背面之注$項再填寫本頁) *1Τ 本紙張尺度適用中國國家橾隼（CNS ) A4規格（2IOX 297公釐） A7 B7 3ϋ3β®03961 w f d 〇 c / J I m m y / 0 0 2 五、發明説明（+ ) 如可爲一複晶（P〇丨ycrystalline )砂層或―非晶 (Amorphous )矽層，沈積厚度約爲5〇〇A〜1000A。 接著，如圖2c所示’利用SACVD法，其操作氣壓約 爲450torr，並以TEOS / 03爲主反應氣體，沈積—二氧 化矽層32在矽層30上，以完成該些溝渠16的溝塡。由於 以TEOS/ Ο;沈積之二氧化矽層32’係沈積於矽層30上， 故不會有如習知技藝般沈積速率不同的問題產生。 之後，請參照第2d圖，進行乾式密化處理及去除砂氮 化物層24上之二氧化矽層32，以形成如圖2d所示的淺溝 渠隔離。其中’去除矽氮化物層24上之二氧化矽層32的 方式’例如可利用化學機械硏磨法，或是利用乾蝕刻製程 皆可’爲了方便說明起見，本實施例以化學機械硏磨法爲 例。 進行乾式密化及化學機械硏磨處理的時機，可有不同 的先後順序，例如先進行乾式密化製程後再以化學機械硏 磨法來硏磨；或先以化學機械硏磨法硏磨後再進行乾式密 化製程皆可。進行乾式密化時，係將晶片置於一包括氣氣 及氮氣的環境中，例如氧氣佔2 %〜1〇 %，其餘皆爲氮氣 之環境，以約1000 t：〜1100 °C的溫度，花費約爲30分鎳 至2小時的時間來完成。如此，矽層30將完全氧化成二氣 化矽，所以密化後溝渠I6內有氧化物的存在而無矽廢30 的存在。又’密化時其二氧化矽層32雖有收縮現象，但因 矽層30受熱氧化成二氧化矽，故矽層3〇所形成的二氣化 矽已大約補償（Compensate )因收縮而短少的二氧化矽朦 本紙張尺度適用中國國家棣準（CNS ) A4規格（2i〇'x297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標隼局員工消費合作社印^ 經濟部中央樣隼局員工消費合作社印狀309630 File I 3 961 w Γ. Doc / JI mmy / 002 __B7 Printed by the Employees ’Consumer Cooperative of the Central Sample Falcon Bureau of the Ministry of Economic Affairs 5. Description of the invention (I) The present invention relates to the formation of a shallow trench isolation (STI) Method, and in particular, it relates to a method of depositing a silicon layer on the surface of a trench by chemical vapor deposition to form a trench-free shallow trench isolation. Trench isolation (Trench Isolation), the application of VLSI manufacturing has become more and more common. For example, the metal oxide semiconductor (MOS) isolation technology that has been widely used in the new generation of memory systems and the production of dynamic random access memory (DRAM) and so on. The principle of the former is to use anisotropic dry etching (Dry Etching) to "dug out" a ditch between the MOS, and then successively introduce insulating materials, such as silicon dioxide. In the latter case, the trench is no longer used for isolation, but as a capacitor of the DRAM memory cell, so that the area of the capacitor is increased without compromising the degree of DRAM accumulation. However, due to the design rule (Design Rule) tending to shrink, when deep sub-half micron (Deep Sub-Half Micron) technology with a minimum line width of only 0.18 μm is developed, how to improve the isolation of shallow trenches Ability (Gap filling) has become more and more important. Please refer to Figures la ~ lc, which illustrates a conventional method for forming shallow trench isolation by Sub-Atmospheric Chemical Vapor Deposition (SACVD) method. Using tetra-Ethyl-Ortho-Silicate (TEOS) / ozone (03) as the main reaction gas, the shallow trench isolation formed has good consistency (Conformity), which is now the ability of the gully The better choice when it gets more difficult. ^ — 叫 ------ ck ------ 定 ------ ^ — (please read the $ item on the back and then fill in this page) This paper size is applicable to China National Standard (CNS) A4 Specifications (210X297 mm) Employee Consumer Cooperation of the Central Ministry of Economic Affairs of the Ministry of Economic Affairs ft India Poly A7 B7__ 5. Invention Description (>) First, as shown in Figure la, a semiconductor substrate 10, such as a silicon substrate, is formed After a pad oxide layer 12 and a silicon nitride layer 14, dry contact etching is used to form a plurality of trenches 16, and a thin oxide layer 18 is formed in the trenches 16, for example, directly by thermal oxidation or deposition. Next, as shown in FIG. 1b, using SACVD method, the operating pressure is about 450 torr, and the main reaction gas is TEOS / 03, Shen Zhen-silicon dioxide layer 11 is on the silicon nitride layer 14 and the trench 16, To complete the gully 16 of these ditches. After that, the above-mentioned device is subjected to densification and chemical mechanical polishing steps to remove the silicon dioxide layer 11 on the silicon nitride layer 14 to form a shallow trench isolation as shown in FIG. 1c. Although the isolation of shallow trenches formed with TEOS / 03 has good consistency, due to the surface sensitivity of TE0S / 03, it will have different deposition rates on different thin film layers. Void will be created in the ditch. Furthermore, after the densification step, the silicon dioxide layer 11 will shrink (shrink) by about 5% -10%, resulting in poor quality of the shallow trench isolation after formation. In view of this, the main purpose of the present invention is to provide a method of forming shallow trench isolations so that no voids are generated in the trenches. The secondary objective of the present invention is to provide a method of forming shallow trench isolations to make up the silicon dioxide layer that shrinks after densification. To achieve the above object of the invention, a method for forming shallow trench isolation is proposed, which includes the following steps: a- providing a semiconductor substrate, and sequentially forming a pad oxide layer and a silicon nitride layer on the substrate; 4-T —---- Ο ------ 1T ------ A. (Please read the precautions on the back before filling in this page) This paper size is applicable to China National Standards (CNS & A4 specifications (210X297 C) Printed by the Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs F | e & 3❽ mv / 002 A7 __E__ V. Description of the invention (more) b. Define the silicon nitride layer and the pad oxide layer to form a plurality of trenches on the substrate ; C. Forming a thin oxide layer in the trench; d. Forming a sand layer; e. Forming an oxide layer to fill the trench; f. Densifying the oxide layer and simultaneously oxidizing the silicon layer completely; and g. Remove the oxide layer on the silicon nitride layer to form a shallow trench isolation. In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is described below in conjunction with The attached drawings are described in detail as follows. Description: Figures la ~ lc illustrate a conventional method of forming shallow trench isolation by SACVD; and Figures 2a ~ 2d illustrate a preferred embodiment of the present invention, a method of forming shallow trench isolation by SACVD. Referring to FIG. 2a, on a semiconductor substrate 20, such as a silicon substrate, a pad oxide layer 22 and a silicon nitride layer 24 are sequentially formed. Then, dry etching is used to form a plurality of trenches 26, and the trenches 26 A thin oxide layer 28 is formed on the surface, for example, directly by thermal oxidation. Then, referring to FIG. 2b, a silicon layer 30 is deposited on the silicon nitride layer 24 and the trench 26 by low-pressure chemical vapor deposition (LPCVD) 'Example (please read the $ item on the back and then fill out this page) * 1Τ This paper size is applicable to the Chinese National Falcon (CNS) A4 specification (2IOX 297 mm) A7 B7 3ϋ3β®03961 wfd 〇c / JI mmy / 0 0 2 5. Description of the invention (+) If it can be a polycrystalline (Polycrystalline) sand layer or an amorphous (Amorphous) silicon layer, the deposition thickness is about 500A ~ 1000A. Then, as shown in Figure 2c Show 'using SACVD method, its operating pressure is about 450torr, and With TEOS / 03 as the main reaction gas, a silicon dioxide layer 32 is deposited on the silicon layer 30 to complete the trenches of these trenches 16. Since TEOS / O; the deposited silicon dioxide layer 32 'is deposited on silicon On the layer 30, there will be no problems with different deposition rates as in the conventional art. After that, please refer to FIG. 2d for dry densification and removal of the silicon dioxide layer 32 on the sand nitride layer 24 to form The shallow trench isolation shown in Figure 2d. The 'method of removing the silicon dioxide layer 32 on the silicon nitride layer 24' can be, for example, a chemical mechanical polishing method or a dry etching process. For convenience of description, this embodiment uses chemical mechanical polishing Law as an example. The timing of dry densification and chemical mechanical grinding can be different, for example, the dry densification process is carried out before the chemical mechanical grinding method is used; or after the chemical mechanical grinding method is used for grinding It is possible to perform the dry densification process. When performing dry densification, the wafer is placed in an environment including gas and nitrogen, for example, oxygen accounts for 2% ~ 10%, and the rest is nitrogen, at a temperature of about 1000 t: ~ 1100 ° C, It takes about 30 minutes nickel to 2 hours to complete. In this way, the silicon layer 30 will be completely oxidized to silicon dioxide, so after the densification there is oxide in the trench I6 and no silicon waste 30 exists. Also, although the silicon dioxide layer 32 shrinks during densification, the silicon layer 30 is oxidized to silicon dioxide by heat, so the silicon dioxide formed by the silicon layer 30 has been approximately compensated due to shrinkage. The size of the silica paper is applicable to China National Standard (CNS) A4 (2i〇'x297mm) (please read the precautions on the back before filling out this page). Ordered by the Ministry of Economic Affairs, Central Standard Falcon Bureau Staff Consumer Cooperative ^ Seal of the Employees Consumer Cooperative of the Central Falcon Bureau of the Ministry of Economic Affairs
Kiic: I396twf.doc/.limmy/002 A7 B7 五、發明説明（丫） 32 ° 綜上所述，熟悉此藝者應知應用本發明具有如下的優 點： 1. 在形成一 SACVD氧化層之前先沈積形成一矽層，可 避免因SACVD氧化層沈積速率不同所產生之空隙。 2. 密化後SACVD氧化層所減少的體積，約可由矽層所 形成的二氧化矽回補之。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 J 7 (：·Α n 訂 · (請先閱讀背面之注意事項再填寫本頁) 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）Kiic: I396twf.doc / .limmy / 002 A7 B7 5. Description of the invention (Ya) 32 ° In summary, those familiar with this art should know that the application of the present invention has the following advantages: 1. Before forming a SACVD oxide layer A silicon layer is formed by deposition to avoid voids caused by different deposition rates of the SACVD oxide layer. 2. The reduced volume of the SACVD oxide layer after densification can be replaced by the silicon dioxide formed by the silicon layer. Although the present invention has been disclosed as above in a preferred embodiment, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications within the spirit and scope of the present invention. The scope of protection of an invention shall be deemed as defined by the scope of the attached patent application. J 7 (： · Α n order · (Please read the precautions on the back before filling in this page) 7 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm)