TW306073B - - Google Patents

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TW306073B
TW306073B TW85110108A TW85110108A TW306073B TW 306073 B TW306073 B TW 306073B TW 85110108 A TW85110108 A TW 85110108A TW 85110108 A TW85110108 A TW 85110108A TW 306073 B TW306073 B TW 306073B
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Taiwan
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output
circuit
signal
noise
timing
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TW85110108A
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Chinese (zh)
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Nagataka Tanaka
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Toshiba Co Ltd
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經濟部中央橾準局員工消費合作社印製 A7 _____B7_ 五、發明説明（1 ) 本發明係關於由在晶胞內放大信號電荷之放大型 MO S偵測器所構成之固體攝像裝置及使用固體攝像裝置 之系統。 近年來，由於半導體裝置技術之進步，視頻攝像機之 外形及重量皆變小，攜帶方便，廣泛的被使用。電子裝置 中，由於攜帶之需要，其電池係使用電池，但習用之視頻 攝像機之攝像元件係使用CCD偵測器。CCD偵測器在 驅動裝置時，需要使用許多種電壓，因此需要從電池電壓 中產生該電壓之電源電路》以上因素成爲妨礙視頻攝像機 之更進一步之小型化之原因，又成爲妨礙降低消耗功率之 原因。 爲了更容易操作，目前已在研究視頻攝像機之小型輕 量化，又在開發圖素數置更多之固態攝像裝置•但爲了視 頻攝像機之小型及輕置化，不但需要固體攝像裝置之小型 化，而且必須有消耗功率低，使用電壓低之固體攝像裝置 〇 若只是單純的將固體攝像裝置小型化及多圖素化，只 要將圖素細微化即可。然而，若將圖素細微化，則發生每 一圖素之處理信號電荷量減少之問題•因此，固體攝像裝 置之動態範圍減小，不能形成鮮明而解像度良好之影像。 若使用C C D時，因爲利用許多種電壓驅動元件，故 不能以簡單之系統對付攝像機系統之結構及操作。亦即， 爲了應用於攜帶用攝像機及具有個人電腦之攝像機上•需 要一種不但消耗功率低，使用電應低，而且S/N良好之 本紙張尺度遑用中國國家橾隼（CNS) A4規格（210X 297公釐）_ 4 - — I I I 坤衣 I1T— I I I I —-^ (請先閲讀背面之注意事項一_ 寫本頁) 306073 經濟部中央標準局負工消費合作社印袈 五、 發明説明（ 2 ) 1 | 單 一 電源 之固 體 攝 像 裝 置 〇 然 而 C C D 不 能 以單一 電 源 驅 1 1 動 » 不但 不能 頁 現 低 消 耗 功 率 及 低 使 用 電 壓 ，而且 因 爲 將 Ί 圖 素 細微 化後 S / Ν 惡 化 > 故 不 能 滿 足 上 述要求 〇 1 | 請 1 1 可滿 足上 述 要 求 之 其 他 裝 置 9 亦 即 可 實 現低消 耗 功 率 先 閱 1 I 讀 1 及 低 使用 電壓 9 可 使 用 單 電 源 驅 動 之 固 體 攝像裝 置 爲 使 背 t6 1 I 用 放 大型 m曰曰 體 之 Μ 0 S 偵 測 器 〇 之 注 意 1 1 | 這種 固體 攝 像 裝 置 之 特 徴 爲 以 電 晶 體 放 大以感 光 二 極 S.. 1 1 I 體 在 各晶 胞內 檢 測 之 信 號 > 其 靈 敏 度 高 〇 寫 本 1 % Μ 0 S偵 測 器 與 使 用 特 殊 製 程 之 C C D 偵測器 不 同 y 頁 'w«, 1 1 係 利 用D R A Μ 等 半 導 體 記 憶 體 » 處 理 機 等 常用之 Μ 0 S 1 1 製 程 生產 。因 此 » Μ 0 S 偵 測 器 容 易 形 成 在 與半導 體 記 億 1 | 體 或 處理 機相 同 之 半 導 體 晶 粒 上 而 且 容 易 共有與 半 導 體 訂 I 記 憶 體及 處理 機 相 同 之 生 產 線 睿 1 1 1 然而 ，上 述 使 用 放 大 電 晶 體 之 習 用 之 Μ 〇 S偵 測 器 ( 1 1 I 放 大 型Μ 0 S 偵 測 器 ) 不 容 易 去 除 被 稱 爲 固 定圖型 雜 訊 之 1 1 亮 度 不均 。此 外 放 大 型 Μ 0 S 偵 測 器 之 輸 出之動 態 範 圍 線 1 亦 只有6 0 d Β 左 右 若 與 銀 鹽 薄 膜 之 9 0 d Β及 C C D 1 1 偵 測 器之 7 0 d B 比 較 * 極 不 充 分 9 因 此 9 將該放 大 型 1 | Μ 0 S偵 測器 裝 組 於 視 頻 攝 像 機 等 畫 像 系 統 裝置中 時 y 其 1 I 畫 質 在賁 用上 有 極 大 之 限 制 0 I 1 I 第1 圖爲 使 用 放 大 型 Μ 0 S 偵 測 器 之 習 用之固 體 攝 像' 1 1 裝 置 之電 路圖 〇 圈 中 在 縱 1 橫 方 向 以 2 次 元矩陣 狀 排 列 1 1 相 當 於圖 素之 單 位 晶 胞 P 0 一 i — j • 圖 中 只表7TC 2 X 2 1 1 > 但 實際 上爲 數 4 個 X 數 4 個 之 排 列 〇 1 表 示水平 ( 1 1 本紙張尺度遑用中國國家揉準（CNS ) A4規格（210X297公釐）-5 - 經濟部中央棣準局員工消費合作社印製 A7 B7五、發明説明（3 ) row)方向之變數，j表示垂直（column)方向之變數* 各單位晶胞ρο-i — j係由感光二極體l_i_j ，放 大電晶體2 — i — j ，垂直選擇電晶體3— i - j ，及復 置電晶體4 一 i - j所構成。爲了依次選擇排列成2次元 矩陣狀之單位晶胞P 〇 — 1 — 1 ........... ρ 〇 — i 一 j ..........而設有垂直位址電路5及水平位址電路1 3。垂 直位址電路5具有數置對應於n xm結構之2次元矩陣狀 排列之單位晶胞P 〇 - 1 — 1 ’ ......... * ρ 〇 — i — j * .........之橫向排列數（水平方向排列數）之η之成對之位 址输出端子與復置信號端子，而水平位址電路1 3具有數 量對應於n xm結構之2次元矩陣狀排列之單位晶胞Ρ 〇 —1 一 1 ..........ρ 〇 — i — j .........之縱向排列數 (垂直方向排列數）之m之位址输出端子。m，η，i ’ j爲任意之整數。 沿著排列於水平方向之單位晶胞P〇 一 1 — 1 ’ P〇 一 1 — 2 .........，ρ 〇 — 2 — j .........從垂直位址電 路5朝向水平方向，依次配置各1條垂直位址線6_1 ， 6 — 2 ...........各垂直位址線6 — 1 ，6 - 2 ’ ......... 分別連接於垂直位址電路5之η個位址输出端子中之對應 之一個端子。 沿著排列於水平方向之單位晶胞Ρ 0 一 1 一 1 ，Ρ — 1 — 2..........，ρ 〇 — 2 — j ..........，從垂直位址電 路5朝向水平方向依次配置各一條復置信號線7 一 1 ’ 7 —2 ...........各復置信號線7 — 1 ，7 - 2 ........... (請先閱讀背面之注意事果-,填寫本頁) .裝 訂 線 本紙張尺度適用中國國家梯準（CNS)A4規格（ 210X297公釐）-6 - B7 經濟部中央橾準局貝工消費合作社印製 五、發明説明（4 ) 分別 連接 於垂直位址電路5之η個復置 信 疏 端 子 中 之 對 pig 應 之~ 個端 子。 沿著 排列於垂直方向之單位晶胞Ρ 0 — 1 — 1 P 〇 -1 -2 9 · · · » p Q - 2 -- J · · · · … … 9 從 水 平 位 址 電路 13 朝向垂直方向依次配置垂直信 號 線 8 一 1 > 8 — 2， • · · · · · …·各垂直信號線8 — 1 ，8 — 2 ♦ … … … 分 別 連接 於水 平位址電路13之m個位址输 出 端 子 中 之 對 應 之 —個 端子 0 從垂 直位址電路5配置於水平方向 之 垂 直 位 址 線 6 — 1， 6 — 2..........連接於各行之單位 晶 胞 之 垂 直 選 擇 .電 晶體 3 - 1 — 1 ..........之閘極而決定 讀 出 信 號 之 水 平 線 。同 樣的 ，從垂直位址電路5配置於水 平 方 向 之 復 置 線 7 -1 ，7 一 2..........分別連接於對應 之 各 行 之 復 置 電 晶 體4 -1 一 1 ..........之鬧極。 檢測 入射光之感光二極體1 一 i — j 形 成 檢 測 入 射 光 之受 光部 ，並且產生對應於受光量之信 電 荷 由 1 個 感 光二 極體 構成1個圖素。放大電晶體2 — i — j 放 大 該 感 光二 極體 l_i—j所產生之信號電荷 而 將 之 做 爲 檢 測 信 號輸 出。 因爲感光二極體l_i_j之 陰 極 連 接 於 其 本 身 之閘 極而 放大感光二極體1 _ i 一 j之 信 號 電 荷 » 以 對 應 於該 信號 電荷之放大輸出做爲檢測信號 在 吸 極 側 產 生 〇 垂直 選擇電晶體3 —i — j之本身 之 源 極 與 吸 極 之 間 連接 於直 流之系統電源與放大電晶體2 — i — j 之 吸 極 側 之間 ，而 本身之閘極連接於垂直位址電 路 5 之 垂 直 位 址 線 本紙張尺度適用中國國家揉準（CNS>A4規格（ 210X297公釐）* 7 _ A7 __B7_五、發明説明（5 ) 6 — j 。 復置電晶體4 - i - j之本身之源極與吸極之間連接 於直流之系統電源與感光二極體1 一 i 一 j之陰極之間， 在動作時，復置感光二極體1 一 i _ j之信號電荷。 具體言之，垂直選擇電晶體3 — i - j之源極與復置 電晶體4_ i — j之源極共同的連接於直流之系統電源之 吸極電壓端子，以便供給吸極電壓。 如上所述，從垂直位址電路5朝向水平方向配線之垂 直位址線6 6-2 9 ··· · · · _·♦ 之垂直選擇電晶體3 — 1_1 連接於各行之單位晶胞 ……之閘極而決定讀出 請 先 閲 讀 背 夯 Ϊ 事 %2裝 頁 信號之水平線。同樣的，從垂直位址電路5朝向水平方向 配線之復置線7- 7-2 連接於各行之復置電 訂 晶體4 一 1 — 1 ， · · · · · · · · · 之閘極 因此，在讀出具有n xm結構（η行m列之排列結構 )之圖素時，爲了使η線之水平線（行方向線）依照其讀 出掃描順序成爲主動，垂直位址電路5使垂直位址線6 — 1-6-2 .........依次成爲主動，又爲了復置圖素之信號 電荷而將信號输出於输出端子。 以上說明畫像檢測部。除了畫像檢測部之外，又有讀 出該畫像檢測部所檢測之畫像之f出部。輸出部係由負載 電晶體9 一 1 ，9 — 2...........信號傳送電晶體10 — 1-10-2* ..........儲存電容量 11 — 1 ，11 — 2 ...........水平選擇電晶體12 — 1 ，12-2 所構成•其結構如下 本紙張尺度遑用中國國家標準（〇犯）八4規格（2丨0/297公釐）_8_ 線 經濟部中央標準局員工消费合作社印装 A7 306073 ___B7_ 五、發明説明（6 ) 亦即，各列之單位晶胞之放大電晶髖2 — 1 - 1 * 2 -1-2 ..........之源極分別連接於配置在列方向之垂直 信號線8 — 1 ，8 _ 2..........中，與其對應之列。對應 於各列之單位晶胞分別設置1個負載電晶體9 _ 1 ，9 - 2 1 ..........垂直信號線8 — 1 ，8 — 2 ..........之一端 經由各負載電晶體9 一 1 ，9 _ 2 .........中對應之一個電 晶體，及該負載電晶體之源極與吸極連接於直流系統電源 〇 垂直信號線8-1 ，8 - 2 ..........之另一端經由輸 入相當於1行之信號之信號傅送電晶體10_1，10 — 2 .........中與其對應之一個電晶體連接於儲存相當於1行 之信號之儲存電容器1 1 — 1 ，1 1 — 2 .........中與其對 應之一個電容器，而且經由水平位址電路1 3所供給之水 平位址脈波所選擇之水平選擇電晶體12-1 ，12-2 .........連接於信號输出端（水平信號線1 5 )。 亦即垂直信號線8 - 1，8 — 2 .........之另一端經由 信號傳送電晶體1 0 — 1 ，1 0 — 2 ..........中與其對應 之一個電晶體之源極與吸極連接於儲存電容器11-1， 11 — 2，.........中與其對應之一個儲存電容器之一端， 而且經由水平選擇電晶體1 2 — 1 ，1 2 — 2..........中 與其對應之一個電晶體之源極與吸極連接於信號輸出端（ 水平信號線）1 5。各儲存電容器1 1 — 1 ，1 1 — 2，> .........之另一端接地，而信號傳送電晶體1 0 - 1 ，1 0 -2 ..........之閘極連接於共同閘極1 4。在需要傳送信 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）_ 9 - ---------^------1T------^ (請先閱讀背面之注意事.%寫本頁) 經濟部中央標準局*:工消費合作社印製 經濟部中央標準局員工消费合作社印製 A7 ____B7_ 五、發明説明（7 ) 號之時序時於共同閘極1 4上施加信號傳送脈波，使信號 傳送電晶體1 0 _ 1 ，1 0 — 2 .........導逋’即可將出現 在垂直信號線8 — 1 ，8_2 ..........之電壓傳送至放大 信號儲存電容器1 1 — 1 ，1 1 — 2..........而儲存。 水平位址電路13依次選擇每一條水平線需要讀出之 圖素位置。在讀出具有n xm結構（η行m列結構）之圖 素時，產生水平位址脈波，以便對應於1條水平線之讀出 掃描速度，使相當於當時之掃描位置之圖素位置之水平選 擇電晶體1 2 — 1 ，1 2-2 ..........成爲主動· 因此，在讀出具有n xm結構（η行m列）之圖素時 ，可控制依次改變線位置同時讀出該線之圖素之信號。 以下參照第2圖之時序圖說明該MO S型固體攝像裝 置之動作。 從垂直位址電路5施加使該垂直位址線6 - i成爲高 位準之位址脈波於垂直位址線6 — i後，只有該行之選擇 電晶體3 — i — 1 ，3 — i — 2 .........成爲導通，而由該 行之放大電晶體2 — i — 1 ，2_ i — 2 ..........及負載 電晶體9 — 1 ，9_2 .........形成源極跟隨電路。 因此，與放大電晶體2 — i — 1 ，2 — i — 2 ......... 之閘極電壓，亦即與感光二極體1 一 i — l ，1 — i-2 ..........之電壓大致相同之電壓出現於垂直信號線8 - 1 t Q — 2 * ♦畢· a · 〇 此時，若在信號傅送電晶體10— 1 ，10 — 2…… …之共同閘極1 4上施加信號傅送脈波後，在放大信號儲 本紙張尺度遑用中國國家梂準（CNS)A4规格（ 210X297公釐）-10 - ---------批衣------1T------線 (請先閱讀背面之注意事I 填寫本頁) 經濟部中央標準局員工消費合作杜印製 A7 ____B7_ 五、發明説明（8 ) 存電容器1 1 — 1 ，1 1 — 2 .........中儲存由出現於垂直 信號線8 - 1 ，8 - 2..........之電壓與其電容之積所表 示之被放大之信號電荷。 在放大信號儲存電容器1 1 — 1，1 1 一 2.......... 中儲存信號電荷之後，垂直位址電路5在復置線7 — i上 施加復置脈波*該復置脈波使復置電晶體4 一 i 一1 ，4 一 i— 2導通，儲存於感光二極體1 — i — 1 ，1 — i 一 2 .........之信號電荷經由復置電晶體4 — i 一 1 ，4一 i 一 2放電。因此，感光二極體1 一 i — l ，1 — i— 2… ......被復置。 然後，從水平位址電路1 3依次在水平選擇電晶體 1 2 — 1 ，1 2 - 2..........上施加水平位址脈波。此時 ，在施加水平位址脈波之期間內，水平選擇電晶體1 2 — 1*12-2 .........成爲導通。儲存於放大信號儲存電容 器1 1 一 1 ，1 1 一 2 .........之信號電荷通過成爲導通之 水平選擇電晶體1 2 _ 1，1 2 - 2 ..........從儲存信號 输出端（水平信號線）1 5輸出。如此，可產生做爲输出 信號之相當於1行之畫像信號。 依次在下一條行（水平線），下下一條行繼績進行該 動作，即可讀出配置成2次元狀之感光二極體之全部信號 如此，依次改變線位置而進行讀出控制’即可依次產 生相當於1個畫面之畫像信號，而連續的進行該動作，即 可產生動畫像。 本紙張尺度遴用中國國家標準（CNS)A4現格（ 210X297公釐）-11 - ---------姑衣------1T------^ (請先閱讀背面之注意事項%寫本頁) / A7 B7 五、發明説明（9 ) 上述習用之MO S型固體攝像裝置之單位晶胞p 〇 _ i — j必須具有放大來自感光二極體1 — i _ j之電荷信 號之放大電晶體2 - i - j ，選擇讀出信號之線之垂直選 擇電晶體3 — i _ j ，將放大電晶體之閘極充放電之復置 電晶體4 一 i — j等總共3個電晶體。亦即習用之MOS 型固體攝像裝置具有相當於單位圖素之受光部之每一個感 光二極體3個電晶體之結構，故不容易將單位晶胞微細化 ，亦即將攝像裝置本身微細化。 經濟部中央標準局員工消費合作社印製 又因爲利用放大電晶體2 _ i — j放大並输出電荷信 號，故又有該放大電晶體2 — i — j所造成之雜訊等問題 。亦即，放大電晶體2 — i — j係設在做爲圖素之每一單 位晶胞中，但當感光二極體不接受光線時，放大電晶體仍 然產生输出。其原因係因爲放大電晶體之特性上，不能避 免之暗電流，熱雜訊，及閾值電壓之不均勻所造成。這種 現象係成爲矩陣配置之各圖素晶胞分別具有之不同之固有 特性。故即使將均勻之光線照射在全部受光面上*各圖素 所產生之畫像信號之位準皆不相同，變成亮度不均勻之畫 像信號•該亮度不均勻之盡像係雜訊成爲二次元狀的分佈 之雜訊，亦即分布在畫面平面之雜訊，在場所上成爲固定 ，因此被稱爲固定圖型雜訊。該雜訊之問題非常嚴重’若 圖素更微細化時變成更顯著。故使用於攝像時若不改善’ 則不能實用。 本發明之第1目的爲提供一種使用可微細化’可實現 小型化及單一電源化之放大型MO S型固體攝像裝置之各 」 (請先閲讀背面之注意事填寫本頁) 本紙張尺度逋用中國國家標準（CNS)A4規格（ 210X 297公釐）-12- 306073 A7 B7 五、發明説明（l〇 ) 種應用裝置》 本發明之第2目的爲提供一種可產生不受雜訊之影像 ，良好之畫像信號之具有雜訊消除電路之放大型MO S型 固體攝像裝置及其應用裝置。又提供一種可產生不受雜訊 之影響，良好之畫像信號之雜訊消除方法。 本發明包括如下之內容， 本發明之畫像系統之特徵爲包括：具有將光學像導引 至一定位置之光學系統，及將被導引至上述一定位置之光 學像以圖素單位光電變換成對應於上述光學像之光量之電 氣信號之偵測器之畫像處理裝置：具有將該盡像處理裝置 之输出加工成一定型態而输出之信號加工部，上述偵測器 包含配置於上述一定位置之光電變換元件，及連接於該光 電變換元件之放大MO S電晶體，在第1時序時放大並輸 出上述光電變換元件之輸出，在第2時序時輸出與上述光 電變換元件之輸出無關之雜訊之輸出電路；及連接於該輸 出電路之輸出端，從在上述第1及第2時序時之上述輸出 電路觀察之電感相等，而且產生在上述第1及第2時序時 之上述輸出電路之輸出之差值之雜訊去除電略。該裝置係 以電感相同爲特徵之光學系統。 本發明之畫像系統之特徵爲包括具有接受來自被攝體 之光學像•將該光學像導引至一定位置之光學系統，及將_ 上述被導引至一定位置之光學像以圖素單位光電變換成對 應於上述光學像之光量之電氣信號之偵測器之盡像處理裝 置，及將該畫像處理裝置之輸出加工成一定型態而輸出之 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）-13 - ---------#------iT------線 (請先閣讀背面之注意事¾¼寫本頁) 一 經濟部中央標準局貝工消费合作社印製 經濟部中央標準局員工消费合作社印裝 A7 B7 五、發明説明（11 ) 信號加工部，上述偵測器包括：配置於上述一定位置之光 電變換元件；具有連接於該光電變換元件之放大M0 5電 晶體，在第1時序時放大並輸出上述光電變換元件之輸出 ，在第2時序時輸出與上述光電變換元件之輸出無關之雜 訊之输出電路；連接於上述輸出電路之信號線：一端連接 於上述信號線之箝位電容器；連接於該箝位電容器之另一A7 _____B7_ printed by the Employees ’Consumer Cooperative of the Central Department of Economic Affairs of the Ministry of Economic Affairs 5. Description of the invention (1) The present invention relates to a solid-state imaging device composed of an amplified MO S detector that amplifies signal charges in a unit cell and uses solid-state imaging Device system. In recent years, due to advances in the technology of semiconductor devices, the appearance and weight of video cameras have become smaller, portable, and widely used. In electronic devices, the battery is a battery because of the need for portability, but the imaging element of a conventional video camera uses a CCD detector. When driving a device, a CCD detector needs to use many kinds of voltages, so a power supply circuit that generates the voltage from the battery voltage is required. The above factors have hindered the further miniaturization of the video camera, and have also prevented the reduction of power consumption. the reason. In order to make it easier to operate, we have been studying the compactness and weight reduction of video cameras, and we are developing solid-state camera devices with more pixel numbers. Furthermore, a solid-state imaging device with low power consumption and low voltage must be used. If the solid-state imaging device is simply miniaturized and multi-pixelized, the pixels need only be miniaturized. However, if the pixels are miniaturized, a problem occurs that the amount of charge of the processed signal per pixel decreases. Therefore, the dynamic range of the solid-state imaging device is reduced, and a clear and good-resolution image cannot be formed. If CCD is used, because of the use of many types of voltage drive components, the structure and operation of the camera system cannot be handled with a simple system. That is, in order to be applied to a portable camera and a camera with a personal computer, a paper standard with a low power consumption and a low power consumption and a good S / N is required to use the Chinese National Falcon (CNS) A4 specification ( 210X 297 mm) _ 4-— III Kunyi I1T— IIII —- ^ (please read the notes on the back first _ write this page) 306073 Seal of the Workers ’Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention Description (2 ) 1 | Solid-state imaging device with a single power supply. However, the CCD cannot be driven by a single power supply 1 1 »Not only can it not display low power consumption and low operating voltage, but also because the S / Ν deterioration after the refinement of the Ί pixel> cannot be Meet the above requirements 〇1 | Please 1 1 other devices that can meet the above requirements 9 can also achieve low power consumption first reading 1 I read 1 and low use voltage 9 solid-state imaging devices that can be driven by a single power supply for back t6 1 I With enlarged type Attention of the Μ 0 S detector of the body 1 1 | The special feature of this solid-state imaging device is the amplification of the transistor to the photosensitive diode S .. 1 1 I The signal detected by the body in each unit cell > its sensitivity is high 〇Writing book 1% Μ 0 S detector is different from the CCD detector using a special process y page 'w «, 1 1 is produced using the commonly used Μ 0 S 1 1 process such as DRA Μ semiconductor memory» processor. Therefore »Μ 0 S detector is easily formed on the same semiconductor die as the semiconductor memory 1 | body or processor and it is easy to share the same production line as the semiconductor memory and processor 1 1 1 However, the above use The conventional MOS detector (1 1 I amplified MOS detector) for amplifying transistors is not easy to remove the uneven brightness of 1 1 called the fixed pattern noise. In addition, the dynamic range line 1 of the output of the amplified Μ 0 S detector is only about 6 0 d Β if it is compared with the 90 0 d Β of the silver salt film and the 7 0 d B of the CCD 1 1 detector * extremely inadequate 9 Therefore 9 When this magnifying type 1 | Μ 0 S detector is installed in a video camera and other image system devices, its 1 I image quality is extremely limited in its use. 0 I 1 I The first picture shows the use of The conventional solid-state camera of the large-scale Μ 0 S detector '1 1 The circuit diagram of the device. The circle is arranged in a 2-dimensional matrix in the longitudinal 1 horizontal direction. 1 1 corresponds to the unit cell P 0 -i-j of the pixel. In the table, only 7TC 2 X 2 1 1 > but in fact the arrangement of the number of 4 X number of 4 〇1 indicates the level (1 1 paper size using the Chinese National Standard (CNS) A4 specification (210X297 mm) -5-A7 B7 printed by the Employee Consumer Cooperative of the Central Department of Economics of the Ministry of Economy V. Description of the invention (3) row) direction variable, j represents the variable in the vertical direction * each unit crystal The cell ρο-i — j is composed of a photodiode l_i_j, an enlarged transistor 2 — i — j, a vertically selected transistor 3 — i — j, and a reset transistor 4 — i — j. In order to select the unit cells P 〇— 1 — 1 ..... ρ 〇 — i — j arranged in a 2-dimensional matrix in turn, the vertical Address circuit 5 and horizontal address circuit 1 3. The vertical address circuit 5 has unit cells P 〇- 1 — 1 ′ that are arranged in a matrix of two dimensions corresponding to the structure of n xm. * Ρ 〇 — i — j * ... The number of horizontal arrangement (the number of arrangement in the horizontal direction) of η is the pair of address output terminals and reset signal terminals, and the horizontal address circuit 13 has a number of 2-dimensional matrix corresponding to the n xm structure The unit cells P arranged in the shape of P 〇-1 1 1... Ρ 〇-i-j ......... The number of longitudinal arrangements (the number of arrangements in the vertical direction) of m Address output terminal. m, η, i 'j are arbitrary integers. Along the unit cells P〇1-1—1 ′ P〇 一 1-2 that are arranged in the horizontal direction ..., ρ 〇-2—j ... from vertical The address circuit 5 faces the horizontal direction and sequentially arranges 1 vertical address line 6_1, 6-2 ..................... each vertical address line 6-1, 6-2 '... ..... are respectively connected to the corresponding one of the n address output terminals of the vertical address circuit 5. Along the unit cells arranged in the horizontal direction Ρ 0-1 1-1, Ρ — 1 — 2 ...., ρ 〇 — 2 — j .... ,, From the vertical address circuit 5 toward the horizontal direction, one reset signal line 7 a 1 '7-2 ........... each reset signal line 7-1, 7-2 ... ........ (please read the notes on the back-and fill in this page). The paper size of the binding book is applicable to China National Standard (CNS) A4 (210X297mm) -6-B7 Ministry of Economic Affairs Printed by the Central Bureau of Precision Industry Beigong Consumer Cooperative V. Description of the invention (4) Connected to the corresponding pig terminals among the n complex reset terminals of the vertical address circuit 5 respectively. Unit cells arranged in the vertical direction Ρ 0 — 1 — 1 P 〇-1 -2 9 · · · · »p Q-2-J · · · · ... 9 from the horizontal address circuit 13 toward the vertical direction Sequentially arrange vertical signal lines 8-1 > 8-2, ·········································· connected to m addresses of the horizontal address circuit 13 respectively Corresponding to the output terminals-a terminal 0 is arranged from the vertical address circuit 5 to the horizontal vertical address lines 6-1, 6-2 .... connected to the unit cells of each row Vertical selection. Transistor 3-1-1 ........... determines the horizontal line of the read signal. Similarly, the vertical address circuit 5 is arranged in the horizontal reset lines 7 -1, 7-2........ Are respectively connected to the corresponding reset transistors 4 -1-1 of each row .......... The trouble. The photodiode 1-i-j that detects the incident light forms a light-receiving part that detects the incident light, and generates a signal charge corresponding to the amount of received light. One pixel is formed by one photodiode. The amplifying transistor 2 — i — j amplifies the signal charge generated by the photodiode l_i — j and uses it as a detection signal output. Because the cathode of the photodiode l_i_j is connected to its own gate to amplify the signal charge of the photodiode 1_i_j »The amplified output corresponding to the signal charge is used as the detection signal to generate a vertical signal on the side of the absorber. Select transistor 3 —i — j between its source and sink connected to the DC system power supply and amplifier transistor 2 — i — j between the sink side, and its gate connected to the vertical address The paper size of the vertical address line of circuit 5 is applicable to the Chinese National Standard (CNS> A4 specification (210X297mm) * 7 _ A7 __B7_ V. Description of invention (5) 6 — j. Reset transistor 4-i- The source and the sink of j itself are connected between the system power supply of DC and the cathode of the photodiode 1-i-j. During operation, the signal charge of the photodiode 1-i _ j is reset Specifically, the source of the vertical selection transistor 3 — i-j and the source of the reset transistor 4 — i — j are connected to the sink voltage terminal of the DC system power supply in order to supply the sink voltage. As above Place ， Vertical address line 6 from the vertical address circuit 5 toward the horizontal direction 6 6-2 9 ······ _ ·· Vertical selection transistor 3 — 1_1 connected to the unit cell of each row ... For the decision to read, please read the horizontal line of the back-packing signal for% 2. Similarly, the reset line 7-7-2 wired from the vertical address circuit 5 to the horizontal direction is connected to the reset electric crystal of each row 4-1-1, therefore, when reading pixels with an n xm structure (the arrangement structure of n rows and m columns), in order to make the horizontal line of the n line (row direction) Line) becomes active according to its read scan sequence, the vertical address circuit 5 makes the vertical address lines 6-1-6-2 ......... in turn become active, and in order to reset the signal charge of the pixels The signal is output to the output terminal. The image detection unit is described above. In addition to the image detection unit, there is an f output unit that reads the image detected by the image detection unit. The output unit is composed of load transistors 9-1, 9 — 2 ........... signal transmission transistor 10 — 1-10-2 * .......... storage capacity 11 — 1 , 11-2 ........... Horizontal selection transistors 12-1, 12-2 constituted • Its structure is as follows. This paper scale uses the Chinese National Standard (〇 犯) 84 specifications (2 丨0 / 297mm) _8_ Printed and printed on A7 306073 ___B7_ by the Workers ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ___B7_ V. Description of the invention (6) That is, the magnified electric crystal hips of the unit cells of each row 2 — 1-1 * 2- 1-2 The source of .......... is connected to the vertical signal lines 8 — 1, 8 _ 2 .......... which are arranged in the column direction, and the corresponding column . Each unit cell corresponding to each column is provided with one load transistor 9 _ 1, 9-2 1 .......... vertical signal lines 8-1, 8-2 ....... ... One end is connected to the DC system power supply through the corresponding one of the load transistors 9-1, 9_2 ........., and the source and sink of the load transistor. Vertical signal lines 8-1, 8-2 ... The other end of the vertical signal line is fed to the crystal 10_1, 10-2 by inputting a signal equivalent to a signal of one line. The corresponding transistor in it is connected to the storage capacitor 1 1-1, 1 1-2 ... which corresponds to one line of signal, and it corresponds to the capacitor in the horizontal address circuit. 1 3 The horizontal selection transistors 12-1 and 12-2 selected by the supplied horizontal address pulse wave are connected to the signal output terminal (horizontal signal line 15). That is, the other end of the vertical signal line 8-1, 8-2 ......... transmits the transistor through the signal 1 0-1, 1 0-2 .... The source and sink of the corresponding transistor are connected to one end of the storage capacitor corresponding to the storage capacitor 11-1, 11-2, ..., and the transistor 1 is selected via the level — 1, 1 2 — 2 .......... The source and sink of the corresponding one of the transistors are connected to the signal output (horizontal signal line) 1 5. The other end of each storage capacitor 1 1-1, 1 1-2, ......... is grounded, and the signal-transmitting transistor 1 0-1, 1 0 -2 ....... ... the gate is connected to the common gate 14. The Chinese national standard (CNS) A4 specification (210X297 mm) is applicable when the paper size of the letter to be transmitted is _ 9---------- ^ ------ 1T ------ ^ (please Read the notes on the back first.% Write this page) Central Bureau of Standards of the Ministry of Economic Affairs *: printed by the industrial and consumer cooperatives The Central Standards Bureau of the Ministry of Economic Affairs printed the A7 ____B7_ printed by the employee consumer cooperatives A signal transmission pulse wave is applied to the pole 14 to make the signal transmission transistor 1 0 _ 1, 1 0-2 ......... the guide will appear on the vertical signal line 8-1, 8_2. The voltage of ... is transmitted to the amplified signal storage capacitor 1 1-1, 1 1-2. ......... and stored. The horizontal address circuit 13 sequentially selects the pixel position to be read for each horizontal line. When reading pixels with n xm structure (n rows and m columns structure), a horizontal address pulse wave is generated so as to correspond to the reading scanning speed of one horizontal line, so that the pixel position corresponding to the scanning position at that time Horizontal selection transistors 1 2-1, 1 2-2 .......... become active. Therefore, when reading out pixels with n xm structure (n rows and m columns), it can be controlled to change sequentially The line position simultaneously reads the signal of the pixels of the line. The operation of the MO S solid-state imaging device will be described below with reference to the timing chart of FIG. 2. After the vertical address line 6-i is applied to the high-level address pulse from the vertical address circuit 5 after the vertical address line 6-i, only the row select transistors 3-i-1, 3-i — 2 ......... becomes conductive, and the transistor 2 — i — 1, 2_ i — 2 ... and the load transistor 9 — 1 are amplified by the line 9_2 ......... form a source follower circuit. Therefore, the gate voltage of the amplifying transistors 2 — i — 1, 2 — i — 2 ..., that is, the photodiode 1 — i — l, 1 — i-2. ......... The voltage is almost the same as the voltage appears on the vertical signal line 8-1 t Q — 2 * ♦ Bi · a · 〇 At this time, if the signal is sent to the power transmission crystal 10-1, 10-2 … After applying a signal to the common gate 14 to send a pulse wave, use the Chinese National Standard (CNS) A4 specification (210X297mm) -10------- --- approved clothing ------ 1T ------ line (please read the notes on the back first I fill in this page) Employee consumption cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs du printed A7 ____B7_ V. Description of invention ( 8) The storage capacitor 1 1 — 1, 1 1 — 2 ......... is stored by the voltage appearing on the vertical signal line 8-1, 8-2 .... The amplified signal charge represented by the product of capacitance. After storing the signal charge in the amplified signal storage capacitors 1 1-1, 1 1-2 ...., the vertical address circuit 5 applies a reset pulse on the reset line 7-i The reset pulse wave turns on the reset transistors 4-i-1, 4-i-2 and stores the signal in the photodiode 1-i-1, 1-i-2 ......... The charge is discharged through the reset transistors 4-i-1, 4-i-2. Therefore, the photodiodes 1-i-l, 1-i-2 ... are reset. Then, the horizontal address pulses are applied to the horizontal selection transistors 1 2-1, 1 2-2 .... from the horizontal address circuit 13 in sequence. At this time, during the period of applying the horizontal address pulse wave, the horizontal selection transistor 1 2-1 * 12-2 ......... becomes conductive. The signal charge stored in the amplified signal storage capacitors 1 1-1, 1 1-2 ......... selects transistors 1 2 _ 1, 1 2-2 by becoming conductive levels .... From the storage signal output terminal (horizontal signal line) 15 output. In this way, a picture signal equivalent to one line can be generated as an output signal. In turn on the next line (horizontal line), the next line continues to perform this action, you can read out all the signals of the photosensitive diodes configured in a 2-dimensional shape. In this way, change the line position in turn to perform readout control. An image signal equivalent to one screen is generated, and the motion is continuously performed to generate an animated image. The size of this paper is based on the Chinese National Standard (CNS) A4 (210X297mm) -11---------- Guyi ------ 1T ------ ^ (please first Read the notes on the back% to write this page) / A7 B7 5. Description of the invention (9) The unit cell p _ i — j of the above-mentioned conventional MO S-type solid-state imaging device must have magnification from the photosensitive diode 1 — i _ j Amplified transistor 2-i-j of the charge signal, select the vertical selection transistor 3-i _ j of the readout signal line, reset transistor 4-i-which charges and discharges the gate of the amplified transistor j and so on a total of 3 transistors. That is, the conventional MOS type solid-state imaging device has a structure equivalent to three transistors for each light-sensitive diode of the light-receiving portion of the unit pixel, so it is not easy to miniaturize the unit cell, that is, to miniaturize the imaging device itself. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Because the amplifier transistor 2_i — j is used to amplify and output the charge signal, there are also problems such as noise caused by the amplifier transistor 2 — i — j. That is, the amplifying transistor 2-i-j is set in each unit cell as a pixel, but when the photosensitive diode does not receive light, the amplifying transistor still produces output. The reason is because of the dark current, thermal noise, and non-uniformity of the threshold voltage that cannot be avoided due to the characteristics of the amplifying transistor. This phenomenon becomes the different inherent characteristics of each pixel unit of the matrix configuration. Therefore, even if the uniform light is irradiated on all the light-receiving surfaces, the level of the image signal generated by each pixel is different, and it becomes an image signal with uneven brightness. The image with uneven brightness is a second-order element. The distributed noise, that is, the noise distributed on the screen plane, becomes fixed on the place, so it is called fixed pattern noise. The problem with this noise is very serious. It becomes more pronounced when the pixels are more refined. Therefore, it is not practical if it is not improved when used in video shooting. The first object of the present invention is to provide a miniaturized 'MOS type solid-state imaging device that can achieve miniaturization and single power supply' (please read the precautions on the back and fill in this page first). Use the Chinese National Standard (CNS) A4 specification (210X 297mm) -12- 306073 A7 B7 5. Description of the invention (10) kinds of application devices "The second object of the present invention is to provide an image that can be generated without noise , Amplified MO S-type solid-state imaging device with noise cancellation circuit and its application device with good image signal. It also provides a noise-removing method that can produce a good picture signal without being affected by noise. The present invention includes the following contents. The portrait system of the present invention is characterized by including: an optical system that guides an optical image to a certain position, and photoelectric conversion of the optical image guided to the certain position into corresponding units in pixel units The image processing device of the detector for the electrical signal of the light quantity of the optical image: having a signal processing section that processes the output of the image processing device into a certain type and outputs it, the detector includes The photoelectric conversion element and the amplifying MOS transistor connected to the photoelectric conversion element amplify and output the output of the photoelectric conversion element at the first timing, and output noise unrelated to the output of the photoelectric conversion element at the second timing The output circuit connected to the output terminal of the output circuit, the inductance observed from the output circuit at the first and second timings is equal, and the output of the output circuit at the first and second timings is generated The noise of the difference is removed. The device is an optical system characterized by the same inductance. The image system of the present invention is characterized by including an optical system that accepts an optical image from a subject. The optical image is guided to a certain position, and the above-mentioned optical image guided to a certain position is photoelectric in pixel units The image processing device that converts the electrical signal into the electrical signal corresponding to the light quantity of the above-mentioned optical image, and processes the output of the image processing device into a certain type and outputs the paper standard that conforms to the Chinese National Standard (CNS) A4 specification (210X297mm) -13---------- # ------ iT ------ line (please read the notes on the back first ¾¼ write this page) 1. The Ministry of Economic Affairs Printed by the Bureau of Standards, Peking Consumer Cooperatives, printed by the Central Bureau of Economics of the Ministry of Economics, printed by employees of the Consumer Cooperatives A7 B7 V. Description of the invention (11) The signal processing section, the above detectors include: photoelectric conversion elements arranged at certain positions above; The amplifying M0 5 transistor of the photoelectric conversion element amplifies and outputs the output of the photoelectric conversion element at the first timing, and outputs an output circuit that outputs noise that is unrelated to the output of the photoelectric conversion element at the second timing; it is connected to the above The signal line of the output circuit: one end is connected to the clamping capacitor of the above signal line; the other is connected to the clamping capacitor

I 端與一定電位之間之樣品保持電容器；將小於上述箝位電 容器與上述樣品保持電容器之串聯電容量之2倍之電容量 選擇性的施加於上述信號線與一定電位之間之電感修正電 路；及產生在上述第1及第2時序時之上述輸出電路之輸 出之差值之雜訊去除電路。該裝置爲以電感修正之概念爲 特徵之光學系統。 本發明之另一畫像系統之特徵爲包括具有接受來自被 攝體之光學像，將該光學像導引至一定位置之光學系統， 及將被導引至該一定位置之光學像以圚素單位光電變換成 對應於該光學像之光置之電氣信號之偵測器之畫像處理裝 置，及將該畫像處理裝置之輸出加工成一定型態輸出之信 號加工部，該偵測器包括：配置在該一定位置之光電變換 元件；包含連接於該光電變換元件之放大MO S電晶體， 在第1時序時放大並输出上述光電變換元件之輸出，在第 2時序時输出與該光電變換元件之輸出無關之雜訊之输出 電路：連接於該输出電路之輸出端之信號線；输入端連接 於該信號線之源極跟隨電路：一端連接於該源極跟隨電路 之输出端之箝位電容器；連接於該箝位電容器之另一端與 本紙張尺度遑用中國國家樣準（CNS)A4規格（ 210X297公釐）_ - t衣-- (請先閱讀背面之注意事項一 ,^'寫本頁) 訂 經濟部中央橾準局員工消費合作杜印裝 A7 ____B7____ 五、發明説明（i2) 第1一定電位之間之樣品保持電容器：連接於上述箝位電 容量之另一端與第2 —定電位之間*選擇性的箝位該樣品 保持電容器之箝位電容器。該裝置係以可重叠電容量之電 路及源極跟隨器爲特徴之光學系統。 本發明之另一畫像系統之特徴爲包括：具有接受來自 被攝體之光學像，將該光學像導引至一定位置之光學系統 ’及將被導引至該一定位置之光學像以圖素單位光電變換 成對應於該光學像之光量之電氣信號之偵測器之畫像處理 裝置；及將該畫像處理裝置之輸出加工成一定型態輸出之 信號加工部，該偵測器包括：配置在該一定位置之光電變 換元件；包含連接於該光電變換元件之放大MO S電晶體 *在第1時序時放大並輸出該光電變換元件之輸出，在第 2時序時输出與該光電變換元件之输出無關之雜訊之输出 電路；連接於該輸出電路之输出端之信號線；一端連接於 該信號線之箝位電容器：連接於該箝位電容器之另一端與 第1 —定電位之間之樣品保持電容器：及連接於該箝位電 容器之另一端與第2 —定電位之間，以一定之時序箝位該 樣品保持電容器之箝位電晶體。該裝置可應用於以可重疊 電容量之電路爲特徵之全部光學系統。 本發明之另一畫像系統之特徵爲包括：具有接受來自 被攝體之光學像，將該光學像導引至一定位置之光學系統· ，及將被導引至該一定位置之光學像以圖素單位光電變換 成對應於該光學像之光童之電氣信號之偵測器之畫像處理 裝置；及將該畫像處理裝置之输出加工成一定型態而輸出 本紙張尺度適用中國固家標準（CNS)A4規格（ 210X297公釐）-15 - ---------坤衣------，訂------ii (請先閱讀背面之注意事項厂‘寫本頁) " 經濟部中央樣準局貝工消费合作社印製 A7 B7 五、發明説明（13 ) 之信號加工部，該偵測器包括：在第1時序時输出對應於 雜訊及該光量之電壓，在第2時序時输出對應於該雜訊之 電壓之圖素；具有供給該圖素之輸出之第1節，儲存電荷 之第2節，從該第2節傳送根據該第1節之電位控制之一 定量之電荷之第3節之3端子元件；及產生在該第1及第 2時序時之該圖素之輸出之差值之雜訊去除電路。該裝置 係以使用3端子雜訊消除電路爲特徵之光學系統。 本發明之另一晝像系統之特徵爲包括：具有接受來自 被攝體之光學像，將該光學像導引至一定位置之光學系統 ，及將被導引至該一定位置之光學像以圖素單位光電變換 成對應於該光學像之光量之電氣信號之偵測器之畫像處理 裝置；及將該畫像處理裝置之输出加工成一定型態输出之 信號加工部，該偵測器包括：在第1時序時输出對應於雜 訊及該光量之電壓，在第2時序時输出對應於該雜訊之電 壓之圖素；及输出配合在該第1時序時之該圔素之输出電 壓之電荷量，及配合在該第2時序時之該圖素之输出電壓 之電荷量之差之雜訊去除電路。 本發明之另一畫像系統之特徵爲包括：具有接受來自 被攝體之光學像，將該光學像導引至一定位置之光學系統 ，及將被導引至該一定位置之光學像以圖素單位光電變換 成對應於該光學像之光量之電氣信號之偵測器之畫像處理 裝置；及將該畫像處理裝置之输出加工成一定型態而輸出 之信號加工部，該偵測器包括：在第1時序時輸出對應於 雜訊及該光量之第1電氣信號，在第2時序時输出對應於 本紙張尺度遑用中國國家標準（CNS)A4規格（ 210X 297公釐）-16 - ---------批衣------1T------^ (請先閱讀背面之注意事¾..¼寫本頁) * 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（14 ) 該雜訊之第2電氣信號之圖素；及以相同之输入阻抗输入 該第1及第2電氣信號，並輸出該第1與第2電氣信號之 差值之雜訊去除電路。 本發明之另一盡像系統之特徵爲包括：具有接受來自 被攝體之光學像，將該光學像導引至一定位置之光學系統 ;及將被導引至該一定位置之光學像以圖素單位光電變換 成對應於該光學像之電氣信號之偵測器之畫像處理裝置； 及將該畫像處理裝置之輸出加工成一定型態输出之信號加 工部，該畫像處理裝置之輸出動態範圍爲7 0 d B以上。 本發明之畫像系統之特徵爲：該偵測器之输出爲電壓 信號，該畫像處理裝置又包括供給上述偵測器之输出之電 壓-電流變換電路，供給該電壓-電流變換電路之輸出之 電流-電壓變換電路，將該電流-電壓變換電路之输出以 對應於所需靈敏度之增益放大之放大電路，及箝位該放大 電路之输出之箝位電路· 本發明之另一畫像系統之特徵爲該信號加工部具有對 該盡像處理裝置之输出實施一定之製程處理之製程電路， 及將該製程電路之输出變換成複合影像信號之編碼器。 本發明之另一畫像系統之特徵爲，該光學系統包括將 該光學像聚焦之透鏡，調整對該畫像處理裝置之入射光量 之光圈調整裝置，調整該透鏡與許多畫像處理裝置之距離 之聚焦調整裝置，及將該透鏡所聚焦之光學像依照波長分 光成許多光學像，將被分光之光學像供給於許多畫像處理 裝置之分光裝置。 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X 297公釐）-17 - ---------批衣------.玎------^ (請先閱讀背面之注意事ΓΙ-.‘，，填寫本頁) 一 經濟部中央標準局負工消費合作社印製 A7 __B7_ 五、發明説明（15 ) 本發明之另一畫像系統之特徵爲又具有在上述被攝體 上照射光線之光源，該信號加工部包含根據該畫像處理裝 置之输出印刷對應於該被攝體之畫像之印刷裝置，該光學 像爲該光源之光線射在該被攝體而反射之反射光。 本發明之另一畫像系統之特徵爲又具有在該被攝體上 照射光線之光源，該信號加工部包含將該畫像處理裝置之 输出俥送至電話線路之信號變換用數據機，該光學像係該 光源之光線照射在該被攝體上而反射之反射光。 本發明之另一查像系統之特徴爲又具有在該被攝體上 照射光線之光源，使該被攝體與該光源相對的移動之移動 裝置，及檢測該被攝體與該光源之位置關係之位置檢測裝 置，該信號加工部以該位置檢測裝置之输出加工該畫像處 理裝置之输出，該光學像爲該光源之光線照射在該被攝體 上而反射之反射光。 本發明之另一盡像系統之特徵爲，在該畫像處理裝置 中，該畫像朝向一定方向排列成一次元，該光學系統包含 可由移動裝置驅動而移動之透鏡，與該透鏡相距某距離設 在該偵測器側，將該透鏡所產生之光線朝向該一定方向2 分割而供給於該偵測器之一對分離透鏡，該信號加工器檢 測被2分割之該分離透鏡所產生之光線之焦點位置間之距 離，根據該檢測結果產生驅動該移動裝置之信號。 本發明之另一畫像系統之特徵爲又具有在該被攝體上 照射光線之光源，該被攝體爲設在該光源與該偵測器之間 ，已攝影影像之薄膜。 本紙張尺度適用中國國家橾準（CNS)A4規格（210X297公釐）-18 - ---------^------1T------^ (請先閱讀背面之注意事I , 兴寫本頁) * 經濟部中央標準局貝工消费合作杜印製 A7 B7 五、發明説明（I6) 本發明係關於固體攝像裝置，該固體攝像裝置之特徵 爲包括：光電變換元件；具有連接於該光電變換元件之放 大MO S電晶體，在第1時序時放大並輸出該光電變換元 件之输出，在第2時序時輸出與該光電變換元件之輸出無 關之雜訊之输出電路；及連接於輸出電路之输出端，從在 第1及第2時序時之該输出電路觀察之阻抗相等，產生在 該第1及第2時序時之該输出電路之輸出之差值之雜訊去 除電路。依照該結構，其特徵爲又具有連接該輸出電路與 該雜訊去除電路之信號線。該雜訊去除電路具有一端連接 於該信號線之箝位電容器，連接於該箝位電容器之另一端 與箝位電位之間，選擇性的成爲導通之箝位電晶體•連接 於該箝位電容器之另一端與一定電位之間之樣品保持電容 器，及連接於該信號線與一定電位之間之阻抗修正電路· 其特徵又爲該阻抗修正電路具有當該箝位電晶體成爲非導 通時選擇性的成爲導通之轉換元件，及串聯於該轉換元件 ，具有與該箝位電容器與該樣品保持電容器之串聯電容量 相等之修正電容量。該雜訊去除電路具有閘極連接於該信 號線之限幅電晶體（Slice Transistor)，從該輸出電路 觀察之阻抗爲該限幅電晶體之閘極電容量。該雜訊去除電 路又具有連接於該限幅電晶體之源極與限幅脈波供給端子 之間之限幅電容器，及連接於該限幅電晶體之吸極與一定^ 電位之間，充電該差值之限幅電荷傳送電容器。 本發明之另一固體攝像裝置之特徵爲包括：光電變換 元件；具有連接於該光電變換元件之放大MO S電晶體， 本紙張尺度適用中國國家標準（CNS)A4说格（ 210X 297公釐）-19 - 种衣 11 I ^ 11 I 線 (請先閱讀背面之注意事t 梹寫本頁) 成 A7 B7 306073 五、發明説明（17 ) 在第1時序時放大並輸出該光電變換元件之輸出，在第2 時序時輸出與該光電變換元件之輸出無關之雜訊之輸出電 路：連接於該输出電路之信號線；一端連接於該信號線之 箝位電容器；連接於該箝位電容器之另一端與一定電位之 間之樣品保持電容器；將小於該箝位電容器與該樣品保持 電容器之串聯電容量與該箝位電容量之差之2倍之電容選 擇性的施加於該信號線與一定電位之間之阻抗修正電路， 而且產生在該第1時序與第2時序時之該輸出電路之输出 之差值之雜訊去除電路。 本發明之另一固體攝像裝置之特徵爲包括：光電變換 元件；具有連接於該光電變換元件之放大MO S電晶體， 在第1時序時放大並輸出該光電變換元件之輸出*在第2 時序時輸出與該光電變換元件之輸出無關之雜訊之输出電 路；連接於該输出電路之輸出之信號線；輸入端連接於該 信號線之源極跟隨電路；一端連接於該源極跟隨電路之输 出端之箝位電容器；連接於該箝位電容器之另一端與第1 一定電位之間之樣品保持電容器：及連接於該箝位電容器 之另一端與第2 —定電位之間，選擇性的箝位樣品保持電 容器之箝位電晶體。以半導體積體電路元件形成固體攝像 裝置時，在其半導體積體電路元件構造中，該箝位電容器 與該樣品保持電容器在同一基板上平面的重叠而形成。 本發明之另一固體攝像裝置包括之光電變換元件；具 有連接於該光電變換元件之放大MO S電晶體’在第1時 序時放大並输出該光電變換元件之输出，在第2時序時输 ----------种衣------1T------^ {請先閱讀背面之注意事項4.¾本頁) ~ 經濟部中央標準局員工消費合作社印裝 本紙張尺度適用中國國家樣準（CNS > A4現格（2丨〇><297公釐） -20 - A7 B7 經濟部中央橾準局員工消費合作社印掣 五、 發明説明（1S ) 出 與 該光電變換元件 之 輸 出 撕 關 之 雜訊 之 輸 出 電 路 : 連 接 於 該 輸出電路之輸出 端 之 信 就 線 1 —*端 連 接 於 該 信 號 線 之 箝 位 電容器；連接於 該 箝 位 電 容 器 之另 — 端 與 第 1 —- 定 電 位 之 間之樣品保持電 容 器 連 接 於 該箝 位 電 容 器 之 另 —· 端 eta 與 第 2 —定電位之間 > 在 一 定 之 時 序時 箝 位 該 樣 品 保 持 電 容 器 之箝位電晶體。 本發明之固體攝 像 裝 置 之 特 徵 爲包 括 : 在 第 1 時 序 時 輸 出 配合雜訊及入射 光 之 電 壓 1 在 第2 時 序 時 输 出 配 合 該 雜 訊 之電壓之圖素； 及 包 含 具 有 供 給該 圖 素 之 輸 出 之 第 1 節 > 儲存電荷之第2 節 及 從 該 第 2節 傳 送 根 據 該 第 1 節 之 電 位控制之一定量 之 電 荷 之 第 3 節之 3 端 子 元 件 9 並 且 產 生 該第1與第2時 序 時 之 該 圖 素 之输 出 之 差 值 之 雜 訊 去 除 電 路。該3端子元 件 爲 以 該 第 1 節做 爲 閘 極 該 第 2 節 做 爲 源極，該第3節 做 爲 吸 極 之 Μ 0 S 電 晶 體 0 本發明之另一固 體 攝 像 裝 置 之 特徵 爲 包 括 ： 在 第 1 時 序 時 輸出配合雜訊及 入 射 光 之 電 壓 ，在 第 2 時 序 時 输 出 配 合 該 雜訊之電壓之圖 素 及 產 生 配 合在 第 1 時 序 時 之 該 圖 素 之 輸出電壓之電荷 量 與 配 合 在 第 2時 序 時 之 該 圖 素 之 输 出 電 壓之電荷童之差 之 雜 訊 去 除 電 路· 本發明之另一固 體 攝 像 裝 置 之 特徵 爲 包 括 ： 許 多 水 平 選 擇 線：與該水平選 擇 線 交 叉 之 許 多垂 直 信 號 線 f 設 在 該、 水 平 選擇線與該垂直 信 號 線 之 各 交 叉位 置 » 配 合 該 水 平 選 擇 線 之電位選擇性的 活 化 在 該 活 化期 間 內 之 第 1 時 序 時 將 配 合雜訊及入射光 之 第 1 電 氣 信 號輸 出 於 對 應 //G% 之 該 垂 直 頁 訂 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）_ 21 - 請 先 閲 讀 背 ιέ 之 注 意 事 項 J裝 經濟部中央標準局貝工消費合作社印製 306C73 A7 _B7_ 五、發明説明（19 ) 信號線，在該活化期間內之第2時序時，將配合該雜訊之 第2電氣信號输出於對應之該垂直信號線之許多圖素；及 設在許多垂直信號線之各一端上，以相同之输入阻抗輸入 該第1及第2電氣信號，並且輸出該第1與第2電氣信號 之差值之許多雜訊去除電路。 本發明之另一固體攝像裝置之特徴爲包括：許多水平 選擇線：與該水平選擇線交叉之許多垂直信號線；設在該 水平選擇線與該垂直信號線之各交叉點位置，配合該水平 選擇線之電位選擇性的活化，在該活化期間內之第1時序 時將配合雜訊及入射光之第1電氣信號输出於對應之該垂 直信號線，在該活化期間內之第2時序時將配合該雜訊之 第2電氣信號输出於對應之該垂直信號線之許多圇素：及 包含具有連接於許多垂直信號線之各一端之第1節，儲存 電荷之第2節，及從該第2節傳送根據該第1節之電位控 制之一定童之電荷之第3節之3端子元件，而且產生在該 第1及第2時序時之該圖素之輸出之差值之許多雜訊去除 電路。 本發明之另一固體攝像裝置之特徵爲包括：許多水平 選擇線；與該水平選擇線交叉之許多垂直信號線：設在該 水平選擇線與該垂直信號線之各交叉點位置，配合該水平 選擇線之電位選擇性的活化，在該活化期間內之第1時序 時將對應於雜訊及入射光之第1電應輸出於對應之該垂直 信號線，在該活化期間內之第2時序時將配合該雜訊之第 2電壓输出於對應之該垂直信號之許多圖素；及設在該垂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）_ 22 _ I I I I I I I I I 裝— — I I —訂 I I I I I 線 (請先閲讀背面之注意事項寫本頁) ™ 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（2〇 ) 直信號線之各一端，輸出配合該第1電壓之電荷量與配合 該第2電壓之電荷量之差之許多雜訊去除電路。 本發明之另一固體攝像裝置包括：許多水平選擇線； 與該水平選擇線交叉之許多垂直信號線；設在該水平選擇 線與該垂直信號線之各交叉位置，配合該水平選擇線之電 位選擇性的活化，在該活化期間內之第1時序時將配合雜 訊及入射光之第1電氣信號輸出於對應之該垂直信號線， 在該活化期間內之第2時序時將配合該雜訊之第2電氣信 號输出於對應之該垂直信號線之許多圖素：連接於許多垂 直信號線之各一端之許多箝位電容器；連接於許多箝位電 容器之各另一端與第1 一定電位之間之許多樣品保持電容 器；連接於許多箝位電容器之各另一端與第2—定電位之 間，在一定之時序時箝位對應之該樣品保持電容器之許多 箝位電晶體之許多雜訊去除電路。 本發明之另一固體攝像裝置之特徴爲包括：許多垂直 信號線：對應於各垂直信號線設置，在第1時序時將配合 雜訊及入射光之第1電氣信號輸出於對應之該垂直信號線 ，在第2時序時將配合該雜訊之第2電氣信號输出於對應 之該垂直信號線之許多圖素：設在許多垂直信號線之各一 端，以相同之輸入阻抗輸入該第1及第2電氣信號，並且 輸出該第1與第2電氣信號之差值之許多雜訊去除電路/ 本發明之另一固體攝像裝置之特徵爲包括：許多垂直 信號線；對應於許多垂直信號線設置，在第1時序時將配 合雜訊及入射光之第1電氣信號输出於對應之該垂直信號 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 23 - 批衣-- (請先閲讀背面之注意事項I. ,Λ寫本頁) 訂 經濟部中央橾準局員工消费合作社印製 306GV3 ^ B7 五、發明説明（21 ) 線，在第2時序時將配合該雜訊之第1電氣信號输出於對 應之該垂直信號線之許多圖素；及包含具有連接於許多垂 直信號線之各一端之第1節，儲存電荷之第2節，及從該 第2節傳送根據該第1節之電位控制之一定量之電荷之第 3節之3端子元件，並且產生在該第1與第2時序時之該 圖素之輸出之差值之許多雜訊去除電路。 本發明之另一固體攝像裝置之特徴爲包括：許多垂直 信號線；對應於許多垂直信號線設置，在第1時序時將配 合雜訊及入射光之第1電壓輸出於對應之該垂直信號線， 在第2時序時將配合該雜訊之第2電壓輸'出fc對應之該垂 直信號線之許多圖素；設在該多垂直信號線之各一端，輸 出配合該第1電壓之電荷量與配合該第2電壓之電荷量之 差之許多雜訊去除電路。 本發明之另一固體攝像裝置之特徵爲包括：許多垂直 信號線：對應於許多垂直信號線設置，在第1時序時將配 合雜訊及入射光之第1電氣信號輸出於對應之該垂直信號 線，在第2時序時將配合該雜訊之第2電氣信號輸出於對 應之該垂直信號線之許多圖素；連接於許多垂直信號線之 各一端之許多箝位電容器：連接於許多箝位電容器之各另 一端與第1一定電位之間之許多樣品保持電容器；及連接 於該許多箝位電容器之各另一端與第2 —定電位之間，在 一定之時序時箝位對應之該樣品保持電容器之許多箝位電 晶體之許多雜訊去除電路。 本發明之另一固體攝像裝置之特徵爲包括：許多水平 本紙張尺度適用中國國家標準（CNS)A4規格（210X25·7公釐）_ 24 ---------^丨裝------訂-----Η線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央樣準局員工消费合作杜印製 A7 B7 五、發明説明（22 ) 選擇線；與該水平選擇線交叉之垂直信號線：設在該水平 選擇線與該垂直信號線之各交叉點位置，配合該水平選擇 線之電位選擇性的活化，在該活化期間內之第1時序時將 配合雜訊及入射光之第1電氣信號輸出於該垂直信號線， 在該活化期間內之第2時序時將配合該雜訊之第2電氣信 號輸出於該垂直信號線之許多圓素；及設在該垂直信號線 之一端，以相同之輸入阻抗輸入該第1及第2電氣信號， 並且输出該第1與第2電氣信號之差值之雜訊去除電路。 本發明之另一固體攝像裝置之特徵爲包括：許多水平 選擇線；與該水平選擇線交叉之垂直信號k'設在該水平 選擇線與該垂直信號線之各交叉點位置，配合該水平選擇 線之電位選擇性的活化，在該活化期間內之第1時序時將 配合雜訊及入射光之第1電氣信號輸出於該垂直信號線， ^在該活化期間內之第2時序時將配合該雜訊之第2電氣信 號输出於該垂直信號線之許多圖素；及包含具有連接於該 垂直信號線之一端之第1節，儲存電荷之第2節，及從該 第2節傳送根據該第1節之電位控制之一定量之電荷之第 3節之第3端子元件，產生在該第1與第2時序時之該圖 素之輸出端之差值之雜訊去除電路。 本發明之另一固體攝像裝置之特徵爲包括：許多水平 選擇線；與該水平選擇線交叉之垂直信號線；設在該水平 選擇線與該垂直信號線之各交叉點位置，配合該水平選擇 線之電位選擇性的活化，在該活化期間內之第1時序時將 配合雜訊及入射光之第1電壓輸出於該垂直信號線，在該 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X 297公釐）-25 - --------^丨裝------訂-----叫線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央樣隼局員工消費合作社卬裝 A7 ____B7_ 五、發明説明（23 ) 活化期間內之第2時序時將配合該雜訊之第2電壓输出於 該垂直信號線之許多圖素；及設在該垂直信號線之一端而 输出配合該第1電壓之電荷量與配合該第2電壓之電荷童 之差之雜訊去除電路。 本發明之另一固體攝像裝置之特徵爲包括：許多水平 選擇線；與該水平選擇線交叉之垂直信號線：設在該水平 選擇線與該垂直信號線之各交差位置，配合該水平選擇線 之電位選擇性的活化，在該活化期間內之第1時序時將配 合雜訊及入射光之第1電氣信號輸出於該垂直信號線，在 該活化期間內之第2時序時將配合該雜訊> % 2電氣信號 输出於該垂直信號線之許多圖素；連接於該垂直信號線之 一端之箝位電容器；連接於該箝位電容器之另一端與λ 1 一定電位之間之樣品保持電容器；及具有連接於該箝位電 1容器之另一端與第2 —定電位之間，在一定之時序時箝位 該樣品保持電容器之箝位電晶體之雜訊去除電路。 本發明之另一固體攝像裝置半導體積體電路之特徵爲 :在積體電路化時，其構造上具有半導體基板；形成於半 導體基板表面之固體攝像裝置；及形成於該固體攝像裝置 上，具有對應於該許多圖素之許多開口之遮光膜。又具有 選擇性的形成於該開口上之顏色過濾器。又具有形成於該 開口上之微透鏡。 本發明之雜訊消除方法包括：在MOS電晶體之閘極 上施加第1電壓之步驟；復置充電於一端連接於該MO S 電晶體之源極之電容器中之電荷之步驟；在該電容器之另 本紙張尺度適用中國國家標準（CNS)A4規格（210Χ 297公釐）-26 - ---------^^------1Τ-----1 0 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局属工消費合作杜印製 A7 B7_ 五、發明説明（24 ) —端施加第1脈波，將一定之電荷從該MO S電晶體之源 極經由吸極放電之步驟；在該MO S電晶體之閘極上施加 第2電壓之步驟；及在該電容器之另一端施加振幅與該第 1脈波之振幅相同之第2脈波，將相當於該第1電壓與第 2電壓之差值之電荷從該M〇S電晶體之源極傳送至吸極 之步驟。 本發明之抽出差值之雜訊消除方法之特徵爲在第1電 容器之一端施加第1電壓，而在該第1電容器之另一端施 加箝位電壓之步驟；及在該第1電容器之一端施加第2電 壓而將該第1電壓與第2電壓之差值充電11 於#一端直接連接 於該第1電容器之另一端之第2電容器之步驟。該第1電 容器之一端連接於阻抗變換電路之輸出端，而該第1及第 2電壓爲該阻抗變換電路之輸出》該第1及第2電壓之一 $方爲對應於入射在固體攝像元件之圖素之入射光之输出電 壓與從該圖素中產生之固定圖型雜訊電壓之和，另一方爲 該固定圖型雜訊。 以下參照圖式說明本發明之MO S型固體攝像裝置及 其應用裝置之實施例。 固體攝像元件通常係使用C C D偵測器。如第3圖所 示，固體攝像元件之基本結構包括輸入部I ，處理部Π， 及輸出部ΠΙ。輸入部I爲受光部。該受光部I之構造爲將 相當於許多圖素之構成圖素之感光二極體排列而對應於受 光量從各圇素輸出電氣信號之處理部Π係依次讀出各圖素 之信號而且消除雜訊之部分。输出部瓜爲輸出從各圖素讀 本紙張尺度適用中國國家揉準（CNS)A4说格（210X297公釐）_ 27 - ---------------IT-----1 ^ ί ! (請先閲讀背面之注意事項再填寫本頁) A7 ____B7_ 五、發明説明（25 ) 出之信號之電路。C C D偵測器需要許多種驅動電源，不 容易節省能源，而且利用電池驅動時，爲了形成許多種電 壓，需要使用電路規模大之電源電路。 本發明中使用可用單一電源驅動之MO S偵測器取代 C C D偵測器，並在該處理部除了設置讀出控制電路之外 又設置雜訊消除電路而解決MO S偵測器之問題之S/N 問題。如此實現節省能源及小型化》 本發明中使用之MO S偵測器係將n xm個感光二極 體排列成矩陣狀之n xm圖素構造之MO S偵測器。該偵 測器包括將n xm個感光二極體排列成矩^ 之受光部（ 輸入部），具有從構成該受光部之各感光二極體依次讀出 信號之讀出部及雜訊消除電路之處理部，及輸出該處理部 讀出之信號之f出部。 ' 處理部上設有讀出部及本發明之雜訊消除電路。本發 明中使用之MO S偵測器係分別在只取出雜訊成分之時序 與取出包含雜訊成分之信號成分之時序取出信號，從其中 消除雜訊成分而產生無雜訊影響之信號成分。雜訊消除電 路可在只输出雜訊成分時，與輸出雜訊成分及信號成分時 使其阻抗成爲相等，以便可高精確的消除雜訊。因爲具有 這種雜訊消除電路，故本發明中使用之MO S偵測器成爲 達到實用化水平之低雜訊，而且可高速的進行雜訊消除之 高性能MO S偵測器。 若使用本發明之Μ 0 S偵測器做爲固體攝像元件時， MO S偵測器之光電變換用偵測部，及其他電路（I V變 本紙張尺度遑用中國國家標準（CNS ) Α4規格（210X 297公釐）_ 28 _ "" f請先閲讀背面之注意事項再填寫本頁) •裝· 訂 經濟部中央樣準局員工消費合作社印製 經濟部中央標準局貝工消費合作社印製 306073 a? B7 五、發明説明（26 ) 換電路，AGC電路，CLP電路，ADC電路）可使用 一般之MO S製程製造•因此，非常容易在同一半導體晶 粒上形成以上各電路。此外，又可實現低消耗功率，使用 於視頻攝像機時，以單一電壓即可驅動，可簡化電源電路 ，容易實現電池驅動。 第1實施例 系統實施例 以下說明可實現低消耗功率，低電壓化，S/N良好 ，可實施單一電源化之使用MO S型固體'攝fe裝置之各種 系統。 第4圖表示使用MO S偵測器做爲畫像檢測部之裝置 之一般構造。圖中，該裝置係由光學系A1，MOS偵測 β器A 2 ，及信號應用部A 3所構成。光學系A 1係將光學 像導引至MO S偵測器A 2之裝置，具體言之，係配合系 統之用途適當的組合透鏡，稜鏡，針孔，分色鏡，聚焦性 光學纖維，凹面鏡，凸面鏡，顏色過濾器，快門機構，光 圈機構等而構成。 MO S偵測器A 2係將經由光學系統A 1導引之光學 像對應於其光量變換成畫像信號，經過雜訊處理而只輸出 無雜訊之信號成分之裝置。MO S偵測器A 2所具有之該 雜訊消除處理之要素即爲後述之重要要素之一之雜訊消除 電路。 ， 信號應用部A 3係將經過雜訊消除處理之MO S偵測 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） ^ 裝 訂 (請先閲讀背面之注意事項再填寫本頁) - 29 _ 306073 A7 B7 經濟部中央標準局員工消费合作社印製 . 五、發明説明（27 ) 器A 2之输出配合系統之型態加工之裝置。例如系統爲視 頻攝像機時，信號應用部A 3爲將從MO S偵測器A 2輸 出之畫像信號變換成PAL方式’或NT S C方式等複合 影像信號等之應用功能部分。 MO S偵測器A 2可用單一電源驅動，而且使用感光 二極體做爲將光變換成電氣信號之受光部β感光二極體相 當於圖素。配設許多個，及矩陣狀之理由與習用裝置相同 。爲了圖素之細微化，感光二極體之面積變小，因此其输 出變小。爲了放大該小输出而對應於圖素設置放大器（電 晶體）。將通過該放大器（電晶體）時產雜訊（因爲 放大電晶體之特性而不可避免之雜訊成分）經過MO S偵 測器A 2所具有之感光二極體之輸出之復置操作，該復置 操作時之放大器（電晶體）之輸出信號（雜訊成分）之保 1持，利用該保持之輸出信號（雜訊成分）與復置操作前， 或復置操作終了後之放大器（電晶體）之輸出信號（信號 成分+雜訊成分）消除兩者等處理操作消除雜訊而只抽出 信號成分。 將該MO S偵測器A 2形成爲如下之構造，即可產生 輸出信號之電壓振幅爲1 OmV左右以下，輸出電流爲1 Μ A左右以上之1 / f無雜訊之輸出。該Μ ◦ S偵測器 A 2之輸出之動態範圍可提髙至與C C D偵測器相同之 7 0 d B左右或更高。若實施適當之信號處理，則亦可提 高至與銀鹽薄膜相同之9 0 d B左右。 如此’可寅現單一電源，而且使用以高臛敏度放大型 本紙張尺度適用中國國家標準（CNS〉A4規格（.210X 297公釐〉_ 3〇 _ I--------^------,玎-----10 / - (請先閱讀背面之注意事項再填寫本頁) 306073 A7 B7 五、發明説明（28 ) MO S偵測器做爲攝像裝置之各種系統，可實現低消耗功 率，低電壓化，而且可提供S/N良好之放大型MO S型 固體攝像裝置（放大型MO S偵測器）之應用裝置。 第2實施例 將放大型MO S偵測器應用於視頻攝像機 第5圖表示使用本發明之MO S偵測器之視頻攝像機 之實施例》如第5圖所示，本發明之視頻攝像機1 0 0包 括：接受被攝體像之光學系統透鏡101;調整該光學系 統之焦距之焦距調整機構1 0 2;控制調1整免學系統之入 射光量之光圈機構1 1 6及焦距調整機構1 0 2之光圈調 整焦距調整電路1 0 3 ;將經由透鏡1 0 1成像之光學像 以圖素單位變換成對應於該光學像之光置之電氣信號之攝 Φ像元件MOS偵測器105 ;設在MOS偵測器105之 成像面側，於每一圖素具有RGB中之任一彩色過濾器之 彩色過濾器陣列104 :將MOS偵測器105所產生之 電氣信號變換成電壓信號之電流電壓變換電路1 0 6 ;調 整經由電流電壓變換電路1 0 6產生之電壓信號之位準之 AGC電路；箝位經由AGC電路1 0 7其位準成爲相等 之電壓信號之箝位電路（CLP) 108 ;將CLP 1 0 8所產生之输出變換成對應於位準之數位信號之A/ N變換電路（ADC) 1 0 9 ;產生形成做爲系統動作之 基本之時序之時序脈波（時鐘信號）之時序控制電路 110;同步於該時序控制電路110所輸出之時鐘信號 本紙張尺度適用中國國家標隼（CNS)A4規格（210X297公釐）_ 31 - --------7丨裝------訂-----'I線 f f (請先閱請背面之注意事項再填寫本頁) 經濟部中央樣隼局貝工消費合作社印製 經濟部中央橾準局貝工消費合作杜印製 A7 ___B7_ 五、發明説明（29 ) 控制MOS偵測器1 0 5之驅動之TG/SG電路1 1 1 :將ADC 109所產生之數位信號予以製程處理之製 程控制電路112;將經過該製程控制電路112予以製 程處理之信號編碼之編碼電路113;輸出經過編碼之信 號之輸出電路114;將經由輸出電路114輸出之信號 變換成類比信號之數位類比變換電路1 1 5。 具有上述構造之視頻攝像機1 0 0中，從被攝體射入 之光線通過透鏡101入射於MOS偵測器105，而入 射之光線經由光電變換變成電氣信號而成爲電流值輸出。 在MO S偵測器1 0 5上形成有對應於各%圖fe規則的排列 紅，藍，綠之彩色過濾器之彩色過濾器陣列1 0 4。如此 ，從1個MO S偵測器1 0 5中輸出對應於3原色之彩色 畫像信號做爲電氣信號。 ' 從MOS偵測器105輸出之電氣信號經由電流電壓 變換電路106，AGC電路107，CLP電路108 供給於ADC電路109。 ADC電路1 09根據CLP電路1 08所產生之畫 像信號變換成例如1個抽樣值爲8位元之數位資料，將該 資料供給於製程控制電路1 1 2。 製程控制電路1 1 2係由例如色分離電路，箝位電路 * r修正電路，白色限制電路，黑色限制電路，及膝電路 等所構成，視需要對供給之影像信號實施製程處理。又視 需要實施色平衡等處理。經由該製程控制電路112處理 之信號被供給於編碼電路1 1 3。 本紙張尺度適用中國國家標準（CNSM4規格（ 210X 297公釐）_ 32 - --------Γ — 私衣------1T-----1 ^ f 如 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 306073 at _B7 五、發明説明（3〇 ) 編碼電路113運算送到之信號而將之變換成亮度信 號，色差信號。若希望以網路通路視頻攝像機之輸出時， 則在該編碼電路113實施變換成PAL或NTSC方式 等之複合影像信號之處理。 MOS偵測器1〇5，電流電壓變換電路106由 TG/SG (時序產生器/信號產生器）電路1 1 1所產 生之時序信號，同步信號控制時序。該TG/S G電路 111之動作電源及輸出電壓與供給於MOS偵測器 1 0 5之電源位準相同。 然後，影像信號經由输出電路1 1 供fe於D/A變 換電路1 1 5，而D/A變換電路1 1 5將該輸入之信號 變換成類比視頻信號，做爲攝像機信號輪出•影像信號亦 可經由輸出電路1 1 4做爲數位信號直接輸出。各攝像機 4信號被供給於視頻錄影機等記錄裝置及監視裝置* 本實施例中之低消耗功率，低電壓化，而且必須在1 秒內處理3 0幀畫像之視頻攝像機可在水平回描線期間內 消除固定圚型雜訊成分，可提供一種可產生S/N良好， 高畫質畫像信號之視頻攝像機。 本實施例之彩色過濾器陣列1 0 4與做爲攝像裝置之 MO S偵測器1 〇 5係分開。但近年來若考慮C C D裝置 ，則攝像裝置與彩色過濾器成爲一體之裝置亦多。因此， 可使用彩色過濾器陣列1 0 4與MO S偵測器1 0 5成爲 體之結構。彩色過濾器陣列1 04與MOS偵測器1 05 成爲一體之攝像裝置可形成爲如第6圖所示之結構。 本紙張尺度遑用中國國家標準（〇^)八4規格（2丨0/ 297公釐）_33_ I- I I I I n I 裝— I —訂— I I — 線 f ^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央橾準局負工消費合作社印製 306073 A7 _____B7_ 五、發明説明（31 ) 亦即，在許多微細之感光二極體P D配置成矩陣狀而 成之半導體基板S u b之各感光二極體受光面側上利用銘 形成各感光二極體受光面之領域部分開口之遮光掩罩之遮 光膜Ms t ，在其上面形成透明之平滑膜Mf t ，又在其 上形成青綠色過濾器FCy，紫紅色過濾器FMg，及黃 色過濾器F Y e。 感光二極體PD分成紫紅色像用Mg，綠色像用G， 黃色像用Ye，青綠色像用Cy。青綠色過濾器FCy係 形成在綠色像用與青綠色像用感光二極體之受光面上，紫 紅色過濾器F M g係形成在紫紅色像用感~光^1極體之受光 面上，黃色過濾器F Y e係形成在黃色像用感光二極體之 受光面上。然後，在上面形成透明之上面塗敷層0 c ，在 其上面形成微透鏡陣列L m c。微透鏡陣列L m c係排列 *許多微小之透鏡形成，各微小透鏡部分位於感光二極體 P D之受光面上。該微透鏡陣列Lm c可確保射入感光二 極體P D之光之入射量，以便提髙'感光二極體P D之檢測 靈敏度。 若使用上述彩色過濾器一體形成方式之攝像裝置做爲 單板式攝像系統之攝像元件（MOS偵測器1 〇 5 )時， 則不必分開設置彩色過濾器，可省略在MO S偵測器 1 0 5之受光面上，彩色過濾器對各圖素之定位，可節省 光學系統之空間。 f 第3實施例 本紙張尺度適用中國國家標隼（CNS)A4規格（210Χ297公釐）_ 34 - --------—I------ΐτ-----1 ^ (請先閲讀背面之注意事項再填寫本頁) A7 B7 經濟部中央樣準局員工消费合作社印裝 五、 發明説明 ( 32 ) 1 | 將 放 大 型 Μ 0 S 偵 測 器 rrbg 應 用 於 視 頻 攝 像 機 1 I 第 7 圖 表 示 使 用 本 發 明 之 Μ 0 S 偵 測 器 之 另 — 視 頻 攝 1 1 1 像 機 之 實 施 例 〇 第 7 圖 所 示 之 例 爲 針 對 第 5 圖 表 示 之 單 板 /—X 1 I 請 I 式 攝像 系 統 » 將 攝 像 系 統 分 成 R G Β ( 紅 9 綠 > 藍 ) 等 3 先 閲 1 I 讀 1 1 種 系 統 之 3 板 式 視 頻攝 像 機 之 例 0 如 第 7 圖 所 示 > 本 發 明 背 1 1 之 視 頻 攝 像 機 1 0 0 — 2 包 括 ； 接 受 被 攝 體 像 之 光 學 系 統 注 意 重 1 | 透 鏡 1 0 1 ; 調 整 該 光 學 系 統 之 焦 距 之 焦 距 調 整 機 構 Ψ 項 再 填 1 1 0 2 t 控 制 光 學 系 統 之 入 射 光 量 之 光 圈 機 構 1 1 6 及 焦 窝 本 裝 I 距 調 整 機 構 1 0 2 之 光 团 調 整 及 焦 距 調 整 電 路 1 0 3 將 Ά 'w- 1 1 1 透 鏡 1 0 1 所 接 受 之 光 學 像 分 解 成 R G Β 等 i- 原 色 成 分 之 1 1 顏 色 分 解 稜 鏡 2 0 1 R 2 0 1 G 2 0 1 B 形 成 由 各 1 1 顏 色 分 解 稜 鏡 2 0 1 R 2 0 1 G 2 0 1 B 分 解 成 訂 1 R G B 等 三 原 色 成 分 之 盡 像 而 以 圖 素 單 位 變 換 成 對 應 於 1 | 該 光 學 像 之 光 量 之 電 氣 信 疏 之 攝 像 元 件 R 成 分 用 G 成 1 I 分 用 B 成 分 用 Μ 0 S 偵 測 器 1 0 5 R 1 0 5 G 1 線 1 0 5 B : 將 各 Μ 0 S 偵 測 器 1 0 5 R 1 0 5 G 1 1 0 5 B 所 產 生 之 電 氣 信 號 變 換 成 電 壓 信 號 之 R 成 分 系 統 1 1 用 G 成 分 系 統 用 Β 成 分 系 統 用 電 流 電 壓 變 換 電 路 1 1 1 0 6 R • 1 0 6 G » 1 0 6 Β 調 整 電 流 電 壓 變 換 電 路 1 | 1 0 6 R 1 1 0 6 G > 1 0 6 Β 所 產 生 之 電 壓 信 號 之 位 準 1 I 之 R 成 分 系 統 用 9 G 成 分 系 統 用 ， Β 成 分 系 統 用 A G C 電 1 1 I 路 1 0 7 R » 1 0 7 G * 1 0 7 Β * 箝 位 經 由 A G C 電 路 1 1 1 0 7 R » 1 0 >7 G » 1 0 7 Β 而 位 準 成 爲 相 等 之 電 壓 信 1 1 號 之 R 成 分 系 統 用 9 G 成 分 系 統 用 » Β 成 分 系 統 用 箝 位 電 1 1 本紙張尺度適用中國國家標隼（CNS) Μ規格（210X297公釐）-35- 經濟部中央橾準局員工消費合作社印製 A7 ___B7_ 五、發明説明（33 ) 路（CLP) 108R，108G，108B ;將 CLP 108R，108G，108B所產生之輸出變換成對 應位準之數位信號之R成分系統用，G成分系統用，B成 分系統用類比數位變換電路（ADC) 109R， 109G，109B :產生形成做爲系統動作之基本之時 序之時序脈波之時序控制電路110;同步於該時序控制 電路1 1 0所產生之時序脈波控制MOS偵測器1 〇 5之 驅動之R成分系統用，G成分系統用，B成分系統用TG /SG電路111;將從ADC 109R，109G， 1 0 9 B所產生之數位信號輸出予以製程kll之製程控制 電路1 1 2 ;將經由製程控制電路1 1 2予以製程處理之 信號編碼之編碼電路113;控制被編碼之信號之輸入及 輸出之輸出電路114;及將經由输出電路114输出之 ^信號變換成類比信號之數位類比變換電路1 1 5。 具有這種結構之視頻攝像機1 0 0 - 2中，從被攝體 反射之光線通過透鏡101 ，色分解稜鏡201R， 201G ，201B 在MOS 偵測器 105R，1 05G ，1 0 5 B上成像。 各色分解稜鏡201R，201G，201B將光學 像分解成RGB等三原色成分。由色分解稜鏡2 0 1 R ’ 2 0 1 G，2 0 1 B分解成RGB等三原色成分之畫像分 別依照其成分在各該MOS偵測器1 0 5R，1 0 5G ’ 1 〇 5 B上成像π 在MOS偵測器105R，105G，105Β成像 本紙張尺度適用中國國家棣準（CNS)A4規格（ 210X 297公釐）_ 36 _ ---------.1¾.------，玎------^ ! „ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 ___B7_^_ 五、發明説明（34 ) 之R成分，G成分，B成分之光學像在此被光電變換成電 流信號，成爲對應於明亮度之電流值輸出。 從MOS偵測器105R，105G，105B產生 之各成分之電氣信號經由各成分之電流電壓變換電路 106R，106G，106B，AGC 電路 107R， 107G，107B，CLP 電路 108R，108G， 108B 供給於 ADC 電路 109R，109G， 1 0 9 B。 各成分之ADC電路109R，109G，109B 根據從C L P電路1 〇 9產生之畫像信號^變fc成例如1個 抽樣值爲8位元之數位資料，將該資料供給於製程控制電 路 1 1 2 » 製程控制電路1 1 2係例如由r修正電路，白色限制 ^電路，黑色限制電路，膝電路等所構成，視需要對供給之 影像信號實施製程處理》又視需要實施色平衡等處理。由 該製程控制電路1 1 2處理器之信號被傳送至編碼器 1 1 3。編碼器11 3運算送來之信號，實施色平衡等處 理。若利用網路等進行視頻攝像機输出之通信時*在該編 碼器113中實施變換成標準彩色電視廣播方式之PAL 方式及N T S C方式等複合影像信號之處理。 MOS 偵測器 l〇5R，105G，105B，電流 電壓變換電路106R，106G，106B由對應於其 本身系統之TG/SG電路1 1 1所產生之時序信號，同 步信號控制其時序。該TG/SG電路111之動作電源 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐）_ 37 - ---------^-I^------1T------Φ > .ί (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作杜印製 A7 ___B7_ 五、發明説明（35 ) 及输出電壓之位準與供給於MO S偵測器1 0 5之電源位 準相同。 然後，影像信號經由輸出電路1 1 4供給於D/A變 換電路1 1 5，而D/A變換電路1 1 5將輸入之信號變 換成類比視頻信號，將之做爲攝像機信號输出。影像信號 亦可經由輸出電路1 1 4做爲數位信號直接輸出。上述攝 像機信號被供給於視頻錄影機等記錄裝置及監視裝置》 本實施例之低消耗功率，低電壓化，而且在1秒鐘內 需要處理3 0幀畫像之視頻攝像機爲可在水平回描線期間 內消除固定圖型雜訊成分，可確保良好之、N，可產生 高畫質之畫像信號之視頻攝影機。 以上實施例係使用色分解稜鏡將光學像分解成R G B 等三原色成分之例。其他亦可使用分色鏡進行色分解。例 、□利用紅色反射，綠色反射，藍色反射等分色鏡將入射光 分離及分配，將光學像分解成RG B之成分。將該光學像 以R像用，G像用，B像用之MOS偵測器攝像而形成R 像，G像及B像之畫像信號。如此，則不必使用稜鏡亦可 將光學像分成三原色之成分產生。 第4實施例 將放大型MO S偵測器應用於網路系統 第8圖表示將上述視頻攝像機100，100 - 2之 信號經由網路傅送至監視器等之系統結構例。圖中* 3 0 0 爲網路，可爲 L AN (Local Area Network)，公 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）-38 - I I I I — 裝 I ~~ 訂 線 ί· -(請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 306G73 五、發明説明（36) 用線路（電話線路）^專用線等，或Internet，Intranet 等。視頻攝像機100，100 — 2經由介面301連接 於該網路3 0 0。 3 1 0爲靈活的終端設備（Intelligent Terminal) ，相當於個人電腦或工作站等。靈活的終端設備3 1 0具 有包括處理機或主記憶體，時鐘產生器等之電腦本體 3 1 1 ，網路連接用介面3 1 2，畫像顯示用記憶體之視 頻 RAM313，印表機介面 314，SCSI ( Smal 1 Computer System Interface)等標準匯流排介面 3 1 5 ，3 1 7，及視頻攝像機連接用介面3 1、%。以上各構 件由內部匯流排連接。視頻RAM313連接於CRT監 視器，液晶顯示器等監視裝置3 1 8。印表機介面3 1 4 連接於印表機。標準匯流排介面3 1 7連接於光碟裝置， ^硬碟裝置，或DVD (Digital Video Disc)等大容量外 部記憶裝置3 2 0。標準匯流排介面3 1 7連接於例如從 硬拷貝输入圖像之圖像掃描器3 2 1。視頻攝像機連接用 介面3 1 6連接於以上實施例中說明之視頻攝像機1 0 0 〇 根據以上結構，由視頻攝像機1 0 0或1 0 0 — 2攝 像而形成之被攝體之畫像爲了以編碼器113利用網路等 進行視頻攝像機輸出之通信，實施變換成以MP E G方式 經過畫像壓縮處理之數位信號之處理。該複合影像信號做 爲數位資料經由介面3 0 1 ，以在網路之傅送格式輸出於 網路300中。網路300經由介面312連接霣活的終 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）_ 39 _ ----------^------,订------^ - < (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局員工消費合作社印裝 A7 B7. 五、發明説明（37 ) 端設備3 1 〇。若視頻攝像機1 ο 0或1 〇 〇 — 2所產生 之傳送資料係需要俥送至該靈活的終端設備31〇之資料 ’則該靈活的終端設備3 1 0之電腦本身3 1 1從網路 3 0 0經由介面3 1 2输入傳送資料。電腦本身3 1 1從 該傳送資料中抽出畫像資訊部分。因爲視頻攝像機1 〇 〇 或1 0 0 - 2正在進行畫像之壓縮處理，故電腦本身 3 1 1將該畫像伸長，恢復成原來之畫像。然後，將復原 之畫像資料依次寫入視頻RAM3 1 3中。因爲畫像爲動 畫’故視頻RAM3 1 3之畫像資料不斷的更新。結果， 在將視頻RAM3 1 3之畫像資料做爲畫~像1®示之監視裝 置3 1 8上顯示出從視頻攝像機1 0 0或1 0 0 — 2送來 之動畫。 由視頻攝像機1 0 0攝像而形成之被攝體之畫像爲了 Λ以網路等進行視頻攝像機输出之通信而由編碼器113變 換成以MP E G方式予以畫像壓縮處理之數位資料後，經 由介面3 1 6输出於電腦本體3 1 1，電腦本體3 1 1將 該畫像伸長而恢復成原來之畫像。然後，將復原之畫像資 料依次寫入視頻RAM3 1 3中。因爲畫像爲動畫’故視 頻RAM3 1 3之畫像資料不斷的更新。如此，在將視頻 RAM 3 1 3之畫像資料做爲畫像顯示之監視裝置3 1 8 上顯示從視頻攝像機1 0 0送來之動畫。 若電腦本髖311希望將連接於靈活的終端設備 3 1 0之視頻攝象機1 〇 〇之畫像傳送至網路3 0 〇時’ 則編輯成該網路之傳送格式，經由介面3 1 2输出於網路 本紙張尺度適用中國國家標準（CNS)A4規格（210X 297公釐）_ 4〇 - ^ —裝 訂''線 π I (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印«. A7 __B7_ 五、發明説明（38 ) 3 0 0 中。 第5實施例 將放大型MO S偵測器應用於靜止攝像機 第9圖爲使用本發明之MO S偵測器之靜止攝像機之 實施例。如第9圖所示，本發明之靜止攝像機4 0 0包括 •‘具有透鏡系統及光圈，並接受被攝體像之光學系統 4 1 1 ;形成該光學系統4 1 1所接受之像之MOS偵測 器4 1 5 :位於該MO S偵測器4 1 5之成像面與該光學 系統4 1 1之間，可裝卸於該兩者間之光k t，插裝於該 光路上時，將光學系統4 1 1所接受之被攝體像分配於觀 景窗4 1 4，而脫離至光路以外時，將光學系統4 1 1所 接受之被攝體像成像於MO S偵測器4 1 5之成像面之具 1有快門功能之鏡4 1 2 ;將鏡4 1 2之反射光導引至觀景 窗4 1 4之鏡4 1 3 ;從MOS偵測器4 1 5依照色成分 讀出畫像信號之攝像電路416:將該讀出之輸出變換成 數位信號之A/D變換器417;將該A/D變換器 417變換之數位信號以畫面單位保持之幀記憶體418 :將保持於該幀記億體4 1 8之數位信號以畫面單位壓縮 之壓縮電路4 1 9 ;記憶畜像資料之記憶卡4 2 1 :控制 壓縮電路4 1 9所壓縮之畫像資料以便寫入記憶卡4 2 1 中之卡控制電路4 2 0。 依照上述結構，操作未圖示之快門按鈕後’光學系統 4 1 1所接受之被攝體像在MO S偵測器4 1 5上成像。 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 1 — 裝— 1111 —訂— 11 為 (請先閱讀背面之注意事項再填寫本頁) B7 五、發明説明（39 ) Μ〇S偵測器4 1 5係具有本發明中使用之雜訊消除電路 之固體攝像裝置，當光學系統4 1 1所接受之光學像成像 後，以圖素單位變換成對應於該光學像之光量之電氣信號 。爲了可攝影彩色畫像，在MO S偵測器4 1 5之成像面 側設有每一圖素具有R G Β中之任一種彩色過濾器之彩色 過濾器陣列，攝像電路4 16將MO S偵測器4 1 5所產 生之電氣信號依照RG Β之成分分離而將之輸出。電流電 壓變換電路1 0 6將攝像電路4 1 6所產生之依照色成分 之電氣信號變換成數位信號，而變換之數位信號在幀記憶 體418中以畫面單位暫時保持。 Ν 1 保持於幀記憶體418中之數位信號由壓縮電路 4 1 9以畫像單位壓縮，並輸出於卡控制電路4 2 0。卡 控制電路4 2 0控制並記憶該被壓縮之畫像之資料於資料 、己憶媒體之記憶卡4 2 1中。 經濟部中夬爝隼局員工消费合阼汪印裝 (請先閲讀背面之注意事項再填寫本頁) 如此，在記憶卡4 2 1中以畫面單位壓縮每次操作快 門按鈕時被攝影之靜止畫像，並記憶於其中。記憶卡 4 2 1可在攝像機上裝卸自如，而記憶於記憶卡4 2 1中 之畫像則裝插於未圖示之讀取再生裝置中，將畫像資料伸 長並復原後，顯示於監視裝置，或輸出於視頻印表機等硬 拷貝裝置中以供觀賞。 依照本實施例，不但可實現低消耗功率及低電壓化， 並可以髙S /Ν實現每一秒鐘連績攝影許多幀之髙速連攝 動作，可提供精巧’高功能，高性能之靜止攝像機。亦即 可在短時間內消除MO S偵測器中成爲問題之固_^圖型雜 本紙張尺度適用中國國家標準（CNS > Α4規格（210X297公釐） 經濟部中央標準局員工消费合作社印袈 A7 ____B7_ 五、發明説明（4〇 ) 訊成分，可提供S/N良好，可形成髙畫質相片之靜止攝 像機。 第6實施例 將放大型MO S偵測器應用於電話傳真機 第1 0圖表示使用本發明之MO S偵測器之電話傳真 裝置之實施例。圖中表示原理性之結構，將以手寫或印刷 之原稿或照片等片狀原稿5 0 1以未圖示之主搬送機構搬 送至主掃描方向（箭頭B方向），固定於一定位置，以設 在原稿之橫斷方向之MO S偵測器5 0 2½¾原稿之圖像 資訊。503爲光源，504爲在MOS偵測器502之 受光面形成原稿像之透鏡。 MO S偵測器5 0 2;(系將圖素單位之受光部（感光二 ^極體）排列成一次元之直線型偵測器。亦即具有本發明中 使用之雜訊消除電路之單色固體攝像裝置。 在該電話傳真裝置上裝插片狀原稿5 0 1後，未圖示 之主搬送機構將該原稿5 0 1搬送至主掃描方向（箭頭B 之方向）。然後，在固定於一定位置之MOS偵測器 5 0 2之受光面上，經由透鏡5 0 4形成相當於每一線之 原稿之畫像。MO S偵測器5 0 2讀取該成像之原稿之圖 像資訊。 亦即，如此，從Μ 0 S偵測器5 0 2中依照圖素排列 順序，以圖素單位讀出對應於受光置之信號做爲畫像信號 ，故以放大器5 0 5依照其輸出順序將之放大後•以Α/ 本紙張尺度適用中國國家揉準（CNS ) Α4规格（210Χ 297公釐） ^ 裝 訂 旅 气 ί (請先閲讀背面之注意事項再填寫本頁；> -43 - 經濟部中央櫟準局負工消費合作杜印裝 306073 at B7 五、發明説明（41) D變換器5 0 6將該放大之畫像信號變換成數位信號，然 後以數據機5 0 7調變成電話線路用而輸出於電話線路。 在接受側解調其接受之信號，依照接受順序以對應於 信號值之濃度朝向被搬送至主掃描方向之記錄紙之橫斷方 向印刷圖素*即可將畫像再生成硬拷貝。 依照本實施例，不但可降低消耗功率，降低電壓，而 且以高S/N實現高速讀取，可提供一種精巧，高功能， 高性能之電話傳真裝置。亦即可在短時間內消除MO S偵 測器之問題之固定圖型雜訊成分，可提供一種S/N良好 ，可高速的傳送高畫質圖像之電話傅真裝'置< 近年來，直線性偵測器元件已出現可密接於原稿面而 讀取圖像之密接型偵測器。因此，爲了形成爲密接型，可 將導引原稿像之透鏡，由透鏡導引之像可成像，而且將之 '變換成對應於其光量之電氣信號之圖素單位之受光部，及 在原稿面照射照明光之發光元件組成一體而達成，可使用 這種構造。 第7實施例 將放大型MO S偵測器應用於複印機 第1 1圖表示使用本發明MO S偵測器之電子複印機 之實施例。圖中表示原理上之結構。在箱型框體6 0 1上 放置透明玻璃等原稿放置台6 0 2，在原稿放置台6 0 2 上面放置手寫原:滴或印刷原稿，或照片等片狀原稿6 0 3 而以壓蓋6 0 4壓接原稿》 本紙狀度適用中國國家標準見格™ ---------裝------訂------旅 i f (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局貝工消費合作社印装 306073 A7 A7 ___B7_ 五、發明説明（42) 在框體6 Ο 1內，於原稿放置台6 Ο 2之正下方位置 附近設置可從原稿放置台6 0 2之一端至另一端以一定速 度反復移動之光學系統。在此將該反復移動方向稱爲主掃 描方向。光學系統係由棒狀光源605，鏡606，及透 鏡6 0 7所構成，而光源6 0 5係設在與主掃描方向成爲 垂直相交之方向（此方向稱爲副掃描方向）。 在透鏡6 0 7之成像位置設有MO S偵測器6 0 8。 MO S偵測器6 0 8係將圖素單位之受光部（感光二極體 )排列成一次元之直線性偵測器，亦即具有本發明中使用 之雜訊消除電路之單色固體攝像裝置。1 MOS偵測器6 0 8使相當於副掃描方向1條線之圖 像成像而將之變換成對應於受光量之信號。掃描控制器 6 0 9控制MO S偵測器6 0 8以便從MO S偵測器 ^6 0 8依照圖素排列順序以圖素單位黷出對應於受光量之 信號，做爲畫像信號输出，並且控制該光學系統之主掃描 方向驅動移動，以便使光學系統朝向主掃描方向依次移動 。系統控制器6 1 0控制全部系統，並且根據MO S偵測 器6 0 8所產生之對應於受光量之信號控制雷射光源 6 1 1之输出。雷射光源6 1 1產生點狀雷射光束。從雷 射光源611產生之雷射光束由使雷射光束掃描之掃描鏡 ，亦即多邊形鏡612反射而在圓筒狀感光體園筒613 上成像。該成像位置即描畫位置。感光體圓筒6 1 3係以 一定速度朝向一方向旋轉之圓筒。感光體圓筒6 1 3由未 圖示之帶電裝置使其在雷射光束之照射位置之上游位置（ 本紙張尺度逋用中國國家橾準（CNS ) Μ規格（210Χ 297公釐） I---------^------ΐτ------^ ί | (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印製 A7 ___B7_ 五、發明説明（43 ) 描畫位置之上游位置）帶電。 多邊形鏡6 1 2由系統控制器6 1 0控制，以便使點 狀雷射光束在圓筒狀感光體圓简613表面對應於MOS 偵測器6 0 8所產生之信號之输出速度掃描。若感光體圖 筒6 1 3之圓筒旋轉方向爲主掃描方向時，使雷射光束掃 描與該旋轉方向成爲垂直相交之方向，則在圓筒表面形成 對Μ於雷射光束之光量夫去電荷而相當於原稿圖像之潛像 。感光體圓筒613在描畫位置下游位置通過使潛像成爲 可視像之顯像部6 1 4之設置位置時，將位於該位置之潛 像以顯像部6 1 4所供給之著色體顯像使'其fe爲可視像。 然後，從拷貝用紙收容盤6 1 5中每次取出該著色像，轉 印於搬送至感光體圓筒613之下面位置之搬送通路 616內之拷貝用紙。 5 拷貝用紙之搬送速度與感光體圓筒613之旋轉速度 成爲同步，並以1條線單位依次描畫而轉印形成於感光體 圓筒6 1 3表面之潛像之著色像，在拷貝紙上留下與原稿 相同圖像之著色像。搬送通路616係將轉印著色像之拷 貝用紙輸送至排出口之通路，利用設在搬送通路6 1 6之 搬送機構將拷貝紙輸送至排出口。定影部6 1 7係設在排 出口前之著色劑定影用裝置，轉印著色像之挎貝用紙在通 過定影部6 1 7時，著色劑被定影在拷貝紙上後，被排出 於排出口》 依照這種結構，在拷貝時，於原稿放置台6 0 2上放 琴片狀原稿603，以壓蓋604壓接原稿•因爲在原稿 本紙&尺度適用中國國家橾準（CNS 規格（210X297公釐) 一 I-------II------1T------'Λ. ! .. (請先閲讀背面之注意事項再填寫本頁) 46 經濟部中央梂準局貝工消費合作社印製 A7 B7 五、發明説明（44 ) 放置台6 0 2之正下方附近設有以一定速度從原稿放置台 6 0 2之一端至另一端朝向主掃描方向反復移動之光學系 統*故操作開始印刷按鈕後，光學系統中之光源6 0 5， 鏡6 0 6，透鏡6 0 7朝向主掃描方向反復移動。 假設主掃描方向爲縱方向時，原稿放置台6 0 2之橫 方向爲寬度方向。此時，構成光學系統之光源6 0 5照射 相當於原稿放置台6 0 2之寬度之範圍，而構成光學系統 之鏡6 0 6，透鏡6 0 7在MOS偵測器之受光面上形成 該照射之範圍之像。MO S偵測器6 0 8係將圖素單位之 受光部（感光二極體）排列成一次元之直線fe偵測器，亦 即具有本發明中使用之雜訊消除電路之單色固體攝像裝置 因此，在MO S偵測器6 0 8上形成相當於寬度方向 之1條線（亦即相當於副掃描方向之1條線）之圖像而將 之變換成對應於受光Μ之信號。掃描控制器6 0 9控制 MO S偵測器6 0 8，從其中依照圖素排列順序，以圖素 單位讀出對應於受光量之信號做爲盡像信號，並將之輸出 ’而且控制該光學系統之主掃描方向移動，使光學系統依 次移動至主掃描方向。因此，原稿放置台6 0 2之原稿 6 0 2之圖像依次朝向主掃描方向，並且以副掃描方向1 條線單位依照圖素之順序產生對應於受光置之信號。 ' 該信號傳送至系統控制器6 1 0，而系統控制器 6 1 0對應於信猇控制雷射光源6 1 1之輸出。因此，雷 射光源6 1 1發射強度對應於從MO S偵測器6 0 8輸出 本紙張尺度遑用中國國家標準（CNS ) Α4規格（210X 297公釐） ! . I 裝 I I 訂 I 線 ^ ί (請先閲讀背面之注意事項再填寫本頁) -4(- 經濟部中央橾隼局貝工消費合作社印袈 A7 B7_五、發明説明（45 ) 之受光量之光線。 系統控制器6 1 0控制多邊形鏡6 1 2使其與MO S 偵測器608之讀出速度同步而搖擺，因此’與MOS偵 測器6 0 8之讀出速度成爲同步的，由多邊形鏡6 1 2在 感光體圓筒6 1 3上描奎對應於相當於1條線之圖像（亦 即相當於副掃描方向1條線）之光學像圖像。 感光體圖筒613以對應於主掃描速度之周速朝向一 定方向旋轉。感光體圆筒6 1 3在其周面到達多邊形鏡 6 1 2所形成之雷射光之描畫位置時，已由帶電裝置形成 爲帶電。照射雷射光後，接受照射之部分'"之^光體圓筒 6 1 3喪失相當於受到照射之光量之電荷。因此，在感光 體圓筒6 1 3上，多邊形鏡6 1 2所形成之雷射光之描畫 掃描位置之旋轉方向之下游領域留下原稿之圖像做爲潛像 〇 該潛像在通過顯像部6 1 4之位置時，由該顯像部 6 1 4供給之著色劑顯像而成爲可視像。該著像從拷貝用 紙收容盤6 1 5中逐一被抽出而轉印在被搬送至感光體圓 筒6 1 3下面之搬送通路6 1 6之拷貝用紙上。拷貝用紙 之搬送速度與感光體園筒6 1 3之旋轉速度成爲同步，以 1條線單位依次描畫而轉印形成於感光體圓筒6 1 3表面 之潛像之著色像，在拷貝用紙上留下與原稿相同圖像之著 &像。轉印著色像之拷貝用紙由搬送機構經由搬送通路搬 送至排出口，在通過設在排出口前方之定影部6 1 7時， 由定影部6 1 7將著色劑定影在拷貝用紙上排出。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------1¾------1T------1^ 邊 f (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消费合作社印製 A7 _B7__ 五、發明説明（46 ) 依照本實施例，可實現低消耗功率，低電壓化，以高 S/N進行高速讀取，精巧，高功能，高性能之電子複印 機。亦即，可在短時間內消除MO S偵測器之問題之固定 圖型雜訊成分，可提供S/N良好，以高速讀取高畫質之 圖像，並以高速複印之電子複影機。 以上複印機中，原稿之位置係固定，而光學系統朝向 主掃描方向移動。但亦可爲光學系統之位置固定，將原稿 搬送至主掃描方向之結構。上述複印機係單色裝置，但若 在光學系統中設置三原色之彩色過濾器，進行色分解，依 照色別形成潛像，將該色別之潛像以其對應之顏色之著色 劑顯像而實現可形成彩色拷貝之複印機。 第8實施例 將放大型MO S偵測器應用於掃描器 第1 2圖表示使用本發明之MO S偵測器之手提式圖 像掃描器之實施例。如圖中所示，本發明之圖像掃描器 700係在框體701內裝設做爲光源之LED陣列 702及鏡703，輥704而構成。LED陣列702 之長度可達框體7 0 1之全寬度，而且照射框體7 0 1之 下方外部。鏡7 0 3係設在L E D陣列7 0 2之配置位置 附近，將經由L E D陣列7 0 2照明之原稿之圖像經由設 在框體70 1下部之開縫70 1 a收入框體70 1內。 第1 2圖中之手提式圖像掃描器係將框體7 0 1放置 在原稿上，使其在原稿上滑移而以手動操作移動掃描。此 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------^------IT------^ (請先閱讀背面之注意事項褢...寫本頁) 一 -49 - 經濟部中央標準局員工消費合作社印製 A 7 B7 五、發明説明（47) 時，爲了從開縫7 0 1 a以1條線單位收入原稿之圖像而 使該線位置之檢測與讀取成爲同步，設有輥7 〇 4。 爲了使輥7 0 4接觸原稿而藉其與原稿之摩擦旋轉， 從框體7 0 1之下部露出其周面之一部分。該露出位置在 開縫70 la之附近。 在框體7 0 1之內部設有與輥7 0 4之旋轉成爲同步 的檢測其旋轉方向及旋轉童之編碼器7 0 5。在框體 701之內部設有MOS偵測器706，及在MOS偵測 器7 0 6之受光面上形成由鏡7 0 3導引之原稿像之透鏡 7 0 7° MO S偵測器7 0 6係將圖素單位之受光部（感光二 極體）排列成一次元之直線性偵測器。亦即具有本發明所 使用之雜訊消除電路之單色固體攝像裝置•近年來，直線 性偵測器元件大多爲密接於原稿面而讀取圓像之密接型偵 測器。爲了形成爲密接型*可將導引原稿像之透鏡，形成 由透鏡導引之像，並將之變換成對應於其光量之電氣信號 之圖素單位之受光部，及在原稿面照射照明光線之發光元 件組成一體而構成· 在此，爲了說明其原理而表示如第1 2圖之結構。 從MO S偵測器7 0 6中讀出之信號由該編碼器 7 0 5之輸出設定位置之對應，而且使用於控制讀出時序 〇 依照這種結構，將片狀原稿放置於平坦面上，在其上 面放置手提式掃描器，使其在原稿上移動至輥7 0 4可旋 本紙張尺度適用中國國家標隼（CNS ) A4规格（210X297公釐） ---------#-- (請先閱讀背面之注意事項4彡：寫本頁) --s 線 -50 - A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（，。 4〇 ) 1 I 轉之方 向。該移 動 方 向 爲 主 掃 描 方 向 9 此 時 9 L E D 陣 列 1 1 I 7 0 2 照明原稿 面 » 原 稿 之 圖 像 經 由 開 縫 7 0 1 a 射 入 鏡 1 I 7 0 3 上，在鏡 7 0 3 上 反 射 後 由 透 鏡 7 0 7 在 Μ 〇 S 請 1 1 | 偵測器 7 0 6上 成 像 〇 先 聞 1 1 Μ 〇 S偵測 器 7 0 6 爲 線 圖 像 偵 測 器 9 在 固 定 之 背 之 1 1 Μ 0 S 偵測器7 0 6 之 受 光 面 上 9 經 由 透 規 7 0 7 形 成 相 注 意 事 1 1 當於1 條線之原 稿 畫 像 而 讀 取 成 像 之 原 稿 之 圖 像 資 訊 0 項 -it. 1 J 如 上所述， 本 實 施 例 之 手 提 式 圖 像 掃 描 器 係 在 原 稿 上 本 頁 裝 I 放置框 體7 0 1 直 接 在 原 稿 上 滑 移 而 以 手 動 操 作 移 動 掃 1 I 描。此 時，爲了 以 1 條 線 單 位 從 開 縫 7 0 1 a 收 取 原 稿 之 1 I 圈像， 設有該線 位 置 之 檢 測 與 讀 取 之 同 步 用 輥 7 0 4 t 而 1 1 訂 該輥7 0 4接觸 原 稿 > 藉 其 與 原 稿 之 摩 擦 旋 轉 結 果 從 編 1 碼器7 0 5輸出 輥 7 0 4 之 旋 轉 方 向 及 對應 於 旋轉 置 之 1 1 檢測信 號》然後 以 未 圖 示 之 控 制 裝 置 根 據 該 編 碼 器 1 1 7 0 5 所產生之 檢 測 信 控 制 Μ 0 S 偵 測 器 7 0 6 之 输 出 — 1 線 信號使 其與原稿 之 1 條 線 單 位 成 爲 一 致 而 將 之 输 出 « 1 I 本 實施例可 降 低 消 耗 功 率 * 及 降低 電 壓 9 而 且 以 高 S 1 1 | / Ν實 現髙速讀 取 ， 可 提 供 . 種 精 巧 ♦ 高 功 能 高 性 能 之 1 1 I 圖像掃 描裝置。 亦 即 可 在 短 時 間 內 消 除 Μ 0 S 偵 測 器 中 成 1 1 爲問題 之固定圖 型 雜 訊 成 分 1 可 提 供 — 種 S / N 良 好 » 以 1 1 高速傳 送高盡質 圖 像 之 圖 像 掃 描 裝 置 0 、 1 1 本 實施例中 係 說 明 手 提 式 圖 像 掃 描 器 » 但 亦 可 應 用 於 1 | 在原稿 放置台上 放 置 原 稿 * 使 光 學 系 統 進 行 主 掃 描 驅 動 之 1 I 桌上型 圖像掃描 器 〇 此 外 1 亦 可 應 用 於 固 定 光 學 系 統 之 位 1 1 用 通 度 尺 張 紙 本 準 標 家 國 釐 公 7 9 2 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（49 ) 置，將原稿搬送至主掃描方向之裝置。以上圖像掃描器係 以單色裝置爲例說明。但在光學系統中設置3原色之彩色 過濾器進行色分解，產生各色別之盡像信號而實現可產生 彩色畫像之信號之圖像掃描器。此外，以凹面鏡形成光學 系統而將畫像以凹面鏡導引至MO S偵測器，或利用成束 之光纖構成之光學纖維將畫像導引至M〇S偵測器。 第9圖實施例 桌上型彩色圖像掃描器 第9實施例爲使用於桌上形彩色圖像掃描器之光學系 統之結構。在桌上型彩色圖像掃描器中，光學系統係固定 在一定位置，而且朝向主掃描方向掃描原稿。此時，如第 1 3圖所示，在光學系統中設置3原色之彩色過濾器進行 色分解，產生各色別之畫像信號。第1 3圖中，產生畫像 信號之MO S偵測器S爲線性偵測器，係將圖素直線的排 列相當於1條線而構成。在MO S偵測器S之受光面設有 彩色過濾器F。彩色過濾器F係並列的設置分別具有相當 於1條線之寬度及長度之R (紅），G (綠），B (藍） 等各色成分用光學過濾器而構成。在MO S偵測器S之受 光面上經由透鏡L及彩色過濾器形成原稿D P之光學像》 原稿DP由光源LP照射。 彩色過濾器F由驅動移動掃描機構D R支持成可移動 掃描之狀態，以便使R * G，B等各色成分用光學過濾器 本紙張尺度適用中國國家橾準（CNS ) A4規格（2丨0><297公釐） " -52 - I^-- (請先閱讀背面之注意事項4 J'l馬本頁) 訂 線 經濟部中央標準局貝工消費合作社印製 A7 __B7_ 五、發明説明（5〇 ) 移動至MO S偵測器S之受光面上。接受紅色像之光線時 ，使R之色成分用光學過濾器位於MO S偵測器S之受光 面上，接受綠色像之光線時，使G之色成分用光學過濾器 位於M〇 S偵測器S之受光面上，接受藍色像之光線時， 使B之色成分用光學過濾器位於MO S偵測器S之受光面 上，如此與畫像之收集時序成爲同步的控制其移動。 如此，可從MOS偵測器S中產生R，G，B等各色 成分用光學像之盡像信號。 第1 0實施例 將放大型MOS偵測器應用於薄膜掃描裝置 本發明之放大型MO S偵測器亦可應用於在個人電腦 或畫像顯示裝置等中讀入3 5 mm長度薄膜之每一個幀而 產生畫像信號之薄膜掃描裝置。 第1 4圖表示其結構。如圖中所示，該裝置包括由放 大型MOS偵測器所構成之密接型線性偵測器S，設在該 線性偵測器S之受光面之已S顯像之銀鹽長薄膜FM，在 線性偵測器S之受光面位置照明該銀長薄膜F Μ之光源 LP，及在銀鹽長薄膜下兩旁以一定速度輸送至一定方向 之一對搬送輥C。 依照上述結構，以搬送輥C挾持銀鹽長薄膜FM，使 該搬送輥C以一定速度旋轉》如此，可將銀鹽長薄膜FM 以一定速度搬送至一定方向。因此，可利用密接型線性偵 測器S將銀鹽長薄膜FM之像與薄膜搬送速度成爲同步的 本紙張尺度逍用中國國家標準（CNS ) Α4規格（2丨0Χ297公釐) ' -53 - ---------抑衣------ΐτ------0 (請先閲讀背面之注意事項t,¾本頁) 一 經濟部中央標準局員工消費合作社印製 A7 _______B7_ 五、發明説明（51 ) 讀出而產生對應於受光量之信號。該信號已經過雜訊消除 ，可只將畫像成分之薄膜像以線單位變換成電氣信號而輸 出。 第1 1實施例 應用於自動對焦機構 第15圖表示使用本發明之MOS偵測器之具有自動 對焦機構之單眼反射式照相機之實施例。圖中，本發明之 單眼反射式照相機8 0 0包括：具有焦點位置調整機構之 透鏡8 0 1 :形成該透鏡8 0 1所接受之光學像而曝光之 薄膜膠片8 0 3 ;將透鏡8 0 1所接受之光學像導引至照 相機800之觀景窗802a之稜鏡802b:本發明之 自動對焦偵測器模組8 0 4 ;由半鏡構成，設在透鏡 8 0 1之光路上，操作快門後完全脫離該光路之彈跳式觀 景窗鏡8 0 5 ;裝設在該觀景窗鏡8 0 5之背面，當該觀 景窗鏡8 0 5位於該透鏡8 0 1之光路上時，使觀景窗鏡 8 0 5之穿透光學像成像於自動對焦偵測器模組8 0 3上 之副鏡8 0 6。 自動對焦偵測器模組8 0 4係使用具有本發明中使用 之雜訊消除電路之MO S偵測器*如第1 6圖所示，在 MO S偵測器8 0 4 a部分之受光面前面固定有分離透鏡 8 0 4 b。MO S偵測器8 0 4 a係使用具有二次元排列 之受光面之偵測器。如第1 6圖所示’分離透鏡8 0 4 b 係將一對凸透鏡排列而成。經由副鏡8 0 6分配之光學像 本紙張尺度遑用中國國家標準（CNS > A4规格（210X297公釐）-54 - ~ ---------^------tT------^ (請先閲讀背面之注意事項i ,寫本頁) 經濟部中央標準局員工消費合作社印» A7 _____B7_ 五、發明説明（52 ) 由該分離透鏡8 0 4 b分別成像於MO S偵測器8 0 4 a 之受光面上之其他領域。以一對凸透鏡排列數而成之分離 透鏡8 0 4 b將光學像導引至MO S偵測器8 0 4 a之受 光面，即可在該受光面上，於不同之領域分別成像而形成 —對像。 這種照相機中，由透鏡8 0 1接受之被攝體像由觀景 窗鏡805分配至稜鏡802b及副鏡806。被分配至 觀景窗鏡8 0 5之被攝體像通過稜鏡8 0 2 b在觀景窗 8 0 2 a上成像，使照相機8 0 0攝影之被攝體像成爲可 觀察像。 被分配至副鏡8 0 6之被攝體像被導引至自動對焦偵A sample holding capacitor between terminal I and a certain potential; a capacitance less than twice the series capacitance of the clamp capacitor and the sample holding capacitor is selectively applied to the inductance correction circuit between the signal line and a certain potential ; And a noise removal circuit that generates the difference between the outputs of the output circuits at the first and second timings. The device is an optical system featuring the concept of inductance correction. Another image system of the present invention is characterized by including an optical system that receives an optical image from a subject, guides the optical image to a certain position, and the optical image that is guided to the certain position is in pixel units An image processing device that converts photoelectrically into an electrical signal corresponding to the optical signal of the optical image, and a signal processing section that processes the output of the image processing device into a certain type of output, the detector includes: The photoelectric conversion element at a certain position; including an amplified MOS transistor connected to the photoelectric conversion element, which amplifies and outputs the output of the photoelectric conversion element at the first timing, and outputs the output of the photoelectric conversion element at the second timing The output circuit of unrelated noise: the signal line connected to the output end of the output circuit; the input follower connected to the source follower circuit of the signal line: one end connected to the clamp capacitor of the output end of the source follower circuit; connected Use the Chinese National Standard (CNS) A4 specification (210X297mm) at the other end of the clamp capacitor and the paper standard _-tshirt-(please read the back Note one, ^ 'write this page) Order A7 ___B7____ for consumer cooperation of the Central Central Bureau of Economic Affairs of the Ministry of Economic Affairs ____B7____ V. Invention description (i2) The first sample holding capacitor between certain potentials: connected to the above clamp Between the other end of the capacity and the second-fixed potential * Selectively clamp the clamping capacitor of the sample holding capacitor. The device is an optical system with a circuit capable of overlapping capacitance and a source follower. The features of another portrait system of the present invention include: having an optical system that accepts an optical image from a subject, guides the optical image to a certain position, and the optical image to be guided to the certain position is a pixel An image processing device of a detector for photoelectric conversion of a unit into an electrical signal corresponding to the light quantity of the optical image; and a signal processing section that processes the output of the image processing device into a certain type of output, the detector includes: The photoelectric conversion element at a certain position; including the amplified MOS transistor connected to the photoelectric conversion element * Amplifies and outputs the output of the photoelectric conversion element at the first timing, and outputs the output of the photoelectric conversion element at the second timing Output circuit of irrelevant noise; signal line connected to the output end of the output circuit; clamp capacitor connected to the signal line at one end: a sample connected between the other end of the clamp capacitor and the first constant potential Holding capacitor: and connected between the other end of the clamping capacitor and the second-fixed potential, clamping the clamping of the sample holding capacitor at a certain timing Crystals. The device can be applied to all optical systems featuring circuits that can overlap capacitance. Another image system of the present invention is characterized by including: an optical system that accepts an optical image from a subject, directs the optical image to a certain position, and an optical image that is guided to the certain position The image processing device of the photoelectric conversion of the element unit into the detector corresponding to the electrical signal of the optical child of the optical image; and the output of the image processing device is processed into a certain type and the output paper size is applicable to the China Gujia Standard (CNS ) A4 specification (210X297mm) -15---------- Kun Yi ------, order ------ ii (please read the precautions on the back of the factory first 'write this page ) " A7 B7 printed by the Beigong Consumer Cooperative of the Central Bureau of Samples of the Ministry of Economic Affairs 5. The signal processing section of the invention description (13), the detector includes: outputting voltage corresponding to noise and the amount of light at the first timing , The pixel corresponding to the voltage of the noise is output at the second timing; the first section with the output supplied to the pixel, the second section storing the electric charge, the potential according to the first section is transferred from the second section The 3-terminal element in Section 3 that controls a certain amount of charge; and occurs at the first and second times The noise removal circuit of the difference between the output of the pixels in sequence. The device is an optical system characterized by the use of a 3-terminal noise cancellation circuit. Another day image system of the present invention is characterized by including: an optical system that receives an optical image from a subject, guides the optical image to a certain position, and an optical image that is guided to the certain position An image processing device of a detector for photoelectric conversion of element units into electrical signals corresponding to the light quantity of the optical image; and a signal processing section that processes the output of the image processing device into a certain type of output, the detector includes: The voltage corresponding to the noise and the amount of light is output at the first timing, and the pixel corresponding to the voltage of the noise is output at the second timing; and the charge matching the output voltage of the pixel at the first timing is output And the noise removal circuit that matches the difference in the charge amount of the output voltage of the pixel at the second timing. Another image system of the present invention is characterized by including: an optical system that receives an optical image from a subject, guides the optical image to a certain position, and the optical image that is guided to the certain position is pixelated An image processing device of a detector for photoelectric conversion of a unit into an electrical signal corresponding to the light quantity of the optical image; and a signal processing section that processes the output of the image processing device into a certain type of output, the detector includes: The first electrical signal corresponding to the noise and the amount of light is output at the first timing, and the Chinese national standard (CNS) A4 specification (210X 297mm) corresponding to the paper size is output at the second timing-16-- ------- Baiyi ------ 1T ------ ^ (Please read the notes on the back ¾..¼ to write this page) * Printed by Beigong Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs A7 B7 5. Description of the invention (14) The second electrical signal pixel of the noise; and input the first and second electrical signals with the same input impedance and output the difference between the first and second electrical signals Value noise removal circuit. Another feature of the present invention is that it includes: an optical system that receives an optical image from a subject and directs the optical image to a certain position; and an optical image that is guided to the certain position is shown in the figure An image processing device that converts pixel units into photoelectric signals corresponding to the electrical signal of the optical image; and a signal processing section that processes the output of the image processing device into a certain type of output, and the output dynamic range of the image processing device is 7 0 d B or more. The image system of the present invention is characterized in that the output of the detector is a voltage signal, and the image processing device further includes a voltage-current conversion circuit supplying the output of the detector, and an electric current supplied to the output of the voltage-current conversion circuit -A voltage conversion circuit, an amplifier circuit that amplifies the output of the current-voltage conversion circuit with a gain corresponding to the required sensitivity, and a clamp circuit that clamps the output of the amplifier circuit. Another image system of the present invention is characterized by The signal processing unit has a process circuit that performs a certain process on the output of the image processing device, and an encoder that converts the output of the process circuit into a composite image signal. Another image system of the present invention is characterized in that the optical system includes a lens that focuses the optical image, an aperture adjustment device that adjusts the amount of incident light to the image processing device, and a focus adjustment that adjusts the distance between the lens and many image processing devices The device, and the optical image focused by the lens is split into many optical images according to the wavelength, and the split optical image is supplied to the splitting devices of many image processing devices. This paper scale is applicable to China National Standard (CNS) A4 specification (210X 297mm) -17---------- approved clothes ------. 玎 ------ ^ (please first Read the notes on the back ΓΙ-. ', And fill out this page) 1. A7 __B7_ printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (15) Another feature of the present invention is that it has A light source that irradiates light on a subject, the signal processing section includes a printing device that prints an image corresponding to the subject according to the output of the image processing device, and the optical image is reflected by light from the light source hitting the subject Of reflected light. Another image system of the present invention is characterized by having a light source that irradiates light on the subject. The signal processing unit includes a signal conversion data machine that sends the output of the image processing device to a telephone line. The optical image The light reflected by the light source illuminating the subject. Another feature of the imaging system of the present invention is that it has a light source that irradiates light on the subject, moves the subject relative to the light source, and detects the position of the subject and the light source In relation to the position detection device, the signal processing part processes the output of the image processing device with the output of the position detection device, and the optical image is the reflected light reflected by the light of the light source irradiating the subject. Another feature of the present invention is that in the image processing device, the image is arranged in a certain direction toward a certain direction, the optical system includes a lens that can be driven by a mobile device to move, and a certain distance from the lens is set at On the detector side, the light generated by the lens is divided into two in the certain direction and supplied to a pair of separation lenses of the detector. The signal processor detects the focus of the light generated by the separation lens divided by two The distance between the positions generates a signal to drive the mobile device based on the detection result. Another portrait system of the present invention is characterized by having a light source that irradiates light on the subject. The subject is a film that has been taken between the light source and the detector and has captured images. The paper size is applicable to China National Standard (CNS) A4 (210X297mm) -18---------- ^ ------ 1T ------ ^ (please read the back Matters needing attention I, write this page) * A7 B7 du printing by Beigong Consumer Cooperation of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (I6) The present invention relates to a solid-state imaging device, which is characterized by including: photoelectric Conversion element; with an amplified MOS transistor connected to the photoelectric conversion element, amplifying and outputting the output of the photoelectric conversion element at the first timing, and outputting noise unrelated to the output of the photoelectric conversion element at the second timing The output circuit; and the output terminal connected to the output circuit, the impedance observed from the output circuit at the first and second timings is equal, resulting in the difference in the output of the output circuit at the first and second timings Noise removal circuit. According to this structure, it is characterized by having a signal line connecting the output circuit and the noise removal circuit. The noise removal circuit has a clamp capacitor connected to the signal line at one end, connected between the other end of the clamp capacitor and the clamp potential, and selectively becomes a clamp transistor that is turned on • Connected to the clamp capacitor A sample holding capacitor between the other end and a certain potential, and an impedance correction circuit connected between the signal line and a certain potential. The characteristic is that the impedance correction circuit has selectivity when the clamp transistor becomes non-conductive The turned-on conversion element, and the conversion element connected in series, have a correction capacitance equal to the series capacitance of the clamp capacitor and the sample holding capacitor. The noise removal circuit has a slice transistor connected to the signal line, and the impedance observed from the output circuit is the gate capacitance of the slice transistor. The noise removal circuit has a limiting capacitor connected between the source of the limiting transistor and the supply terminal of the limiting pulse wave, and is connected between the sink of the limiting transistor and a certain potential to charge The limiting charge transfer capacitor of this difference. Another feature of the solid-state imaging device of the present invention includes: a photoelectric conversion element; an amplified MOS transistor connected to the photoelectric conversion element, and the paper scale is applicable to the Chinese National Standard (CNS) A4 (210X 297 mm) -19-Seed coat 11 I ^ 11 I line (please read the notes on the back t write this page first) into A7 B7 306073 V. Description of the invention (17) Amplify and output the output of the photoelectric conversion element at the first timing , The output circuit that outputs noise unrelated to the output of the photoelectric conversion element at the second timing: a signal line connected to the output circuit; a clamp capacitor connected to the signal line at one end; another connected to the clamp capacitor A sample holding capacitor between one end and a certain potential; a capacitance less than 2 times the difference between the series capacitance of the clamping capacitor and the sample holding capacitor and the clamping capacitance is selectively applied to the signal line and a certain potential Between the impedance correction circuit and the noise removal circuit that generates the difference between the output of the output circuit at the first timing and the second timing. Another solid-state imaging device of the present invention is characterized by comprising: a photoelectric conversion element; an amplifier MOS transistor connected to the photoelectric conversion element, which amplifies and outputs the output of the photoelectric conversion element at the first timing * at the second timing An output circuit that outputs noise independent of the output of the photoelectric conversion element; a signal line connected to the output of the output circuit; an input terminal connected to the source follower circuit of the signal line; one end connected to the source follower circuit Clamp capacitor at the output; sample holding capacitor connected between the other end of the clamp capacitor and the first certain potential: and between the other end of the clamp capacitor and the second fixed potential, selective The clamping transistor of the clamping sample holding capacitor. When a solid-state imaging device is formed with a semiconductor integrated circuit element, in the structure of the semiconductor integrated circuit element, the clamp capacitor and the sample holding capacitor are formed by planar overlapping on the same substrate. Another solid-state imaging device of the present invention includes a photoelectric conversion element; an amplifier MOS transistor connected to the photoelectric conversion element amplifies and outputs the output of the photoelectric conversion element at the first timing, and outputs at the second timing- --------- seed coat ------ 1T ------ ^ (please read the notes on the back 4.¾ page first) ~ Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs This paper scale is applicable to the Chinese national standard (CNS > A4 present format (2 丨 〇 > < 297 mm) -20-A7 B7 Printed by the Central Consumer ’s Consumer Cooperative of the Ministry of Economic Affairs 5. Description of the invention (1S) Output circuit for noise related to the output of the photoelectric conversion element: connected to the output The signal at the output of the circuit is connected to the clamp capacitor of the signal line on the 1st * end; the sample holding capacitor between the other end of the clamp capacitor and the 1st fixed potential is connected to the clamp The other of the capacitor—between the terminal eta and the second—constant potential> Clamp the transistor of the sample holding capacitor at a certain timing. The features of the solid-state imaging device of the present invention include: outputting a voltage matching noise and incident light at the first timing 1 outputting a pixel matching the noise voltage at the second timing; Section 1 of the output section 2 of the stored charge and section 3 of the section 3 terminal element 9 which transfers a certain amount of charge according to the potential control of the section 1 from the section 2 and generates the sections 1 and 2 Noise removal circuit for the difference of the output of the pixel at the time of timing. The 3-terminal element is a MOS transistor with the first section as the gate, the second section as the source, and the third section as the sink. 0 Another solid-state imaging device of the present invention is characterized by including : Output the voltage matching the noise and incident light at the first timing, output the pixels matching the voltage of the noise at the second timing, and generate the amount of charge matching the output voltage of the pixels at the first timing and A noise removal circuit matching the difference in the charge difference of the output voltage of the pixel at the second timing • Another solid-state imaging device of the present invention is characterized by including: many horizontal selection lines: many crossing the horizontal selection line The vertical signal line f is provided at each intersection of the horizontal selection line and the vertical signal line »The selective activation of the potential of the horizontal selection line will match the noise and incident light at the first timing in the activation period 1st electrical signal output The paper size of the vertical page corresponding to // G% is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) _ 21-Please read the notes on the back of the first J Equipment Central Bureau of Economic Affairs Beigong Consumer Cooperative Print 306C73 A7 _B7_ V. Description of the invention (19) The signal line, at the second timing within the activation period, the second electrical signal matching the noise will be output to many pixels corresponding to the vertical signal line; and A plurality of noise removing circuits provided on each end of many vertical signal lines, input the first and second electrical signals with the same input impedance, and output the difference between the first and second electrical signals. The features of another solid-state imaging device of the present invention include: a number of horizontal selection lines: a number of vertical signal lines crossing the horizontal selection line; they are located at the intersections of the horizontal selection line and the vertical signal line to match The selective activation of the potential of the selection line, the first electrical signal of the noise and incident light is output to the corresponding vertical signal line at the first timing in the activation period, and at the second timing in the activation period The second electrical signal corresponding to the noise is output to many pixels corresponding to the vertical signal line: and includes the first section having each end connected to the many vertical signal lines, the second section storing charge, and from the second section Section 2 transmits the 3-terminal element of Section 3 of a certain amount of charge controlled according to the potential of Section 1 and generates a lot of noise in the difference between the output of the pixels at the first and second timings Remove the circuit. Another feature of the solid-state imaging device of the present invention includes: a plurality of horizontal selection lines; a plurality of vertical signal lines intersecting the horizontal selection line: provided at each intersection point of the horizontal selection line and the vertical signal line, matching Selective activation of the potential of the selection line. At the first timing in the activation period, the first electricity corresponding to noise and incident light should be output to the corresponding vertical signal line, and the second timing in the activation period The second voltage of the noise will be output to many pixels corresponding to the vertical signal; and the paper standard set at the vertical paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) _ 22 _ IIIIIIIII — II — Order IIIII line (please read the notes on the back to write this page) ™ Printed by the Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperative A7 B7 V. Description of invention (2〇) Each end of the straight signal line, the output matches the Many noise removal circuits for the difference between the charge amount of the first voltage and the charge amount matching the second voltage. Another solid-state imaging device of the present invention includes: a plurality of horizontal selection lines; a plurality of vertical signal lines crossing the horizontal selection line; provided at each crossing position of the horizontal selection line and the vertical signal line to match the potential of the horizontal selection line Selective activation, the first electrical signal with noise and incident light will be output to the corresponding vertical signal line at the first timing in the activation period, and the noise will be matched at the second timing in the activation period The second electrical signal of the signal is output to many pixels corresponding to the vertical signal line: many clamping capacitors connected to each end of many vertical signal lines; connected to each other end of many clamping capacitors and the first certain potential Many sample holding capacitors in between; connected between the other ends of many clamping capacitors and the second fixed potential, at a certain timing, the clamping of the corresponding clamping transistors of the sample holding capacitors to remove many noises Circuit. Another feature of the solid-state imaging device of the present invention includes: a number of vertical signal lines: corresponding to the setting of each vertical signal line, and outputting the first electrical signal matching noise and incident light to the corresponding vertical signal at the first timing Line, at the second timing, the second electrical signal matching the noise will be output to many pixels of the corresponding vertical signal line: set at each end of many vertical signal lines, input the first and the same with the same input impedance A second electrical signal, and a plurality of noise removal circuits that output the difference between the first and second electrical signals / Another solid-state imaging device of the present invention is characterized by including: a number of vertical signal lines; corresponding to the setting of a number of vertical signal lines , At the first time sequence, the first electrical signal with noise and incident light will be output to the corresponding vertical signal. The paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297mm) 23-Approval-(please First read the notes on the back I.  , Λ write this page) Order 306GV3 ^ B7 printed by the Employees ’Consumer Cooperative of the Central Department of Economic Affairs of the Ministry of Economic Affairs 5. The description of the invention (21) line, at the second timing, the first electrical signal of the noise will be output to the corresponding corresponding Many pixels of the vertical signal line; and includes the first section connected to each end of the many vertical signal lines, the second section storing electric charge, and the quantitative control according to the potential control of the first section transmitted from the second section The 3-terminal element in the third section of the charge, and many noise removal circuits that generate the difference in the output of the pixels at the first and second timings. Another feature of the solid-state imaging device of the present invention includes: a number of vertical signal lines; corresponding to the setting of a number of vertical signal lines, the first voltage corresponding to noise and incident light is output to the corresponding vertical signal line at the first timing , At the second time sequence, the second voltage output of the noise will be used to output many pixels of the vertical signal line corresponding to fc; it is provided at each end of the multiple vertical signal lines and outputs the amount of charge matching the first voltage Many noise removal circuits that differ from the amount of charge matching the second voltage. Another feature of the solid-state imaging device of the present invention is that it includes: a number of vertical signal lines: corresponding to the arrangement of a number of vertical signal lines, and outputting the first electrical signal matching noise and incident light to the corresponding vertical signal at the first timing Line, at the second timing, the second electrical signal corresponding to the noise will be output to many pixels corresponding to the vertical signal line; many clamping capacitors connected to each end of many vertical signal lines: connected to many clamps Many sample holding capacitors between each other end of the capacitor and the first certain potential; and between the other ends of the many clamping capacitors and the second-constant potential, the corresponding sample is clamped at a certain timing Many noise removal circuits for many clamping transistors of holding capacitors. The features of another solid-state imaging device of the present invention include: many levels of the paper scale are applicable to the Chinese National Standard (CNS) A4 specification (210X25 · 7mm) _ 24 --------- ^ 丨 Installed-- ---- Subscribe ----- Η line (please read the precautions on the back before filling in this page) A7 B7 for consumer cooperation of the Central Prototype Bureau of the Ministry of Economic Affairs 5. Print description (22) Select the line; and The vertical signal line where the horizontal selection line crosses: set at each intersection of the horizontal selection line and the vertical signal line, in conjunction with the selective activation of the potential of the horizontal selection line, at the first timing within the activation period The first electrical signal matching the noise and incident light is output on the vertical signal line, and the second electrical signal matching the noise is output on the many vertical elements on the vertical signal line at the second timing within the activation period; and A noise removal circuit is provided at one end of the vertical signal line, inputs the first and second electrical signals with the same input impedance, and outputs the difference between the first and second electrical signals. Another feature of the solid-state imaging device of the present invention includes: a plurality of horizontal selection lines; a vertical signal k ′ crossing the horizontal selection line is provided at each intersection of the horizontal selection line and the vertical signal line, in cooperation with the horizontal selection The potential of the line is selectively activated, and the first electrical signal of the noise and incident light is output to the vertical signal line at the first timing in the activation period, ^ at the second timing in the activation period The second electrical signal of the noise is output to many pixels of the vertical signal line; and includes the first section connected to one end of the vertical signal line, the second section that stores charge, and the transmission from the second section according to The electric potential of the first section controls a certain amount of electric charge, and the third terminal element of the third section generates a noise removal circuit for the difference between the output terminals of the pixels at the first and second timings. Another feature of the solid-state imaging device of the present invention is that it includes: a number of horizontal selection lines; vertical signal lines crossing the horizontal selection line; each cross point of the horizontal selection line and the vertical signal line is located to cooperate with the horizontal selection The potential of the line is selectively activated. At the first timing within the activation period, the first voltage of noise and incident light will be output to the vertical signal line. The Chinese standard (CNS) A4 specifications are applicable to the paper size. (210X 297mm) -25--------- ^ 丨 installed ------ ordered ----- call line (please read the notes on the back before filling this page) Central Ministry of Economic Affairs Sample Falcon Bureau employee consumer cooperatives outfitted A7 ____B7_ V. Description of invention (23) At the second timing within the activation period, the second voltage of the noise will be output to many pixels of the vertical signal line in accordance with the noise; and set at the vertical At one end of the signal line, a noise removal circuit that outputs the difference between the charge amount matching the first voltage and the charge child matching the second voltage is output. Another feature of the solid-state imaging device of the present invention includes: a plurality of horizontal selection lines; a vertical signal line crossing the horizontal selection line: provided at each intersection of the horizontal selection line and the vertical signal line, in cooperation with the horizontal selection line The selective activation of the potential will output the first electrical signal of the noise and incident light on the vertical signal line at the first timing in the activation period, and will match the noise at the second timing in the activation period News>% 2 electrical signals are output on many pixels of the vertical signal line; a clamping capacitor connected to one end of the vertical signal line; a sample connected between the other end of the clamping capacitor and a certain potential of λ 1 is held A capacitor; and a noise removal circuit having a clamping transistor connected between the other end of the clamping capacitor 1 and the second fixed potential, clamping the sample holding capacitor at a certain timing. Another feature of the semiconductor integrated circuit of the solid-state imaging device of the present invention is that: when the integrated circuit is formed, it has a semiconductor substrate on its structure; a solid-state imaging device formed on the surface of the semiconductor substrate; and a solid-state imaging device formed on the solid-state imaging device The light-shielding film corresponding to the many openings of the many pixels. It also has a color filter selectively formed on the opening. It also has a microlens formed on the opening. The noise elimination method of the present invention includes: the step of applying a first voltage to the gate of the MOS transistor; the step of resetting the charge charged in the capacitor whose one end is connected to the source of the MOS transistor; In addition, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210Χ 297 mm) -26---------- ^^ ------ 1Τ ----- 1 0 (please first Read the precautions on the back and fill in this page) A7 B7_ Printed by the Ministry of Economic Affairs, Central Bureau of Industry and Commerce, A7 B7_ V. Description of invention (24) — The first pulse is applied at the end to transfer a certain charge from the MOS transistor The step of discharging the source through the sink electrode; the step of applying a second voltage to the gate of the MOS transistor; and applying a second pulse wave with the same amplitude as the first pulse wave to the other end of the capacitor, The step of transferring the charge corresponding to the difference between the first voltage and the second voltage from the source to the sink of the MOS transistor. The method for removing noise in the present invention is characterized by the steps of applying a first voltage to one end of the first capacitor and applying a clamping voltage to the other end of the first capacitor; and applying to the one end of the first capacitor The second voltage is the step of charging the difference between the first voltage and the second voltage 11 at the # end to directly connect the second capacitor at the other end of the first capacitor. One end of the first capacitor is connected to the output of the impedance conversion circuit, and the first and second voltages are the output of the impedance conversion circuit. One of the first and second voltages corresponds to the incident on the solid-state imaging element The sum of the output voltage of the incident light of a pixel and the fixed pattern noise voltage generated from the pixel, the other is the fixed pattern noise. Hereinafter, embodiments of the MOS solid-state imaging device and its application device of the present invention will be described with reference to the drawings. Solid-state imaging devices usually use CC detectors. As shown in FIG. 3, the basic structure of the solid-state imaging element includes an input section I, a processing section Π, and an output section ΠΙ. The input unit I is a light receiving unit. The structure of the light-receiving part I is such that the photodiodes constituting the pixels corresponding to many pixels are arranged, and the processing part Π that outputs electrical signals from each pixel corresponding to the amount of light received sequentially reads the signals of each pixel and eliminates The noise part. The output section is suitable for the output of the paper scales of each pixel reading. The Chinese National Standardization (CNS) A4 format (210X297 mm) is used _ 27---------------- IT --- --1 ^ ί! (Please read the precautions on the back before filling in this page) A7 ____B7_ 5. The circuit of the signal from the invention description (25). The C C D detector needs many kinds of driving power, which is not easy to save energy. In addition, when using battery driving, in order to form many kinds of voltages, a large-scale power circuit needs to be used. In the present invention, a MOS detector that can be driven by a single power supply is used to replace the CCD detector, and in addition to a readout control circuit and a noise cancellation circuit are provided in the processing section to solve the problem of the MO S detector / N question. In this way, energy saving and miniaturization are achieved. The MO S detector used in the present invention is a MO S detector of n x m pixel structure in which n xm photosensitive diodes are arranged in a matrix. The detector includes a light-receiving portion (input portion) in which n xm photosensitive diodes are arranged in a rectangular shape, a reading portion that sequentially reads signals from each photosensitive diode that constitutes the light-receiving portion, and a noise cancellation circuit The processing section, and the f output section that outputs the signal read by the processing section. The processing section is provided with a readout section and the noise cancellation circuit of the present invention. The MOS detector used in the present invention extracts signals at the timing of extracting only the noise components and the timing of extracting the signal components containing the noise components, respectively, and eliminates the noise components from them to produce signal components free of noise effects. The noise elimination circuit can make the impedance equal when outputting only the noise component and outputting the noise component and the signal component, so that the noise can be eliminated with high accuracy. Because of this noise cancellation circuit, the MO S detector used in the present invention becomes a high-performance MO S detector that achieves a practical level of low noise and can perform noise elimination at high speed. If the MOS detector of the present invention is used as a solid-state imaging element, the photoelectric conversion detection part of the MO S detector and other circuits (IV-changed paper standards should not use the Chinese National Standard (CNS) Α4 specification (210X 297mm) _ 28 _ " " f, please read the notes on the back before filling in this page) • Packing • Order the Ministry of Economic Affairs Central Sample Bureau Employee Consumer Cooperative Printed by the Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperative Printed 306073 a? B7 V. Description of the invention (26) Replacement circuit, AGC circuit, CLP circuit, ADC circuit) can be manufactured using the general MOS process • Therefore, it is very easy to form the above circuits on the same semiconductor die. In addition, it can achieve low power consumption. When used in video cameras, it can be driven with a single voltage, which can simplify the power circuit and facilitate battery drive. Embodiment 1 System Embodiment The following describes various systems that use a MO S-type solid-state camera device that can realize low power consumption, low voltage, and good S / N, and can implement a single power supply. Fig. 4 shows the general structure of the device using the MOS detector as the image detection section. In the figure, the device is composed of an optical system A1, a MOS detector β 2 and a signal application unit A 3. The optical system A 1 is a device that guides the optical image to the MO S detector A 2. Specifically, it is a combined lens, prism, pinhole, dichroic mirror, focusing optical fiber suitable for the purpose of the system, It consists of concave mirror, convex mirror, color filter, shutter mechanism, aperture mechanism, etc. The MOS detector A 2 is a device that converts the optical image guided by the optical system A 1 into a portrait signal corresponding to its light quantity, and outputs only signal components without noise after noise processing. The element of the noise elimination processing of the MOS detector A 2 is a noise elimination circuit which is one of the important elements described later. , Signal Application Department A 3 will detect the MOS after noise reduction. This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm) ^ Binding (please read the precautions on the back before filling this page )-29 _ 306073 A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs.  5. Description of the invention (27) The output of the device A 2 matches the type processing of the system. For example, when the system is a video camera, the signal application part A 3 is an application function part that converts the image signal output from the MO S detector A 2 into a composite video signal such as the PAL method or NT S C method. The MOS detector A 2 can be driven by a single power source, and uses a photodiode as the light-receiving part which converts light into an electrical signal. The β photodiode is equivalent to a pixel. There are many reasons for the arrangement, and the matrix is the same as the conventional device. In order to miniaturize the pixels, the area of the photodiode becomes smaller, so its output becomes smaller. In order to amplify this small output, an amplifier (transistor) is provided corresponding to the pixels. The noise generated by the amplifier (transistor) (the noise component that is unavoidable due to the characteristics of the amplified transistor) is reset by the output of the photosensitive diode of the MO S detector A 2. The output signal (noise component) of the amplifier (transistor) during reset operation is maintained, and the retained output signal (noise component) is used with the amplifier before the reset operation or after the reset operation (electric The output signal of the crystal) (signal component + noise component) eliminates both processing operations to eliminate noise and extract only the signal component. The MOS detector A 2 is formed as follows to generate a 1 / f noise-free output with a voltage amplitude of the output signal of about 1 OmV or less and an output current of about 1 M A or more. The dynamic range of the output of the M ◦ S detector A 2 can be raised to about 70 dB or higher than the C C D detector. If proper signal processing is implemented, it can be increased to about 90 d B, which is the same as that of the silver salt film. In this way, a single power supply can be used, and the magnified type with high sensitivity can be used. This paper standard is applicable to the Chinese national standard (CNS> A4 specification (. 210X 297mm> _ 3〇_ I -------- ^ ------, 玎 ----- 10 /-(Please read the precautions on the back before filling this page) 306073 A7 B7 5. Description of the invention (28) MOS detectors are used as various systems for camera devices, which can achieve low power consumption and low voltage, and can provide magnified MO S type solid-state camera devices (amplified type) with good S / N MOS detector) application device. The second embodiment applies an enlarged MO S detector to a video camera. FIG. 5 shows an embodiment of a video camera using the MO S detector of the present invention. As shown in FIG. 5, the video camera 10 of the present invention 0 includes: an optical system lens 101 that accepts a subject image; a focal length adjustment mechanism 1 0 2 that adjusts the focal length of the optical system; an aperture mechanism 1 1 6 that controls the amount of incident light that adjusts the system and the focal length adjustment mechanism 1 0 2 Aperture adjustment focal length adjustment circuit 1 0 3; the optical image formed by the lens 101 is converted into pixel units corresponding to the optical signal of the optical image by the pixel unit MOS detector 105; set On the imaging surface side of the MOS detector 105, a color filter array 104 having any color filter in RGB in each pixel: converts the electrical signal generated by the MOS detector 105 into a current voltage of a voltage signal Conversion circuit 106; AGC circuit that adjusts the level of the voltage signal generated by the current-voltage conversion circuit 106; Clamp circuit (CLP) 108 that clamps the level of the voltage signal through the AGC circuit 107 to become equal ; Loss generated by CLP 1 0 8 A / N conversion circuit (ADC) 1 0 9 that converts to a digital signal corresponding to the level; generates a timing control circuit 110 that forms a timing pulse (clock signal) that forms the basic timing as a system action; synchronizes with the The clock signal output by the timing control circuit 110 is in accordance with the Chinese National Standard Falcon (CNS) A4 specification (210X297mm) _ 31--------- 7 丨 installed ------ ordered- --- 'I line ff (please read the precautions on the back and then fill out this page) Printed by the Ministry of Economic Affairs Central Falcon Bureau Shellfish Consumer Cooperative Printed by the Ministry of Economic Affairs Central Bureau of Fine Arts Shellfish Consumer Cooperative Du Printed A7 ___B7_ V. Description of the invention (29) TG / SG circuit 1 1 1 that controls the driving of the MOS detector 105: a process control circuit 112 that processes the digital signal generated by the ADC 109 for the process; it will be processed through the process control circuit 112 The processed signal is encoded by an encoding circuit 113; an output circuit 114 that outputs the encoded signal; a digital analog conversion circuit 115 that converts the signal output through the output circuit 114 into an analog signal. In the video camera 100 having the above-mentioned structure, the light incident from the subject enters the MOS detector 105 through the lens 101, and the incident light is converted into an electrical signal through photoelectric conversion to become a current value output. On the MO S detector 105, a color filter array 104 corresponding to the regular arrangement of the red, blue, and green color filters of each% map is formed. In this way, a color image signal corresponding to 3 primary colors is output from one MOS detector 105 as an electrical signal. 'The electrical signal output from the MOS detector 105 is supplied to the ADC circuit 109 through the current-voltage conversion circuit 106, the AGC circuit 107, and the CLP circuit 108. The ADC circuit 1009 converts the image signal generated by the CLP circuit 108 into, for example, digital data with a sampling value of 8 bits, and supplies the data to the process control circuit 112. The process control circuit 1 1 2 is composed of, for example, a color separation circuit, a clamp circuit * r correction circuit, a white limit circuit, a black limit circuit, and a knee circuit, etc., and performs process processing on the supplied image signal as necessary. If necessary, color balance and other processes are implemented. The signal processed by the process control circuit 112 is supplied to the encoding circuit 113. This paper scale is applicable to Chinese national standard (CNSM4 specification (210X 297mm) _ 32--------- Γ — private clothing ------ 1T ----- 1 ^ f if (please first Read the precautions on the back and fill in this page) Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 306073 at _B7 V. Description of the invention (3) The encoding circuit 113 calculates the signal sent and converts it into a luminance signal and a color difference signal If you want to use the output of the network channel video camera, the encoding circuit 113 will be converted into a composite video signal such as PAL or NTSC. MOS detector 105, current voltage conversion circuit 106 by TG / The timing signal generated by the SG (timing generator / signal generator) circuit 1 1 1 and the synchronization signal control the timing. The operation power and output voltage of the TG / SG circuit 111 and the power bit supplied to the MOS detector 105 Then, the video signal is supplied to the D / A conversion circuit 1 1 5 through the output circuit 1 1, and the D / A conversion circuit 1 1 5 converts the input signal into an analog video signal, which is used as a camera signal. • The image signal can also be used as digital through the output circuit 1 1 4 The signal is output directly. The 4 signals of each camera are supplied to recording devices such as video recorders and monitoring devices. * The low power consumption and low voltage in this embodiment, and the video camera that must process 30 frames of images within 1 second can be During the horizontal retrace period, the fixed noise component is eliminated, and a video camera capable of generating high-quality image signals with good S / N can be provided. The color filter array 104 in this embodiment and the MO as the camera device The S detector 105 is separate. However, in recent years, if the CCD device is considered, there are many devices in which the camera device and the color filter are integrated. Therefore, the color filter array 104 and the MO S detector 1 can be used. 0 5 becomes the structure of the body. The color filter array 1 04 and the MOS detector 1 05 are integrated into a camera device that can be formed into the structure shown in Figure 6. This paper standard uses the Chinese National Standard (〇 ^) 8. 4 Specifications (2 丨 0 / 297mm) _33_ I- IIII n I Pack — I — Order — II — Line f ^ (Please read the precautions on the back side before filling out this page) Printed by the cooperative 306073 A7 __ ___B7_ V. Description of the invention (31) That is, each photosensitive diode on the light-receiving surface side of the semiconductor substrate S ub in which many fine photosensitive diodes PD are arranged in a matrix is formed on the light-receiving side of each photosensitive diode to receive light The light-shielding film Ms t of the light-shielding mask partially open in the surface area is formed with a transparent smooth film Mf t on it, and a cyan filter FCy, a fuchsia filter FMg, and a yellow filter FY e are formed thereon. The photodiode PD is divided into Mg for a magenta image, G for a green image, Ye for a yellow image, and Cy for a cyan image. The cyan filter FCy is formed on the light-receiving surface of the photodiode for green images and the cyan image, and the fuchsia filter FM g is formed on the light-receiving surface of the fuchsia image-sensitive photodiode. The yellow filter FY e is formed on the light-receiving surface of the photodiode for yellow images. Then, a transparent top coating layer 0 c is formed on the top, and a microlens array L m c is formed on the top. The microlens array L m c is arranged * Many tiny lenses are formed, and each tiny lens part is located on the light receiving surface of the photodiode PD. The microlens array Lm c can ensure the incident amount of light incident on the photodiode PD, so as to improve the detection sensitivity of the photodiode PD. If the above-described color filter integrated camera device is used as the imaging element (MOS detector 105) of the single-plate camera system, there is no need to separately set color filters, and the MOS detector 10 can be omitted. 5. On the light-receiving surface, the positioning of each pixel by the color filter can save the space of the optical system. f Third Embodiment This paper scale is applicable to China National Standard Falcon (CNS) A4 specification (210Χ297mm) _ 34---------— I ------ Ιτ ----- 1 ^ (Please read the precautions on the back and then fill out this page) A7 B7 Printed by the Central Consumer Council of the Ministry of Economic Affairs Employee Consumer Cooperative V. Description of the invention (32) 1 | Apply the magnifying Μ 0 S detector rrbg to the video camera I Figure 7 shows another example of the use of the M 0 S detector of the present invention-video camera 1 1 1 camera embodiment. The example shown in Figure 7 is for the single board shown in Figure 5--X 1 I Please I-type camera system »Divide the camera system into RG Β (Red 9 Green> Blue), etc. 3 First Reading 1 I Read 1 1 Example of a 3 Panel Video Camera of 1 System 0 As shown in Figure 7 > Back of the invention 1 1 Video camera 1 0 0 — 2 Including; The optical system that accepts the subject's image Note 1 | Lens 1 0 1; Adjust the optical system The focal length adjustment mechanism of the distance is filled with 1 1 0 2 t. The aperture mechanism 1 1 6 that controls the amount of incident light of the optical system and the focal socket are installed. I The optical group adjustment and focal length adjustment circuit of the distance adjustment mechanism 1 0 2 will change Ά 'w- 1 1 1 Lens 1 0 1 The received optical image is decomposed into RG Β and other i- primary color components 1 1 Color decomposition 珜 鏡 2 0 1 R 2 0 1 G 2 0 1 B Formed by each 1 1 color Decompose 珜 鏡 2 0 1 R 2 0 1 G 2 0 1 B into the image of the three primary color components such as 1 RGB, and convert it into pixel units to the imaging element R which corresponds to 1 | The component uses G into 1 I. The component uses B. The component uses Μ 0 S detector 1 0 5 R 1 0 5 G 1 line 1 0 5 B: Each Μ 0 S detector 1 0 5 R 1 0 5 G 1 1 0 5 B R component system for converting electrical signals generated into voltage signal 1 1 For G component system B Current-voltage conversion circuit for sub-system 1 1 1 0 6 R • 1 0 6 G »1 0 6 Β Adjust the voltage signal generated by the current-voltage conversion circuit 1 | 1 0 6 R 1 1 0 6 G > 1 0 6 Β Level 1 I For R component system 9 G component system, B component system AGC circuit 1 1 I circuit 1 0 7 R »1 0 7 G * 1 0 7 Β * Clamp via AGC circuit 1 1 1 0 7 R »1 0 > 7 G» 1 0 7 Β and the level becomes equal to the voltage signal No. 1 1 for the R component system 9 G component system »Β component system clamp 1 1 This paper size is suitable for China National Standard Falcon (CNS) Μ specification (210X297 mm) -35- A7 ___B7_ printed by the Employee Consumer Cooperative of the Central Department of Economics of the Ministry of Economy V. Invention Description (33) Road (CLP) 108R, 108G, 108B; CLP 108R The output generated by 108G, 108B is converted into R component system, G component system, B component system analog digital conversion circuit (ADC) 109R, 109G, 109B of the digital signal corresponding to the level. Basic The timing control circuit 110 of the timing pulse of the sequence; the timing pulse generated in synchronization with the timing control circuit 1 1 0 controls the driving of the MOS detector 105 for the R component system, the G component system, and the B component system Use the TG / SG circuit 111; output the digital signals generated from the ADC 109R, 109G, 1 0 9 B to the process control circuit 1 1 2 of the process kll; encode the signal processed by the process control circuit 1 1 2 into the process An encoding circuit 113; an output circuit 114 that controls the input and output of the encoded signal; and a digital analog conversion circuit 115 that converts the ^ signal output through the output circuit 114 into an analog signal. In the video camera 1 0 0-2 with this structure, the light reflected from the subject passes through the lens 101, and the color decomposition is carried out 201R, 201G, 201B imaging on the MOS detector 105R, 105G, 105B . Each color decomposes 201R, 201G, 201B to decompose the optical image into three primary color components such as RGB. The image is decomposed into two primary color components such as RGB, 2 0 1 R '2 0 1 G, and 2 0 1 B by color decomposition. The MOS detectors 1 0 5R, 1 0 5G' 1 〇5 B Imaging π on MOS detectors 105R, 105G, 105B imaging. The paper size is applicable to China National Standard (CNS) A4 specification (210X 297mm) _ 36 _ ---------. 1¾. ------, 玎 ------ ^! „(Please read the precautions on the back before filling out this page) A7 ___ B7 _ ^ _ printed by the Employees’ Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (34 ) The optical image of the R component, G component, and B component is photoelectrically converted into a current signal to become a current value output corresponding to the brightness. The electrical signals of each component generated from the MOS detectors 105R, 105G, 105B pass The current-voltage conversion circuits 106R, 106G, 106B, AGC circuits 107R, 107G, 107B, CLP circuits 108R, 108G, 108B of each component are supplied to the ADC circuits 109R, 109G, 109 B. The ADC circuits 109R, 109G of each component, 109B According to the image signal ^ 9 generated from the CLP circuit 109 changes fc into, for example, a digital data with a sampling value of 8 bits, and supplies the data to the process control circuit 1 1 2 »The process control circuit 1 1 2 r Correction circuit, white limit circuit, black limit circuit, knee circuit, etc., process processing is performed on the supplied image signal if necessary "and color balance and other processing are carried out as needed. The process control circuit 1 1 2 processor The signal is transmitted To the encoder 1 1 3. The encoder 11 3 calculates the signal sent, and performs color balance processing. If the network is used to communicate with the video camera output * The encoder 113 is converted into a standard color TV broadcast method PAL mode and NTSC mode and other composite image signal processing. MOS detector 10R, 105G, 105B, current voltage conversion circuit 106R, 106G, 106B are generated by the TG / SG circuit 1 1 1 corresponding to its own system The timing signal and the synchronization signal control the timing. The operation power of the TG / SG circuit 111 This paper standard applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) _ 37---------- ^- I ^ ------ 1T ------ Φ >. ί (Please read the precautions on the back before filling out this page) Du7 A7 ___B7_ for consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs 5. Invention description (35) and the level of the output voltage and supply to the MO S detector 1 0 The power level of 5 is the same. Then, the video signal is supplied to the D / A conversion circuit 1 1 5 through the output circuit 1 14, and the D / A conversion circuit 1 15 converts the input signal into an analog video signal and outputs it as a camera signal. The image signal can also be directly output as a digital signal through the output circuit 1 1 4. The above camera signals are supplied to recording devices and monitoring devices such as video recorders. The video camera with low power consumption and low voltage in this embodiment, which needs to process 30 frames of portraits within 1 second, can be used during horizontal retrace A video camera that internally eliminates fixed pattern noise components to ensure good image quality and high-quality image signals. The above embodiment is an example in which an optical image is decomposed into three primary color components such as R G B using color decomposition jelly. Other dichroic mirrors can also be used for color decomposition. For example, □ Use red reflection, green reflection, blue reflection and other dichroic mirrors to separate and distribute the incident light, and decompose the optical image into RGB components. The optical image is captured by a MOS detector for R image, G image, and B image to form a portrait signal of R image, G image, and B image. In this way, it is possible to divide the optical image into the components of the three primary colors without using 珜 鏡. Fourth Embodiment Applying an amplified MOS detector to a network system. FIG. 8 shows an example of a system configuration in which the signals of the video cameras 100, 100-2 are sent to a monitor or the like via a network. In the picture * 3 0 0 is the network, which can be L AN (Local Area Network), the standard of the public paper is in accordance with the Chinese National Standard (CNS) A4 specification (210X297mm) -38-IIII — I ~~ 线 线 ί ·-(Please read the precautions on the back before filling this page) 306G73 printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (36) Line (telephone line) ^ dedicated line, etc., or Internet, Intranet . The video cameras 100, 100-2 are connected to the network 300 via an interface 301. 3 1 0 is a flexible terminal (Intelligent Terminal), equivalent to a personal computer or workstation. The flexible terminal 3 1 0 has a computer body 3 1 1 including a processor or main memory, a clock generator, etc., an interface 3 1 2 for network connection, a video RAM 313 for an image display memory, and a printer interface 314 , SCSI (Smal 1 Computer System Interface) and other standard bus interfaces 3 1 5, 3 1 7, and video camera connection interface 31,%. The above components are connected by internal busbars. The video RAM 313 is connected to a monitoring device 318 such as a CRT monitor or a liquid crystal display. The printer interface 3 1 4 is connected to the printer. The standard bus interface 3 1 7 is connected to an optical disk device, a hard disk device, or a large-capacity external memory device 3 2 0 such as a DVD (Digital Video Disc). The standard bus interface 3 1 7 is connected to, for example, an image scanner 3 2 1 that inputs images from hard copy. The video camera connection interface 3 1 6 is connected to the video camera 1 0 0 0 described in the above embodiment. According to the above structure, the portrait of the subject formed by the video camera 100 0 or 1 0 0-2 shooting is to encode The device 113 uses a network or the like to communicate with the output of the video camera, and converts it into a digital signal that has undergone image compression processing in the MP EG method. The composite image signal is output as digital data on the network 300 via the interface 301 in a network format. The network 300 is connected to the live final paper standard via the interface 312. The standard of the Chinese National Standard (CNS) A4 (210X297 mm) _ 39 _ ---------- ^ ------, order ------ ^- < (Please read the precautions on the back before filling in this page) Printed by the Consumer Cooperative of the Central Provincial Bureau of the Ministry of Economic Affairs A7 B7. V. Invention description (37) Terminal equipment 3 1 〇. If the transmission data generated by the video camera 1 ο 0 or 1 〇〇-2 needs to be sent to the flexible terminal device 31〇 ', then the flexible terminal device 3 1 0 computer 3 1 1 from the network 3 0 0 Input and send data via interface 3 1 2. The computer itself 3 1 1 extracts the portrait information part from the transmission data. Since the video camera 1 〇 〇 or 1 0 0-2 is in the process of compressing the image, the computer itself 3 1 1 stretches the image to restore the original image. Then, the restored portrait data is sequentially written into the video RAM 313. Because the portraits are moving pictures, the portrait data of the video RAM3 1 3 is continuously updated. As a result, the video data sent from the video camera 100 or 100 2 is displayed on the monitoring device 3 1 8 that uses the portrait data of the video RAM 3 1 3 as a picture to image 1®. The image of the object formed by the video camera 100 0 is converted by the encoder 113 into digital data subjected to image compression processing by the MP EG method for communication of the video camera output through the network, etc., through the interface 3 16 is output to the computer body 3 1 1, and the computer body 3 1 1 stretches the portrait and restores the original portrait. Then, the restored image data is sequentially written into the video RAM 313. Because the image is an animation, the image data of the video RAM3 1 3 is continuously updated. In this way, the video device sent from the video camera 100 is displayed on the monitoring device 3 1 8 that uses the portrait data of the video RAM 3 1 3 as a portrait display. If the computer computer 311 wishes to transfer the portrait of the video camera 1 〇 connected to the flexible terminal device 3 1 0 to the network 3 0 0 ', it will be edited into the transmission format of the network via the interface 3 1 2 Printed on the Internet. The paper standard is in accordance with Chinese National Standard (CNS) A4 (210X 297 mm) _ 4〇- ^ —Binding '' line π I (please read the precautions on the back before filling in this page) Central Ministry of Economic Affairs Printed by the Bureau of Standards and Staff Consumer Cooperative «A7 __B7_ V. Description of the invention (38) 3 0 0. Fifth Embodiment An enlarged MO S detector is applied to a still camera. FIG. 9 is an embodiment of a still camera using the MO S detector of the present invention. As shown in FIG. 9, the still camera 400 of the present invention includes an optical system 4 1 1 that has a lens system and an aperture and accepts a subject image; the MOS that forms the image received by the optical system 4 1 1 Detector 4 1 5: Located between the imaging surface of the MO S detector 4 1 5 and the optical system 4 1 1, the light kt that can be mounted between the two, when inserted into the optical path, will The subject image received by the optical system 4 1 1 is allocated to the viewing window 4 1 4, and when it is out of the optical path, the subject image received by the optical system 4 1 1 is imaged on the MO S detector 4 1 5 the imaging surface of the mirror with a shutter function 4 1 2; guide the reflected light of the mirror 4 1 2 to the viewing window 4 1 4 mirror 4 1 3; from the MOS detector 4 1 5 according to the color composition Camera circuit 416 that reads the image signal: A / D converter 417 that converts the read output into a digital signal; frame memory 418 that holds the digital signal converted from the A / D converter 417 in units of screens: Compressed circuit 4 1 9 that compresses the digital signal of the digital memory 4 1 8 held in the frame in picture units; memory card 4 2 1 that stores animal image data: controlled by the compressed circuit 4 1 9 Profile portrait in order to write the memory card 421 in the card control circuits 420. According to the above structure, the subject image received by the optical system 4 1 1 after operating the shutter button (not shown) is imaged on the MO S detector 4 15. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) 1 — Pack — 1111 — Order — 11 is (please read the precautions on the back before filling this page) B7 5. Description of the invention (39) Μ〇 The S detector 4 15 is a solid-state imaging device with a noise cancellation circuit used in the present invention. After the optical image received by the optical system 4 11 is imaged, it is converted into light quantity corresponding to the optical image in pixel units Electrical signal. In order to be able to photograph color portraits, a color filter array with any color filter in RG Β is provided for each pixel on the imaging surface side of the MO S detector 415, and the camera circuit 4 16 detects the MO S The electrical signals generated by the devices 4 1 5 are separated according to the components of RG B and output. The current-voltage conversion circuit 106 converts the electrical signal according to the color component generated by the imaging circuit 4 16 into a digital signal, and the converted digital signal is temporarily held in the frame memory 418 in units of screens. The digital signal held by Ν 1 in the frame memory 418 is compressed by the compression circuit 4 1 9 in units of portraits, and output to the card control circuit 4 2 0. The card control circuit 4 2 0 controls and memorizes the data of the compressed portrait in the data and memory card 4 21 of the memory media. The Ministry of Economic Affairs Zhongshen Falcon Bureau employee consumption package is printed (please read the precautions on the back before filling out this page). In this way, the memory card 4 2 1 is compressed in units of screens and is still frozen every time the shutter button is operated. Portrait, and remember it. The memory card 4 2 1 can be loaded and unloaded on the camera, and the portrait stored in the memory card 4 2 1 is inserted in a reading and reproducing device (not shown). After the portrait data is extended and restored, it is displayed on the monitoring device. Or output to hard copy devices such as video printers for viewing. According to the present embodiment, not only can low power consumption and low voltage be achieved, but also high-speed continuous shooting motion of many frames per second of continuous photography per second can be achieved by high-speed S / N, which can provide a compact, high-function, high-performance still camera. It is also possible to eliminate the problematic solids in the MO S detector in a short period of time. ^^ Graphic miscellaneous paper scales are applicable to China National Standards (CNS > Α4 specifications (210X297 mm).览 A7 ____B7_ V. Description of the invention (4) A still camera with good S / N, which can form high-quality photos. The sixth embodiment applies an enlarged MO S detector to the telephone fax machine. Figure 0 shows an embodiment of a telephone facsimile device using the MOS detector of the present invention. The figure shows the principle structure, which will be handwritten or printed manuscripts or photographs and other sheet manuscripts. The transport mechanism is transported to the main scanning direction (arrow B direction), fixed at a certain position, with the MOS detector 5 0 2½¾ image information of the original set in the transverse direction of the original. 503 is the light source, and 504 is the MOS detection The light-receiving surface of the detector 502 forms a lens of the original image. The MO S detector 5 0 2; (is a linear detector that arranges the light-receiving portion (photosensitive diode) of the pixel unit into a one-dimensional element. That is With the noise cancellation circuit used in the present invention Monochrome solid-state imaging device. After inserting the sheet-shaped original 501 on the telephone facsimile device, the main transport mechanism (not shown) transports the original 501 to the main scanning direction (direction of arrow B). A light-receiving surface of the MOS detector 5 0 2 fixed at a certain position forms a portrait of each line of the original through the lens 5 0 4. The MO S detector 5 0 2 reads the image information of the imaged original That is, in this way, the signal corresponding to the light-receiving position is read out in the pixel unit as the portrait signal from the MOS detector 50 2 according to the pixel arrangement order, so the amplifier 50 5 is used in accordance with its output order After magnifying it, the Chinese National Standard (CNS) Α4 specification (210Χ 297 mm) is applicable to Α / This paper standard ^ Binding travel air (please read the precautions on the back before filling this page; > -43- The Ministry of Economic Affairs, the Central Oak Quasi-Bureau's negative work consumer cooperation Du Printing 306073 at B7 V. Description of invention (41) D converter 5 0 6 Convert the amplified image signal into a digital signal, and then use modem 5 0 7 to change into a telephone The line is used for output on the telephone line. Demodulate it on the receiving side The received signal can be regenerated into a hard copy of the image by printing pixels * in the order of acceptance toward the transverse direction of the recording paper transported to the main scanning direction according to the density of the signal value. According to this embodiment, not only can the power consumption be reduced , Reduce the voltage, and achieve high-speed reading with high S / N, can provide a compact, high-function, high-performance telephone fax device. You can also eliminate the fixed pattern of MOS detector problems in a short time The information component can provide a phone with good S / N and high-speed transmission of high-quality images. < In recent years, linear detectors have emerged that can be in close contact with the original surface to read images. Therefore, in order to form a contact type, the lens that guides the original image, the image guided by the lens can be imaged, and it is converted into the light-receiving unit of the pixel unit of the electrical signal corresponding to its light amount, and The light emitting elements that illuminate the surface light are integrated into one body, and such a structure can be used. Seventh embodiment An enlarged MO S detector is applied to a copier. FIG. 11 shows an embodiment of an electronic copier using the MO S detector of the present invention. The figure shows the structure in principle. Place the transparent glass and other original placing table 6 0 2 on the box-shaped housing 6 0 1, and place the handwriting original on the original placing table 6 0 2: drop or printed originals, or sheet originals such as photographs 6 0 3 and press the cover 6 0 4 Crimped manuscript》 This paper is suitable for Chinese national standard see grid ™ --------- install ------ order ------ travel if (please read the notes on the back first (Fill in this page again) 306073 A7 A7 ___B7_ Printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs 5. Description of the invention (42) Set in the frame 6 Ο 1 near the position immediately below the original table 6 Ο 2 An optical system that moves repeatedly at a certain speed from one end of the original placing table 602 to the other end. Here, this repeated movement direction is referred to as the main scanning direction. The optical system is composed of a rod-shaped light source 605, a mirror 606, and a lens 607, and the light source 605 is provided in a direction perpendicular to the main scanning direction (this direction is called a sub-scanning direction). A MOS detector 608 is provided at the imaging position of the lens 607. MOS detector 6 0 8 is a linear detector that arranges the light-receiving portion (photodiode) of the pixel unit into a one-dimensional element, that is, a monochrome solid-state camera with a noise cancellation circuit used in the present invention Device. 1 MOS detector 6 0 8 images an image corresponding to one line in the sub-scanning direction and converts it into a signal corresponding to the amount of received light. The scanning controller 6 0 9 controls the MO S detector 6 0 8 to output the signal corresponding to the received light amount in pixel units from the MO S detector ^ 6 0 8 according to the pixel arrangement order, and outputs it as a portrait signal, And control the main scanning direction of the optical system to drive movement, so that the optical system sequentially moves toward the main scanning direction. The system controller 6 1 0 controls all the systems, and controls the output of the laser light source 6 1 1 according to the signal corresponding to the received light quantity generated by the MO S detector 6 0 8. The laser light source 6 1 1 generates a point-shaped laser beam. The laser beam generated from the laser light source 611 is reflected by a scanning mirror that scans the laser beam, that is, the polygon mirror 612, and is imaged on the cylindrical photoreceptor cylinder 613. The imaging position is the drawing position. The photoreceptor cylinder 6 1 3 is a cylinder rotating in one direction at a certain speed. The photoreceptor cylinder 6 1 3 is made to be upstream of the laser beam irradiation position by a charging device (not shown) (This paper standard uses the Chinese National Standards (CNS) M specifications (210Χ 297 mm) I-- ------- ^ ------ Ιτ ------ ^ ί | (Please read the precautions on the back before filling in this page) Printed A7 ___B7_ by the Consumer Labor Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (43) The position upstream of the drawing position) is charged. The polygon mirror 6 1 2 is controlled by the system controller 6 10 so that the spot laser beam scans on the surface of the cylindrical photoconductor 613 corresponding to the output speed of the signal generated by the MOS detector 608. If the rotation direction of the cylinder of the photoreceptor barrel 6 1 3 is the main scanning direction, the laser beam scanning and the rotation direction perpendicularly intersect, and the amount of light emitted from the laser beam is formed on the surface of the cylinder. The electric charge is equivalent to the latent image of the original image. When the photoreceptor cylinder 613 passes the installation position of the developing section 6 1 4 that makes the latent image a visible image at a position downstream of the drawing position, the latent image at that position is displayed with the coloring body supplied by the developing section 6 1 4 The image makes' fe is a visible image. Then, each time the colored image is taken out from the copy paper storage tray 615, the copy paper is transferred to the transfer path 616 transferred to the lower position of the photoreceptor cylinder 613. 5 The transfer speed of the copy paper is synchronized with the rotation speed of the photoreceptor cylinder 613, and the color image of the latent image formed on the surface of the photoreceptor cylinder 6 1 3 is sequentially drawn and transferred on a line unit and left on the copy paper The color image of the same image as the original. The conveying path 616 is a path for conveying copy paper to which the colored image is transferred to the discharge port, and conveys the copy paper to the discharge port by the conveying mechanism provided in the conveying path 6 1 6. The fixing section 6 1 7 is a device for fixing the coloring agent in front of the discharge port. When the paper for transferring the colored image passes through the fixing section 6 17, the coloring agent is fixed on the copy paper and then discharged to the discharge port. According to this structure, at the time of copying, a sheet-shaped manuscript 603 is placed on the manuscript placing table 602, and the manuscript is pressed against the mandrel 604. Because the & scale of the manuscript is applicable to the Chinese National Standard (CNS standard (210X297 1) I ------- II ------ 1T ------ 'Λ.... (Please read the notes on the back before filling in this page) 46 Central Ministry of Economic Affairs A7 B7 printed by the Bureau Cooperative Consumer Co., Ltd. V. Description of invention (44) Near the placement table 6 0 2 there is an optic that moves repeatedly from one end of the original placement table 6 0 2 to the other in the main scanning direction at a certain speed System * Therefore, after the start printing button is operated, the light source 6 0 5, the mirror 6 0 6, and the lens 6 0 7 in the optical system repeatedly move toward the main scanning direction. Assuming that the main scanning direction is the vertical direction, the original placing table 6 0 2 The horizontal direction is the width direction. At this time, the irradiation of the light source 605 constituting the optical system is equivalent to the original The range of the width of the stage 6 0 2 and the mirror 6 0 6 and lens 6 0 7 forming the optical system form an image of the illuminated range on the light receiving surface of the MOS detector. The MO S detector 6 0 8 will The light-receiving part (photodiode) of the pixel unit is arranged as a linear linear fe detector, that is, a monochrome solid-state imaging device with a noise cancellation circuit used in the present invention. Therefore, the MOS detector 6 An image corresponding to one line in the width direction (that is, one line corresponding to the sub-scanning direction) is formed on 0 8 and converted into a signal corresponding to the received light M. The scanning controller 6 0 9 controls the MO S detection The detector 6 0 8 reads out the signal corresponding to the amount of received light in pixel units as the best image signal according to the pixel arrangement order, and outputs it as well as controls the movement of the main scanning direction of the optical system to make the optical The system moves to the main scanning direction in sequence. Therefore, the image of the original 6 0 2 of the original placing table 6 0 2 is sequentially oriented toward the main scanning direction, and a line unit in the sub-scanning direction is generated in the order of pixels in accordance with the order of pixels. Signal. 'This signal is transmitted to the system controller 6 1 0, and the system controller 6 1 0 corresponds to the output of the laser light source 6 1 1. The emission intensity of the laser light source 6 1 1 corresponds to the output of the paper size from the MO S detector 6 0 8. China National Standard (CNS) Α4 specification (210X 297mm)!. I installed II ordered I line ^ ί (please read the precautions on the back before filling this page) -4 (-Ministry of Economic Affairs Central Bureau Falcon Bureau shellfish consumption Cooperative cooperative seal A7 B7_ V. Invention description (45) The amount of light received. The system controller 6 1 0 controls the polygon mirror 6 1 2 to oscillate in synchronization with the readout speed of the MOS detector 608, so the 'readout speed with the MOS detector 608 becomes synchronized by the polygonal mirror 6 1 2 On the photoreceptor cylinder 6 1 3, draw an optical image corresponding to an image corresponding to one line (that is, equivalent to one line in the sub-scanning direction). The photoconductor barrel 613 rotates in a certain direction at a peripheral speed corresponding to the main scanning speed. When the peripheral surface of the photoreceptor cylinder 6 1 3 reaches the drawing position of the laser light formed by the polygon mirror 6 1 2, it is already charged by the charging device. After the laser light is irradiated, the irradiated part's light cylinder 6 1 3 loses a charge equivalent to the amount of light irradiated. Therefore, on the photoreceptor cylinder 6 1 3, the area downstream of the direction of rotation of the scanning position of the laser beam formed by the polygon mirror 6 1 2 leaves the image of the original as a latent image. The latent image passes through the development At the position of the portion 6 1 4, the coloring agent supplied from the developing portion 6 1 4 is developed to become a visible image. This image is drawn out one by one from the copy paper storage tray 6 1 5 and transferred onto the copy paper transported to the transport path 6 1 6 under the photoconductor cylinder 6 1 3. The transfer speed of the copy paper and the rotation speed of the photoreceptor cylinder 6 1 3 are synchronized, and the color image of the latent image formed on the surface of the photoreceptor cylinder 6 1 3 is sequentially drawn and transferred on a line unit on the copy paper Leave the work & image of the same image as the original. The copy paper on which the colored image is transferred is transported by the transport mechanism to the discharge port through the transport path, and when passing through the fixing unit 6 17 provided in front of the discharge port, the fixing unit 6 17 fixes the colorant on the copy paper and discharges it. The paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) --------- 1¾ ------ 1T ------ 1 ^ side f (please read the back side first (Notes to fill out this page) A7 _B7__ printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention description (46) According to this embodiment, low power consumption, low voltage, and high S / N for high-speed reading Take, compact, high-function, high-performance electronic copier. That is, the fixed pattern noise component that can eliminate the problem of the MO S detector in a short time, can provide electronic images with good S / N, high-speed reading of high-quality images, and high-speed copying machine. In the above copier, the position of the original is fixed, and the optical system moves toward the main scanning direction. However, it is also possible to fix the position of the optical system and transport the original to the main scanning direction. The above-mentioned copier is a monochromatic device, but if the color filters of the three primary colors are installed in the optical system to perform color decomposition, a latent image is formed according to the color type, and the latent image of the color type is developed with a corresponding color developer A copier that can form color copies. Eighth embodiment An enlarged MO S detector is applied to the scanner. Figure 12 shows an embodiment of a portable image scanner using the MO S detector of the present invention. As shown in the figure, the image scanner 700 of the present invention is constructed by mounting an LED array 702 and a mirror 703 as a light source in a frame 701, and a roller 704. The length of the LED array 702 can reach the full width of the frame 701, and illuminate the outside of the frame 701 below. The mirror 7 0 3 is provided near the arrangement position of the LED array 7 0 2, and the image of the original illuminated by the LED array 70 2 is received in the frame 70 1 through the slit 70 1 a provided in the lower part of the frame 70 1 . The portable image scanner in Figure 12 places the frame 701 on the original, slides it on the original, and scans by manual operation. This paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) --------- ^ ------ IT ------ ^ (Please read the notes on the back first褢 ... write this page) I-49-A 7 B7 is printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. The invention description (47), in order to receive the original manuscript in one line unit from the slit 7 0 1 a The image is synchronized with the detection and reading of the line position, and a roller 704 is provided. In order to make the roller 704 contact the original and rotate by friction with the original, a part of its peripheral surface is exposed from the lower part of the frame 701. The exposed position is near the slit 70 la. Inside the housing 701, an encoder 705 which detects the rotation direction and rotation of the roller 704 in synchronization with the rotation of the roller 704 is provided. A MOS detector 706 is provided inside the frame 701, and a lens 7 0 7 ° MO S detector 7 is formed on the light-receiving surface of the MOS detector 706 to form the original image guided by the mirror 703 0 6 is a linear detector that arranges the light-receiving part (photodiode) of the pixel unit as a one-dimensional element. That is, a monochrome solid-state imaging device having a noise cancellation circuit used in the present invention. In recent years, most of the linear detector elements are close-contact detectors that are closely attached to the original surface and read a circular image. In order to form a close-fitting type *, a lens that guides the original image, forms an image guided by the lens, and converts it into a light-receiving unit in pixel units of an electrical signal corresponding to its light amount, and illuminates the original surface The light-emitting elements are integrated and formed. Here, in order to explain the principle, the structure shown in FIG. 12 is shown. The signal read from the MO S detector 7 0 6 corresponds to the position set by the output of the encoder 7 0 5 and is used to control the reading timing. According to this structure, the sheet original is placed on a flat surface , Place a hand-held scanner on it, and move it to the roller 7 0 4 on the original manuscript. The size of the rotatable paper is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210X297mm) --------- #-(Please read the notes 4 on the back first: write this page) --s line-50-A7 B7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (, 4〇) 1 I Turn around. This moving direction is the main scanning direction 9 At this time 9 LED array 1 1 I 7 0 2 Illuminates the original surface »The image of the original is shot into the mirror 1 I 7 0 3 through the slit 7 0 1 a and on the mirror 7 0 3 After reflection, the lens 7 0 7 is imaged on the Μ〇S please 1 1 | detector 7 0 6 〇 first smell 1 1 Μ 〇S detector 7 0 6 is a line image detector 9 on a fixed back 1 1 Μ 0 S detector 7 0 6 on the light-receiving surface 9 through the rule 7 0 7 to form a precautions 1 1 When reading the image information of the imaged original on a line of the original portrait 0 items-it 1 J As mentioned above, the portable image scanner of this embodiment is to place the page on the original manuscript I. Place the frame 7 0 1 to slide directly on the original manuscript and move the scan manually. At this time, in order to receive the 1 I circle image of the original from the slit 7 0 1 a in units of 1 line, a roller 7 0 4 t for the detection and reading of the line position is provided and 1 1 sets the roller 7 0 4 Contact original> The rotation direction of the encoder 7 0 5 output roller 7 0 4 and the corresponding detection signal of the rotation position 1 1 from the encoder 7 0 5 by its friction rotation result with the original The detection signal generated by the encoder 1 1 7 0 5 controls the output of the Μ 0 S detector 7 0 6 — 1 line signal makes it consistent with 1 line unit of the original and outputs «1 I Reduce power consumption * and voltage 9 and achieve high-speed reading with high S 1 1 | / Ν, which can provide compact and high-performance 1 1 I image scanning device. In a short time, it can eliminate the fixed pattern noise component in the Μ 0 S detector that is 1 1 in the problem 1 can provide — a kind of good S / N »high-quality images at a high speed of 1 1 Scanning device 0, 1 1 This embodiment describes a portable image scanner »but can also be applied to 1 | Place the original on the original placing table * Make the optical system perform the main scanning drive 1 I Desktop image scanning 〇In addition 1 can also be applied to the position of the fixed optical system 1 1 Use a ruler to print the paper standard standard home Guo Ligong 7 9 2 Printed A7 B7 by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention description (49) The device that transports the original to the main scanning direction. The above image scanner is described using a monochrome device as an example. However, a color filter of three primary colors is provided in the optical system to perform color decomposition, and generate an image signal of each color to realize an image scanner that can generate a signal of a color portrait. In addition, a concave mirror is used to form an optical system and the image is guided to the MOS detector by the concave mirror, or an optical fiber composed of bundled optical fibers is used to guide the image to the MOS detector. Embodiment 9 of Fig. 9 Desktop color image scanner The ninth embodiment is a structure of an optical system used for a desktop color image scanner. In the desktop color image scanner, the optical system is fixed at a certain position, and the original is scanned toward the main scanning direction. At this time, as shown in Fig. 13, a color filter of three primary colors is provided in the optical system to perform color decomposition to generate image signals of different colors. In Fig. 13, the MO S detector S that generates the portrait signal is a linear detector, which consists of arranging the straight lines of pixels as one line. A color filter F is provided on the light receiving surface of the MO S detector S. The color filters F are arranged side by side with R (red), G (green), B (blue) and other color components corresponding to the width and length of one line. An optical image of the original document DP is formed on the light receiving surface of the MO S detector S through the lens L and the color filter. The original document DP is illuminated by the light source LP. The color filter F is supported by a driving mobile scanning mechanism DR to be in a state of movable scanning, so that optical filters for various color components such as R * G, B, etc. This paper scale is applicable to the Chinese National Standard (CNS) A4 specifications (2 丨 0 > < 297mm) " -52-I ^-(please read the notes on the back of the page 4 J'l horse page) A7 __B7_ printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economics and Development (5〇) Move to the light receiving surface of MO S detector S. When receiving the light of the red image, the optical component of the color component of R is located on the light-receiving surface of the MO S detector S, and when receiving the light of the green image, the optical component of the G component is detected by the optical filter When the light of the blue image is received on the light-receiving surface of the detector S, the optical filter of the color component of B is placed on the light-receiving surface of the MO S detector S, so that its movement is synchronized with the collection timing of the image. In this way, the full image signals of the optical images for the color components of R, G, B and the like can be generated from the MOS detector S. The tenth embodiment applies the amplified MOS detector to the thin film scanning device. The amplified MOS detector of the present invention can also be applied to each of the 35 mm-length films read in a personal computer or an image display device, etc. A thin film scanning device that generates a picture signal from a frame. Figure 14 shows the structure. As shown in the figure, the device includes a close-contact linear detector S composed of an amplified MOS detector, and a silver salt long film FM on the light-receiving surface of the linear detector S that has been developed by S imaging The light source LP of the silver long film FM is illuminated at the position of the light receiving surface of the linear detector S, and a pair of conveying rollers C are transported at a certain speed on both sides under the silver salt long film. According to the above configuration, the silver salt long film FM is held by the transport roller C, and the transport roller C is rotated at a constant speed. Thus, the silver salt long film FM can be transported to a certain direction at a constant speed. Therefore, the close-contact linear detector S can be used to synchronize the image of the silver salt long film FM with the film transport speed. This paper standard can be used in accordance with the Chinese National Standard (CNS) Α4 specification (2 丨 0Χ297mm). --------- Yiyi ------ Ιτ ------ 0 (Please read the notes on the back t, ¾ this page) Printed by an employee consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _______B7_ V. Description of the invention (51) It produces a signal corresponding to the amount of light received by reading. The signal has been eliminated by noise, and only the film image of the image component can be converted into an electrical signal in line units and output. Embodiment 11 Applied to an autofocus mechanism FIG. 15 shows an embodiment of a monocular reflex camera with an autofocus mechanism using the MOS detector of the present invention. In the figure, the monocular reflex camera 800 of the present invention includes: a lens 8 0 1 with a focus position adjustment mechanism: a thin film film 8 0 3 that forms an optical image received by the lens 80 1 and is exposed; the lens 8 0 1. The received optical image is guided to the viewfinder 802a of the camera 800. The 802b: the autofocus detector module 8 0 4 of the present invention; it is composed of a half mirror and is set on the optical path of the lens 80 1. After the shutter is operated, the bouncing viewfinder mirror 8 0 5 completely separated from the optical path; installed on the back of the viewfinder mirror 8 0 5, when the viewfinder mirror 8 0 5 is located on the optical path of the lens 8 0 1 At this time, the penetrating optical image of the viewfinder mirror 805 is imaged on the auxiliary mirror 806 on the auto focus detector module 803. The auto focus detector module 8 0 4 uses the MO S detector with the noise cancellation circuit used in the present invention * As shown in FIG. 16, the light received by the MO S detector 8 0 4 a part A separation lens 8 0 4 b is fixed in front of the surface. MO S detector 8 0 4 a is a detector with a light-receiving surface with a two-dimensional array. As shown in Fig. 16, the 'separating lens 8 0 4 b is formed by arranging a pair of convex lenses. The size of the optical image paper distributed through the sub-mirror 806 uses the Chinese National Standard (CNS> A4 specification (210X297mm) -54-~ --------- ^ ------ tT ------ ^ (Please read the precautions i on the back, write this page) Printed by the Employees ’Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs» A7 _____B7_ V. Description of the invention (52) Imaged separately by the separation lens 8 0 4 b In other areas on the light-receiving surface of MO S detector 8 0 4 a. Separation lens 8 0 4 b formed by a pair of convex lenses arranged to guide the optical image to the light receiving of MO S detector 8 0 4 a The image can be formed on the light-receiving surface in different areas to form an object image. In this camera, the subject image received by the lens 801 is distributed from the viewfinder lens 805 to the 802b and 802b. Sub-mirror 806. The subject image assigned to the viewfinder mirror 8 0 5 is imaged on the viewfinder 8 0 2 a by 珜 鏡 8 0 2 b, making the subject image captured by the camera 8 0 0 available Observe the image. The subject image assigned to the sub-mirror 8 0 6 is directed to auto focus detection

測器模組8 0 4。自動對焦偵測器模組8 0 4係由MO S 偵測器8 0 4 a所構成，而在MO S偵測器8 0 4 a部分 之受光面前面設置分離透鏡8 0 4 b。該分離透鏡 8 0 4 b在MO S偵測器8 0 4 a之受光面上之各其他領 域內形成攝體像。因爲MO S偵測器8 0 4 a產生對應於 與在形成受> 光面之各圖素對應之感光二極體上成像之光學 像之光量之電氣信號，故依次將之讀出。 自動對焦偵測器模組8 0 4中，事實上由分離透鏡 8 0 4 b將MO S偵測器8 0 4 a部分之受光面分割於2 個畫像成像領域，若分別成像於2個畫像成像領域之被攝 體像之焦距對正時，如第1 6A圖中之8 0 6A所示， MO S偵測器8 0 4 a之输出係以各分割之畫像成像領域 之基準圖素位置P0，P0 >爲中心，分別出現相同之畫 本紙張尺度適用中國國家標準（CNS)A4規格（2丨0X297公釐）_ 55 _ ---------^------ir------^ (請先聞讀背面之注意事項I,〜寫本頁) 一 經濟部中央標準局負工消費合作社印製 A7 B7 五、發明説明（53) 像。 在前焦距（焦點位置從薄膜面偏向前位置之狀態）時 ，如第16B圖中806B所示，MOS偵測器804a 之输出係在較各被分割之畫像成像領域之基準圖素位置 P0，P0 >更靠近內側之位置分別出現相同畫像之狀態 〇 在後焦距（焦點位置從薄膜面偏向後位置之狀態）時 ，如第16C圖中806c所示，MOS偵測器804a 之输出係在較各被分割之畫像成像領域之基準圖素位置 P0，P0 >更偏離外側之位置分別出現相同畫像之狀態 〇 因此，根據MO S偵測器8 0 4 a之輸出計算調整透 鏡8 0 1之焦距使其朝向該MO S偵測器8 0 4 a之输出 以各該被分割之畫像成像領域之基準圖素位置P0， P 0 /爲中心，分別出現相同畫像之狀態所需之控制量而 控制相當於該控制量之焦點位置調整機構。如此，可調整 透鏡8 0 1之焦距使其與薄膜面對焦。 操作快門後，觀景窗鏡8 0 5彈跳而脫離光路，故透 鏡8 0 1所接受之被攝體像在薄膜面上成像，薄膜曝光而 攝影焦距對正之被攝體像。 具有本發明之自動對焦機構之照相機可在低消耗功率 ，低電壓之條件下實現焦距狀態之檢測，而且以髙S/N 實現高速讀取，即使在以髙速快門速度攝影時，或高速連 "攝攝影時，皆可從容的跟隨而檢測焦距狀態，可進行立即 本紙張尺度遑用中國國家標準（CNS)A4现格（ 210X297公釐）_ 56 - 抑衣-- (請先閱讀背面之注意事項一.‘寫本頁)Detector module 8 0 4. The auto focus detector module 8 0 4 is composed of a MO S detector 8 0 4 a, and a separation lens 8 0 4 b is provided in front of the light receiving surface of the MO S detector 8 0 4 a part. The separation lens 80 4 b forms a subject image in each of the other areas on the light receiving surface of the MO S detector 8 0 4 a. Since the MO S detector 804 a generates an electrical signal corresponding to the light quantity of the optical image formed on the photosensitive diode corresponding to each pixel forming the light receiving surface, it is sequentially read out. In the auto focus detector module 804, in fact, the separating lens 8 0 4 b divides the light-receiving surface of the MO S detector 8 0 4 a into two image imaging areas. The focal length of the subject image in the imaging area is aligned, as shown in 8 0 6A in Figure 16A, the output of the MO S detector 8 0 4 a is the reference pixel position of the divided image imaging area P0, P0 > as the center, respectively, the same picture paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297mm) _ 55 _ --------- ^ ----- -ir ------ ^ (Please read the precautions I on the back, ~ write this page) 1. A7 B7 printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (53). At the front focal length (the state where the focus position is shifted from the film surface to the forward position), as shown at 806B in Figure 16B, the output of the MOS detector 804a is at the reference pixel position P0 of each divided image imaging area P0 > In the state closer to the inner side, the same image appears respectively. In the back focus (the state where the focus position is deviated from the film surface to the back position), as shown in FIG. Compared with the reference pixel positions P0, P0 > of the divided image imaging areas, the positions of the same portrait appear separately. Therefore, the lens 8 0 1 is calculated and adjusted according to the output of the MO S detector 8 0 4 a The focal length is oriented toward the output of the MO S detector 8 0 4 a. The control amount required for the state of the same portrait is centered on the reference pixel position P0, P 0 / of each divided image imaging area. And control the focus position adjustment mechanism equivalent to the control amount. In this way, the focal length of lens 801 can be adjusted to focus on the film surface. After the shutter is operated, the viewfinder lens 805 bounces off the optical path, so the subject image received by the lens 801 is imaged on the film surface, and the film image is exposed and the subject image is aligned with the photographic focal length. The camera with the autofocus mechanism of the present invention can realize the detection of the focal length state under the condition of low power consumption and low voltage, and realize high-speed reading with high S / N, even when shooting with high shutter speed, or high-speed continuous " When taking pictures, you can follow it easily and detect the focal length status, you can immediately use the paper standard to use the Chinese National Standard (CNS) A4 spot (210X297mm) _ 56-Yiyi-(please read the back first Note 1. Write this page)

，1T 經濟部中央標準局貝工消费合作社印製 A7 __B7 五、發明説明（54 ) 對焦控制而攝影鮮明之盡像*亦即可在短時間內消除 MO S偵測器之問題之固定圖型雜訊成分，以良好之S/ N高速的讀取高畫質圖像而以高速檢測對焦狀態，可立即 進行對焦控制，可攝影鮮明之畫像。 以上係以單眼反射式照相機爲例說明。但自動對焦機 構亦可應用於透鏡快門照相機，望逮鏡，及光學顯微鏡等 〇 以下參照圖式說明上述各系統中使用之低雜訊MO S 偵測器，亦即有效的去除固定圈型雜訊，例如可產生7 0 d B以上之大输出動態範圍之MO S偵測器，該MO S偵 測器所使用之雜訊消除電路，及單位晶胞之具體例。 放大型MO S偵測器所構成之固體攝像裝置之受光部 係使用感光二極體，以電晶體放大每一晶胞中由感光二極 體檢測之信號，其特徵爲靈敏度高。 通常放大型MO S型固體攝像裝置（放大型MO S偵 測器所構成之固體攝像裝置）中，將相當於每一單位晶胞 之圖素之受光部之感光二極體之输出信號經由設在該單位 晶胞之放大電晶體放大而取出。因此，在放大時，放大電 晶體之閾值電壓之偏差重叠於信號上。因此，即使每一單 位晶胞之各感光二極體之電位相同，因爲該感光二極體所 靥之單位晶胞之放大電晶體分別各不相同，而且各放大電 晶體之閾值電壓不相同*故輸出信號不成爲相同。因此， 若再生放大型MO S型固體攝像裝置所攝影之畫像時，即 產生對應於各單位晶胞之放大電晶體之閾值偏差之雜訊。 ¥紙張尺度適用中國國家標準（€奶）八4规格（210/ 297公釐）_57 _ ---------批衣------、訂------^ (請先閲讀背面之注意事項>~寫本頁) ~ 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（55 ) 如此，放大型MO S型固體攝像裝置（放大型MO S 偵測器所構成之固體攝像裝置）中，各單位晶胞之放大電 晶體之閾值電壓不相同，各單位晶胞有其固有電壓•故不 能避免發生位置上固定於再生之畫像而分佈之雜訊，亦即 二次元狀之雜訊。該雜訊在二次空間之畫面上其位置爲固 定，故被稱爲固定圖型雜訊。 以下說明之本發明中所使用之雜訊消除電路係爲了消 除固定圇型雜訊而設置者。 以下說明使用在晶胞內放大信號電荷之放大型MO S 偵測器之固體攝像裝置及其雜訊消除電路之具體例。 第1 2實施例 第17圖爲本發明第12實施例之MOS型固體攝像 裝置之結構。單位晶胞P 4 — i _ j在縱，橫方向排列成 二次元矩陣狀。圖中雖然只表示2 X 2，但實際上爲數4 個X數4個。i爲水平（row)方向之變數，j爲垂直 (column)方向之變數》第2 1圖表示各單位晶胞P4 — i 一 j之詳細構造* 本發明中使用之固體攝像裝置之應用領域爲視頻攝像 機，電子靜止照相機，數位照相機，電話傳真機，複印機 ，及掃描器等。 從垂直位址電路5朝向水平方向配線之垂直位址線6 —1 ，6 — 2..........連接於各行之單位晶胞上而決定讀 出信號之水平線。同樣的，從垂直位址電路朝向水平方向 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）-58 - ---------xi衣------1T------0 (請先閱讀背面之注意事¾.. ,>ίν寫本頁) · 30θ%^73 Α7 Β7 經濟部中央標準局貞工消費合作社印製 五、 發明説明（ 56 ) 1 I 配 線 之 復 置線 7 一 1 » 7 — 2 … … … 連 接於 各 列 之 單 位 晶 1 I 胞 9 1 1 各 列 之單 位 晶 胞 連 接於 朝 向 列 方 向 配置 之 垂 直 信 號 線 1 I 請 1 I 8 — 1 8 - 2 * … • · · … 9 而 在 垂 直 信 號線 8 — 1 9 8 — 先 閲 1 | 讀 1 2 …之 一 端 設 置 負 載 電 晶 體 9 — 1， 9 — 2 〇 負 載 背 1 1 之 1 電 晶 體 9 -1 f 9 一 2 … … … 之 閘 極 與 吸極 共 同 的 連 接 於 意 1 Ψ 1 吸 極 電 壓 端子 2 9 1 1 垂 直 信號 線 8 — 1 1 8 — 2 » … … …之 另 — 端 連 接 於 寫 本 1 裝 Μ 0 S 電 晶體 2 6 一 1 » 2 6 一 2 … … …之 閘 極 0 Μ 0 S 頁 1 1 電 晶 體 2 6 - 1 « 2 6 一 2 … … … 之 源 極連 接 於 Μ 0 S 電 1 1 晶 體 2 8 -1 2 8 — 2 … … … 之 吸 極， Μ 0 S 電 晶 體 1 I 2 6 — 1 ，2 6 一 2 t … … … 2 8 — 1 ，2 8 — 2 … … 1 訂 I … 成 爲 源 極跟 鼸 電 路 0 Μ 0 S 電 晶 體 2 8 - 1 2 8 — 2 1 1 I 9 … … … 之閘 極 連 接 於 共 同 閘 極 端 子 3 6 0 1 1 Μ 0 S電 晶 體 2 6 — 1 2 6 — 2 ，· · ♦ … … 與 Μ 0 S 气 1 1 電 晶 體 2 8 - 1 2 8 — 2 · · ««· 之 連接 點 經 由 樣 品 保 線 1 持 電 晶 體 3 0 一 1 3 0 — 2 «*« «·« … 連接 於 箝 位 電 容 器 1 | 3 2 — 1 ，3 2 — 2 … … … 之 一 端 〇 在箝 位 電 容 器 3 2 1 I 一 1 » 3 2 - 2 » … • · * … 之 另 —* 端 並 聯 樣品 保 持 電 容 器 1 1 I 3 4 — 1 ，3 4 — 2 … … … 與 箝 位 電 晶體 4 0 — 1 9 1 1 4 0 — 2 > ··· … … 〇 樣 品 保 持 電 容 器 3 4 - 1 ) 3 4 — 2 ' 1 1 * … … … 之另 一 端 接 地 〇 箝 位 電 容 器 3 2 - 1 9 3 2 — 2 1 1 » … … … 之另 — 端 經 由 水 平 選 擇 電 晶 體 12 — 1 » 1 2 — 1 1 2 » … … …連 接 於 信 號 輸 出 端 ( 水 平 信 號線 ) 1 5 〇 1 1 張 紙 本 华 標 家 國 困 中 用 通 釐 公 7 29 A7 B7 經濟部中央標準局員工消費合作社印製 五 •發明説明 ( 57 ) 1 1 垂 直 位 址 電 路 5 係 整 理 許 多 ( 在 此 爲 2 個 ) 信 號 而 移 1 1 I 位 之 電 路 9 可 由 第 1 8 1 9 或 2 0 圖 所 示 之 任 —· 電 路 實 1 1 I 現 0 在 第 1 8 圚 所 示 之 例 中 9 從 許 多 輸 出 端 依 次 移 位 輸 入 請 1 1 信 號 4 6 而 輸 出 之 位 址 電 路 4 4 之 輸 出 由 多 工 器 4 8 與 2 先 閱 讀 1 1 輸 入 信 號 5 0 合 成 〇 在 第 1 9 圖 所 示 之 例 中 9 將 編 碼 输 入 背 1 1 5 4 解 碼 之 解 碼 器 5 2 之 輸 出 由 多 工 器 5 6 與 2 m 入 信 號 意 畫 1 | 5 8 合 成 0 第 2 0 圖 所 示 之 例 中 將 2 個 位 址 電 路 6 0 a Ψ 習 1 I » 6 0 b 之 输 出 整 合 做 爲 各 行 之 控 制 信 號 線 0 寫 本 裝 I 第 2 1 圖 表 示 第 1 7 圖 所 示 單 位 晶 胞 Ρ 4 一 1 — 1 之 貝 1 1 I —. 結 構 例 0 在 此 只 表 示 單 位 晶 胞 Ρ 4 — 1 — 1 之 結 傅 » 1 1 其 他 單 位 晶 胞 P 4 一 1 一 2 亦 採 用 相 同 之 結 稱 0 1 1 如 圚 中 所 示 本 實 施 例 之 Μ 0 S 型 固 體攝像 裝 置 之 單 訂 1 位 晶 胞 包 括 檢 測 入 射 光 之 感 光 二 極 體 6 2 感 光 二 極 體 1 I 6 2 之 陰 極 連 接 於 閘 極 而 放 大 其 檢 測 信 號 之 放 大 電 晶 體 1 I 6 4 設 在 放 大 電 晶 體 6 4 之 閘 極 與 吸 極 之 間 而 進 行 反 饋 1 1 線 動 作 之 復 置 電 晶 體 6 6 及 連 接 於 放 大 電 晶 體 6 4 之 吸 極 1 » 選 擇 讀 出 信 之 水 平 線 之 垂 直 選 擇 電 晶 體 6 5 0 1 1 從 垂 直 位 址 電 路 5 朝 向 水 平 方 向 配 線 之 水 平 位 址 線 6 1 1 — 1 連 接 於 垂 直 選 擇 電 晶 體 6 5 之 閘 極 而 選 擇 讀 出 信 號 之 1 1 線 〇 同 樣 的 » 從 垂 直 位 址 電 路 5 朝 向 水 平 方 向 配 線 之 復 置 1 | 線 7 一 1 連 接 於 復 置 電 晶 體 6 6 之 閘 極 〇 1 I 通 常 放 大 型 Μ 0 S 型 固 體 攝 像 裝 置 中 ， 放 大 電 晶 體 1 1 I 6 4 之 閾 值 電 壓 之 偏 差 重 叠 於 信 號 上 9 故 即 使 感 光 二 極 體 1 1 6 2 之 電 位 相 同 I 其 输 出 信 號 不 成 爲 相 同 I 將 照 相 之 畜 像 1 1 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐）_ 6() A7 B7 經濟部中央樣準局負工消費合作社印裝 五、 發明説明 ( 58 ) 1 I 再 生 時 » 發 生 對 應 於 放 大 電 晶 體 6 4 之 閾 值 偏 差 等 之 二 次 1 I 元 狀 之 雜 訊 之 固 定 圖 型 雜 訊 〇 亦 即 在 放 大 型 Μ 0 S 型 固 體 1 1 1 攝 像 裝 置 中 9 即 使 在 其 全 部 受 光 面 照 射 均 勻 之 光 線 y 從 配 請 1 1 置 成 矩 陣 狀 之 各 圖 素 中 產 生 之 畫 像 信 號 之 位 準 在 各 圖 素 中 先 閱 讀 1 1 不 成 爲 相 同 » 成 爲 亮 度 不 均 之 奎 像 信 號 〇 該 亮 度 不 均 勻 之 背 ιέ 之 1 1 蜜 像 爲 雜 訊 成 爲 二 次 元 狀 分 佈 之 雜 訊 ♦ 亦 即 分 佈 於 畫 面 平 注 意 事 1 1 面 之 雜 訊 » 因 爲 其 位 置 固 定 故 稱 爲 固 定 圖 型 雜 訊 〇 項 vm- 1 1 因 此 9 本 實 施 例 中 9 係 使 用 在 單 位 晶 胞 中 使 復 置 電 晶 % 本 頁 ά. | 體 ( 第 1 圖 所 示 習 用 例 中 之 4 — i — j ( i j = 1 9 2 1 I 9 3 4 … … … ) 9 在 第 2 1 圖 爲 電 晶 體 6 6 ) 反 嫌 減 1 1 I 小 固 定 圖 型 雜 訊 而 且 如 第 1 7 圖 所 示 在 水 平 選 擇 電 晶 1 1 訂 體 1 2 之 前 設 置 更 抑 制 減 小 之 固 定 圖 型 雜 訊 之 電 路 而 構 成 1 之 雜 訊 去 除 電 路 ( 雜 訊 去 除 電 路 ) 〇 1 1 第 1 7 圖 中 之 雜 訊 去 除 電 路 係 在 電 壓 領 域 設 定 信 號 與 1 1 雜 訊 之 差 值 之 相 關 雙 重 抽 樣 型 電 路 但 雜 訊 去 除 電 路 之 型 1 線 1 I 式 不 限 定 爲 相 關 雙 重 抽 樣 型 亦 可 使 用 其 他 各 種 雜 訊 去 除 電 路 〇 1 I 以 下 參 照 第 2 2 A I 2 2 B 9 2 2 C 圖 說 明 本 實 施 例 1 1 之 特 徵 之 單 位 晶 胞 之 反 饋 動 作 所 產 生 之 放 大 電 晶 體 6 4 之 1 1 閾 值 電 壓 修 正 原 理 〇 第 2 2 A 圖 表 示 晶 胞 電 路 圖 〇 第 1 1 2 2 B 9 2 2 C 圖 表 示 放 大 電 晶 體 6 4 之 電 位 圖 9 1 1 第 2 2 B 圇 之 狀 態 爲 垂 直 選 擇 電 晶 體 6 5 斷 路 * 復 置 1 | 電 晶 體 6 6 導 通 時 之 狀 態 1 亦 即 在 垂 直 信 號 線 8 上 施 加 基 1 I 準 電 壓 時 之 電 位 〇 在 此 狀 態 下 » 電 子 通 過 復 置 電 晶 體 6 6 1 1 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） -61 - 經濟部中央標準局貝工消費合作杜印製 A7 B7 五、發明説明（59 ) 之閘極通道到達該復置電晶體6 6之吸極後’其吸極電壓 下降。 復置電晶體6 6之吸極與閘極之間連接器成爲導通之 該復置電晶體6 6 ’故閘極電壓亦下降’流入之電子數：a 減少。最後，如第2 2 C圖所示’成爲施加於源極之基準 電壓與通道電位成爲相等。在此狀態下’通道電位成爲從 外部施加之電壓，故電晶體構造上之不均勻不會出現。 如此，依照本實施例，在放大電晶體6 4之閘極與吸 極之間插入反娥電晶體（復置電晶體6 6) ’藉著在源極 施加一定電壓之反饋動作’即可修正閾值之不均勻。 以下參照第2 3圖之時序圖表說明上述MOS型固體 攝像裝置之動作。因爲負載電晶體9之共同吸極端子2 0 ，阻抗變換電路之電晶體2 8之共同閘極端子3 6，箝位 電晶體4 0之共同源極端子3 8係由D C驅動，故不表示 於時序圖表中。 在垂直位址線6 - 1上施加髙位準之位址脈波後，連 接於該垂直位址線6 - 1之單位晶胞P4 — 1一1 ，P4 -1-2 ..........之垂直選擇電晶體6 5成爲導通，由放 大電晶體6 4，與負載電晶體9 — 1 ，9 一 2 .........構 成源極跟隨電路。 使樣品保持電晶體3 0 — 1 ，3 0 — 2 .........之共 同閘極3 7成爲高位準而將樣品保持電晶體3 0 - 1 ， 30 — 2 ..........導通。此後，使箝位電晶體40 — 1 ， 4 0-2 ..........之共同閘極4 2成爲高位準而將箝位電 本紙張尺度逋用中國國家標率（CNS ) A4規格（210XW7公釐）_ 62 _ ---------批衣------ir------線 (請先閱讀背面之注意事項|..4,寫本頁) ™ 經濟部中央標準局員工消费合作杜印製 A7 ___B7__ 五、發明説明（60 ) 晶體4 0 — 1 ’ 4 0 — 2 ’ .........導通。 然後，使箱位電晶體4 0 - 1 ，4 0 — 2..........之 共同閘極4 2成爲低位準而將箝位電晶體40 — 1，40 一 2 .........截止。如此，出現於垂直信號線8 _ 1 ，8 - 2 ..........之信號加雜訊成分被儲存於箝位電容器3 2 — 1 , 2 2 —^ 2 ，··*···.·· pfj 〇 然後·將垂直位址脈之電位復原成低位準，在復置線 7 - 1上施加高位準之復置脈波後，連接於該復置線7 - 1之單位晶胞P4-1 — 1，P4— 1 — 2 .........之復置 電晶體6 6導通，输出電路6 8之输入端子之電荷被復置 9 再於垂直位址線6 - 1上施加高位準位址脈波後，連 接於該垂直位址線6 — 1之單位晶胞P4— 1 — 1 ，P4 -1-2 ..........之垂直選擇電晶體6 5導通，由放大電 晶體6 4與負載電晶體9 — 1 ，9 一 2 ..........構成源極 跟踪電路，在垂直信號線8 — 1，8 — 2..........上只出 現信號成分被復置之雜訊成分。 如上所述，因爲箝位電容器32 - 1 ，32 — 2，… ……中儲存信號加雜訊成分，故在箝位節4 1 一 1 * 4 1 —2 ..........上只出現垂直信號線8 — 1 ，8 — 2 ......... 之電壓變化，亦即從信號成分加雜訊成分中減去雜訊成分' 之無固定圚型雜訊之信號電壓。 然後，使樣品保持電晶體30 — 1 ，30 - 2 ....... …之共同閘極3 7之電位成爲低位準而將樣品保持電晶體 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）_ 63 _ ---------餐------1T------^ (請先閱讀背面之注意事項I S寫本頁) 經濟部中央標準局貝工消費合作社印製 A7 _____B7___ 五、發明説明（6i) 30-1 » 30 — 2 * .........截止。如此，在樣品保持電 容器34 — 1 ，34 — 2..........中儲存出現於箝位節 41 — 1*41 — 2* .........之無雜訊電K。 然後，在水平選擇電晶體12 — 1 ，12 — 2 ....... …上依次施加水平位址脈波而從輸出端子（水平信號線） 15讀出儲存於樣品保持電容器34 — 1 ，34 - 2，… ......之無雜訊感光二極體6 2之信號。 以後，同樣的對垂直位址線6 — 2，6 — 3.......... 重複進行上述動作，即可取出配置成二次元狀之全部晶胞 之信號· 在此，說明第2 3圓之時序之前後關係。其所必須之 順序如下。 垂直位址脈波之上昇。樣品保持脈波之上昇。箝位脈 波之上昇—復置脈波之上昇—復置脈波之下降-樣品保持 脈波之下降—垂直位址脈波之下降* 垂直位址脈波之上昇，樣品保持脈波之上昇，箝位脈 波之上昇之前後關係可爲隨意，但最好爲如上述之順序。 如此，依照第2 3圖之動作，在箝位節4 1上出現有 信號（加雜訊）時與放大電晶體之閘極復置而無信號時之 差電壓，故由於某種原因而不能因單位晶胞之反饋動作而 去除放大電晶體6 4之閾值不均勻所產生之固定圖型雜訊' 被補償。亦即，由箝位電晶髖30，箝位電容量31 ，樣 品保持電晶體4 0 ·及樣品保持電容器3 4所構成之電路 成爲雜訊消除器。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）_ 64 - ： ---------^------ΐτ------^ (請先閲讀背面之注意事項ίγ寫本頁) 一 經濟部中央標準局負工消費合作社印製 A7 B7 五、發明説明（62 ) 本實施例之雜訊消除器經由源極跟隨電路所構成之阻 抗變換電路2 6，2 8連接於垂直信號線8。亦即垂直信 號線連接於電晶體2 6之閛極。因爲閘極電容量極小，故 晶胞之放大電晶體64只充電垂直信號線8 — 1 ，8 — 2 ..........，故C R之時間常數短，可立即成爲正常狀態。 因此，可加快復置脈波之施加時序，可在短時間內使雜訊 消除器動作。電視信號在雜訊消除動作時必須在水平熄滅 期間內進行*故可在短時間內正確的進行雜訊消除爲其特 徴•又因爲在包含於雜訊消除動作中之信號加雜訊输出時 與雜訊输出時，從單位晶胞觀察時之雜訊消除器之阻抗相 同，故可正確的進行雜訊消除。 亦即，在 '雜訊成分^輸出時，及'信號成分+雜訊 成分^輸出時，從單位晶胞觀察之雜訊消除電路之阻抗實 質上相同。因此，在兩個輸出時，雜訊成分實質上變成相 同，計算兩者之差值，即可正確的消除雜訊輸出而只取出 信號成分。因此，可正確的消除雜訊。從單位晶胞觀察雜 訊消除電路時，在阻抗之觀點上只能觀察到閘極電容器， 而且其電容量極小，故可在短時間內確實的消除雜訊· 以下說明本實施例之構造· 由第1 7圖之電路結構可知，因爲箝位電容器3 2與 樣品保持電容器3 4直接連接而且互相接近，故可將之層' 叠於同一面上形成，可將雜訊消除電路部分小型化。 具體言之，如第2 4圖所示，經由第1絕緣膜7 4在 矽基板7 2上形成第1電極7 6而構成樣品保持電容器 ---------^------、訂------0 (請先閱讀背面之注意事項1.心寫本頁) ~ 本紙張尺度逋用中國國拿標率（CNS ) Μ規格（210X297公釐> _ 65 - 經濟部中央樣準局貝工消费合作社印製 A7 _B7_ 五、發明説明（63 ) 34，再經由第2絕緣膜7 8在第1電極76上形成第2 電極8 0而構成箝位電容器3 2。 由圖中可知，第1電極7 6成爲共同電極，而且箝位 電容器3 2與樣品保持電容器3 4層疊，故與分別形成時 比較，可在1/2之面積上產生相同之電容量》 本實施例中’單位晶胞P4 — 1 — 1 ，P4 — 1 — 2 ...........垂直位址電路6，水平位址電路1 3等周邊電 路係形成在P —型基板上設置P +型不純物層之半導體基板 上。 第2 5A，2 5 B圚爲上述半導體基板之斷面圖。 如第2 5A圖所示，在p_型基板8 1上設置P +型不 純物層8 2之半導體基板上形成感光二極體8 3等晶胞要 素。 如此形成半導體基板，則可利用P—/P+分界之擴散 電位防止發生於p-型基板8 1之暗電流之一部分流入P + 側。 以下簡單說明詳細解析電子流動之結果。對於發生於 P—側之電子而言，P+不純物層8 2之厚度L可能被認定 爲P +與P -之濃度之比倍，亦即L · p +/ p -。 亦即，如第2 5 B圖所示，可能被認定爲從暗電流發 生源之p-基板8 1至感光二極體8 3之距離延長p+/ P—倍。暗電流除了從基板深部流入之外，又有發生於感 光二極體8 3附近之耗盡層內之電流。發生於耗盡層內之 暗電流量與從基板深部流入之暗電流量幾乎相同。耗盡層 本紙張尺度逋用中國國家標準（CNS ) Μ規格（210X 297公釐）ββ 裝 I訂I I I I I I線 (請先閱讀背面之注意事項寫本頁) 經濟部中央樣準局貝工消费合作杜印策 A7 __B7_ 五、發明説明（64 ) 之厚度大約爲1 左右，從基板深部流入之暗電流又從 大約1 0 0 之深度流入。該深度又被稱爲p型半導體 內部之電子擴散距離。暗電流與厚度之差無關的成爲相等 之理由爲在耗盡層內部之每單位體稹之暗電流之發生或然 率較高。原理上，發生於耗盡層內之暗電流不能與信號電 流分離•故減少從基板深部流入之成分即可減少暗電流。 因爲在p-型基板7 1上設置p-型不純物層7 2之半 導體基板上形成晶胞1故可防止基板電位因暗電流之發生 而變動。因爲P型基板較厚，故電阻小，因此可使雜訊去 除電路確實的動作。 因爲元件溫度上昇後，來自基板深部之成分急速的增 加，此爲重要因素。其尺度爲來自基板深部之成分充分小 於在耗盡層發生之成分。具體言之，只要來自基板深部之 暗電流小於來自耗盡層內部之暗電流1位數即可。亦即將 P+/P-設定爲1 0而將來自基板深部之暗電流設定爲大 約1 / 1 0即可。 來自基板深部之暗電流在由η型基板及p型阱所構成 之半導體基板中幾乎不存在，但爲了使其與半導體基板成 爲相同位準，必須將Ρ+/Ρ-設定爲1 〇 〇而使來自基板 深部之暗電流成爲大約1/1 00。 習用之具有實績之C CD中，η型之埋入通道之不純 物濃度大約爲1 〇 iec m-3，而包圍穩定的製造該埋入通 道之擴散層所需之埋入通道之p型層（在此爲p型基板） 之不純物濃度大約爲1 〇 lsc m_3。 本紙張尺度遑用中國國家標芈（CNS > A4規格（210X297公釐)~ ~ I 裝 II 訂—— 線 (請先閱讀背面之注意事項\4 .舄本頁) ™ 經濟部中央橾準局貝工消費合作杜印製 A7 ___B7 五、發明説明（65) p+/p-爲10時’ P+層之澳度大約爲 1 〇iecm-3左右，p+/p-爲1 〇 〇時，大約爲 1 成爲與n型之埋入通道之不純物濃度之大 約1 〇iecm_3大致上相同，或反轉1個位數。 因此，習用之具有實績之C CD中，完全未考慮使用 這種不純物濃度之P+層。若降低p-層之澳度時，則基板 之薄片電阻值增高· 然而，因爲放大型MO S攝像裝置中無C C D之埋入 通道，故不必降低p-層之濃度即可某一程度的任意設定 p +/ p -之數值* 降低P型阱之電阻值，改善由η型基板及p型阱所構 成之半導體基板之構造，亦可構成晶胞。 第2 6圚爲在η型基板8 5上使用薄片電阻值小之 Ρ+阱8 6之單位晶胞之斷面圖。第2 7圖爲C C D之單 位晶胞之斷面圖。 爲了穩定的製造，C CD之單位晶胞之η型基板8 7 ，Ρ型阱8 6，η型埋入通道8 9之不純物濃度分別設定 爲大約1 014cm -3，大約1 〇15cm_3，大約 1 〇 1 e c m _3。 因爲η型感光二極體9 0之不純物濃度可在某一程度 內任意的設定，故製造上無太多限制。在上述不純物濃度· 時，Ρ型阱8 6之薄片電阻值大約爲1 0 ΟΚΩ/口。 C C D即使其數值髙達上述數值，其雜訊仍非常小。 在放大型MO S攝像裝置中使用雜訊去除電路時，該 本紙張尺度遑用中國國家揉準（CNS)A4規格（210Χ297公釐）_ 68 _ ---------批衣------IT------^ (請先閱讀背面之注意事項广4寫本頁) ~ A7 B7 經濟部中央橾準局負工消費合作社印製 五、 發明説明 ( 66 ) 1 1 P 型 阱 之 薄 片 電 阻 值 非 常 重 要 9 其 理 由 爲復置脈波所造成 1 1 之 P 型 阱 8 6 之 電 位 擾 亂 平 靜 所 需 之 時 間必須匹配應用該 1 1 裝 置 之 系 統 〇 1 1 請 1 I 現 行 之 N T S C 方 式 之 電 視 方 式 中 ，使雜訊去除電路 先 閱 1 I 動 讀 1 作 之 時 間 爲 水 平 回 描 線 期 間 之 大 約 1 1 〔 β s〕之期間 背 ιέ 1 1 之 1 〇 因 此 Ρ 型 阱 8 6 之 電 位 擾 亂 必 須 在 該期間內平靜至 注 意 1 事 1 0 • 1 C m V 左 右 〇 1 I 0 1 C m V 之 極 小 值 係 起 因 於 C C D之雜訊電壓 窝 本 1 裝 輸 出 大 約 爲 此 數 值 0 根 據 解 析 結 果 爲 了在1 1 〔仁S〕 頁 1 1 之 極 短 時 間 內 平 靜 成 爲 0 1 C m V 之極小數值，必須 1 1 使 P 型 阱 8 6 之 薄 片 電 阻 成 爲 1 K Q / □以下。此數值爲 1 1 習 用 C C D 之 大 約 1 / 1 0 0 0 訂 | 因 此 必 須 將 P 型 阱 8 6 之 不 純 物 濃度設定爲大約 « | I 1 0 0 倍 例 如 在 上 述 Ρ 型 基 板 時 所 述 ，在C C D中係不 1 I 可 能 達 到 之 濃 度 0 因 爲 在 髙 解 像 度 方 式 中，水平回描線期 1 線 間 爲 3 • 7 7 C β S 必 須 將 P 型 阱 8 6之薄片電阻值 1 設 定 爲 3 0 0 Ω 以 下 0 1 1 其 他 變 更 例 爲 在 基 板 上 形 成 髙 濃 度 之Ρ +型三明治層 1 1 » 將 其 表 面 形 成 爲 濃 度 比 其 濃 度 更 低 之 Ρ型層。 1 | 第 2 8 rwr 閫 爲 在 P 一型基板ε 1 與P型層9 3之間形成 1 I P +型三 三明治層ε 2 之半導體基板之結構圖。第2 9圖爲' 1 1 | 在 η 型 S 板 9 5 與 P 型 層 9 7 之 間 形 成 Ρ +型三明治層 1 1 I 9 6 之 半 導 體 基 板 之 結 構 圖 0 1 1 這 種 P +型三 i 3； 3治層可利用高加速度之兆伏特離子注 1 1 本紙張尺度適用中國國家橾窣（CNS) Μ規格（ 210X 297公釐）—69 - 3060V3 經 濟 部 中 央 標 準 Μ 員 X 消 費 合 作 社 印 .製. A7 Β7 五、 發明説明 ( 67 ) 1 | 入 機 實現 〇 1 I 在該 Ρ 型 層上除了 形 成 單位晶 胞 之 構 成 要 素 之 感 光 二 1 1 1 極 體 8 3 » 電 晶體等之 外 1 又形成 水 平 位 址 電 路 > 垂 直 位 1 I 請 1 I 址 電 路等 周 邊 電路。 先 閱 I I 讀 1 I 第3 0 圖 爲以高漉 度 P 型阱3 0 包 圔 感 光 二 極 體 8 3 背 1 1 之 1 之 周 圍， 以 其 他Ρ型阱 1 0 2形成 η 型 基 板 1 0 1 上 之 其 注 意 1 事 1 他 部 分而 構 成 之半導體 基 板 之結構 圖 〇 1 I 因爲 採 用 這種結構 » 故 可防止 暗 電 流 洩 漏 至 感 光 二 極 寫 本 裝 I 體 8 3中 〇 半 導體基板 1 0 1亦可 爲 Ρ _型基板 > 貝 1 1 I 形成 晶 胞 周邊之水 平 位 址電路 或 垂 直 位 址 電 路 之 —- 部 1 1 分 或 全部 之 Ρ 型阱之濃 度 係 在電路 設 計 時 決 定 〇 因 爲 與 晶 1 1 胞 之 最佳 值 不 相同，故 亦 可 形成爲 與 形 成 攝 像 領 域 之 Ρ 型 訂 1 阱 不 同之 Ρ 型 層。 1 | 第3 1 圍 爲在η型 基 板 10 5 上 形 成 構 成 攝 像 領 域 之 1 I P 型 阱1 0 6 ，而且分 開 的 形成構 成 周 邊 電 路 之 其 他 Ρ 型 1 1 線 阱 1 0 7 之 半 導體基板 之 結 構圖》 1 由於 上 述 結構，故 可 形 成適合 於 各 構 成 要 素 之 Ρ 型 阱 1 1 〇 該 η型 基 板 1 0 5亦 可 爲 P 一型基板。 1 1 第3 2 圖 表示在η 型 基 板1 0 5 上 形 成 設 置 攝 像 領 域 1 | 之 P +型三 L明治層1 0 S ί及低濃度f >型層1 C 9 並且在 1 I 周 邊 電路 部 分 形成其他 P 型 阱1 0 7 之 圖 〇 1 1 I 由於 上 述 結構，故 可 形 成適合 於 各 構 成 要 素 之 Ρ 型 阱 1 1 I I 可 防止 暗 電 流洩漏至 感 光 二極體 中 • 該 η 型 基 板 1 0 5 1 1 亦 可 爲Ρ -型基板。 1 1 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐> _ 7〇 經濟部中央標準局貝工消費合作社印製 A7 ____B7__ 五、發明説明（68) 如上所述，依照本實施例，因爲在放大電晶體6 4之 閘極與吸極之間裝插反娥電晶體（復置電晶體6 6)，在 源極上施加一定電壓之反绩動作，故可修正閾值之不均勻 〇 又因爲經由雜訊消除器输出單位晶胞之輸出，故可更 抑制配合單位晶胞之放大電晶體之閾值不均勻之固體圇型 雜訊。在雜訊消除器中，因爲箝位電容器32 — 1 ，32 一 2 ..........(以統稱爲3 2，其他具有附加數字之構件 亦相同）與樣品保持電容器3 4直接連接而接近*故可將 之層叠的形成於同一面上，可將電容器小型化。 又因爲將單位晶胞之输出經由阻抗變換電路供給於雜 訊消除器，故在雜訊輸出時與信號+雜訊輸出時，從單位 晶胞觀察之雜訊消除器之阻抗大致上相同，故在兩種輸出 時，雜訊成分大致上相同，計算兩者之差值，即可正確的 消除雜訊輸出，可只取出信號成分，可正確的消除雜訊。 從單位晶胞觀察雜訊消除器時，在阻抗之觀點上只能觀察 到閘極電容器，其電容量極小，故可在短時間內確實的消 除雜訊。 使用由P-型不純物基體，及形成於p_型不純物基體 上之P+型不純物層所構成之基板做爲形成單位晶胞之半 導體基板|則可減少進入單位晶胞中之暗電流*而且可使, 基板表面之電位成爲穩定，故使雜訊消除電路確實的動作 0 以下說明第12實施例中變更雜訊消除電路部分之實 ( CNS ) ( 210X297/^-jt ) - 71 - ----------^------IT------0 (請先閲讀背面之注意事項I. 5寫本頁) ~ 經濟部中央標準局員工消費合作社印製 A7 _____B7 五、發明説明（69 ) 施例。 第1 3實施例 第3 3圖爲本發明所使用之第1 3實施例之使用放大 型MO S放大型MO S偵測器之攝像裝置之電路結構圖。 單位晶胞P 4 - i - j附近之電路結構與第1 2實施例相 同》 與垂直信號線8 — 1 ，8 — 2 ..........成爲串聯的連 接分離電晶體2 0 2 — 1，2 0 2-2 ..........，在分離 電晶體202 - 1，202 — 2..........與水平選擇電晶 體1 2 _ 1 ，1 2 - 2..........之間設置放大電容器 206 — 1 ’ 206 — 2...........本實施例中，在水平 選擇電晶體之前未設置雜訊消除器•代之設置調整放大係 數之放大電容器。 以下參照第3 4圓說明本實施例之動作。 在垂直位址線6 - 1上施加高位準位址脈波之同時， 在分離電晶體2 0 2之共同閘極2 0 4上施加高位準脈波 使該電晶體導通。如此，可將單位晶胞之放大電晶體6 4 之輸出經由垂直信號線8傳送至放大電容器2 0 6，儲存 放大之信號電荷。 然後，將分離電晶體2 0 2之共同閘極2 0 4之電位 恢復成低位準，使分離電晶體2 0 2斷路。 在復置線7 0 1上施加髙位準之復置脈波，使復置電 晶體6 6導通，然後，將垂直位址線6 - 1之位準復原成 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐）_ - ~ ~ I I I n n I n 裝 I I I n ^ I I 線 (請先閲讀背面之注意事項一i,.,..寫本頁) ~ 五、發明説明（70 ) 低位準，使垂直選擇電晶體6 5斷路後，放大電晶體6 4 之通道電位成爲與基準電壓相等•然後，使水平選擇電晶 體1 2依次導通，依次讀出儲存於放大電容器2 0 6中之 放大信號電壓。 假設放大電容器2 0 6之電容置值爲C a *感光二極 體6 2之電容量值爲C s時，此時之信號電荷之放大係數 變成C a/C s。放大係數應該爲與習用型相同或更大， 故將C a之數值設定爲與垂直信號線8之電容量值C r相 同或更大。 以下說明第3 4圖所示時序之前後關係。其所需之順 序有如下之2種》 (1)垂直位址脈波之上昇—分離電晶體之閘極脈波 之下降—復置脈波之上昇—垂直位址脈波之下降復置脈 波之下降 (2 )分離電晶體之閘極脈波之上昇—分離電晶體之 閘極脈波之下降—復置脈波之上昇—復置脈波之下降 經濟部中央揉準局貝工消费合作社印製 垂直位址脈波之上昇*分離電晶體之閘極脈波之上昇 之前後圇可爲任意。 第1 4實施例 第3 5圖爲使用本發明第1 4實施例之放大型MO S 偵測器之攝像裝置之電路結構圖•單位晶胞P 4 - i _ j 附近之電路結構與第12實施例相同。 垂直信號線8 — 1 ，8 — 2..........之另一端經由箝 本紙張尺度逋用中國國家橾準（CNS > A4規格（210X297公釐） ~ -fd - 經濟部中央橾隼局貝工消費合作杜印製 30晚确73 A7 __B7_ 五、發明説明（Ή ) 位電容器1 3 1-1 ，1 3 1 - 2 ..........抽樣保持電晶 體1 3 3 — 1 ，1 3 3 — 2 ..........水平選擇電晶體1 2 一 1 ，1 2 — 2..........連接於信號输出端（水平信號線 )15。在箝位電容器131 — 1，131-2.......... 與樣品保持電晶體1 3 3-1，1 3 3 — 2..........之連 接點（箝位節145-1，145 — 2..........）連接箝 位電晶體13 2 — 1，132 — 2..........之吸極。 箝位電晶體1 3 2 — 1，1 3 2 - 2..........之源極 連接於共同源極端子1 4 1 ，閘極連接於共同閘極端子 1 4 2。樣品保持電晶體1 3 3 - 1 ，1、% - 2 ....... …與水平選擇電晶體1 2 — 1 ，1 2 — 2 ..........之連接 點經由樣品保持電容器134 — 1 ，134 — 2 .......... 接地。 ' 第3 6圚表示本實施例之時序圖。雜訊消除動作原理 與圖NA09完全相同。 第1 5實施例 第3 7圇爲使用本發明第1 5實施例之放大型MO S 偵測器之攝像裝置之電路結構圖。單位晶胞P 4 - i - j 附近之電路結構與第12實施例相同。 第1 5實施例係將第1 2實施例之阻抗變換電路連接 於第1 4實施例之雜訊消除器之例。本實施例中，箝位電 晶體1 3 2之共同源極係以DC驅動。 本紙張尺度適用中國國家標準（CNS>A4規格（ 210X297公釐）_ 74 I .i^------"------'· # i | (請先閱讀背面之注意事項再填寫本頁) 經濟部中央樣準局貝工消費合作社印袈 A7 _B7_ 五、發明説明（72) 第1 6實施例 第3 8圖爲使用第1 6實施例之放大型MO S偵測器 之攝像裝置之電路結構圖。單位晶胞p 4 - i - j附近之 電路結構與第12實施例相同。 負載電晶體9 — 1 ’ 9 — 2 ’ .........與相反側之垂直 信號線8 — 1 ，8 — 2 .........之端部分別連接於限幅電晶 體1 5 0 — 1 ，1 5 0 — 2 ..........之閘極。限幅電晶體 150-1*150-2*.........之源極連接於限幅電容 器1 5 2 — 1 ’ 1 5 2 - 2 ’ .........之一端’限幅電容器 152 — 1 ' 152 — 2 » .........之各一端―接於限幅脈 波供給端子1 54。爲了復置限幅電晶體1 50 — 1， 15 0-2 -.........之源極電位，在限幅電晶體之源極與 限幅電源端子158之間設置限幅復置電晶體156—1 ，156 — 2 ..........，而該電晶體 156 — 1 ，156 —2 ..........之閘極連接於限幅復置端子1 6 0。 限幅電晶體150-1 ，150-2 ..........之吸極 連接於限幅電荷傅送電容器162 — 1 ，162 — 2，… ……。爲了復置限幅電晶體1 5 0 — 1 ，1 5 0 — 2 ，… ……之吸極電位，在吸極與儲存吸極電源端子1 6 4之間 設置吸極復置電晶體1 6 6 — 1 ，1 6 6 — 2........... 該電晶體1 6 6 — 1，1 6 6 — 2..........之閘極連接於 吸極復置端子168·限幅電晶體150—1，150— 2 .........之吸極經由從水平位址電路1 3供給之水平位址 脈波所驅動之水平選擇電晶體1 2 — 1 ，1 2_ 2 ....... 本紙張尺度適用中國國家標準（〇^>八4洗格（2丨0父297公釐）_75_ ； 裝 訂~''^, | f (請先閱讀背面之注意事項再填寫本頁) 經濟部中央橾準局貝工消费合作社印製 A7 ___B7_ 五、發明説明（73 ) …連接於信號輸出端1 5 » 如上所述，第1 6實施例之MOS偵測器之單位晶胞 P 4 — i - j之構造與第1 7圖所示第1 2實施例相同， 但雜訊消除器部分之構造不相同。第1 5實施例之雜訊消 除器將出現於垂直信號線8 — 1 ，8 - 2_..........之電壓 經由限幅電晶體1 5 0之閘極電容器變換成電荷，在電荷 領域進行減算而抑制雜訊，爲其特徴* 該裝置中，假設限幅電容器1 5 2之容量值爲CS1時 ，最後被讀出於水平信號線15之電荷（第2限幅電荷） 爲 、1 C si X (Vsch— Voch) 1出現與有信號時與被復置而無信號時之差成比例之電荷， 故可抑制因單位晶胞內之放大電晶體6 4之閾值不均勻而 產生之固定圖型雜訊。如此，將出現於垂直信號線8之電 壓變換成電荷，在電荷領域內進行減法之電路結構亦可稱 爲雜訊消除器》 第1 7實施例 第3 9圖爲使用本發明第1 7實施例之放大型MOS 偵測器之攝像裝置之電路結構圓。單位晶胞P 4 — i — j 附近之電路結構與第12實施例相同。 第1 7實施例係在第1 7圖所示第1 2實施例中省略 本紙張尺度逋用中國國家梂準（CNS ) Α4规格（210X297公釐）—76 - ； 裝 訂 ~線 ί - (請先閲讀背面之注意事項再填寫本頁) 經濟部中央樣準局貝工消费合作社印製 A7 B7 五、發明説明（74 ) 源極跟隨電晶體所構成之阻抗變換電路之實施例。 第1 8實施例 第4 0，4 1圖爲使用本發明之第1 8實施例之放大 型MO S偵測器之攝像裝置之電路結構圖。單位晶胞P 4 _ i — j附近之電路結構與第1 2實施例相同。 本實施例中有許多部分與第3 5圖所示第1 4實施例 相同。其不同之處爲將用來修正在"^信號成分+雜訊成分 ^輸出時與只有|雜訊成分#之輸出時，從單位晶胞側觀 察之雜訊消除器之阻抗之不同之電容器cUp P 1 6 0 —1 ，160 — 2 .........經由開關 162 — 1 ，162 ~ 2 ..........，與垂直信號線8 — 1 ，8 — 2..........成 爲並聯的連接於較箝位電容器1 3 1 - 1 ，1 3 1 — 2， 1.........更靠近攝像領域（單位晶胞）側。在第4 0圖中， 修正電容器1 6 0與開關1 6 2係連接在箝位電容量 1 3 1與攝像領域之間，在第4 1圖中係連接於攝像領域 與負載電晶體9之間。 如此，依照本實施例，在具有雜訊去除電路之MO S 型固體攝像元件中，於垂直信號線8上設置修正電容器 1 6 0，故可抑制成爲發生雜訊之原因之雜訊去除動作中 之電容量變化，可更降低雜訊。亦即在感光二極體選擇後 之信號加雜訊輸出時，與復置終了後之雜訊輸出時，從晶 胞觀察之阻抗變成相等’故可正確的消除雜訊。 第1 8實施例之變更例爲，在第1 7圖所示之第1 2 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X 297公釐）-77 - 裝 訂 線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印製 A7 B7 五、發明説明（75 ) 實施例，第3 7圖所示之第1 5實施例，第3 9圖所示之 第1 7實施例之雜訊消除器中連接修正用電容器。 第1 3〜1 8實施例中係說明雜訊消除電路部分與第 1 2實施例不同之實施例。以下說明單位晶胞之結構與第 1 2〜1 8實施例不同之其他實施例。 第1 9賁施例 其全部結構與第1 7圖所示之第1 2實施例相同，故 不另外圖示。其特徴爲使用第4 2圖所示之單位晶胞P 5 以取代第17圖所示之單位晶胞P4。 、 * 本實施例之單位晶胞P 5中，反鳙電晶體（復置電晶 體）6 6經由反饋電容器2 1 2連接於放大電晶體6 4之 閘極。 考 第2 0實施例 全部結構與第1 7圖所示之第1 2實施例相同，故不 另外圖示。其特徵爲使用第4 3圖所示單位晶胞P 6取代 第1 7圖所示之單位晶胞P 4 ^ 本實施例之單位晶胞P 6除了具有第1 9實施例之結 構之外，又在放大電晶體6 4之閘極與復置線7 — 1之間 連接排出電晶體2 1 4。排出電晶體2 1 4之閘極經由共 同閘極線2 1 6 — 1連接於垂直位址電路5。 ; 第2 1實施例 本紙張尺度遑用中國國家標準（CNS ) A4規格（210X 297公釐）-78,- 0 裝 訂 線 ί f (請先閲讀背面之注意事項再填寫本頁) 經濟部中央樣準局員工消费合作杜印製 A7 ____ B7 五、發明説明（76 ) 全部結構與第1 7圖所示之第1 2實施例相同，故不 另外圖示。其特徵爲使用第4 4圖所示之單位晶胞p 7取 代第1 7圖之單位晶胞p 4。 本實施例之單位晶胞P 7除了具有第1 2實施例之結 構之外’又在放大電晶體6 4之閘極（與復置電晶體之連 接點）與感光二極體6 2之間連接傅送電晶體。傳送電晶 體2 1 8之閘極經由共同閘極線2 2 0 — 1連接於垂直位 址電路5。 第1 9實施例〜第2 1實施例亦與第1 2實施例相同 的不能變更雜訊消除部分。亦即第1 7〜、45圖中之說明 亦可同樣的應用於第19實施例〜21實施例。 本發明不受上述實施例之限制，可變更實施。例如只 要可製造單位晶胞之放大電晶體而不發生閾值不均衡，則 4不會發生固體圖型雜訊，故可省略雜訊消除器。或者，即 使發生固體圖型雜訊，只要不影響畫質，即可同樣的省略 雜訊消除器。 在各實施例之雜訊消除器中，無輸入信號時讀出之信 號電流（只有雜訊成分）愈小，雜訊愈小，故最好使施加 於儲存吸極電源端子之電壓與視頻偏壓成爲相等。所謂視 頻偏壓係指從水平信號線15將信號以電流型式讀出時， 水平信號線1 5大致上固定之電壓。第45圖表示之實現 之變更例。輸出信號端1 5連接於運算放大器1 76 ，而 在運算放大器17 6之輸入輸出端間連接負載電阻1 7 8 •如此，信號電流強制的流進負載電阻1 7 8，水平信號 本紙張尺度適用中國國家棣準（CNS)A4規格（210X297公釐）_ 了9 _ ----------t------.訂------1^ f . { (請先閲讀背面之注意事項再填寫本頁) A7 _____B7 _ 五、發明説明（π) 線1 5假想的被固定於某一電壓，亦即視頻偏壓。 (請先閲讀背面之注意事項再填寫本1) 以上單位晶胞係說明排列成二次元矩陣狀之實施例’ 但本發明亦可應用於將單位晶胞排列成一次元陣列狀之攝 像裝置。 第2 2實施例 第2 2實施例係使用將出現於垂直信號線8 — 1 ’ 8 —2..........之電壓經由限幅電晶體1 5 0之閘極電容器 變換成電荷，在電荷領域內進行減法而抑制雜訊之雜訊消 除電路。亦即在電荷領域內消除雜訊之方，亦即限幅雜 訊消除方式。 第4 6圖爲使用放大型MO S偵測器之固體攝像裝置 之電路圖。相當於圖素之單位晶胞PO—i — j ( P 〇 - 1 — 1 ，P 0 - 1 一 2..........）在縱向及橫向排列成二 次元矩陣狀》在各單位晶胞P 0 - i - j上分別設置構成 1個圖素之受光部之一個感光二極體1。1一1—1爲單 位晶胞P 1 — 1 - 1之感光二極體，1 一 1 _ 2爲單位晶 經濟部中央樣隼局員工消費合作社印製 胞PI — 1 — 1 — 2之感光二極體，〜，1 — 3 — 3爲單 位晶胞P 1 — 3 — 3之感光二極體》 1個單位晶胞PO—i - j上有放大感光二極體1 ( 1 — 1 — 1 ，1 — 1 — 2 ’ 〜，1 — 3 — 3)之檢測信號 之一個放大電晶體2 (2-2 — 1 ，2 — 1 — 2，〜，2 -3 - 3 )，選澤讀出信號之線之一個垂直選擇電晶體3 (3-1一1 ，3-1 — 2，〜3-3-3)，復置信號 本紙張尺度逋用中國國家揉準（CNS ) A4規格（210X297公釐） -80 - A7 B7 306G73 五、發明説明（78 ) 電荷之一個復置電晶體4 (4 — 1 — 1，4 — 1 — 2，〜 ，4 — 3 — 3 )。 這種構造之許多個單位晶胞排列成行列二次元狀。圖 中係排列3 X 3個晶胞，但實際上排列更多之單位晶胞。 從垂直位址電路5朝向水平方向配線之水平位址線6 (6 — 1 ，6 — 2，6 — 3)連接於垂直選擇電晶體3之 閘極而決定讀出信號之線。同樣的從垂直位址電路5朝向 水平方向配線之復置線7 (7 — 1 ，7 — 2，7 — 3)連 接於復置電晶體4之閘極。放大電晶體2之源極連接於配 置在列方向之垂直信號線8 (8 — 1 ，8、一#2，8 — 3) ，在其一端設置負載電晶體9 (9一1 ，9 — 2，9 — 3 )° 垂直信號線8 (8 - 1，8 — 2，8 — 3)之另一端 4分別連接於限幅電晶體1 50 (1 50 — 1 ，150 — 2 ，1 5 0 — 3 )之閘極。限幅電晶體1 5 0之源極連接於 限幅電容器 152 (152-1，152-2，152 — 3)，其另一端連接於限幅脈波供給端子154。爲了復 置限幅電晶體1 5 0之源極電位，在限幅電晶體1 5 0之 源極與限幅電源端子1 5 8之間設置限幅復置電晶體 156(156-1，156-2，156-3)，而該 電晶體1 5 6之閘極連接於限幅復置端子1 6 0。 限幅電晶體1 5 0之吸極連接於限幅電荷傅送電容器 162 (162 - 1，162-2，162- 3) » 爲了 復置限幅電晶體1 5 0之吸極電位，在限幅電晶體1 5 0 本紙張尺度適用中國國家標準（CNsTa4^格（210Χ297^* ) ~ — 一 81 - I—-------¥------1Τ------i ^ ί (請先閱讀背面之注意事項再填寫本頁) 經濟部中央揉準局貝工消費合作社印製 經濟部中央標準局貝工消費合作社印$. A7 ____B7____ 五、發明説明（79 ) 之吸極與儲存吸極電源端子1 5 4之間設置吸極復置電晶 體 166(166 — 1，166-2，166 — 3)，而 該電晶體1 6 6之閘極連接於吸極復置端子1 6 8。限幅 電晶體1 5 0之吸極經由從水平位址電路1 4供給之選擇 脈波所驅動之水平選擇電晶體12(12—1，12—2 ，1 2 — 3)連接於水平信號線1 5。 上述雜訊消除電路之部分即爲本實施例之特徵部分。 該雜訊消除電路將出現於垂直信號線8之電壓變換成電荷 ，在電荷領域進行減法而抑制雜訊。 以下說明本裝置之驅動方法。第4 7½¼表示本裝置 之動作之時序圖。第4 8圖爲限幅電晶體1 5 0之電位圖 〇 以下參照第4 7圖說明。首先，施加使水平位址線6 1之電位成爲高位準之位址脈波1 0 1後，只有該線之 垂直選擇電晶體3導通，由該線之放大電晶體2及負載電 晶體9構成源極跟踪電路。然後，在垂直信號線8及限幅 電晶體1 5 0之閘極出現放大電晶體2之閘極電壓，亦即 與感光二極體1之電壓大致上相同之電壓。 然後，在限幅復置端子1 6 0上施加限幅復置脈波 106，使限幅電晶體156導通，將限幅電容器152 之電荷初期化。然後將限幅復置電晶體1 5 6斷路，在限 幅脈波供給端子1 5 4上施加第1限幅脈波1 0 7 »如此 ，第1限幅電荷越過施加信號電壓之限幅電晶體1 5 0之 閘極下之通道電位Vsch被傳送至吸極。此時，在吸極復 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） ^ I n n n .^1 n I I I n n I I n T I n I n I _ 泉 一' 03. τ* ^ /. (請先閲讀背面之注意事項再填寫本頁) 經濟部中央揉準局員工消费合作社印製 A7 B7 五、發明説明（80 ) 置端子1 6 8上施加吸極復置脈波1 0 8，而吸極復置電 晶體1 6 6導通，故吸極電位被固定在儲存吸極電源端子 1 6 4之電壓Vsdd。因此，第1限幅電荷通過吸極復置 電晶體1 6 6被排出。 然後，切斷吸極復置電晶體1 6 6後，施加使復置線 7_1之電位成爲高位準之復置脈波103，使該線之復 置電晶體4導通而復置信號電荷◊如此，出現垂直信號線 8及限幅電晶體1 5 0之閘極上無信號電荷時之電壓（無 信號成分，只有雜訊成分之狀態，相當於該雜訊成分之電 壓）。然後，在限幅脈波供給端子154^¼加第2限幅 脈波1 0 9。如此，第2限幅電荷越過施加無信號電荷時 之電壓（相當於雜訊成分之電壓）之限幅電晶體1 5 0之 閘極下之通道電位V 被傅送至吸極。此時，因爲吸極 4復置電晶體1 6 6斷路，故第2限幅電荷被傳送至連接於 吸極之限幅電荷傳送電容器1 6 2。 然後，從水平位址電路1 4依次在水平選擇電晶體上 施加水平選擇脈波105 (105-1，105 — 2 ’ 105 — 3)，依次從水平信號線（信號輸出端）15取 出相.當於1條線之信號。在下一條線，下下一條線上依次 繼續進行上述動作，即可讀出二次元狀之全部信號° 該裝置中，假設限幅電容器1 5 2之電容量爲Csl時 ，最後被讀出於水平信號線1 5之電荷（第2限幅電荷） 變成 > 本紙張尺度適用中國國家標準（CNS ) A4規格（ 210X297公釐）〇〇 -〇〇 ----------Ί裝------訂------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央橾隼局員X消費合作杜印製 A7 __B7 _ 五、發明説明（81), 1T Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 __B7 V. Description of the invention (54) Focus control and vivid photography * The fixed pattern that can eliminate the problem of the MO S detector in a short time The noise component reads high-quality images at high speed with good S / N and detects the focus state at high speed. Focus control can be performed immediately and vivid portraits can be photographed. The above is explained using a monocular reflex camera as an example. However, the autofocus mechanism can also be applied to lens shutter cameras, telescopes, and optical microscopes. The following describes the low noise MO S detector used in the above systems with reference to the drawings, that is, effectively removes the fixed ring type noise For example, a MOS detector capable of generating a large output dynamic range of 70 dB or more, a noise cancellation circuit used by the MOS detector, and a specific example of a unit cell. The light-receiving part of the solid-state imaging device composed of an amplified MOS detector uses a photodiode to amplify the signal detected by the photodiode in each cell with transistors, which is characterized by high sensitivity. Normally, the magnified MO S solid-state imaging device (solid-state imaging device constituted by the magnified MO S detector) outputs the output signal of the photodiode corresponding to the light-receiving portion of the pixel of each unit cell through The amplified transistor in the unit cell is amplified and taken out. Therefore, during amplification, the deviation of the threshold voltage of the amplification transistor is superimposed on the signal. Therefore, even if the potentials of the photodiodes of each unit cell are the same, because the amplifying transistors of the unit cell that the photodiode is in are different from each other, and the threshold voltages of the amplifying transistors are different * Therefore, the output signals are not the same. Therefore, when the image captured by the magnification type MOS solid-state imaging device is reproduced, noise corresponding to the threshold deviation of the magnification transistor of each unit cell is generated. ¥ The paper size is in accordance with Chinese National Standard (€ Milk) 84 specifications (210/297 mm) _57 _ --------- approved clothing ------, order ------ ^ ( Please read the precautions on the back > ~ write this page) ~ A7 B7 printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention description (55) As such, the magnified MO S solid-state camera device (magnified MO S In the solid-state imaging device constituted by the detector), the threshold voltages of the amplified transistors of each unit cell are different, and each unit cell has its own inherent voltage. News, that is, the noise of the second element. The position of this noise is fixed on the screen of the secondary space, so it is called fixed pattern noise. The noise cancellation circuit used in the present invention described below is provided for eliminating fixed-line noise. The following describes a specific example of a solid-state imaging device using an amplified MOS detector that amplifies signal charges in a cell and its noise cancellation circuit. 12th Embodiment FIG. 17 is a structure of a MOS solid-state imaging device according to a 12th embodiment of the present invention. The unit cells P 4 — i _ j are arranged in the form of a quadratic matrix in the vertical and horizontal directions. Although only 2 X 2 is shown in the figure, it is actually 4 X and 4 X. i is a variable in the horizontal direction and j is a variable in the vertical direction. Figure 21 shows the detailed structure of each unit cell P4-i-j * The application field of the solid-state imaging device used in the present invention is Video cameras, electronic still cameras, digital cameras, telephone fax machines, copiers, and scanners. Vertical address lines 6-1, 6-2 wired from the vertical address circuit 5 to the horizontal direction . . . . . . . . . The unit cells connected to each row determine the horizontal line of the read signal. Similarly, from the vertical address circuit to the horizontal direction, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) -58---------- xiyi ------ 1T- ----- 0 (Please read the notes on the back first ¾. .  , > ίν write this page) · 30θ% ^ 73 Α7 Β7 Printed by the Zhengong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy 5. Description of the invention (56) 1 I Wiring reset line 7 1 1 »7 — 2 ... The unit cell connected to each column 1 I cell 9 1 1 The unit cell connected to each column is connected to the vertical signal line arranged in the direction of the column 1 I please 1 I 8 — 1 8-2 *… Signal line 8 — 1 9 8 — Read 1 | Read 1 2 ... One end is equipped with a load transistor 9 — 1, 9 — 2 〇 Load back 1 1 1 1 Transistor 9 -1 f 9 1 2…… gate The pole and the sink are connected to the common 1 Ψ 1 Sink voltage terminal 2 9 1 1 Vertical signal line 8 — 1 1 8 — 2 »…… the other — The end is connected to the writing book 1 Install Μ 0 S transistor 2 6 One 1 »2 6 One 2 ... gate of 0 Μ 0 S Page 1 1 Transistor 2 6-1 «2 6-2 ... The source of… is connected to the Μ 0 S electrical 1 1 crystal 2 8 -1 2 8 — 2…… the sink, Μ 0 S transistor 1 I 2 6 — 1 , 2 6 a 2 t…… 2 8 — 1, 2 8 — 2… 1 Set I… to become the source and the circuit of the embedding 0 Μ 0 S transistor 2 8-1 2 8 — 2 1 1 I 9…… The gate of… is connected to the common gate terminal 3 6 0 1 1 Μ 0 S transistor 2 6 — 1 2 6 — 2……… with Μ 0 S gas 1 1 transistor 2 8-1 2 8 — 2 · The connection point of «« »is connected to the clamping capacitor 1 | 3 2 — 1, 3 2 — 2…… via the sample holding wire 1 holding transistor 3 0 1 1 3 0 — 2« * «« · «… One end is at the clamp capacitor 3 2 1 I -1 »3 2-2»… • • *… and the other-* terminal is in parallel with the sample holding capacitor 1 1 I 3 4 — 1, 3 4 — 2… and the clamp Potential transistor 4 0 — 1 9 1 1 4 0 — 2 > ····· 〇Sample holding capacitor 3 4-1) 3 4 — 2 '1 1 * ... the other end is grounded. The clamping capacitor 3 2-1 9 3 2 — 2 1 1 »…… the other end is selected via the horizontal selection transistor 12 — 1» 1 2 — 1 1 2 »…… Connected to the signal output (horizontal signal line) 1 5 〇1 1 piece of paper Chinese standard home country Tongli Gong 7 29 A7 B7 Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs • Description of the invention (57) 1 1 Vertical address circuit 5 arranges many (here 2) signals and shifts 1 1 I bit of the circuit 9 can be any as shown in Figure 1 8 1 9 or 2 0-circuit real 1 1 I present 0 In the example shown in the first eighteenths, 9 is sequentially shifted from many outputs, input 1 1 signal 4 6 and the output of the address circuit 4 4 is output by the multiplexers 4 8 and 2 first read 1 1 The input signal 5 0 is synthesized. In the example shown in FIG. 1 9 9 the code is input to the decoder 1 1 5 4 The output of the decoder 5 2 is demultiplexed by the multiplexers 5 6 and 2 m Incoming signal drawing 1 | 5 8 Synthesis 0 In the example shown in Figure 2 0, the two address circuits 6 0 a Ψ Xi 1 I »6 0 b are integrated as the control signal lines of each row. I Figure 2 1 shows the unit cell P 4-1-1 of the unit cell shown in Figure 17 1 1 I-.  Structural example 0 here only represents the unit cell P 4-1-1 junction »1 1 Other unit cells P 4-1-1 2 also use the same junction name 0 1 1 as shown in the example The single-order 1-bit cell of the Μ 0 S type solid-state imaging device includes a photodiode that detects incident light 6 2 A photodiode 1 I 6 2 whose cathode is connected to a gate electrode and an amplification transistor 1 I that amplifies its detection signal 6 4 is set between the gate and the sink of the amplifying transistor 6 4 for feedback 1 1 line reset transistor 6 6 and the sucker 1 connected to the amplifying transistor 6 4 »Select the horizontal line of the read signal Vertical selection transistor 6 5 0 1 1 Horizontal address line 6 1 1 — 1 wired from the vertical address circuit 5 to the horizontal direction is connected to the gate of the vertical selection transistor 6 5 to select the 1 1 line of the read signal. Same »from vertical position The address circuit 5 is reset to the horizontal wiring 1 | Line 7-1 is connected to the gate of the reset transistor 6 6 〇1 I Normally magnified MOS type solid-state imaging device, amplify the transistor 1 1 I 6 4 The deviation of the threshold voltage is superimposed on the signal 9, so even if the potential of the photodiode 1 1 6 2 is the same I, the output signal is not the same I. The photographed animal image 1 1 This paper scale applies the Chinese National Standard (CNS) A4 specification (210X297mm) _ 6 () A7 B7 Printed by the Consumer Labor Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs 5. Description of the invention (58) 1 I During regeneration »A second deviation of the threshold corresponding to the amplified transistor 6 4 occurs, etc. 1 I The fixed pattern noise of the element-shaped noise. That is, in the magnified Μ 0 S type solid 1 1 1 in the imaging device 9 Even if it is irradiated with uniform light on all its light-receiving surface y from the allocation 1 1 into a matrix The image signal generated in each pixel of the shape The level is read first in each pixel. 1 1 does not become the same »becomes a quasi-image signal with uneven brightness. The back of the uneven brightness 1 1 The honey image is noise and becomes a quadratic distribution noise. The noise distributed on the screen side 1 1 is a fixed pattern noise. Because it is fixed in position, it is called a fixed pattern noise. Term vm-1 1 So 9 In this embodiment, 9 is used in the unit cell to reset the transistor. % This page ά.  | Body (4 in the idiomatic example shown in Figure 1 — i — j (ij = 1 9 2 1 I 9 3 4……) 9 in Figure 2 1 shows transistor 6 6) Anti-suspect reduction 1 1 I Small fixed pattern noise and as shown in Figure 17 before the horizontal selection transistor 1 1 order 1 2 is set to suppress the reduced fixed pattern noise circuit to form 1 noise removal circuit (noise (Removal circuit) 〇1 1 The noise removal circuit in Figure 17 is a double sampling type circuit that sets the correlation between the difference between the signal and 1 1 noise in the voltage field, but the type 1 line 1 I type of the noise removal circuit is not limited For the correlated double sampling type, various other noise removal circuits can also be used. The following refers to the 2nd AI 2 2 B 9 2 2 C diagram to illustrate the amplification caused by the feedback action of the unit cell with the characteristics of this embodiment 1 1 Transistor 6 4 of 1 1 threshold The principle of voltage correction. The 2nd 2 A diagram shows the cell circuit diagram. The 1st 1 2 2 B 9 2 2 C diagram shows the potential of the amplified transistor 6 4 9 1 1 The 2 2 B state is the vertical selection transistor 6 5 Open circuit * Reset 1 | Transistor 6 6 State at turn-on 1 That is, the potential when a base 1 I quasi-voltage is applied to the vertical signal line 8 In this state »electrons pass through the reset transistor 6 6 1 1 The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) -61-The Central Standards Bureau of the Ministry of Economic Affairs, Beigong Consumer Co., Ltd. printed the A7 B7. V. The invention description (59) The gate channel reaches the reset power After the sink of the crystal 6 6 ', its sink voltage drops. The connector between the sink and the gate of the reset transistor 6 6 becomes conductive. The reset transistor 6 6 'so the gate voltage also drops'. The number of electrons flowing in: a decreases. Finally, as shown in Fig. 2 2C, the reference voltage applied to the source becomes equal to the channel potential. In this state, the 'channel potential becomes a voltage applied from the outside, so unevenness in transistor structure does not occur. In this way, according to this embodiment, an anti-transistor transistor (reset transistor 6 6) is inserted between the gate electrode and the sink electrode of the amplifying transistor 64, which can be corrected by 'feedback action by applying a certain voltage at the source' The threshold is not uniform. The operation of the MOS solid-state imaging device described above will be described below with reference to the timing chart in FIG. 23. Because the common sink terminal 20 of the load transistor 9, the common gate terminal 36 of the transistor 28 of the impedance conversion circuit, and the common source terminal 38 of the clamp transistor 40 are driven by DC, it is not expressed In the timing chart. After applying the address pulse wave of the high level on the vertical address line 6-1, the unit cell P4-1-1, P4 -1-2 connected to the vertical address line 6-1. . . . . . . . . . The vertical selection transistor 6 5 becomes conductive, by amplifying the transistor 6 4 and the load transistor 9-1, 9 1 2. . . . . . . . . Constitute the source follower circuit. Keep the sample transistor 3 0 — 1, 3 0 — 2. . . . . . . . . The common gate 3 7 becomes the high level and holds the sample 3 0-1, 30-2. . . . . . . . . . Turn on. Thereafter, the clamp transistors 40-1, 4 0-2. . . . . . . . . . The common gate 4 2 becomes a high level and the paper standard of the clamped electric paper is adopted to the Chinese national standard (CNS) A4 specification (210XW7 mm) _ 62 _ --------- batch approve --- --- ir ------ Wire (Please read the notes on the back first |. . 4, write this page) ™ The Ministry of Economic Affairs Central Standards Bureau employee consumption cooperation du printed A7 ___B7__ V. Description of invention (60) Crystal 4 0 — 1 ’4 0 — 2’. . . . . . . . . Turn on. Then, make the box transistors 4 0-1, 4 0-2. . . . . . . . . . The common gate 4 2 becomes a low level and will clamp the transistors 40 — 1, 40 — 2. . . . . . . . . cutoff. As such, it appears on the vertical signal lines 8_1, 8-2. . . . . . . . . . The signal plus noise components are stored in the clamping capacitor 3 2 — 1, 2 2 — ^ 2, · ** ···. ·· pfj 〇then · Revert the potential of the vertical address pulse to the low level, apply the reset pulse wave of the high level on the reset line 7-1, and then connect to the unit cell P4 of the reset line 7-1 -1 — 1, P4— 1 — 2. . . . . . . . . The reset transistor 6 6 is turned on, the charge of the input terminal of the output circuit 6 8 is reset 9, and then the high level address pulse is applied to the vertical address line 6-1, and then connected to the vertical address line 6- Unit cell of 1 P4-1-1, P4 -1-2. . . . . . . . . . The vertical selection transistor 6 5 is turned on by the amplification transistor 6 4 and the load transistor 9 — 1, 9 1 2. . . . . . . . . . The source tracking circuit is formed, and the vertical signal lines 8-1, 8-2. . . . . . . . . . Only the noise components where the signal components are reset appear. As mentioned above, because the clamping capacitors 32-1, 32-2, ... store the signal plus noise components, so in the clamping section 4 1-1 * 4 1-2. . . . . . . . . . Only vertical signal lines 8 — 1, 8 — 2 appear. . . . . . . . .  The voltage change, that is, the signal voltage of the unfixed noise with the noise component subtracted from the signal component plus the noise component. Then, the sample is kept in the transistor 30-1, 30-2. . . . . . .  … The potential of the common gate 3 7 becomes a low level and the sample is maintained at the transistor. The paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) _ 63 _ --------- Meal- ---- 1T ------ ^ (Please read the notes on the back of IS to write this page) A7 _____B7___ printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs V. Description of Invention (6i) 30-1 »30 - 2 * . . . . . . . . . cutoff. In this way, the capacitors 34-1, 34-2 are held in the sample. . . . . . . . . . The medium storage appears in the clamping section 41 — 1 * 41 — 2 *. . . . . . . . . No noise electric K. Then, select transistors 12-1, 12-2 at the level. . . . . . .  ... Horizontal address pulses are applied in sequence and read from the output terminal (horizontal signal line) 15 and stored in the sample holding capacitors 34-1, 34-2, ... . . . . . The signal of the noise-free photodiode 62. In the future, the same applies to the vertical address lines 6-2, 6-3. . . . . . . . . .  By repeating the above operations, the signals of all the cells arranged in a quadratic shape can be taken out. Here, the relationship between the timing of the second and third circles will be described. The necessary sequence is as follows. The rise of the vertical address pulse. The sample keeps the pulse wave rising. Clamp pulse rise—Reset pulse rise—Reset pulse fall—Sample hold pulse fall—Vertical address pulse drop * Vertical address pulse rise, sample hold pulse rise The relationship between the rise and fall of the clamp pulse can be arbitrary, but it is better to be in the above order. In this way, according to the operation of Figure 23, the difference voltage when the signal (plus noise) appears on the clamping node 41 and the gate of the amplifier transistor is reset without the signal, so it cannot be for some reason Due to the feedback action of the unit cell, the fixed pattern noise generated by the uneven threshold of the amplified transistor 64 is compensated. That is, the circuit composed of the clamp transistor 30, the clamp capacitance 31, the sample holding transistor 40 and the sample holding capacitor 34 becomes a noise canceller. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) _ 64-: --------- ^ ------ ΐτ ------ ^ (please read the back first (Notes to write this page) 1. A7 B7 printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (62) Impedance conversion circuit formed by the source follower circuit of the noise canceller of this embodiment 2 6 , 2 8 is connected to the vertical signal line 8. That is, the vertical signal line is connected to the transistor pole of transistor 26. Because the gate capacitance is extremely small, the amplified transistor 64 of the unit cell only charges the vertical signal lines 8-1, 8-2. . . . . . . . . . Therefore, the short time constant of CR can immediately become a normal state. Therefore, the application timing of the reset pulse wave can be accelerated, and the noise canceller can be operated in a short time. The TV signal must be performed within the horizontal extinction period during the noise elimination operation *, so the noise elimination can be performed correctly in a short time.It is also because of the signal and noise output included in the noise elimination operation. When the noise is output, the impedance of the noise canceller when viewed from the unit cell is the same, so the noise can be correctly eliminated. That is, when the 'noise component ^ is output, and the' signal component + noise component ^ output, the impedance of the noise cancellation circuit observed from the unit cell is substantially the same. Therefore, at both outputs, the noise components become substantially the same, and by calculating the difference between the two, the noise output can be correctly eliminated and only the signal components can be taken out. Therefore, the noise can be correctly eliminated. When observing the noise cancellation circuit from the unit cell, only the gate capacitor can be observed from the viewpoint of impedance, and its capacitance is extremely small, so it can be surely eliminated in a short time. The structure of this embodiment is explained below. It can be seen from the circuit structure of FIG. 17 that because the clamping capacitor 32 and the sample holding capacitor 34 are directly connected and close to each other, the layers can be stacked on the same surface, and the noise elimination circuit can be miniaturized. . Specifically, as shown in FIG. 24, the first electrode 76 is formed on the silicon substrate 72 via the first insulating film 74 to form a sample holding capacitor --------- ^ ---- -、 Subscribe ------ 0 (Please read the notes on the back 1. (Heart writes this page) ~ This paper scale uses the Chinese national standard rate (CNS) Μ specification (210X297 mm> _ 65-A7 _B7_ printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. ) 34, a second electrode 80 is formed on the first electrode 76 via the second insulating film 78 to form a clamping capacitor 32. It can be seen from the figure that the first electrode 76 becomes a common electrode, and the clamping capacitor 3 2 and the sample holding capacitor 3 4 are stacked, so compared with when formed separately, the same capacitance can be generated in an area of 1/2 "In this embodiment, the 'unit cell P4 — 1 — 1, P4 — 1 — 2. . . . . . . . . . . Peripheral circuits such as the vertical address circuit 6, the horizontal address circuit 13 and the like are formed on a semiconductor substrate provided with a P + type impurity layer on the P − type substrate. The 2nd 5A and 2 5B are cross-sectional views of the semiconductor substrate. As shown in FIG. 25A, a cell element such as a photodiode 8 3 is formed on a semiconductor substrate provided with a p + type impurity layer 8 2 on a p_ type substrate 8 1. By forming the semiconductor substrate in this way, the diffusion potential of the P- / P + boundary can be used to prevent a part of the dark current occurring on the p-type substrate 81 from flowing into the P + side. The following is a brief description of the results of detailed analysis of electronic flow. For electrons that occur on the P-side, the thickness L of the P + impurity layer 82 may be regarded as the ratio of the concentration of P + and P-, that is, L · p + / p-. That is, as shown in Fig. 25B, it may be considered that the distance from the p-substrate 8 1 where the dark current is generated to the photodiode 8 3 is extended by p + / P-fold. In addition to the dark current flowing from the deep part of the substrate, there is also a current that occurs in the depletion layer near the photodiode 83. The amount of dark current occurring in the depletion layer is almost the same as the amount of dark current flowing from the deep part of the substrate. The paper size of the depleted layer uses the Chinese National Standard (CNS) Μ specifications (210X 297mm) ββ binding I IIIIII line (please read the precautions on the back to write this page) Ministry of Economic Affairs Central Bureau of Samples Consumption Cooperation Du Yince A7 __B7_ 5. The thickness of the invention description (64) is about 1 and the dark current flowing from the deep part of the substrate flows from the depth of about 100. This depth is also called the electron diffusion distance inside the p-type semiconductor. The reason why the dark current and the thickness difference do not become equal is that the probability of occurrence of dark current per unit volume inside the depletion layer is high. In principle, the dark current occurring in the depletion layer cannot be separated from the signal current. Therefore, reducing the component flowing from the deep part of the substrate can reduce the dark current. Since the unit cell 1 is formed on the semiconductor substrate on which the p-type impurity layer 7 2 is provided on the p-type substrate 7 1, the substrate potential can be prevented from changing due to the occurrence of dark current. Because the P-type substrate is thick, the resistance is small, so the noise removal circuit can be surely operated. This is an important factor because the component temperature rises rapidly after the element temperature rises. Its scale is that the composition from the deep part of the substrate is sufficiently smaller than the composition occurring in the depletion layer. Specifically, it is sufficient if the dark current from the deep part of the substrate is less than one digit of the dark current from inside the depletion layer. That is, P + / P- is set to 10 and the dark current from the deep part of the substrate is set to about 1/10. The dark current from the deep part of the substrate hardly exists in the semiconductor substrate composed of the n-type substrate and the p-type well, but in order to make it the same level as the semiconductor substrate, it is necessary to set Ρ + / Ρ- to 100 The dark current from the deep part of the substrate is about 1/100. In the conventional CD with practical performance, the impurity concentration of the n-type buried channel is about 1 〇iec m-3, and the p-type layer of the buried channel required for the stable manufacturing of the diffusion layer of the buried channel In this case, the impurity concentration of the p-type substrate) is approximately 10 μsc m_3. This paper standard uses the Chinese National Standard (CNS &A; A4 size (210X297mm) ~ ~ I Pack II Order —— line (please read the notes on the back \ 4. (This page) ™ A7 printed by the Beicong Consumer Cooperation Department of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs ___B7 V. Description of the invention (65) p + / p- is 10 ’The degree of P + is about 1 〇iecm-3, p + When / p- is 1000, approximately 1 becomes approximately the same as approximately 100 cm3 of the impurity concentration of the n-type buried channel, or is inverted by 1 digit. Therefore, the conventional C CD with actual performance does not consider the use of the P + layer with such impurity concentration at all. If the degree of p-layer is reduced, the sheet resistance of the substrate will increase. However, because there is no buried channel for CCD in the magnifying MOS camera, there is no need to reduce the concentration of the p-layer to a certain degree. Set the value of p + / p-* Reduce the resistance value of the P-well, improve the structure of the semiconductor substrate composed of the n-type substrate and the p-type well, and also constitute the unit cell. The second 6th graph is a cross-sectional view of a unit cell using a p + well 86 with a small sheet resistance value on an n-type substrate 85. Figure 27 is a cross-sectional view of the unit cell of CC D. For stable manufacturing, the impurity concentration of the n-type substrate 8 7 of the unit cell of CD, the p-type well 86, the n-type buried channel 8 9 is set to about 1 014cm -3, about 1015cm_3, about 1 〇1 ecm _3. Since the impurity concentration of the n-type photodiode 90 can be arbitrarily set within a certain degree, there is not much limitation in manufacturing. At the above impurity concentration, the sheet resistance value of the P-well 86 is approximately 10 ΟΚΩ / port. Even if its value reaches the above value, its noise is still very small. When the noise removal circuit is used in the magnifying MO S camera device, the paper size is based on the China National Standard (CNS) A4 specification (210Χ297mm) _ 68 _ --------- approved clothing- ----- IT ------ ^ (please read the notes on the back and write the page 4) ~ A7 B7 Printed by the Central Bureau of Economics of the Ministry of Economic Affairs, Consumer Cooperatives 5. Description of the invention (66) 1 1 The sheet resistance value of the P-well is very important. 9 The reason is that the time required for the P-well 8 6 to be disturbed and calm due to the reset pulse must match the system using the device. 1 1 1 1 Please 1 I In the current NTSC TV mode, the noise removal circuit is read first. I The dynamic read time is about 1 1 [β s] during the horizontal traceback period. Therefore, the P type The disturbance of the potential of the well 8 6 must be calm during this period until attention is paid to 1 thing 1 0 • 1 C m V or so 〇1 I 0 1 C m The minimum value of V is due to the noise voltage of the CCD. The output of this device is about this value. 0 According to the analysis result, it becomes 0 1 C m V in the very short time of 1 1 [ren S] page 1 1 The value must be 1 1 so that the sheet resistance of the P-well 8 6 becomes 1 KQ / □ or less. This value is 1 1 about 1/1 0 0 0 of the conventional CCD | Therefore, the impurity concentration of the P-well 8 6 must be set to about «| I 1 0 0 times. For example, as described in the above P-type substrate, the CCD Central system is not 1 I. Possible concentration 0 because in the high resolution mode, the horizontal retrace period 1 is 3 between the lines • 7 7 C β S The sheet resistance value 1 of the P-well 8 6 must be set to 3 0 0 Ω The following 0 1 1 other modification example is to form a high-concentration P + type sandwich layer 1 1 »on the surface of the substrate to form a P-type layer with a lower concentration than the concentration. 1 | No. 2 8 rwr is a structure diagram of a semiconductor substrate in which a 1 I P + type triple sandwich layer ε 2 is formed between the P type substrate ε 1 and the P type layer 93. Figure 2 9 is' 1 1 | Structure of a semiconductor substrate in which a p + type sandwich layer 1 1 I 9 6 is formed between an n-type S plate 9 5 and a p-type layer 9 7 0 1 1 This P + type three i 3; 3 layers can use megavolt ions with high acceleration Note 1 1 The paper size is suitable for China National Standard (CNS) Μ specification (210X 297 mm)-69-3060V3 Central Standard of the Ministry of Economic Affairs Μ Staff X Consumer Cooperative Printed . system.  A7 Β7 Fifth, the description of the invention (67) 1 | Into the machine to achieve 〇1 I in the P-type layer in addition to the formation of the unit cell of the photosensitive element 2 1 1 1 Polar body 8 3 »Transistors and other 1 formed Horizontal address circuit> Vertical bit 1 I Please peripheral circuit such as 1 I address circuit. Read first II Read 1 I No. 3 0 The picture shows a high-density P-well 3 0 surrounding the photodiode 8 3 around the back 1 1 1 and other p-wells 1 0 2 to form an n-type substrate 1 0 1 It's the attention 1 thing 1 The structure diagram of the semiconductor substrate composed of other parts 〇1 I Because of this structure », it can prevent the leakage of dark current to the photosensitive diode writer I body 8 3 〇Semiconductor substrate 1 0 1 It can also be a P_type substrate> Shell 1 1 I The concentration of the P-type well of the horizontal or vertical address circuit forming part 1 1 1 or 1 of the cell is determined at the time of circuit design. The optimal value is different from the crystal 1 1 cell, so it can also be formed as a P-type layer different from the P-type 1 well formed in the imaging field. 1 | No. 3 1 is a semiconductor substrate formed on the n-type substrate 10 5 by forming an IP-type well 1 0 6 that constitutes the imaging field, and separately forming other p-type 1 1 line wells 1 0 7 constituting the peripheral circuit Figure 1 Because of the above structure, a p-type well 1 1 0 suitable for each constituent element can be formed. The n-type substrate 1 0 5 can also be a p-type substrate. 1 1 Figure 3 2 shows the formation of the imaging area 1 on the n-type substrate 1 0 5 | P + type three L Meiji layer 1 0 S ί and low concentration f > type layer 1 C 9 and in 1 I peripheral circuit Partially formed picture of other P-type well 1 0 7 〇1 1 I Because of the above structure, it is possible to form a P-type well 1 1 II suitable for each constituent element to prevent dark current from leaking into the photodiode • The n-type substrate 1 0 5 1 1 may also be a P-type substrate. 1 1 This paper scale applies the Chinese National Standard (CNS) A4 specification (210X297mm> _7〇 A7 printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. V. Description of invention (68) As mentioned above, in accordance with this implementation For example, because an anti-transistor (reset transistor 6 6) is inserted between the gate and the sink of the amplifying transistor 64, the reverse action of applying a certain voltage to the source can correct the unevenness of the threshold 〇Because the output of the unit cell is output through the noise canceller, the solid-cell noise with uneven threshold of the amplified transistor matching the unit cell can be more suppressed. In the noise canceller, because the clamping capacitor 32 — 1, 32 one 2. . . . . . . . . . (Together referred to as 3 2 and other components with additional numbers are also the same.) The sample holding capacitor 34 is directly connected to be close to * so it can be stacked on the same surface and the capacitor can be miniaturized. Also, because the output of the unit cell is supplied to the noise canceller through the impedance conversion circuit, the impedance of the noise canceller observed from the unit cell is approximately the same when the noise is output and when the signal + noise is output, so In both outputs, the noise components are roughly the same, and the difference between the two can be calculated to correctly eliminate the noise output. Only the signal components can be taken out, and the noise can be correctly eliminated. When observing the noise canceller from the unit cell, only the gate capacitor can be observed from the impedance point of view, and its capacitance is extremely small, so it can be surely eliminated in a short time. Use a substrate composed of a P-type impurity substrate and a P + type impurity layer formed on the p_ type impurity substrate as the semiconductor substrate forming the unit cell | thereby reducing the dark current entering the unit cell * and Therefore, the potential on the surface of the substrate becomes stable, so that the noise canceling circuit operates reliably. The following describes the implementation of changing the noise canceling circuit part in the twelfth embodiment (CNS) (210X297 / ^-jt)-71---- ------- ^ ------ IT ------ 0 (Please read the notes I on the back first.  5 Write this page) ~ Printed by the Employees ’Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 _____B7 V. Description of the invention (69) Examples. Embodiment 13 Embodiment 33 is a circuit configuration diagram of an imaging device using an amplification type MO S amplification type MO S detector according to the 13th embodiment used in the present invention. The circuit structure near the unit cell P 4-i-j is the same as in the 12th embodiment "and the vertical signal lines 8-1, 8-2. . . . . . . . . . Become a series connection separation transistor 2 0 2 — 1, 2 0 2-2. . . . . . . . . . , In the separation transistor 202-1, 202-2. . . . . . . . . . With the level selection transistor 1 2 _ 1, 1 2-2. . . . . . . . . . Amplifier capacitor 206 — 1 ’206 — 2. . . . . . . . . . . In this embodiment, the noise canceller is not provided before the transistors are selected horizontally. Instead, an amplifier capacitor for adjusting the amplification factor is set. The operation of this embodiment will be described below with reference to circle 34. While applying a high level address pulse on the vertical address line 6-1, a high level pulse is applied on the common gate 204 of the separation transistor 202 to turn on the transistor. In this way, the output of the amplifying transistor 6 4 of the unit cell can be transmitted to the amplifying capacitor 206 via the vertical signal line 8 to store the amplified signal charge. Then, the potential of the common gate 204 of the split transistor 202 is restored to a low level, so that the split transistor 202 is disconnected. Apply the reset pulse wave of the high level on the reset line 701 to make the reset transistor 6 6 turn on, and then, the level recovery cost of the vertical address line 6-1 is applicable to the Chinese standard falcon (paper) CNS) A4 specification (210X297mm) _-~ ~ III nn I n with III n ^ II line (please read the note 1 on the back first, i .. ,. . Write this page) ~ V. Description of the invention (70) Low level, after the vertical selection transistor 6 5 is disconnected, the channel potential of the amplification transistor 6 4 becomes equal to the reference voltage • Then, the horizontal selection transistor 1 2 is turned on in turn , Sequentially read the amplified signal voltage stored in the amplifying capacitor 206. Assuming that the capacitance setting value of the amplifying capacitor 206 is C a * when the capacitance value of the photodiode 6 2 is C s, the amplification factor of the signal charge at this time becomes C a / C s. The amplification factor should be the same as or larger than that of the conventional type, so the value of C a is set to be the same as or larger than the capacitance value C r of the vertical signal line 8. The following describes the timing relationship shown in Figure 34. The required sequence is as follows: (1) The rise of the vertical address pulse—the fall of the gate pulse of the separation transistor—the rise of the reset pulse—the fall of the vertical address pulse—the reset pulse The fall of the wave (2) the rise of the gate pulse of the separation transistor-the fall of the gate pulse of the separation transistor-the rise of the reset pulse-the fall of the reset pulse The rise of the pulse wave of the vertical address printed by the cooperative society * The rise and fall of the gate pulse wave of the separation transistor can be arbitrary. 14th Embodiment FIG. 35 is a circuit configuration diagram of an imaging device using the amplified MOS detector of the 14th embodiment of the present invention. The circuit configuration near the unit cell P 4-i _ j and the 12th The embodiment is the same. Vertical signal lines 8 — 1, 8 — 2. . . . . . . . . . At the other end, the Chinese National Standard (CNS> A4 specification (210X297 mm) is used through the paper size of the clamp. Description of the invention (Ή) bit capacitors 1 3 1-1, 1 3 1-2. . . . . . . . . . Sampling and holding transistors 1 3 3 — 1, 1 3 3 — 2. . . . . . . . . . Level selection transistors 1 2-1, 1 2-2. . . . . . . . . . Connected to the signal output (horizontal signal line) 15. The clamp capacitor 131 — 1, 131-2. . . . . . . . . .  Hold the transistor with the sample 1 3 3-1, 1 3 3 — 2. . . . . . . . . . Connection point (clamping section 145-1, 145-2. . . . . . . . . . ) Connect the clamp transistor 13 2-1, 132-2. . . . . . . . . . Sucker. Clamp transistor 1 3 2 — 1, 1 3 2-2. . . . . . . . . . The source is connected to the common source terminal 1 4 1, and the gate is connected to the common gate terminal 1 4 2. Sample holding transistor 1 3 3-1, 1,%-2. . . . . . .  … And level selection transistors 1 2 — 1, 1 2 — 2. . . . . . . . . . The connection point through the sample holding capacitor 134-1, 134-2. . . . . . . . . .  Ground. 'The 3rd to 6th diagrams show the timing chart of this embodiment. The principle of noise elimination is exactly the same as that of NA09. Fifteenth Embodiment The third to seventh embodiment is a circuit configuration diagram of an imaging device using the amplified MO S detector according to the fifteenth embodiment of the present invention. The circuit structure near the unit cell P 4-i-j is the same as in the twelfth embodiment. The 15th embodiment is an example in which the impedance conversion circuit of the 12th embodiment is connected to the noise canceller of the 14th embodiment. In this embodiment, the common source of the clamp transistors 1 3 2 is driven by DC. This paper scale is applicable to Chinese national standard (CNS> A4 specification (210X297mm) _74I. i ^ ------ " ------ '· # i | (Please read the precautions on the back before filling in this page) Ministry of Economic Affairs, Central Bureau of Standards and Approval Beigong Consumer Cooperative A7 _B7_ V. DESCRIPTION OF THE INVENTION (72) 16th Embodiment FIG. 38 is a circuit configuration diagram of an imaging device using the amplified MOS detector of the 16th embodiment. The circuit structure near the unit cell p 4-i-j is the same as in the twelfth embodiment. Load transistor 9 — 1 ’9 — 2’. . . . . . . . . The vertical signal lines 8 — 1, 8 — 2 on the opposite side. . . . . . . . . The ends are connected to the limiting electric crystal 1 5 0 — 1, 1 5 0 — 2. . . . . . . . . . Of the gate. Limiting transistor 150-1 * 150-2 *. . . . . . . . . The source is connected to the limiting capacitor 1 5 2 — 1 ’1 5 2-2’. . . . . . . . . One end's limiting capacitor 152 — 1 '152 — 2 ». . . . . . . . . One end of each-connected to the limiting pulse supply terminal 1 54. In order to reset the limiting transistor 1 50 — 1, 15 0-2-. . . . . . . . . For the source potential, a limiting reset transistor 156-1, 156-2 is provided between the source of the limiting transistor and the limiting power terminal 158. . . . . . . . . . , And the transistor 156-1, 156-2. . . . . . . . . . The gate is connected to the limiting reset terminal 160. Limiting transistors 150-1, 150-2. . . . . . . . . . The sink is connected to the limiting charge transfer capacitors 162-1, 162-1, ... In order to reset the sucker potential of the limiting transistor 1 5 0 — 1, 1 5 0 — 2,..., A sink reset transistor 1 6 is provided between the sink and the storage sink power terminal 1 6 4 6 — 1, 1 6 6 — 2. . . . . . . . . . .  The transistor 1 6 6 — 1, 1 6 6 — 2. . . . . . . . . . The gate is connected to the sink reset terminal 168. Limiting transistor 150-1, 150-2. . . . . . . . . The sucker is driven by the horizontal address pulses supplied from the horizontal address circuit 1 3 to the horizontal selection transistor 1 2 — 1, 1 2_ 2. . . . . . .  This paper scale is applicable to the Chinese national standard (〇 ^ > 8 4 wash grid (2 丨 0 father 297 mm) _75_; binding ~ '' ^, | f (please read the precautions on the back before filling this page) Ministry of Economic Affairs Printed by the Central Bureau of Industry and Commerce Beigong Consumer Cooperative A7 ___B7_ V. Description of the invention (73)… connected to the signal output terminal 1 5 »As mentioned above, the unit cell P 4 — i of the MOS detector of the 16th embodiment -The structure of j is the same as the 12th embodiment shown in Figure 17, but the structure of the noise canceller part is different. The noise canceller of the 15th embodiment will appear on the vertical signal lines 8-1, 8, - 2_. . . . . . . . . . The voltage is converted into a charge through the gate capacitor of the limiting transistor 1 50, and the noise is reduced in the charge field to suppress the noise, which is its special feature * In this device, assuming that the capacity of the limiting capacitor 1 5 2 is CS1, Finally, the charge (the second limit charge) read from the horizontal signal line 15 is, 1 C si X (Vsch—Voch) 1 appears a charge proportional to the difference between when there is a signal and when it is reset without a signal, Therefore, it is possible to suppress the fixed pattern noise generated due to the uneven threshold of the amplified transistor 64 in the unit cell. In this way, the circuit structure that converts the voltage appearing on the vertical signal line 8 into electric charge and performs subtraction in the electric charge field can also be referred to as a noise canceller. For example, the circuit structure of the imaging device of the amplified MOS detector is round. The circuit structure near the unit cell P 4-i-j is the same as in the twelfth embodiment. The 17th embodiment is omitted in the 12th embodiment shown in FIG. 17 The paper size is adopted. The Chinese National Standard (CNS) Α4 specification (210X297 mm) -76-; Binding ~ line ί-(please Read the precautions on the back first and then fill out this page) A7 B7 printed by the Beigong Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs V. Invention Description (74) An example of an impedance conversion circuit composed of source follower transistors Eighteenth Embodiment Figures 40, 41 are circuit diagrams of an imaging device using the amplified MOS detector of the eighteenth embodiment of the present invention. The circuit structure in the vicinity of the unit cell P 4 — i — j is the same as in the 12th embodiment. Many parts of this embodiment are the same as the 14th embodiment shown in Fig. 35. The difference is that the capacitor will be used to correct the difference in impedance of the noise canceller observed from the unit cell side when the " ^ signal component + noise component ^ is output and when only the output of the | noise component # cUp P 1 6 0 —1, 160 — 2. . . . . . . . . Via switch 162 — 1, 162 ~ 2. . . . . . . . . . , With vertical signal lines 8 — 1, 8 — 2. . . . . . . . . . Be connected in parallel to the clamp capacitor 1 3 1-1, 1 3 1-2, 1. . . . . . . . . Closer to the camera field (unit cell) side. In Figure 40, the correction capacitor 160 and switch 16 2 are connected between the clamp capacitance 1 3 1 and the imaging field, and in Figure 41, they are connected between the imaging field and the load transistor 9 between. In this way, according to the present embodiment, in the MO S type solid-state imaging device with a noise removal circuit, the correction capacitor 160 is provided on the vertical signal line 8, so that it is possible to suppress the noise removal operation that causes noise. The change of the electric capacity can further reduce noise. In other words, when the signal after the selection of the photodiode is added to the noise output, and the noise output after the reset is completed, the impedance observed from the cell becomes equal to each other, so the noise can be eliminated correctly. The modification example of the eighteenth embodiment is that the paper standard shown in Figure 17 is the Chinese National Standard (CNS) A4 specification (210X 297mm) -77-binding line (please read the back side first Matters needing attention and then fill out this page) A7 B7 printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (75) Example, example 15 shown in Figure 37, example 15 shown in Figure 3, item No. 3 shown in Figure 3 In the noise canceller of the seventh embodiment, a correction capacitor is connected. The first to third embodiments describe an embodiment in which the noise canceling circuit part is different from the first embodiment. The following describes other embodiments in which the unit cell structure is different from the first 2 to 18 embodiments. Embodiment 19 The entire structure is the same as that of Embodiment 12 shown in Fig. 17, so it is not shown separately. The special feature is to use the unit cell P 5 shown in FIG. 42 instead of the unit cell P4 shown in FIG. 17. * In the unit cell P 5 of this embodiment, the anti-battery transistor (reset transistor) 6 6 is connected to the gate of the amplifier transistor 6 4 via the feedback capacitor 2 12. The 20th embodiment has the same structure as the 12th embodiment shown in Fig. 17, so it is not shown separately. It is characterized by using the unit cell P 6 shown in FIG. 43 to replace the unit cell P 4 shown in FIG. 17 ^ The unit cell P 6 of this embodiment has the structure of the 19th embodiment in addition to The drain transistor 2 1 4 is connected between the gate of the amplifying transistor 6 4 and the reset line 7-1. The gate of the drain transistor 2 1 4 is connected to the vertical address circuit 5 via a common gate line 2 1 6-1. ; 21st Example This paper standard uses the Chinese National Standard (CNS) A4 specification (210X 297 mm) -78,-0 binding line ί f (please read the precautions on the back before filling this page) Central Ministry of Economic Affairs Duplicate printing of A7 ____ B7 by the consumer cooperation of the sample bureau V. Description of the invention (76) The entire structure is the same as the 12th embodiment shown in Fig. 17, so it is not shown separately. It is characterized by replacing the unit cell p 4 of FIG. 17 with the unit cell p 7 shown in FIG. 4 4. In addition to the structure of the first embodiment, the unit cell P 7 of this embodiment is also between the gate of the amplifying transistor 64 (connection point with the reset transistor) and the photosensitive diode 62 Connect the Fu power crystal. The gate of the transmission transistor 2 1 8 is connected to the vertical address circuit 5 via the common gate line 2 2 0-1. The nineteenth embodiment to the twenty-first embodiment are also the same as the twelfth embodiment, and the noise cancellation section cannot be changed. That is, the descriptions in Figures 17 to 45 can be similarly applied to the 19th to 21st embodiments. The present invention is not limited by the above-mentioned embodiments, and can be implemented with changes. For example, as long as amplifying transistors of a unit cell can be manufactured without threshold imbalance, solid pattern noise will not occur, so the noise canceller can be omitted. Or, even if solid pattern noise occurs, the noise canceller can be omitted as long as it does not affect the image quality. In the noise canceller of each embodiment, the smaller the signal current (only the noise component) read out when there is no input signal, the smaller the noise, so it is better to make the voltage applied to the storage sink power terminal and the video bias The pressure becomes equal. The video bias voltage refers to a voltage at which the horizontal signal line 15 is substantially fixed when the signal is read out from the horizontal signal line 15 in a current pattern. Figure 45 shows an example of changes to the implementation. The output signal terminal 15 is connected to the operational amplifier 1 76, and the load resistor 1 7 8 is connected between the input and output terminals of the operational amplifier 17 6 • In this way, the signal current flows into the load resistance 1 7 8 forcibly. China National Standards (CNS) A4 specification (210X297mm) _ 了 9 _ ---------- t ------. Order ------ 1 ^ f.  {(Please read the precautions on the back before filling in this page) A7 _____B7 _ 5. Description of Invention (π) Line 15 is supposedly fixed to a certain voltage, which is the video bias. (Please read the precautions on the back before filling in this 1) The above description of the unit cell system is an embodiment arranged in the form of a quadratic matrix. However, the present invention can also be applied to a camera device in which the unit cells are arranged in a primary array. The second 22nd embodiment The second 22nd embodiment uses the vertical signal lines 8-1 ’8 -2. . . . . . . . . . The voltage is converted into a charge by the gate capacitor of the limiting transistor 150. The noise elimination circuit performs subtraction in the charge field to suppress noise. That is, the method of eliminating noise in the field of charge, that is, the method of limiting noise elimination. Figure 46 is a circuit diagram of a solid-state imaging device using an amplified MOS detector. The unit cell PO-i — j (P 〇-1 — 1, P 0-1 — 2. . . . . . . . . . ) Arranged in the form of a two-dimensional matrix in the vertical and horizontal directions》 A photodiode 1 constituting the light-receiving part of one pixel is provided on each unit cell P 0-i-j. 1-1-1 is the unit crystal Cell P 1-1-1 photodiode, 1-1 _ 2 is the unit of the Ministry of Economic Affairs Central Sample Falcon Bureau Employee Consumer Cooperative printed cell PI-1-1-2 photodiode, ~, 1- 3-3 is the unit cell P 1-3-3 of the photosensitive diode "1 unit cell PO-i-j has an enlarged photosensitive diode 1 (1-1-1, 1-1-2 ' ~, 1 — 3 — 3) Amplified transistor 2 of the detection signal (2-2 — 1, 2 — 1 — 2, ~, 2-3-3), a vertical selection of the line of the selected signal Transistor 3 (3-1-1, 3-1-2, ~ 3-3-3), reset signal sheet paper size using the Chinese National Standard (CNS) A4 specification (210X297mm) -80-A7 B7 306G73 V. Description of the invention (78) A reset transistor 4 of charge (4 — 1 — 1, 4 — 1 — 2, ~, 4 — 3 — 3). In this structure, many unit cells are arranged in rows and columns. In the figure, 3 X 3 unit cells are arranged, but in fact more unit cells are arranged. The horizontal address line 6 (6-1, 6-2, 6-3) wired from the vertical address circuit 5 toward the horizontal direction is connected to the gate of the vertical selection transistor 3 to determine the line for reading the signal. The same reset line 7 (7-1, 7-2, 7-3) wired from the vertical address circuit 5 toward the horizontal direction is connected to the gate of the reset transistor 4. The source of the amplifying transistor 2 is connected to the vertical signal line 8 (8-1, 8, 1 # 2, 8-3) arranged in the column direction, and a load transistor 9 (9-1, 9-2) is provided at one end thereof , 9 — 3) ° The other end 4 of the vertical signal line 8 (8-1, 8-2, 8-3) is connected to the limiting transistor 1 50 (1 50-1, 150-2, 1 5 0- 3) The gate. The source of the limiting transistor 150 is connected to the limiting capacitor 152 (152-1, 152-2, 152-3), and the other end is connected to the limiting pulse wave supply terminal 154. In order to reset the source potential of the limiting transistor 1 50, a limiting reset transistor 156 (156-1, 156) is set between the source of the limiting transistor 1 50 and the limiting power terminal 1 5 8 -2, 156-3), and the gate of the transistor 1 56 is connected to the limiting reset terminal 160. The collector of the limiting transistor 1 5 0 is connected to the limiting charge transfer capacitor 162 (162-1,162-2,162-3) »In order to reset the suction potential of the limiting transistor 1 5 0, the limit Transistor 1 5 0 This paper scale is applicable to the Chinese national standard (CNsTa4 ^ Grid (210Χ297 ^ *) ~ — 一 81-I —------- ¥ ------ 1Τ ------ i ^ ί (Please read the precautions on the back before filling out this page) Printed by the Ministry of Economic Affairs, Central Bureau of Standardization, Beigong Consumer Cooperative Printed by the Ministry of Economic Affairs, Central Bureau of Standardization, Beigong Consumer Cooperative  A7 ____B7____ Fifth, the invention description (79) A reset transistor 166 (166-1, 166-2, 166-3) is provided between the suction electrode and the storage suction power terminal 1 5 4 and the transistor 1 The gate of 6 6 is connected to the reset terminal 1 6 8 of the sink. The suction electrode of the limiting transistor 1 50 is connected to the horizontal signal line through the horizontal selection transistor 12 (12-1, 12-2, 1 2-3) driven by the selection pulse supplied from the horizontal address circuit 14 1 5. The part of the noise cancellation circuit described above is a characteristic part of this embodiment. The noise cancellation circuit converts the voltage appearing on the vertical signal line 8 into electric charge, and performs subtraction in the electric charge field to suppress noise. The following describes the driving method of this device. The 4th 7½¼ shows the timing chart of the operation of this device. Figure 4 8 is the potential diagram of the limiter transistor 1 50. The following description will be made with reference to FIG. 4 7. First, after applying the address pulse 1 0 1 that makes the potential of the horizontal address line 61 high, only the vertical selection transistor 3 of the line is turned on, which is composed of the amplification transistor 2 and the load transistor 9 of the line Source tracking circuit. Then, the gate voltage of the amplifying transistor 2 appears at the vertical signal line 8 and the gate of the limiting transistor 1 50, that is, a voltage substantially the same as the voltage of the photodiode 1. Then, a limiting reset pulse wave 106 is applied to the limiting reset terminal 160, so that the limiting transistor 156 is turned on, and the charge of the limiting capacitor 152 is initialized. Then, the limiting reset transistor 1 5 6 is opened, and the first limiting pulse wave 1 0 7 is applied to the limiting pulse wave supply terminal 1 5 4 »In this way, the first limiting charge crosses the limiting power of the applied signal voltage The channel potential Vsch under the gate of the crystal 150 is transmitted to the sink. At this time, the Chinese National Standard (CNS) A4 specification (210X297 mm) is applicable to the paper size of the sucker copy ^ I n n n. ^ 1 n I I I n n I I n T I n I n I _ Quan Yi '03.  τ * ^ /.  (Please read the precautions on the back before filling out this page) A7 B7 printed by the Employee Consumer Cooperative of the Ministry of Economic Affairs of the Ministry of Economic Affairs. 5. Description of the invention (80) Apply the reset pulse 1 0 8 to the terminal 1 6 8, Since the reset transistor 1 6 6 is turned on, the potential of the sink electrode is fixed at the voltage Vsdd of the storage sink power terminal 1 6 4. Therefore, the first limit charge is discharged through the reset transistor 16 6. Then, after the sink reset transistor 1 6 6 is cut off, a reset pulse 103 is applied to make the potential of the reset line 7_1 high, and the reset transistor 4 of the line is turned on to reset the signal charge ◊ , The voltage when there is no signal charge on the gate of the vertical signal line 8 and the limiting transistor 1 50 (no signal component, only the noise component, which is equivalent to the voltage of the noise component). Then, a second limiting pulse 109 is added to the limiting pulse wave supply terminal 154 ^ ¼. In this way, the channel potential V under the gate of the limiting transistor 1 5 0 of the second limiting charge over the voltage at which no signal charge is applied (equivalent to the voltage of the noise component) is sent to the sink. At this time, since the reset transistor 1 6 6 of the sink electrode 4 is disconnected, the second limit charge is transferred to the limit charge transfer capacitor 1 6 2 connected to the sink electrode. Then, a horizontal selection pulse 105 (105-1, 105 — 2 ′ 105 — 3) is applied to the horizontal selection transistors in order from the horizontal address circuit 14 and the phases are sequentially taken from the horizontal signal line (signal output terminal) 15. It should be the signal of 1 line. On the next line, continue the above actions in sequence on the next line, you can read all the signals of the second element. In this device, assuming that the capacitance of the limiting capacitor 1 5 2 is Csl, it is finally read as a horizontal signal The charge of line 15 (the second limit charge) becomes > This paper scale applies the Chinese National Standard (CNS) A4 specification (210X297mm) 〇〇-〇〇 ---------- Ί installed- ----- Subscribe ------ ^ (Please read the precautions on the back before filling in this page) The Central Department Falcon Bureau of the Ministry of Economic Affairs X Consumer Cooperation Du Printed A7 __B7 _ V. Description of Invention (81)

CsiX ( V sch_ V Och) 出現與有信號時與被復置而無信號時之差成比例之電荷， 故可抑制因放大電晶體2之閾值不均勻而產生之雜訊。亦 即產生雜訊消除器之功能。 此時，晶胞之放大電晶體2只要驅動垂直信號線8及 限幅電晶體1 5 0之閘極即可，而限幅電晶體1 5 0之閘 極電容器可設計爲與習用之大箝位電容量比較非常小之電 容器，故雜訊抑制所需之時間可大幅度的減少。因此，可 在實際上供給電視信號時之水平熄滅期間1 內li實外抑制雜 訊。 本實施例中，在 '雜訊成分'輸出時與^信號成分+ 雜訊成分#輸出時，從單位晶胞觀察時之雜訊消除電路之 β阻抗大致上相同。因此，在該兩個輸出時，雜訊成分大致 上成爲相同，計算兩者之差值，即可正確的去除雜訊輸出 而可只取出信號成分。因此，可正確的消除雜訊。從單位 晶胞觀察雜訊消除電路時，在阻抗之觀點上只有閘極電容 器，其容童非常小，故可在短時間內確實的消除雜訊。 第2限幅脈波1 0 7可能受到其前方之第1限幅脈波 1 0 7之影響。此時，爲了使第1及第2限幅脈波1 0 7 ，1 0 9之條件成爲相同，在第1限幅脈波1 0 7之正前 方設置模擬限幅脈波最爲有效。上述之條件係指在正前方 是否有脈波。本實施例中，爲了使其與正前方具有第1限 幅脈波之第2限幅脈波發生共同作用，在第1限幅脈波之 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） ---------— ¥------II------Ά. ί ! (請先閱讀背面之注意事項再填寫本頁) A7 B7 經濟部中央標準局貝工消費合作社印製 五、 發明説明 ( 82 ) 1 | 前 設 置 模 擬 限 幅脈 波 〇 1 I 在 第 1 限 幅脈 波 1 — 7 與 第 1 限 幅 脈 波 1 0 9 之 振 幅 1 1 I 相 同 之 微 妙 電 壓條 件 下 » 可 能 發 生 不 能 在 微 小 信 號 領 域 不 請 1 1 1 能 讀 出 信 疏 電 荷， 或 直 線 性 變 差 之 現 象 〇 因 此 9 將 第 2 限 先 閲 讀 1 1 幅 脈 波 1 0 9 之振 幅 設 定 爲 大 於 第 1 限 幅 脈 波 1 0 7 之 振 背 面 之 1 1 幅 > 在 第 2 限 幅脈 波 1 0 9 讀 出 之 電 荷 上 重 曼 偏 壓 電 荷 > 注 意 事 1 1 則 動 作 較 穩 定 。將 第 2 限 幅 脈 波 1 0 9 之 寬 度 設 定 爲 大 於 項 再 1 填 1 袅 I 第 1 限 幅 脈 波 10 7 之 寬 度 亦 爲 有 效 之 方 法 〇 寫 本 頁 假 設 水 平 位址 線 6 —- 1 之 高 位 準 之 垂 直 位 址 脈 波 前 緣 '—✓ 1 1 I 位 置 爲 P 1 後緣 位 置 爲 Ρ 2 復 置 線 7 « .1 之 信 疏 之 前 1 1 I 緣 位 置 爲 P 3 ，後 緣 位 置 爲 Ρ 4 施 加 於 限 幅 復 置 端 子 1 1 訂 1 1 6 0 上 之 限 幅復 置 脈 波 之 丄丨- 刖 緣 位 置 爲 P 5 後 緣 位 置 爲 P 6 9 施 加 於 限幅 脈 波 供 給 端 子 1 5 4 上 之 第 1 限 幅 脈 波 1 1 1 0 7 與 第 2 限幅 脈 波 1 0 9 中 第 1 限 幅 脈 波 1 0 7 之 前 1 1 緣 位 置 爲 P 7 ，後 緣 位 置 爲 Ρ 8 » 第 2 限 幅 脈 波 1 0 9 之 .泉 1 I 前 緣 位 置 爲 P 9， 後 緣 位 置 Ρ 1 0 » 施 加 於 吸 極 復 置 端 子 1 6 8 上 之 吸 極復 脈 波 之 mXJU 刖 緣 位 置 爲 P 1 1 後 緣 位 置 1 1 I 爲 P 1 2 時 各信 號 位 置 之 時 間 關 係 爲 1 1 1 P 1 < P 6 < P 7 < Ρ 8 < P 3 < P 4 < P 9 < P 1 0 < 1 1 1 P 2 1 I P 8 < P 1 1 < P 1 2 < Ρ 9 1 1 I 最 好 P 1 1 < P 4 2 < Ρ 3 < P 4 0 1 1 1 1 本紙張尺度逋用中國國家橾準（CNS > A4規格（2丨0X297公釐〉 -85 - 306G73 A7 ____ B7_ 五、發明説明（83 ) PI ，P5之前後關係可爲任意。P3與PI 1之位 置關係，P4與P 1 2之位置關係可任意。 晶胞之結構不限定於第4 6圇之結構，亦可如第4 9 圖所示使用感光二極體1與放大電晶體2之間裝插傳送電 晶體2 8之結構。如第4 9圖所示，若採用使用傳送電晶 體2 8之結構，則可先將無信號時之電壓供給於垂直信號 線8，然後使傳送電晶體2 8導通而輸出有信號時之電壓 。此時，最好將限幅電晶體1 5 0之導電型設定爲與晶胞 之電晶體相反之導電型。亦即，若晶胞係由η通道型電晶 體所構成，則限幅電晶體1 5 0使用0通1<道^較佳。本發 明不受第4 6圖，第4 9圖所示結構之限制，亦可應用於 將感光二極之檢測信號經由電晶體輸出之晶胞。 經濟部中央揉準局員工消费合作社印裝 (請先閲讀背面之注意事項再填寫本頁) 因爲無信號時讀出之信號電流小則雜訊較小，故使施 "加於儲存吸極電源電子1 6 4之電壓與與視頻偏壓成爲大 致上相等。所謂視頻偏應係指從水平信號線1 5上以電流 方式讀出信號時，水平信號線1 5大致上固定之電壓。如 第4 5圖所示，若使用運算放大器3 1之輸入輸出端間連 接負載電阻2 9之視頻放大器，信號電流強制的流入負載 電阻29 ，水平信號線15假想的被固定於某一電壓》以 上即爲視頻偏壓。 本發明不受上述實施例之限定，可在不超過其要旨之 範圍內變更實施。 如上所述，依照本實施例，在使用放大型Μ 0 S偵測 器之固體攝像裝置中，於垂直信號線之端部與水平選擇電 本紙張尺度通用中國國家橾準（0奶）八4規格（210'乂297公釐）_ ~— 經濟部中央標準局員工消费合作社印製 A7 _B7 五、發明説明（84 ) 晶體之間設置將出現於垂直信號線之電壓變換成電荷，在 電荷領域內進行減法而抑制雜訊之雜訊去除電路，故可縮 短抑制因放大電晶體之閾值不均勻而產生之固定圖型雜訊 ，可在供給電視信號時之水平熄滅期間內抑制雜訊。 亦即，在 ' 雜訊成分#輸出時，與^信號成分+雜訊 成分f输出時，從單位晶胞觀察之雜訊消除電路之阻抗大 致上相同•因此，在該兩個输出時，雜訊成分大致上成爲 相同，計算兩者之差值，即可正確的消除雜訊输出而可只 取出信號成分。因此，可正確的消除雜訊。若從單位晶胞 觀察雜訊消除電路時，在阻抗之觀點上，^%閘極電容器 ，而且其電容量極小，故可在短時間內確實的消除雜訊。 因此，依照本實施例，可提供一種可縮短抑制因放大 電晶體閾值不均勻而產生之固定圇型雜訊所需之時間，即 '使在供給電視信號時之水平熄滅期間內亦可充分的抑制雜 訊之固體攝像裝置》 第2 3實施例 第2 3實施例中說明雜訊消除電路之其他結構例。本 實施例之雜訊消除電路從水平選擇電晶體側依次並聯箝位 電晶體，樣品保持電容器，串聯箝位電容器，樣品保持電 容器，亦即重叠雜訊消除方式。 ' 在半導體基板上設置將感光二極體，將該感光二極體 之輸出供給於閘極之放大電晶體，串聯於該放大電晶體之 垂直選擇電晶體，及排出感光二極體之信號之復置電晶所 本紙張尺度適用中國國家橾率（CNS ) A4規格（210X297公釐） --------Ί^------,-ιτ------:泉 ^ f (請先閲讀背面之注意事項再填寫本頁)CsiX (V sch_ V Och) has a charge proportional to the difference between when there is a signal and when it is reset without a signal, so that the noise generated by the uneven threshold of the amplifier transistor 2 can be suppressed. This is the function of the noise canceller. At this time, the amplifying transistor 2 of the unit cell only needs to drive the vertical signal line 8 and the gate electrode of the limiting transistor 1 50, and the gate capacitor of the limiting transistor 1 50 can be designed as a conventional clamp Capacitors with very small potential capacitances can reduce the time required for noise suppression significantly. Therefore, it is possible to suppress noise during the horizontal extinguishment period 1 when the TV signal is actually supplied. In this embodiment, when the "noise component" is output and when the ^ signal component + noise component # is output, the β impedance of the noise cancellation circuit when viewed from the unit cell is substantially the same. Therefore, at these two outputs, the noise components become approximately the same, and by calculating the difference between the two, the noise output can be correctly removed and only the signal components can be taken out. Therefore, the noise can be correctly eliminated. When observing the noise elimination circuit from the unit cell, there is only a gate capacitor from the viewpoint of impedance, and its capacity is very small, so it can eliminate noise in a short time. The second limiting pulse 1 0 7 may be affected by the first limiting pulse 1 0 7 in front of it. At this time, in order to make the conditions of the first and second limiting pulses 1 0 7 and 1 0 9 the same, it is most effective to set an analog limiting pulse just before the first limiting pulse 1 107. The above condition refers to whether there is a pulse wave directly in front. In this embodiment, in order to interact with the second amplitude limiting pulse wave having the first amplitude limiting pulse wave directly in front of it, the Chinese National Standard (CNS) Α4 specification is applied to the original paper scale of the first amplitude limiting pulse wave ( 210X 297mm) ---------— ¥ ------ II ------ Ά. Ί! (Please read the precautions on the back before filling this page) A7 B7 Ministry of Economic Affairs Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards 5. Description of the invention (82) 1 | Set the analog amplitude limiting pulse wave 〇1 I at the amplitude of the first amplitude limiting pulse 1-7 and the first amplitude limiting pulse 1 0 9 1 1 I Under the same subtle voltage conditions »It may happen that you ca n’t be invited in the field of small signals. 1 1 1 The signal can be read out, or the linearity is deteriorated. So 9 read the 2nd limit first 1 1 pulse The amplitude of 1 0 9 is set to be greater than the 1 1 amplitude on the back of the 1st limiting pulse wave 1 0 7 > the charge read on the charge of the second limiting pulse 1 0 9 is biased on the charge > 1 1 the action is more Set. Set the width of the second limiting pulse 1 0 9 to be greater than the term and then fill in 1 * 1. The width of the first limiting pulse 10 7 is also an effective method. Write this page assuming a horizontal address line 6 --- 1 The vertical address of the high level of the pulse is the leading edge of the pulse wave'—✓ 1 1 I position is P 1 The trailing edge position is P 2 The reset line 7 «.1 Before the letter 1 1 I edge position is P 3, trailing edge position Apply P 4 to the limiter reset terminal 1 1 Set 1 1 6 0 The limiter reset pulse is the same-the edge position is P 5 and the trailing edge position is P 6 9 is applied to the limit pulse supply terminal 1 1 4 4 1st limiting pulse 1 1 1 0 7 and 2nd limiting pulse 1 0 9 1st limiting pulse 1 0 7 before 1 1 The edge position is P 7 and the trailing edge position is P 8 »2nd limiting pulse 1 0 9 of the spring 1 I. The leading edge position is P 9 and the trailing edge position P 1 0» The mXJU of the sucker complex pulse wave applied to the sink reset terminal 1 6 8 Fate The position is P 1 1 The trailing edge position 1 1 I is P 1 2 The time relationship of each signal position is 1 1 1 P 1 < P 6 < P 7 < Ρ 8 < P 3 < P 4 < P 9 < P 1 0 < 1 1 1 P 2 1 IP 8 < P 1 1 < P 1 2 < Ρ 9 1 1 I preferably P 1 1 < P 4 2 < Ρ 3 < P 4 0 1 1 1 1 This paper scale uses the Chinese National Standard (CNS & A4 specifications (2 丨 0X297mm> -85-306G73 A7 ____ B7_ V. Invention description (83) PI, the relationship between P5 before and after For arbitrary. The positional relationship between P3 and PI 1 and the positional relationship between P4 and P 1 2 can be arbitrary. The structure of the unit cell is not limited to the structure of the 46th wall, as shown in Fig. 49. The structure of the transmission transistor 28 can also be interposed between the photodiode 1 and the amplifying transistor 2. As shown in Figure 49, if the structure using the transmission transistor 28 is adopted, the voltage when no signal is supplied to the vertical signal line 8 first, and then the transmission transistor 28 is turned on to output the voltage when there is a signal . At this time, it is preferable to set the conductivity type of the limiting transistor 150 to the conductivity type opposite to the transistor of the cell. That is, if the unit cell system is composed of an n-channel type electric crystal, it is preferable to use 0 pass 1 < channel ^ for the limiting transistor 150. The present invention is not limited by the structures shown in Fig. 46 and Fig. 49, and can also be applied to the cell outputting the detection signal of the photodiode through the transistor. Printed by the Employee Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). Because the signal current read out when there is no signal is small, the noise is small. The voltage of the power supply electronics 164 becomes substantially equal to the video bias voltage. The so-called video biasing refers to a voltage that is substantially fixed when the horizontal signal line 15 is read out from the horizontal signal line 15 by current. As shown in Figure 45, if a video amplifier with a load resistor 29 is connected between the input and output terminals of the operational amplifier 31, the signal current flows into the load resistor 29 forcibly, and the horizontal signal line 15 is assumed to be fixed to a certain voltage The above is the video bias. The present invention is not limited by the above embodiments, and can be modified and implemented within the scope not exceeding the gist thereof. As described above, according to this embodiment, in a solid-state imaging device using an amplified MOS detector, the size of the electric paper sheet is selected at the end of the vertical signal line and horizontally. General Chinese National Standard (0 Milk) 8 4 Specifications (210 '297 mm) _ ~ — Printed by the Consumer Standardization Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _B7 V. Description of Invention (84) The voltage between the vertical signal lines is set between the crystals and converted into charges. A noise removal circuit that performs subtraction to suppress noise, so it can shorten the suppression of fixed pattern noise generated due to the uneven threshold of the amplified transistor, and can suppress noise during the horizontal extinction period when the TV signal is supplied. That is, when the “noise component # is output, and the ^ signal component + the noise component f is output, the impedance of the noise cancellation circuit observed from the unit cell is approximately the same. Therefore, when the two outputs are The signal components are almost the same, and the difference between the two can be calculated to eliminate the noise output correctly and only the signal components can be taken out. Therefore, the noise can be correctly eliminated. When observing the noise elimination circuit from the unit cell, from the viewpoint of impedance, ^% gate capacitor and its capacitance is extremely small, so it can eliminate noise in a short time. Therefore, according to this embodiment, it is possible to provide a method that can reduce the time required for suppressing the fixed-type noise generated due to the unevenness of the threshold of the amplified transistor, that is, it can also be sufficient during the horizontal extinction period when the TV signal is supplied. Noise-reducing solid-state imaging device "23rd Embodiment The 23rd embodiment describes other examples of the structure of the noise cancellation circuit. The noise canceling circuit of this embodiment sequentially clamps the transistor, the sample holding capacitor, the series clamping capacitor, and the sample holding capacitor in parallel from the horizontal selection transistor side, that is, the overlapping noise canceling method. 'Set up the photodiode on the semiconductor substrate, supply the output of the photodiode to the amplifying transistor of the gate, connect the vertical selection transistor in series with the amplifying transistor, and discharge the signal of the photodiode The paper size of the reset electronic crystal is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) -------- Ί ^ ------,-ιτ ------: Quan ^ f (Please read the notes on the back before filling this page)

經濟部中央橾隼局員工消費合作社印R A7 B7 五、發明説明（85) 構成之單位晶胞排列成行列二次元狀而構成之攝像領域， 連接於該垂直選擇電晶體之閘極而且配置於行方向之許多 垂直選擇線，驅動各垂直選擇線之垂直位址電路，配置在 讀出該放大電晶體之電流之列方向之許多垂直信號線，設 在許多垂直信號線之一端之許多負載電晶體，設在該垂直 信號線之另一端之許多水平選擇電晶體，依次供給選擇脈 波信號於各水平選擇電晶體之閘極之水平選擇移位電晶體 ，從該垂直信號線上經由該水平選擇電晶體讀出信號電流 之水平信號線，及設在該垂直信號線端部與該水平選擇電 晶體之間之雜訊去除電路之固體攝像裝置~中 < 其特徵爲， 該雜訊去除電路係從該水平選擇電晶體側依次並聯箝位電 晶體，樣品保持電容器，串聯箝位電容器，樣品保持電容 器。 ' 本發明之特徵爲，在上述各結構中，在半導體基板上 之同一平面內重叠全部或一部分箝位電容器與樣品保持電 容器。此外，亦可使復置吸極電源電壓與視頻偏壓成爲大 致上相同。 依照上述結構，可直接連接箝位電容器與樣品保持電 容器而互相靠近的配置，故可在同一面上重叠形成。因此 *與在半導體基板上並聯的配置箝位電容器與樣品保持電 容器之方式比較，只要以1/2之面積即可產生相同之電 容量，可將元件細微化· 第5 0圖爲使用第2 3實施例之放大型MO S偵測器 之固體攝像裝置之電路結構圖。圖中，與第4 6圖相同之 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X 297公釐）~一 ---------$------，訂------ ; 一 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（86 ) 部分以相同記號表示而不再詳細說明。 本裝置與第4 6圖所示之裝置不同之處爲去除雜訊之 雜訊消除電路。雜訊消除電路中，從垂直信號線8 ( 8 — 1 ，〜，8 — 3 )側依次串聯樣品保持電晶體3 0 ( 3 0 -1 ，〜，30-3)及箝位電容器32 (32 — 1，〜 • 3 2-3)，而在箝位電容器3 2與水平選擇電晶體 12 (12-1 ，12-2，12-3)之連接點並聯樣 品保持電容器34 (34 -1 ，〜，34 — 3)與箝位電 晶體 40 (40 — 1 ，〜，40 — 3)。 以下說明本裝置之驅動方法。第5 1½¼本裝置之動 作之時序圖表。 以下參照第5 1圖說明本裝置之動作。首先，在樣品 保持電晶體3 0上施加樣品脈波1 0 6，在雜訊抑期間內 1，使樣品保持電晶體3 0成爲導通狀態。然後，將使水平 位址線6，例如使水平位址線6 - 1之電位成爲高位準之 位準脈波101施加於從垂直位址電路5產生之該水平位 址線6 — 1上。 如此，只有閘極連接於該水平位址線6 - 1之排列第 1行及單位晶胞P1 — 1-1 ，P — 1-1-2 .......... P1 — 1 — η 之選擇電晶體 3 (3-1 — 1 ，3-1 — 2 ..........3 — 1 一 η )導通。然後，由連接於該導通之選 捧電晶體 3 (3-1-1 ，3 — 1-2 .......... 3 — 1 — η)之放大電晶體（2 — 1 — 1 ，2 — 1-2 .......... 2 -1-η)與負載電晶體9 — 1 一 1 ，9-1 — 2 ....... 本紙張尺度適用中國國家揉率（CNS ) Α4规格（2丨0 X 297公釐）。η -89 - 一-—裝 訂 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央樣準局WC工消费合作社印製 A7 _____B7_ 五、發明説明（87 ) •••9 一 1 _n )構成源極跟隨電路。 在垂直信號線8 — 1,8 — 1 — 2.......... 8 一 1 一 η上出現放大電晶體2~1_1 ，2 — 1 — 2.......... 2 —1 — η之閘極電蹏，亦即與感光二極體1 — 1 一 1 ，1 —1 一 2 ’ ......... 1 一 1 一 η之電壓大致相同之電壓。此 時，在箝位電晶髖40 (40 — 1 — 1 ，40 — 1 — 2， .........4 0 _ 1 — η )之閘極上施加箝位脈波1 〇 2，使 箱位電晶體 40 (40 — 1 — 1 ，40 — 1 — 2.......... 40 — 1 — η)導通，將箝位節 36 (36-1 ，36 — 2 .......... 3 6 — η )之電壓固定爲與箝~位源3 8之電 壓相同。 然後，使箝位電晶體40 (40 — 1 — 1 ，40 — 1 —2.......... 40 - 1 — η)斷路後，從垂直位址電路5 ”中產生使復置線7 - 1成爲高位準之復置脈波1 0 3，將 之施加於復置線7 - 1上，使連接於該復置線7 — 1之排 列第1行及單位晶胞PI — 1 — 1 ，Ρ1-1-2....... …P-1-n之復置電晶體4(4一1_1 ，4一1一2 .........4 一 1 一 η )導通，將信號電荷復置。如此箝位節 36 — 1 — 1 ，36 — 1 — 2.......... 3 6 — 1_η 上出 現以箝位電容器3 2與抽樣保持電容器3 4分割在感光二 極體 1 — 1 — 1，1 — 1 — 2.......... 1 — 1 — η 上有信 號電荷時與信號電荷被復置時之電壓之差之電壓，加上箝 位電源3 8之電壓之電壓。 亦即，假設箝位電容器3 2之電容童值爲CCi，樣 本紙張尺度適用中國國家標準（CNS ) A4规格（210 X 29"；公釐） ---------装------1T------Λ f ί . (請先閲讀背面之注意事項再填寫本頁) -90 - 經濟部中央棣準局負工消费合作杜印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨0Χ297公釐） A7 ____B7 五、發明説明（88 ) 品磉持電容器3 4之電容值爲Ceh，感光二極體1上有信 號電荷時之電荷爲Εβη，感光二極體1被復置時之電荷爲 丘„時，即出現以Ccl與C eh分割與Ε„之差電荷而得 之電壓加上箝位電源3 8之電壓之電壓。亦即出現Ccl/ (Ccl+ Ceh)倍之信號電壓。 亦即將信號成分Ccl/Ccl+Ceh)倍。 然後，以水平位址電路1 4在水平選擇電晶體1 2 - 1 — 1 ，1 2 — 1 — 2.......... 1 2 — 1 — η 上依次施加 水平選擇脈波105 (105-1，〜，105-3)， 從水平信號線1 5中依次取出相當於1條''線信號。在下 一條線，下下一條線依次繼績該動作，即可讀出二次元狀 之全部單位晶胞之信號。 假設水平位址線6 - 1之高位準之垂直位址脈波前緣 *位置爲P1 ，後緣位置爲P2，復置線7 — 1之信號之前 緣位置爲P 3，後緣位置爲P 4，施加於樣品保持電晶體 3 0之樣品脈波1 0 6之前緣位置爲P 5，後緣位置爲 P 6，施加於箝位電晶體4 0之閘極之箝位脈波1 0 2之 前緣位置爲P 7 ·後緣位置爲P 8時，各信號位置之時間 關係成爲 P1<P8<P3<P4<P6<P2 PI ，P5，P7之前後關係可爲任意。 最好 P1<»P5<P7。 在無輸入信號時，讀出信號電流小時雜訊較少•故本 -91 一 ----------^------,訂------Λ - ί · (请先閲讀背面之注意事項再填寫本育) 經濟部中央標準局員工消費合作社印製 A7 __B7 五、發明説明（89) 實施例中將施加於箝位電源3 8之電壓與視頻偏壓設定爲 大致上相等。所謂視頻偏壓係指從水平信號線1 5以電流 方式讀出信號時，水平信號線1 5大致上成爲固定之電壓 •如第4 5圖所示，使用運算放大器1 7 6之输入輸出端 子連接於負載電阻器1 7 8之視頻放大器時，信號電流強 制的流入負載電阻器1 7 8，水平信號線1 5假想的被固 定於其一電壓。此即爲視頻偏壓。 如上所述，本實施例中，雖然雜訊消除電路之結構不 同，但與第2 2實施例中說明之裝置相同的，可抑制固定 圖型雜訊。此時，由電路結構可知，因爲電容器3 2 與樣品保持電容器3 4直接互相連接而靠近，故可將之層 叠形成於同一面上。 具體言之，如第2 4圖所示，經由第1絕緣膜7 4在 '矽基板7 2上形成第1電極7 6而構成樣品保持電容器 34，又經由第2絕緣膜7 8在第1電極7 6上形成第3 電極8 0而構成箝位電容器3 4。由圓中可知，第1電極 7 6成爲共同電極，而且箝位電容器3 2與樣品保持電容 器3 4層叠，故與並聯的形成箝位電容器3 2與樣品保持 電容器3 4之結構比較，以1/2之面積即可產生相同之 電容量值。 本發明不受上述實施例之限制。基本晶胞之結構不限 定於第5 0圚之結構，可適當的變更。例如，亦可使用在 感光二極體1與放大電晶體2之間裝插傳送電晶體之方式 。亦可爲省略選擇電晶體之方式，或省略復置電晶體之方 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） ' -92 - ---------Ί裝------訂------；泉 一 f (請先閲讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（ 90 式。只要是經由電晶體输出感光二極體之檢測信號之晶胞 ，即可應用。 如上所述，依照本實施例，在使用放大型MO S偵測 器之固體攝像裝置中，設計構成雜訊去除電路之各要素之 連接關係，即可減小雜訊去除電路之箝位電容器與樣品保 持電容器所需之面積，可將元件微細化。 第2 4實施例 第52，53圖爲本發明中使用之第2 4實施例之固 體攝像裝置之電路結構圖· 以下說明降低固定圖型雜訊爲目的之第5 2圖之結構 。圖中，由將選擇讀出感光二極體1(1一1 -1,1- 2 ，1 — 3 — 3)之信號之線之放大電晶體2 ( 2 - 3 - 3 ) 信號之線之垂直選擇電晶體3 (3—1—1 ， ，〜，3—3—3)，及復置信號電荷之復置 4—1 — 1 ， 4 — 1_ 4 一 3 — 3 ) 經濟部中央標準局員工消费合作杜印製 位晶胞以3 X 3之行列排列成三次元狀。當然 更多之單位晶胞。 從垂直位址電路5朝向水平方向配線之水 ，選擇讀出 3-1-2 電晶體4 ( 所構成之單 實際上排列 ---------1------ST------A. i f (請先閲讀背面之注意事項再填寫本頁) 6 平位址線6 6_2，6 - 3)連接於垂直選擇電晶體3之 閘極而決定讀出信號之線。同樣的，從垂直位址電路5朝 向水平方向配線之復置線7 (7 — 1 ，7 — 2 ，7 — 3) 連接於復置電晶體4之閘極。放大電晶體2之源極連接於 本紙張尺度適用中國國家標準（CNS ) A4规格（210 X 297公釐） -93 - 經濟部中央橾準局貝工消費合作社印褽 A7 B7 五、發明説明（91) 朝向列方向配置之垂直信號線8 (8 — 1 ，8 — 2，8 — 3)，在其一端上設有負載電晶體9 (9 — 1 ，9一2， 9 - 3 )。 負載電晶體9之閘極連接於負載電晶體驅動線3 5。 負載電晶體8不一定由驅動線3 5驅動，亦可將負載電晶 體8之閘極連接於源極。 垂直信號線8之另一端連接於由箝位電容器131 ( 131 — 1，131-2，131 — 3)，箝位電晶體 132(132-1，132-2，132-3)，樣品 保持電晶體 133 (133 — 1 ，133、一#2，133 — 3)，樣品保持電容器134 (134 — 1 ，134 — 2 ，134 — 3)所構成之雜訊去除電路。該雜訊去除電路 經由從水平位址電路14所供給之選擇脈波所選擇之水平 ”選擇電晶體12 (12-1 ，12-2，12-3)連接 於水平信號線1 5。 本裝置中，在較箝位電容器更朝向攝像領域側，經由 開關 202 (202-1 ，202 — 2 ，202 — 3) 與垂直信號線8並聯的設置修正用電容器20 1 (2 0 1 -1 ，201-2，201 — 3)。在第 52 圖中，修正 電容器2 0 1與開關2 0 1係設在箝位電容器1 3 1與攝 像領域之間。在第5 3圖中，則設在攝像領域與負載電晶 體9之間。修正電容器2 0 1上施加一定電壓之偏壓。 假設修正電容器2 0 1之電容置值爲CCMP，箝位電 容器1 3 1之電容置爲CCL，樣品保持電容器1 3 4之電 本紙張尺度適用中國國家標準（CNS ) A4规格（210 X 297公釐） I---------裝-- f (請先閱讀背面之注意事項再填寫本頁) 訂 94 A7 306G73 _B7_ 五、發明説明（92 ) (請先閲讀背面之注意事項再填寫本頁) 容童值爲CSH。本實施例中，在樣品保持期間內’開關 2 0 2成爲導通。此時，在樣品保持時’連接於垂直信號 線8之電容量值爲Printed by the Ministry of Economic Affairs, Central Falcon Bureau Employee Consumer Cooperatives R A7 B7 V. Description of the invention (85) The unit unit cell is arranged in rows and columns to form the field of imaging, connected to the gate of the vertically selected transistor and arranged in The many vertical selection lines in the row direction drive the vertical address circuits of each vertical selection line, and the many vertical signal lines arranged in the column direction for reading out the current of the amplifying transistor, and the many load circuits provided at one end of many vertical signal lines Crystals, a plurality of horizontal selection transistors provided at the other end of the vertical signal line, sequentially supplying selection pulse signals to the horizontal selection shift transistors of the gates of each horizontal selection transistor, and selecting from the vertical signal line via the horizontal selection The solid-state imaging device of the horizontal signal line of the transistor readout signal current and the noise removal circuit provided between the end of the vertical signal line and the horizontal selection transistor is characterized by the noise removal circuit Select the transistor side from this level in order to parallel clamp transistor, sample holding capacitor, series clamping capacitor, sample holding capacitor . The present invention is characterized in that, in each of the above-mentioned structures, all or part of the clamp capacitor and the sample holding capacitor are superposed on the same plane on the semiconductor substrate. In addition, the reset sink power supply voltage and the video bias voltage can be made substantially the same. According to the above structure, the clamp capacitor and the sample holding capacitor can be directly connected to each other and arranged close to each other, so they can be formed to overlap on the same surface. Therefore, compared with the method of arranging a clamping capacitor and a sample holding capacitor in parallel on a semiconductor substrate, as long as the area of 1/2 can produce the same capacitance, the device can be miniaturized. Figure 50 shows the use of the second The circuit structure diagram of the solid-state imaging device of the amplified MOS detector of the third embodiment. In the picture, the same paper size as the 4th and 6th figures adopts the Chinese National Standard (CNS) A4 specification (210X 297mm) ~ 一 --------- $ ------, order- -----; 1. (Please read the precautions on the back before filling in this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. The description of invention (86) is indicated by the same symbol and will not be described in detail. The difference between this device and the device shown in Figure 46 is the noise removal circuit for removing noise. In the noise cancellation circuit, the sample holding transistor 3 0 (3 0 -1, ~, 30-3) and the clamping capacitor 32 (32 are connected in series in order from the vertical signal line 8 (8-1, ~, 8-3) side — 1, 3 3 2-3), and the sample holding capacitor 34 (34 -1) is connected in parallel at the connection point of the clamping capacitor 3 2 and the level selection transistor 12 (12-1, 12-2, 12-3) ~, 34-3) and clamp transistor 40 (40-1, ~, 40-3). The following describes the driving method of this device. Section 5 1½¼ Timing chart of the operation of this device. The operation of this device will be described below with reference to FIG. 51. First, the sample pulse transistor 106 is applied to the sample holding transistor 30, and during the noise suppression period 1, the sample holding transistor 30 is turned on. Then, a level pulse line 101 that makes the potential of the horizontal address line 6, for example, the potential of the horizontal address line 6-1 to a high level, is applied to the horizontal address line 6-1 generated from the vertical address circuit 5. In this way, only the gate is connected to the first row of the horizontal address line 6-1 and the unit cells P1-1-1, P-1-1-2 ..... P1-1 — Η selection transistor 3 (3-1 — 1, 3-1 — 2... 3 — 1 — η) is turned on. Then, the amplifier transistor (2 — 1 — η) connected to the conducting selected transistor 3 (3-1-1, 3 — 1-2 ..... 3 — 1 — η) 1, 2-1-2 ......... 2 -1-η) and load transistor 9-1-1, 9-1-2 ....... This paper size applies to China National kneading rate (CNS) Α4 specification (2 x 0 297 mm). η -89-I-—Binding (please read the notes on the back before filling in this page) A7 _____B7_ Printed by the WC Industrial and Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economy V. Invention description (87) ••• 9 1 1 _n) Form the source follower circuit. Amplifying transistors 2 ~ 1_1, 2 — 1 — 2 .... appear on vertical signal lines 8 — 1, 8 — 1 — 2 .... .. 2 —1 — η of the gate electrode, that is, the voltage of the photodiode 1 — 1 — 1, 1 — 1 — 2 '......... 1 — 1 — 1 η Of voltage. At this time, the clamp pulse wave 1 〇2 is applied to the gate electrode of the clamp transistor 40 (40 — 1 — 1, 40 — 1 — 2, ......... 4 0 _ 1 — η) , Make the box transistor 40 (40 — 1 — 1, 40 — 1 — 2 .......... 40 — 1 — η) turn on, and clamp the clamp section 36 (36-1, 36 — 2 .......... 3 6 — η) is fixed at the same voltage as the clamp source 3 8. Then, after the clamp transistor 40 (40 — 1 — 1, 40 — 1 —2 ......... 40-1 — η) is disconnected, a complex reset is generated from the vertical address circuit 5 ″ Set the line 7-1 to become the reset pulse wave 1 0 3 of the high level, and apply it to the reset line 7-1, so that the arrangement of the first line connected to the reset line 7-1 and the unit cell PI- 1 — 1, P1-1-2 ....… P-1-n reset transistor 4 (4--1_1, 4-1-1-2 ......... 4--1 A η) is turned on, and the signal charge is reset. In this way, the clamping nodes 36 — 1 — 1, 36 — 1 — 2 .... 3 6 — 1_η appear with the clamping capacitor 3 2 and sampling Holding capacitor 3 4 is divided between the photodiode 1 — 1 — 1, 1 — 1 — 2 .......... 1 — 1 — η The voltage when there is signal charge and when the signal charge is reset The voltage of the difference is added to the voltage of the clamping power supply 3 8. That is, assuming that the capacitance child value of the clamping capacitor 32 is CCi, the sample paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 29 "; Mm) --------- install ------ 1T ------ Λ f ί. (Please read the precautions on the back before filling this page) -90- The Ministry of Economic Affairs, Central Bureau of Pre-Examination, Duty-to-use, consumer cooperation, and the printed paper size is in accordance with Chinese National Standard (CNS) Α4 specifications (2 丨 0Χ297mm) A7 ____B7 5. Description of the invention (88) Product Capacitance Capacitor 3 4 Capacitance Value Is Ceh, the charge when the signal charge on the photodiode 1 is Εβη, and the charge when the photodiode 1 is reset is qi, that is, the difference between the Ccl and C eh and the difference between the charge Voltage plus the voltage of the clamping power supply 3 8. That is, the signal voltage of Ccl / (Ccl + Ceh) times appears. That is, the signal component Ccl / Ccl + Ceh) times. Then, the horizontal address circuit 14 The horizontal selection transistors 1 2-1 — 1, 1 2 — 1 — 2 .......... 1 2 — 1 — η, the horizontal selection pulse wave 105 (105-1, ~, 105- 3), from the horizontal signal line 15 in order to take the equivalent of a ”line signal. In the next line, the next line in succession of this action, you can read the signal of all the unit cells of the second element. Suppose the leading edge of the vertical address pulse at the high level of the horizontal address line 6-1 is P1, the trailing edge position is P2, and the letter of the reset line 7-1 The leading edge position of the number is P 3, the trailing edge position is P 4, the sample pulse wave 1 0 6 applied to the sample holding transistor 30 The leading edge position is P 5, the trailing edge position is P 6, applied to the clamp transistor 4 The clamp pulse of the gate of 0 1 0 2 The leading edge position is P 7 · When the trailing edge position is P 8, the time relationship of each signal position becomes P1 < P8 < P3 < P4 < P6 < P2 PI, P5, The relationship before and after P7 can be arbitrary. Preferably P1 < »P5 < P7. When there is no input signal, the signal current is small when the read signal is small. Therefore, this book -91 1 ------------ ^ ------, order ------ Λ-ί · (Please read the precautions on the back before filling in this education) A7 __B7 printed by the employee consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention description (89) In the embodiment, the voltage and video bias applied to the clamping power supply 3 8 are set Is roughly equal. The so-called video bias voltage means that when the signal is read out from the horizontal signal line 15 by current, the horizontal signal line 15 becomes approximately a fixed voltage. As shown in Figure 4 5, the input and output terminals of the operational amplifier 1 7 6 are used When connected to the video amplifier of the load resistor 1 7 8, the signal current forcibly flows into the load resistor 1 7 8, and the horizontal signal line 15 is virtually fixed to a voltage. This is the video bias. As described above, in this embodiment, although the structure of the noise canceling circuit is different, it is the same as the device described in the 22nd embodiment, and the fixed pattern noise can be suppressed. At this time, it can be seen from the circuit structure that the capacitor 3 2 and the sample holding capacitor 34 are directly connected to each other, so that they can be stacked on the same surface. Specifically, as shown in FIG. 24, the first electrode 76 is formed on the silicon substrate 72 via the first insulating film 74 to form the sample holding capacitor 34, and the second insulating film 78 is formed on the first A third electrode 80 is formed on the electrode 76 to form a clamp capacitor 34. As can be seen from the circle, the first electrode 76 becomes a common electrode, and the clamping capacitor 32 and the sample holding capacitor 34 are stacked. Therefore, compared with the structure of the parallel formation of the clamping capacitor 3 2 and the sample holding capacitor 34, 1 / 2 area can produce the same capacitance value. The present invention is not limited by the above embodiments. The structure of the basic unit cell is not limited to the 50th structure, and can be changed appropriately. For example, a method of interposing a transmission transistor between the photodiode 1 and the amplifying transistor 2 can also be used. It can also omit the method of selecting the transistor or omit the method of resetting the transistor. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) '-92---------- Ί Install ------ order ------; Quan Yi f (please read the precautions on the back before filling in this page) A7 B7 5. Description of invention (90 type. As long as the photosensitive diode is output through the transistor The unit cell of the detection signal of the body can be applied. As mentioned above, according to this embodiment, in the solid-state imaging device using the amplified MOS detector, the connection relationship of each element constituting the noise removal circuit is designed, namely The area required for the clamp capacitor and the sample holding capacitor of the noise removal circuit can be reduced, and the components can be miniaturized. The second and fourth embodiments Figures 52 and 53 are solid-state imaging of the second and fourth embodiments used in the present invention Circuit diagram of the device · The following describes the structure of Figure 5 2 for the purpose of reducing fixed pattern noise. In the figure, the photodiode 1 (1 1 1 -1, 1- 2, 1 — 3 — 3) The signal line is amplified by transistor 2 (2-3-3) The signal line is vertically selected by transistor 3 (3—1— 1, 3, 3, 3, 3), and reset of the reset signal charge 4-1, 1, 4, 1_ 4, 1, 3, 3) Employee consumption cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs, the Du Indian printing unit cell The rows and columns of 3 X 3 are arranged in three dimensions. Of course more unit cells. From the vertical address circuit 5 toward the horizontal wiring water, choose to read 3-1-2 transistor 4 (the list is actually arranged --------- 1 ------ ST- ----- A. If (please read the precautions on the back before filling in this page) 6 horizontal address line 6 6_2, 6-3) Connect to the gate of the vertical selection transistor 3 to determine the line to read the signal . Similarly, the reset line 7 (7-1, 7-2, 7-3) wired from the vertical address circuit 5 to the horizontal direction is connected to the gate of the reset transistor 4. The source of the amplifying transistor 2 is connected to this paper. The standard is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) -93-Printed by the Ministry of Economic Affairs, Central Bureau of Industry and Commerce, Beigong Consumer Cooperative A7 B7 V. Description of invention ( 91) The vertical signal line 8 (8-1, 8-2, 8-3) arranged toward the column direction is provided with a load transistor 9 (9-1, 9-2, 9-3) at one end thereof. The gate of the load transistor 9 is connected to the load transistor drive line 35. The load transistor 8 is not necessarily driven by the drive line 35, and the gate of the load transistor 8 may be connected to the source. The other end of the vertical signal line 8 is connected to a clamping capacitor 131 (131-1, 131-2, 131-3), a clamping transistor 132 (132-1, 132-2, 132-3), and the sample remains charged Noise removal circuit composed of crystal 133 (133 — 1, 133, # 2, 133 — 3), and sample holding capacitor 134 (134 — 1, 134 — 2, 134 — 3). The noise removal circuit is connected to the horizontal signal line 15 via the “selected transistor 12 (12-1, 12-2, 12-3) selected by the selection pulse supplied from the horizontal address circuit 14. The device In the middle, the capacitor for correction 20 1 (2 0 1 -1, 201) is installed in parallel with the vertical signal line 8 via the switch 202 (202-1, 202-2, 202-3) more toward the imaging field side than the clamping capacitor -2, 201 — 3). In Figure 52, the correction capacitor 2 0 1 and the switch 2 0 1 are located between the clamping capacitor 1 3 1 and the imaging field. In Figure 5 3, they are located in the imaging Between the field and the load transistor 9. A bias voltage of a certain voltage is applied to the correction capacitor 2 01. Assume that the correction capacitor 2 0 1 has a capacitance setting of CCMP, the clamping capacitor 1 3 1 has a capacitance of CCL, and the sample holding capacitor 1 3 4 The size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) I --------- installed-f (Please read the precautions on the back before filling this page ) Order 94 A7 306G73 _B7_ V. Description of the invention (92) (Please read the precautions on the back before filling in this page) The value of Rongtong is CSH. In the example, the 'switch 2 0 2 is turned on during the sample holding period. At this time, the value of the capacitance connected to the vertical signal line 8 during the sample holding is

C = C CMP+ C SH 因此，修正«容器2 0 1之電容量值c CMP係在 2 { C c L — C c L * Csh/ ( CcL+ CsH)} > CcmP〉Ο 之範圍內設定。如此設定，則在樣品保持時連接於垂直信 號線8之電容量與無修正電容器2 Ο 1時比較，接近箝位 電容器1 3 1之電容量值C η之大小。因此，差值V ^變 1成更小，故雜訊亦變成更小。 以下說明動作。第5 4圔爲該裝置之動作時序圖。本 實施例中，修正電容器201 (201 — 1 ’ 201 — 2 經濟部中央樣準局男工消费合作社印裝 ，2 0 1 — 3 )係設在較箝位電容器更朝向攝像領域側， 而且經由開關 202 (202 — 1 ，202-2，202 一 3)並聯於垂直信號線8。第52圖中，修正電容器 2 0 1及開關2 0 2係設在箝位電容器1 3 1與攝像領域 之間。第5 3圖中，係設在攝像領域與負載電晶體9之間 '。在樣品保持期間內，開關2 0 2成爲導通。 假設施加使水平位址線6 - 1之位準成爲高位準之位 址脈波101。此時只有該線之垂直選擇電晶體3導通。 本紙張尺度適用中國國家揉準（CNS〉A4規格（210X297公釐）~~~ 經濟部中央標準局員工消費合作社印裝 A7 B7 _ 五、發明説明（93 ) 然後，使負載電晶體驅動線3 5之位準成爲髙位準’則由 被選擇之線之放大電晶體2與負載電晶體8構成源極跟隨 電路。此時，在垂直信號線8上出現放大電晶體2之閘極 電壓，亦即與感光二極體1之電壓大致相同之電壓。此時 ，在箝位電晶體1 3 2之閘極上施加箝位脈波1 0 2，使 箝位電晶體1 3 3導通，將箝位節1 4 5之電壓固定爲與 箝位電源1 7之電壓相同之電壓。 然後，使箝位電晶體1 3 2成爲斷路後，使負載電晶 體驅動線3 5之位準成爲低位準。然後，施加使復置線7 -1之位準成爲髙位準之復置脈波1 0 3' fe復置電晶體 4導通而復置信號電荷。然後，又使負載電晶體驅動線 3 5之位準成爲高位準，則在箝位節1 4 5上出現將感光 二極體1上有信號電荷時與信號電荷被復置時之電壓差相 1加之電壓。 然後，在樣品保持電晶體1 3 3之閘極上施加樣品保 持脈波1 0 4，使樣品保持電晶體1 3 3導通，將該信號 傅送至樣品保持電容器1 3 4。然後，從水平位址電路 14依次在水平選擇電晶體12上施加水平選擇脈波 105(105-1，105 — 2，105-3)，從水 平信號線1 5中依次取出相當於1條線之信號。 在下一條線，下下一條線上依次繼績進行該動作，即 可讀出二次元狀之全部信號。 該裝置中，最後在箝位節1 4 5上出現有信號時與被 復置而無信號時之差之電壓，故可抑制因放大電晶體2之 本紙張尺度遑用中國國家橾隼（CNS)A4規格（210X297公釐） ---------^------1T------Λ f f (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印装 A7 __ B7 五、發明説明（94) 閾值不均勻所造成之雜訊。亦即由箝位電容器1 3 1 ，箱 位電晶體1 3 2，樣品保持電晶體133，及樣品保持電 容器1 3 4所構成之電路成爲雜訊去除電路，抑制二次元 狀雜訊之固定圖型雜訊之發生。 亦即，在 >雜訊成分輸出時，與 ''信號成分+雜訊 成分^輸出時，從單位晶胞觀察之雜訊消除電路之阻抗大 致上成爲相同。因此，在該兩個输出時，雜訊成分成爲大 致上相同，計算兩者之差值，即可正確的去除雜訊輸出而 可只取出信號成分。因此，可正確的消除雜訊。 依照第2 4實施例之結構，即使無修^正％容器2 0 1 及開關2 0 2等構件，只要是可確保箝位脈波爲2 0 0 ( n s )以上之時間宽度之電路，即具有充分之雜訊去除能 力。 ' 亦即，在雜訊去除電路中，儲存於樣品保持電容器中 之信號電荷係由樣品保持電容器之大小與電極間之電壓差 之稹決定。各電極間之電壓差係由樣品保持電容器1 3 4 之電容量值C SH與箝位電容器1 3 1之電容置值C 之比 決定》因此，爲了加大出現於樣品保持電容器之信號電荷 ，必須增大樣品保持電容器之電容量，而且與其對應的加 大箝位電容器之電容置。結果，爲了產生充分之信號電荷 ，需要相當大之箝位電容器之電容量。然而，若箝位脈波 能確保充分之脈波寬度則無問題。 單位晶胞之放大電晶體2不但需要驅動垂直信號線8 之電容童，又必須驅動箝位電容器。若是可確保抑制雜訊 本紙張尺度適用中國國家橾準（CNS ) Α4規格（210 X 297公釐） --------------1T------,Λ. t ί (請先閲讀背面之注意事項再填寫本頁) -97 - 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（95 ) 所需之時間則無問題。但若MO S型固體攝像裝置係用來 做爲電視攝影機時，則成爲問題*實際上供給電視信號係 是否必須於較短之水平熄滅期間內進行時，在該較短之水 平熄滅期間內，雜訊抑制之時間不足，不能完全去除。 若感光二極體1中有信號，而在箝位垂直信號線8時 連接於垂直信號線8之電容器，亦即箝位電容器1 3 1之 電容量C CI_之大小與感光二極體1中無信號，樣品保持時 連接於垂直信號線8之電容器之電容量C (但C = CCL CSH/ ( CCL+ CSH))互不相同時’即發生不能消除雜 訊之問題。本發明中，於樣品保持期間內修正電容器 2 0 1連接於垂直信號線8，連接於該垂直信號線8之電 容器之電容置配合樣品保持期間外之電容量值。 本發明中，開關2 0 2在樣品保持期間內成爲導通而 進行以上動作。如此，在樣品保持時連接於垂直信號線8 之電容器之電容量變成C = C CMP + C SH Therefore, the value of c CMP for the correction of «container 2 0 1 is set within the range of 2 {C c L — C c L * Csh / (CcL + CsH)} > CcmP> Ο. With this setting, the capacitance connected to the vertical signal line 8 when the sample is held is compared with the value without the correction capacitor 2 001, which is close to the capacitance value C η of the clamp capacitor 1 3 1. Therefore, the difference V ^ becomes 1 smaller, so the noise also becomes smaller. The operation will be described below. Section 54 is the timing chart of the operation of the device. In this embodiment, the correction capacitor 201 (201-1'201-2 printed by the Central Sample Bureau of the Ministry of Economic Affairs, male industrial consumer cooperative, 2 0 1 — 3) is located more toward the imaging field side than the clamping capacitor, and The switch 202 (202-1, 202-2, 202-3) is connected in parallel to the vertical signal line 8. In Fig. 52, the correction capacitor 201 and the switch 202 are provided between the clamp capacitor 1 31 and the imaging area. In Figure 5 3, it is located between the imaging field and the load transistor 9 '. During the sample holding period, the switch 202 is turned on. Suppose that an application is made such that the level of the horizontal address line 6-1 becomes the address pulse 101 of the high level. At this time, only the vertical selection transistor 3 of the line is turned on. This paper scale is applicable to the Chinese National Standard (CNS> A4 specification (210X297mm) ~~~ Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 _ V. Description of invention (93) Then, the load transistor drive line 3 The level of 5 becomes the high level ', the source follower circuit is formed by the amplified transistor 2 of the selected line and the load transistor 8. At this time, the gate voltage of the amplified transistor 2 appears on the vertical signal line 8, That is, the voltage is almost the same as the voltage of the photodiode 1. At this time, the clamp pulse 1 0 2 is applied to the gate electrode of the clamp transistor 1 3 2 to turn on the clamp transistor 1 3 3 and turn the clamp The voltage of the bit node 1 4 5 is fixed at the same voltage as the voltage of the clamp power supply 17. Then, after the clamp transistor 1 3 2 is turned off, the level of the load transistor drive line 3 5 becomes a low level. Then, a reset pulse wave 1 0 3 ′ fe reset transistor 4 that makes the level of the reset line 7 -1 a high level is applied to reset the signal charge. Then, the load transistor drive line 3 5 The level becomes the high level, then there will be a signal on the photosensitive diode 1 on the clamping section 1 4 5 The voltage difference between the charge and the signal charge is reset by 1. The voltage of the sample holding transistor 1 3 3 is then applied to the gate of the sample holding transistor 1 3 3 to make the sample holding transistor 1 3 3 conduct. This signal is sent to the sample holding capacitor 134. Then, the horizontal selection pulse wave 105 (105-1, 105-2, 105-3) is applied to the horizontal selection transistor 12 in order from the horizontal address circuit 14 The signal lines 1 and 5 take out signals corresponding to 1 line in sequence. On the next line, the next line performs this action in sequence, so that all the signals of the second element can be read out. In this device, the clamping section is finally 1 4 5 There is a voltage difference between when there is a signal and when it is reset without a signal, so it is possible to suppress the use of the China National Falcon (CNS) A4 specification (210X297 mm) due to the enlargement of the original paper size of the transistor 2- -------- ^ ------ 1T ------ Λ ff (Please read the precautions on the back before filling this page) Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Printed A7 __ B7 5. Description of the invention (94) Noise caused by uneven threshold. That is, the clamp capacitor 1 3 1, box The circuit formed by the transistor 1 3 2, the sample holding transistor 133, and the sample holding capacitor 1 3 4 becomes a noise removal circuit, suppressing the occurrence of fixed pattern noise of the second-order noise. That is, in > When the noise component is output, the impedance of the noise cancellation circuit observed from the unit cell becomes approximately the same as when the signal component + noise component ^ is output. Therefore, the noise component becomes approximately Same as above, calculate the difference between the two, you can correctly remove the noise output and you can only take out the signal components. Therefore, the noise can be correctly eliminated. According to the structure of the 24th embodiment, even if there are no components such as the correction container 20 1 and the switch 2 0 2, as long as it is a circuit that can ensure the time width of the clamping pulse to be more than 200 (ns), that is Has sufficient noise removal capability. That is, in the noise removal circuit, the signal charge stored in the sample holding capacitor is determined by the size of the sample holding capacitor and the voltage difference between the electrodes. The voltage difference between the electrodes is determined by the ratio of the capacitance value C SH of the sample holding capacitor 1 3 4 and the capacitance setting value C of the clamping capacitor 1 3 1》 Therefore, in order to increase the signal charge appearing in the sample holding capacitor, The capacitance of the sample holding capacitor must be increased, and the capacitance of the clamping capacitor should be increased accordingly. As a result, in order to generate sufficient signal charge, a considerable capacitance of the clamping capacitor is required. However, there is no problem if the clamp pulse can ensure a sufficient pulse width. The amplifying transistor 2 of the unit cell not only needs to drive the capacitor of the vertical signal line 8, but also must drive the clamping capacitor. If it can ensure the suppression of noise, the paper standard is applicable to China National Standard (CNS) Α4 specification (210 X 297 mm) -------------- 1T ------, Λ. t ί (please read the precautions on the back before filling in this page) -97-A7 B7 printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention description (95) The time required is no problem. However, if the MO S type solid-state imaging device is used as a TV camera, it becomes a problem. * In fact, whether the supply of the TV signal system must be performed within a short horizontal extinction period. The noise suppression time is insufficient and cannot be completely removed. If there is a signal in the photodiode 1, and the capacitor connected to the vertical signal line 8 when the vertical signal line 8 is clamped, that is, the capacitance C CI_ of the clamp capacitor 1 3 1 and the photodiode 1 There is no signal in the middle. When the sample is held, the capacitance C of the capacitor connected to the vertical signal line 8 (but C = CCL CSH / (CCL + CSH)) is different from each other. In the present invention, the correction capacitor 201 is connected to the vertical signal line 8 during the sample holding period, and the capacitance of the capacitor connected to the vertical signal line 8 matches the capacitance value outside the sample holding period. In the present invention, the switch 202 is turned on during the sample holding period to perform the above operation. In this way, the capacitance of the capacitor connected to the vertical signal line 8 becomes when the sample is held

C = CcMP+ CsH 若將修正電容器c CMP之電容量在 2 { C C L _ C c L * Csh/ ( CcL + CsH)}〉CcMF»〉Ο 之範圍內設定時·，與無修正電容器2 Ο 1時比較’連接於 樣品保持期間內之垂直信號線8之電容器之電容量（樣品 本紙張尺度逋用中國國家標準（CNS ) A4規格（210 X 297公釐） I 裝 訂 II 旅 ί ί (請先閱讀背面之注意事項再^寫本頁) -98 - 經濟部中央梯準局員工消費合作社印«. A7 B7 五、發明説明（96) 保持電容置1 3 4與箝位電容器1 3 1 )接近連接於樣品 保持期間外之垂直信號線8之電容器之電容量，亦即只有 箝位電容器1 3 1之電容量（=電容量Cct)之狀態時之 電容置值C ^之大小。因此’其差值V “變成更小，故雜 訊亦變小。 第5 5圖表示垂直信號線電位與箝位節電位之時間變 化。本實施例中，例如當信號爲^零#而成爲暗時，若在 箝位時垂直信號線電位復原之電位與在樣品保持時復原之 電位相同，則在樣品保持終了時刻之箝位節之電位不會復 原至接近△ V 之數值而成爲、零〃。因>此#，不會發生雖 然是在暗時而且信號爲'零'時，但仍出現相當於 △ V ^之信號等問題。因此可防止因av cc之不均勻而發 生之雜訊。 ’ 若無修正電容器201及開關202等構件時，感光 二極體1中有信號，而在箝位垂直信號線8時連接於垂直 信號線8之電容器，亦即箝位電容器1 3 1之電容量值 C ^之大小與感光二極體中無信號，在樣品保持時連接於 垂直信號線8之大容器之電容量C (但C = Ccl_· C SH/ (C % + C SH )之大小變成互不相同時，則發生不能消除 雜訊之狀況。以下說明此狀況。 爲了觀察雜訊最顯著之攝像條件之低照度狀態下之動 作，若信號爲0時，亦即感光電晶體復置前與復置後之感 光電晶體電位相同時，第5 6圖中表示垂直信號線電位與 箝位節電位之時間變化》 _ ^紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) I Is I -- - - - -I - -- l> i - -I- is- ί - - - - i -:-- 1^1 ζ (請先閲讀背面之注意事項再填寫本頁) -99 - 經濟部中央標準局属工消費合作社印製 A7 __B7___ 五、發明説明（97) 如圖中所示，信號電壓出現於垂直信號線8後，使箝 位電晶體1 3 2導通後之垂直信號線電位成爲在箝位之同 時立即成爲箝位電位，然後再復原成信號線電位。不能立 即成爲信號線電位之理由爲，電位根據負載電晶體9之電 阻值R ^與箝位電容器量C 之稹r = R TR · C η所決定 之時間常數變化。實事上元件之數值中，R TR大約爲1 Ο (Κ Ω ) ，C CL大約爲1 (PF) ，zr成爲大約10 (η s )，成爲充分飽和必須要200 (ns)。 第5 4圖所示之動作必須在1個水平熄滅期間內完成 ，故箝位脈波大多不能成爲200 (ns、上。因此， 實際上，元件中，於箝位時垂直信號線電位未充分飽和至 信號電位之狀態下，箝位電晶體成爲斷路。因此，箝位節 之電位在箝位電晶體成爲斷路後不能成爲箝位電位，只偏 '差△ V CL。 第5 6圖表示樣品保持時之箝位節之電位與垂直信號 線電位之時間變化。此時，連接於垂直信號線之電容量爲 箝位電容量與樣品保持電容量之串聯合成電容量，其電容 量值爲 C = C SH 9 CCL// CSH + C〇l) 此時之延遲時間常數/爲 ί Ζ" — R T R * C = R τ R * C s Η " Ccl/Csh+CcL) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐了_ 100 - 一 ----------丨裝------訂-----7"線 一 ί (請先閲讀背面之注意事項再填寫本頁) 經濟部中央樣準局員工消費合作杜印製 A7 __B7 五、發明説明（98 ) 此數值與箝位時之延遲時間常數r比較非常小。因此，在 樣品保持時，垂直信號線之電位復原成原來電位所需之時 間較箝位時之時間快。 因此，即使例如信號爲0而成爲暗時，垂直信號線電 位復原成箝位時之電位與在樣品保持時復原之電位相同， 在樣品保持終了時刻之箝位節之電位不能成爲0而復原至 接近△ V ct之數值。亦即，雖然爲暗時而信號爲0，仍出 現相當於△ V 之信號，而且該△ V Clj不均勻，因而成爲 在雜訊電路中不能去除之雜訊留下。 1 1 本實施例中，在樣品保持期間內，開關2 0 2成爲導 通狀態》如此，在樣品保持時連接於垂直信號線之電容量 成爲C = CcMP + CsH If the capacitance of the correction capacitor c CMP is set within the range of 2 {CCL _ C c L * Csh / (CcL + CsH)}> CcMF »> Ο, and the uncorrected capacitor 2 Ο 1 Compare 'Capacitance of the capacitor connected to the vertical signal line 8 during the sample holding period (the sample paper size uses the Chinese National Standard (CNS) A4 specification (210 X 297 mm) I binding II travel ί ί (please read first (Notes on the back ^ write this page) -98-Printed by the Employee Consumer Cooperative of the Central Escalation Bureau of the Ministry of Economic Affairs «A7 B7 V. Description of Invention (96) The holding capacitor is set 1 3 4 and the clamping capacitor 1 3 1) The capacitance of the capacitor of the vertical signal line 8 outside the sample holding period, that is, the value of the capacitance setting C ^ when only the capacitance (= capacitance Cct) of the clamping capacitor 1 3 1 is in the state. Therefore, the difference V becomes smaller, so the noise also becomes smaller. Figure 55 shows the time change of the potential of the vertical signal line and the potential of the clamping node. In this embodiment, for example, when the signal is ^ zero # When it is dark, if the potential of the vertical signal line during clamping is the same as the potential restored when the sample is held, the potential of the clamping node at the end of the sample holding will not restore to a value close to △ V and become, zero 〃 Because of this>, there will be no problems such as a signal equivalent to △ V ^ even when it is in the dark and the signal is 'zero'. Therefore, it is possible to prevent the occurrence of impurities due to the unevenness of av cc If there is no correction capacitor 201 and switch 202, there is a signal in the photodiode 1, and the capacitor connected to the vertical signal line 8 when the vertical signal line 8 is clamped, that is, the clamping capacitor 1 3 1 The size of the capacitance value C ^ has no signal in the photosensitive diode, and the capacitance C of the large container connected to the vertical signal line 8 when the sample is held (but C = Ccl_ · C SH / (C% + C SH) When the size becomes different from each other, the situation that the noise cannot be eliminated occurs The following describes this situation. In order to observe the operation in the low-illumination state where the noise is the most significant in the recording conditions, if the signal is 0, that is, the potential of the photosensitive transistor before resetting and after resetting is the same, the fifth Figure 6 shows the time variation of the potential of the vertical signal line and the potential of the clamping node "_ ^ The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) I Is I-----I--l > i--I- is- ί----i-:-1 ^ 1 ζ (please read the precautions on the back before filling this page) -99-A7 printed by the Industrial and Consumer Cooperative Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs __B7___ V. Description of the invention (97) As shown in the figure, after the signal voltage appears on the vertical signal line 8, the potential of the vertical signal line after the clamping transistor 1 3 2 is turned on becomes the clamping potential immediately at the time of clamping. Then restore to the signal line potential. The reason why the signal line potential cannot be immediately obtained is that the potential changes according to the time constant determined by the resistance value R ^ of the load transistor 9 and the clamp capacitor quantity C = R TR · C η In the actual value of the component, R TR is about 1 Ο (Κ Ω) , C CL is approximately 1 (PF), zr becomes approximately 10 (η s), and 200 (ns) is necessary for full saturation. The operation shown in Figure 5 4 must be completed within one horizontal extinction period, so clamp Most of the pulse wave cannot be 200 (ns, up. Therefore, in fact, in the device, the clamping transistor becomes disconnected when the vertical signal line potential is not sufficiently saturated to the signal potential during clamping. Therefore, the clamping node The potential cannot become the clamping potential after the clamping transistor becomes open circuit, only the deviation is ΔV CL. Figure 56 shows the time variation of the potential of the clamping node and the potential of the vertical signal line when the sample is held. At this time, the capacitance connected to the vertical signal line is the series combined capacitance of the clamping capacitance and the sample holding capacitance, and its capacitance value is C = C SH 9 CCL // CSH + C〇l) The delay at this time Time constant / is — RTR * C = R τ R * C s Η " Ccl / Csh + CcL) This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm_100-one- -------- 丨 installation ------ order ----- 7 " line one (please read the precautions on the back before filling in this page) Employee consumption cooperation Printed A7 __B7 5. Description of the invention (98) This value is very small compared with the delay time constant r during clamping. Therefore, when the sample is held, the time required for the potential of the vertical signal line to return to the original potential is shorter than when clamping Therefore, even when, for example, the signal is 0 and becomes dark, the potential of the vertical signal line is restored to the same potential as that of the clamp when the sample is held, and the potential of the clamp node at the end of the sample cannot be 0 to restore to a value close to △ V ct. That is, although it is dark and the signal is 0, A signal equivalent to △ V appears, and the △ V Clj is not uniform, so it becomes the noise that cannot be removed in the noise circuit. 1 1 In this embodiment, during the sample holding period, the switch 202 becomes conductive "State" As such, when the sample is held, the capacitance connected to the vertical signal line becomes

C = C CMP+ C SH 若將修正電容器c CMP之電容置在 2 { CCL— C〇L* C S Η / ( CcL+ CsH) }〉CcMP〉0 之範圍內設定時，與無修正電容器時比較，接近cCI^之數 值。因此，差值v 變成更小，故雜訊亦變成更小。 第5 5圖表示垂直信號線電位與箝位節電位之時間變 ί匕。本實施例中，若例如信號爲〇而成爲暗時’垂直信號 線電位復原至箝位時之電位與復原至樣品保持時之電位相 同時，在樣品保持終了時之箝位節之電位不會復原成接近 ---------^ d------IT------^ Λ. (请先閱讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家標準（CNS ) A4規格（2丨Ο X 297公釐） 101 - 經濟部中央樣準局貝工消费合作社印製 A7 ___B7_ 五、發明説明（99 ) △ V π之數值但成爲0。因此不會發生雖然成爲暗時而信 號爲0 ，但出現相當於Δν ct之信號之問題。因此，可防 止因△ V π之偏差而發生雜訊。 以上爲每單位晶胞中，將1個感光二極體結構之 MO S偵測器與各種雜訊消除電路組合之結構之MO S型 固體攝像裝置之實施例。 以下說明每單位晶胞中，將2個感光二極以上之許多 感光二極體結構之MO S偵測器與各種雜訊消除電路組合 之結構之MO S型固體攝像裝置之實施例。 第2 5實施例 第2 5實施例爲每單位晶胞中，將2個感光二極體結 構之Μ 0 S偵測器與各種雜訊消除電路組合而成之結構例 〇 第5 7圖爲第2 5實施例之MO S型固體攝像裝置之 結構之概略圖。圖中，將相當於圖素之單位晶胞Ρ 1 _ i 一 j在縱向及橫向排列成二次元矩陣狀。圖中只表示2 X 2個之結構，但實際上爲例如縱橫方向數千個x數千個之 結構。i爲水平（row)方向之變數，j爲垂直（column )方向之變數。本發明中，各單位晶胞P 1 一 i _ j具有 2個做爲受光部之感光二極體，而非1個。因爲具有2個 感光二極體，故各單位晶胞實質上成爲2個圖素動作。第 6 1 ，6 2圖表示各單位晶胞p 1 一 1 _ j之詳細結構。 以上說明之固體攝像裝置之應用領域爲視頻攝像機’ 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐）_ 1〇2 _ ---------扣衣------，玎------0 (請先閱讀背面之注意事項一 .--7,寫本頁) 一 經濟部中央樣準局只工消費合作社印製 A7 ___B7 ___ 五、發明説明（10°) 電子靜止攝像機，數位攝像機，電話傳真，複印機，掃描 機等。 從垂直（column)位址電路5朝向水平方向（row) 配線之水平（row)位址線6 — 1 ，6 — 2 .........連接於各 行之單位晶胞而決定讀出信號之水平線（row方向線）· 同樣的，從垂直位址電路5朝向水平方向（roff方向）配 線之復置線7 — 1，7 — 2..........連接於各列之單位晶 胞*如後文中所述，因爲本資施例之單位晶胞含有2個感 光二極體，故從垂直位址電路5又有第1感光二極體選擇 線22 — 1，22 — 2 ..........，第2感光二極體選擇線 24 — 1 ，24 — 2 .........朝向水平方向输出，各選擇 線亦連接於各行之單位晶胞。 各列之單位晶胞連接於朝向方向配置之垂直（ column)信號線8 - 1 ，8 — 2..........，而在垂直信號 線8 — 1 ，8 — 2 ..........之一端設有負載電晶體9 一 1 ，9 — 2...........負載電晶體9 — 1 ，9 — 2.......... 之閘極與吸極共同的連接於吸極電壓端子2 0。 垂直信號線8 - 1，8 - 2..........之另一端連接於 雜訊消除電路。亦即，本發明中使用之雜訊消除電路係由 MOS 電晶體 26 — 1 ，26 — 2 ..........28 — 1 ， 2 8-2 ...........樣品保持電晶體30 — 1 ，30 — 2' ...........箝位電容器3 2 — 2，3 2 — 2..........樣品 保持電容器34—1 ，34 — 2..........箝位電晶體40 —1 ，4 0 — 2 ..........水平（row)選擇電晶體1 2 — 本紙張尺度適用中國國家榡準（CNS)A4规格（2丨0X297公釐）-103 - ---------^------IT------^ (請先閲讀背面之注意事1^寫本頁) 一 經濟部中央標準局貝工消费合作社印製 306073 at __B7_ 五、發明説明（101) 1，1 2 - 1 ..........所構成。 垂直信號線8 — 1 ，8-2..........之另一端連接於 雜訊消除電路之構成要素之MOS電晶體26 — 1 ，26C = C CMP + C SH If the capacitance of the correction capacitor c CMP is set within the range of 2 {CCL— C〇L * CS Η / (CcL + CsH)}> CcMP> 0, it is close to that without the correction capacitor The value of cCI ^. Therefore, the difference v becomes smaller, so the noise also becomes smaller. Figure 55 shows the time variation of the vertical signal line potential and the clamp node potential. In this embodiment, if, for example, the signal is 0 and becomes dark, the potential of the vertical signal line when it is restored to the clamp is the same as the potential when it is restored to the sample hold, the potential of the clamp node at the end of the sample hold Restored to be close to --------- ^ d ------ IT ------ ^ Λ. (Please read the precautions on the back before filling out this page) This paper uses the country of China Standard (CNS) A4 specification (2 丨 X 297 mm) 101-A7 ___B7_ printed by the Beigong Consumer Cooperative of the Central Bureau of Samples of the Ministry of Economic Affairs V. Invention description (99) The value of △ V π is 0 Therefore, although the signal becomes 0 when it becomes dark, the signal equivalent to Δν ct does not occur. Therefore, the occurrence of noise due to the deviation of Δ V π can be prevented. The above is an embodiment of a MOS type solid-state imaging device in which a MOS detector with a photosensitive diode structure and various noise cancellation circuits is combined per unit cell. The following describes an embodiment of a MOS solid-state imaging device in which a MOS detector with a plurality of photosensitive diodes of more than two photosensitive diodes and various noise cancellation circuits is combined per unit cell. The 25th embodiment The 25th embodiment is a structure example in which 2 MOS detectors with two photosensitive diode structures and various noise canceling circuits are combined per unit cell. A schematic diagram of the structure of the MOS solid-state imaging device according to the 25th embodiment. In the figure, the unit cells P 1 — i — j corresponding to the pixels are arranged in the form of a quadratic matrix in the longitudinal and lateral directions. The figure shows only 2 X 2 structures, but in reality, for example, a structure of thousands x thousands in the vertical and horizontal directions. i is a variable in the horizontal direction and j is a variable in the vertical direction. In the present invention, each unit cell P 1-i _ j has two photosensitive diodes as light-receiving parts instead of one. Since there are two photosensitive diodes, each unit cell becomes essentially two pixel operations. Figures 6 1 and 6 2 show the detailed structure of each unit cell p 1-1 _ j. The application field of the solid-state camera device described above is a video camera. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) _ 1〇2 _ --------- Clothing --- --- ， 玎 ------ 0 (please read the notes 1 on the back first. --7, write this page) A7 ___B7 ___ printed by the Central Sample Bureau of the Ministry of Economic Affairs Printed by the only consumer cooperative (10 °) Electronic still camera, digital camera, telephone fax, copier, scanner, etc. From the vertical (column) address circuit 5 toward the horizontal direction (row), the horizontal (row) address lines 6-1, 6-2 ... connected to the unit cell of each row determine the read The horizontal line of the output signal (row direction line) · Similarly, the reset line 7-1, 7-2 .... connected from the vertical address circuit 5 to the horizontal direction (roff direction) is connected to The unit cell of each column * is described later, because the unit cell of this embodiment contains two photosensitive diodes, so there is a first photosensitive diode selection line 22-1 from the vertical address circuit 5. , 22-2 ........., the second photosensitive diode selection line 24-1, 24-2 ......... output toward the horizontal direction, each selection line is also connected to Unit cells of each row. The unit cells of each column are connected to the vertical signal lines 8-1, 8-2.... Arranged in the direction, and the vertical signal lines 8-1, 8-2 .. ........ One end is equipped with load transistors 9-1, 9, 2-2 .......... Load transistors 9-1, 9-2 ....... The gate electrode and the sink electrode are connected to the sink voltage terminal 20 in common. The other end of the vertical signal lines 8-1, 8-2 .... is connected to the noise cancellation circuit. That is, the noise cancellation circuit used in the present invention is composed of MOS transistors 26-1, 26-2 ......... 28-1, 2 8-2 ... ... Sample holding transistor 30 — 1, 30 — 2 ′ ........... Clamping capacitor 3 2 — 2, 3 2 — 2 .......... Sample holding Capacitors 34-1, 34-2 ......... Clamping transistors 40-1, 4 0-2 ..... Row selection transistors 1 2— This paper scale is applicable to China National Standard (CNS) A4 (2 丨 0X297mm) -103---------- ^ ------ IT ------ ^ (please first Read the notes on the back 1 ^ write this page) 1. Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy 306073 at __B7_ V. Description of the invention (101) 1, 1 2-1 ..... Pose. The other end of the vertical signal line 8-1, 8-2 ... is connected to the MOS transistor 26-1, 26, which is a constituent element of the noise cancellation circuit

-2 ..........之閘極。雜訊消除電路之構成要素之MO S-2 The gate of .......... MO S of the components of the noise cancellation circuit

電晶體2 6 - 1 ，2 6 — 2 .........之源極連接於MO S 電晶體2 8 — 1 ，2 8 - 2 ..........之吸極，MO S電晶 體 26 — 1，26 — 2...........28 — 1，28 — 2， .........成爲源極跟隨電路動作。MO S電晶體2 8 — 1 ， 28 — 2 .........之閘極連接於共同閘極端子36。Transistor 2 6-1, 2 6-2 ......... The source is connected to MO S transistor 2 8-1, 2 8-2 .... Pole, MOS transistor 26 — 1, 26 — 2 .......... 28 — 1, 28 — 2, ......... becomes the source follow circuit action. The gates of the MOS transistors 2 8 — 1, 28 — 2 ......... are connected to the common gate terminal 36.

MO S 電晶體 2 6 — 1 ，2 6 - 2..........與MO S 電晶體28 - 1 ，28 - 2..........之連接點經由同樣爲 雜訊消除電路之構成要素之樣品保持電晶體3 0 — 1 ， 3 0-2 ..........連接於箝位電容器32-1，32 — 2 ..........之一端。在雜訊消除電路之構成要素之箝位電容 器3 2 — 1 ，3 2 - 2..........之一端並聯樣品保持電容 器34-1 ，34-2..........與箝位電晶體40-1 ， 4 0-2。 雜訊消除電路之構成要素之樣品保持電容器3 4 — 1 * 3 4 — 2 ..........之另一端接地。箱位電容器3 2 — 1 •32-2 ..........之另一端經由水平選擇電晶體1 2 — 1*12-2·.........連接於信號输出端（水平信號線）- 1 5 β 水平（row)選擇電晶體1 2 _ 1 ，1 2 — 2 ....... …經由從依次切換水平（row)位址之電路，亦即選擇水平 ---------^------,訂------^ (請先閱讀背面之注意事項一 \寫本頁) * 本紙張尺度適用中國國家橾準（CNS)A4规格（ 210X297公釐）-1〇4 - 五、發明説明（l〇2) 位址電路 A7 B7 供給之水平位址脈波所選擇之水平（row) 選擇電晶體1 2 _ 1 2-2 V · · « · · « · · · 連接於信號输出 端（水平信號線）1 5。 垂直位址電路5係將許多條線之信號，本例中爲4條 線之信號整理而移位之電路。亦即垂直位址電路5具有4 條X η組之端子，依次切換4條一組之端子群，使其每次 —組的成爲主動。此動作係由第58，59或60圖中之 任一電路實現 請 先 閱 讀 背 * 事 項 經濟部中央標準局貝工消費合作社印装 第5 位輸入信 入信號5 第5 入之解碼 第6 移位電晶 中，在同 第6 結構例。 他單位晶 8圇之 號4 6 0合成 9圖之 器5 2 0圖之 體6 0 —端子 例中，多工器4 8將從許多输出端依次移 而输出之移位暫存器4 4之輸出與4個输 〇 例中，多工器5 6將解碼編碼器5 4之輸 之輸出與4個输入信號5 8合成。 資施例中，使用分別具有許多端子之4個 a ，60b，60c，60d，將其輸出 位置之輸出整合做爲各行之控制信號線。 第5 7 圖所示單位晶胞P 1 _ 1 — 1之一 表示單位晶胞P 1 — 1 — 1之結構，但其 1圖爲 在此只 胞P1 — 1 — 2，〜亦採用相同之結構 如圖中所示，本實施例之MO S型固髖攝像裝置之單 位晶胞包括：在垂直方向（column)鄰接之2個感光二極 體62a，62b :選擇其中之任一感光二極體62a ， 6 2 b之檢測信號做爲單位晶胞之输出之2個感光二極體 選擇電晶體6 3 a ，6 3 b ;及從單位晶胞中输出由各選 本紙張尺度逋用中國國家揉準（CNS)A4规格（ 210X297公釐）_ 1〇5 - i 裝 訂 經濟部中央標準局貝工消費合作杜印«. A7 B7__ 五、發明説明（1〇3) 擇電晶體63a ，63b選擇之感光二極體62a ， 6 2 b之輸出信號之輸出電路6 8。 各選擇開關63a ，63b成爲獨立的通斷。將各選 擇開關接通，即可將儲存於感光二極體6 2 a，6 2 b之 電荷以時間分割方式供給於输出電路6 8。 输出電路6 8係由以下之構件所構成·亦即由在閘極 接受從感光二極體6 2 a，6 2 b供給之電荷信號並將之 放大之放大電晶體6 4，選擇讀出信號之單位晶胞之垂直 選擇電晶體6 5，及將施加於放大電晶體6 4之閘極之電 荷充放電之復置電晶體6 6所構成。 從垂直位址電路5朝向水平方向（row方向）配線之 水平位址線6 — 1連接於垂直（column)選擇電晶體6 5 之閘極而選擇讀出信號之線。同樣的，從垂直位址電路5 朝向水平方向配線之復置線7—1 ，感光二極體選擇線 22 — 1 ，24 — 1分別連接於復置電晶體66之閘極， 感光二極體選擇電晶體63a ，63b之閘極。 如此，本實施例之MO S型固體攝像裝置之單位晶胞 與習用之1個感光二極體/單位晶胞之結構不同，具有許 多感光二極體/單位晶胞之結構。在此，具有在垂直方向 (column)鄰接之2個感光二極體共有1個输出電路6 8 之結構。亦即1個感光二極體/單位晶胞之結構時，每單' 位晶胞相當於1個圖素，但許多感光二極體/單位晶胞之 結構時，具有許多做爲受光部之感光二極體，故受光部之 數量可分別做爲圖素，因此，每一單位晶胞成爲許多圖素 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐）_ 1〇6 ---------1------1T------線 (請先閲讀背面之注意事項一 寫本頁) ( 經濟部中央標準局員工消费合作社印製 A7 __B7 五、發明説明（104) 之結構。 本賁施例中，單位晶胞係由2個感光二極體所構成， 在每單位晶胞內具有包含用來選擇各感光二極體之2個電 晶體在內總共5個電晶體。亦即，依照本實施例之MO S 型固體攝像裝置之單位晶胞之結構，相當於1個圖素之每 1個感光二極體只需要2·5個電晶體。因此，與1個感 光二極體需要3個電晶體之第1圖所示習用之結構比較， 每一圖素之電晶體數量爲2·5個之本實施例每一圖索可 減少電晶體數量0 · 5個*因此，可縮小每一個圖素之佔 有面稹，若爲同一圖素數置之固體攝像裝置*則可製作更 小型化之固體攝像裝置* 本實施例之MO S型固體攝像裝置之單位晶胞之特徵 爲2個感光二極體6 2 a ，6 2b經由選擇電晶體6 3 a ，6 3 b分別連接於輸出電路6 8。亦即感光二極體 62a ，62b並聯。當然，以許多感光二極體62共用 —個輸出電路6 8之方法除了上述方法之外，又有其他方 •例如只將1個感光二極體連接於輸出電路6 8，其他感 光二極體係經由連接於輸出電路6 8之上述1個感光二極 體連接於输出電路6 8 |亦即利用串聯連接之方法》然而 ，利用串聯連接之方法不容易在不破壞儲存於其他感光二 極體之檢測信號之條件下，獨立的讀出許多感光二極體之' 各輸出信號。因此，最好使用實施例所示之結構。 通常，在放大型MO S型固體攝像裝置中，係將相當 於各單位晶中之圚素之受光部，亦即感光二極體之輸出信 t ( CNS ) Λ4^ ( 2.0X297^ ) _ 1〇? _ ----------^------ίτ------0 (請先閱讀背面之注意事項^,.寫本頁) ~ A7 B7 306073 五、發明説明（1〇5) 請 先 閱 讀 背 之 注 意 事 項 號經由設在該單位晶胞中之放大電晶體6 4放大而取出。 因此•在放大時，放大電晶體6 5之閾值電壓之不均勻重 疊於信號上。因此，即使各單位晶胞中之感光二極體6 2 之電位分別爲相同，因爲該感光二極體所靥之單位晶胞之 放大電晶體爲分開，而各放大電晶體6 4之閾值電壓不相 同，故輸出信號不成爲相同，若再生攝像之畫像，即產生 對應於放大電晶體6 4之閾值不均勻之雜訊。 訂 如上所述，各單位晶胞之放大電晶體6 4之閾值電壓 不相同，在各單位晶胞中有固有之電壓，故成爲在位置上 固定於再生之畫像而分佈之雜訊，亦即二次元狀雜訊。因 爲該雜訊在二次元空間之畫面上其位置爲固定，故被稱爲 固定圖型雜訊。在上述說明中已敘述· 線 經濟部中央樣準局貝工消費合作社中製 因此，本實施例中，設置抑制固定圖型雜訊之雜訊去 除電路，以取代習用之第1圖之電路圖所示之由输出部之 信號傳送電晶體與儲存電容器所構成之電路。第5 7圖中 之雜訊去除電路係在電壓領域計算信號與雜訊之差值之相 關雙重抽樣型電路。但雜訊去除《路之型式不限定於相關 雙重抽樣型，亦可使用其他各種雜訊去除電路· 以下參照第6 2圖之時序圔表說明具有上述雜訊消除 電路之本發明中所使用之MO S型固體攝像裝置之動作。 因爲負載電晶體9之共同吸極端子2 0，阻抗變換電路之' 電晶體2 8之共同閘極端子3 6，箝位電晶體之共同源極 端子3 8係由D C驅動，故在該時序圖表中不表示。 亦即，構成阻抗變換電路之電晶體2 8 - 1 ，·2 8 — 本紙張尺度遑用中國國家標準（CNS〉A4規格（ 210X297公釐）_ 1〇8 _ 經濟部中央橾準局男工消費合作社印製 A7 _B7__ 五、發明説明（l〇6) 2，.........之共同閘極端子3 6之電壓在該MO S型固體 攝像裝置動作時係成爲高位準狀態，經常成爲導通。箝位 電晶體4 0 — 1 ，4 0 — 2..........之共同源極端子3 8 之電壓在該MO S型固體攝像裝置動作時係經常成爲低電 位。因爲共同源極端子3 6之電位成爲高位準，故阻抗變 換電路之電晶體2 8 — 1 ，2 8 — 2..........經常成爲導 通’與垂直信號線8 - 1 ，8 - 2..........所傳送之信號 位準（電壓位準）成爲對應的驅動電晶體26 — 1 ’ 26 —2...........故與垂直信號線8 - 1 ，8 — 2 .......... 從電晶體26 — 1 ，26 - 2 ..........及電晶體28-1 ，2 8 — 2..........之電路傳送之信號位準成爲對應的輸 出電壓信號。如圖中所示電晶體26 — 1 ，26 — 2，… ......及電晶體2 8 _ 1 ，2 8 — 2 ..........中分別成爲對 應之成對之電晶體將其源極與吸極串聯而連接於系統電源 之正極側（一定位準之直流電壓）及接地位準側，若電晶 體28-1 ，28 — 2..........導通時，與垂直信號線8 -1*8-2 ..........所傅送之信號位準成爲對應的驅動 電晶體26-1 ，26-2 .........而可在一定位準之直 流電壓範圍內輸出電壓。亦即以電晶體26 — 1 · 26 — 2..........及電晶體2 8 — 1 ，2 8 — 2..........變換阻 抗而將對應於垂直信號線8_1 ，8 — 2 ..........所傳送 之信號位準之電壓信號供給於雜訊消除電路。 從電晶體2 6 — 1 ，2 6 - 2 ..........及電晶體2 8 一 1 ，2 8 — 2..........所構成之阻抗變換電路產生之輸 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）-109 — (請先閱讀背面之注意事項一 %寫本頁) -裝 訂 A7 A7 經濟部中央標準局員工消费合作社印袈 ___B7_ 五、發明説明（107) 出經由對應於垂直信號線8 — 1 ，8 — 2..........設置之 樣品保持電晶體3 0 — 1 ，3 0 — 2 .........傳送至同樣 的對應於垂直信號線8 - 1，8 - 2 .........設置之箝位 電容器3 2 — 1 ，3 2 — 2..........。當樣品保持電晶體 30-1 * 30-2 ..........成爲導通時，從阻抗變換電 路產生之輸出被傳送至對應之箝位電容器3 2 - 1 ，3 2 —2 ..........而儲存在其中。若樣品保持電容器3 0 — 1 ，3 0 - 2..........成爲斷路時，則可停止傳送從垂直信 號線8 — 1 ，8 — 2 ..........產生之输出。 本裝置在攝像動作中，構成阻抗變換電路之電晶體 28-1*28-2«.........之共同閘極端子36之電壓 成爲高位準狀態，經常成爲導通狀態•箝位電晶體4 0 - 1 ，40 — 2 ..........之共同源極端子38之電壓經常成 爲低位準。 在此狀態下，在水平（row)位址線6 _ 1施加高位 準（邏輯信號位準)之位址脈波後，連接於該水平 位址線6 — 1之單位晶胞Ρ1 — 1 — 1 ，P1 — 1-2， .........之垂直選擇電晶體6 5成爲導通，而由放大電晶體 6 4及負載電晶體9 — 1，9 一 2..........構成源極跟隨 電路。 放大電晶體6 4之閘極上可施加感光二極體6 2 a 6 2 b中由選擇電晶體6 3 a ，6 3 b選擇之任一感光二 極體之電壓。放大電晶體6 4放大施加於該閘極之電壓而 將之供給於吸極，故以選擇電晶體6 3 a，6 3 b選擇感 本紙張尺度遑用中國國家橾準（CNS>A4規格（ 210X297公釐）_ HQ _ II I I I 裝 II I 訂 I I 線 (請先閲讀背面之注意事項*...舄本頁) 一 經濟部中央標準局爲工消费合作杜印装 A7 B7 五、發明説明（1〇8) 光二極體62a ，62b，即可從單位晶胞中，將本身所 具有之對應於感光二極體之受光量之電壓供給於垂直（ row)信號線8 — 1 ，8 - 2 ..........中，對應於該單位 晶胞之垂直（row)信號線。 雜訊消除電路中，使其構成要素之樣品保持電晶體 3 0 - 1 ，3 0 — 2 ..........之共同閘極3 7成爲高位準 而使樣品保持電晶體3 0 - 1 ，3 0 - 2 ..........成爲導 通。如此，垂直信號線8 - 1 ，8 — 2 ..........所產生之 輸出，嚴格言之，經由阻抗變換電路變換阻抗之垂直信號 線8 — 1 ，8-2 ..........之輸出被傳送至箝位電容器 3 2 — 1，3 2 - 2。 雜訊消除電路將其構成要素之箝位電晶體4 0 — 1 ， 4 0 — 2，.........之共同閘極4 2之電位以一定週期在一 定時間寬度內成爲高位準而使各箝位電晶體4 0 — 1 ， 4 0-2 ..........成爲導通。如此，該箝位電晶體4 0 — 1 ，4 0 _ 2 ..........使雜訊消除電路之構成要素之箝位 電容器3 2 - 1 ，3 2 _ 2..........與樣品保持電容器 34 — 1 * 34 — 2 ..........之連接點之電位在該一定時 間寬度之間成爲共同源極端子3 8之施加電壓位準之低位 準，樣品保持電容器34 - 1 ，34 - 2 ..........之電位 降低至該共同源極端子3 8之電壓位準。亦即樣品保持電' 容器3 4 — 1. ’ 3 4 - 2 ’ .........之一端接地而成爲接地 位準》在此狀態下，樣品保持電容器34 - 1 ，34 — 2 ..........之電荷成爲共同源極端子3 8之電壓位準之低位 ---------装------.玎------^ / (請先閱讀背面之注意事項广，>寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X 297公釐）-HI - 經濟部中央標準局員工消费合作社印策 A7 B7 五、發明説明（1〇9) 準，故樣品保持電容器3 4 — 1 ，3 4 — 2 ..........中之 儲存電荷被放電而成爲低位準之穩定狀態。該位準即爲復 置狀態下之位準。經過相當於該一定時間寬度之時間後， 復置狀態被解除。 然後，在復置線7_ 1上施加高位準之復置脈波後， 連接於該復置線7_1之單位晶胞P1 — 1 一 1，P1 — 1 — 2 ..........之復置電晶體6 6成爲導通。因爲復置電 晶體6 6係復置放大電晶體6 4之输入側電荷之電路，故 因該復置而將输出電路6 8之輸入端子之電荷復置。亦即 輸出電路6 8之输入變成零· 因此，輸出電路6 8只输出其構成要素之放大電晶體 6 4之輸出成分。在此狀態下，放大電晶體6 4之输出成 分爲對應於該放大電晶體6 4所具有之閾值不均勻之雜訊 成分。 如此，由於單位晶胞Pl-l-l ，P1-1 — 2 ， .........之復置，输出電路6 8產生感光二極體6 2中無信 號電荷時之放大電晶體6 4之輸出成分，亦即對應於該放 大電晶體6 4所具有之閾值不均勻之雜訊成分，爲輸出信 號。 然後，使雜訊消除電路之構成要索之箝位電晶體4 0 -1 >40-2 ..........之共同閘極4 2之電位成爲低位 準（邏輯信號位準)，使箝位電晶體40 — 1 ， 4 0-2-.........成爲斷路。因爲使該箝位電晶體40 — 1 > 40 — 2 ..........成爲斷路，故雜訊消除電路之構成 本紙張尺度遑用中國國家梂準（CNS)A4規格（ 210X297公釐）-112 - ---------^------ΐτ------^ ί·'' (請先閱讀背面之注意事項寫本頁) 經濟部中央橾準局貝工消費合作社印製 A7 ___B7_ 五、發明説明（110) 要素之箝位電容器3 2 — 1 ，3 2 — 2..........與樣品保 持電容器34 — 1 ，34 — 2..........之連接點與共同源 極端子分離，樣品保持電容器34 - 1 ，34 - 2 ....... …成爲可傳送垂直信號線8 - 1 ，8 - 2..........所產生 之输出之狀態。 因此，出現於垂直信號線8 - 1 ，8 - 2之雜訊成分 被儲存於由箝位電容器32-1 ，32 — 2..........與樣 品保持電容器3 4 — 1 ，3 4 — 2..........所構成之串聯 電容器中。箝位之時序係在箝位脈波截止之時，亦即在復 置脈波與P D選擇脈波之間。 如此完成雜訊成分之儲存後，進入讀出信號成分之步 驟。單位晶胞P1 — 1 — 1 ’P1 — 1 — 2 ’ .........中， 在復置後，於感光二極體62a ，62b內進行信號電荷 之儲存，然後將之讀出。讀出時，係於雜訊成分之儲存之 每一步驟時，先讀出感光二極體6 2 a ，然後在下一個雜 訊成分之儲存步驟終了後讀出感光二極體6 2 b，在下一 次雜訊成分之儲存步驟終了後讀出感光二極體6 2 a。如 此交替的進行。 在讀出儲存於感光二極體6 2 a之信號電荷時，於感 光二極體選擇線2 2 _ 1上施加高位準之選擇脈波。如此 ，從單位晶胞P 1 — 1 - 1 ，P 1 — 1 — 2 .........內之' 输出電路6 8中输出感光二極體6 2 a之输出信號（亦即 '信號電荷成分+雜訊成分*")，並由各單位晶胞P1 — 1一1 ，PI — 1 — 2..........內之放大電晶體64放大 本紙張尺度遑用中國囷家梂準（CNS)A4現格（ 210X297公釐）-113 - ---------批衣------1T------^ (請先閱讀背面之注意事Ϊ5...填寫本頁) 一 經濟部中央橾準局貝工消費合作社印製 A7 B7 五、發明説明（m) 而供給於對應於該單位晶胞之垂直信號線8 - 1 ，8 — 2 9 · · · · · · · · · 〇 如上所述，因爲在由箝位電容器32 — 1 ，32_2 ..........與樣品保持電容器3 4 — 1 ，3 4 — 2.......... 所構成之串聯電容器中已儲存雜訊成分，故在該串聯電容 器之連接點之箝位節41 — 1 ，41 — 2..........上只出 現垂直信號線8 _ 1，8 _ 2 ..........之電壓變化成分， 亦即從'信號成分+雜訊成分^減去 ''雜訊成分之信號 ，亦即無固定圖型雜訊之對應於感光二極體6 2 a之受光 量之檢測输出，即信號成分電壓* 如此，先讀出^雜訊成分'，然後，讀出 '信號成分 +雜訊成分# ，則可同時去除因復置動作而產生之隨意雜 訊。 然後，使樣品保持電晶體30 — 1，30 — 2，…… …之共同閘極3 7之電位成爲低位準。如此，各樣品保持 電晶體30 — 1，30 — 2..........成爲斷路，而因其斷 路而切斷從垂直信號線8-1 ，8 - 2 ..........供給於雜 訊消除電路之输出信號。 因此，由箝位電容器3 2 — 1 ，3 2 — 2 ..........與 樣品保持電容器3 4 — 1 ，34-2 ..........所構成之串 聯電容器所進行之抽樣終了，在由各箝位電容器3 2 - 1_ *32-2·.........與樣品保持電容器34 — 1 ，34 — 2 ..........所構成之串聯電容器中保持在此之前儲存之電 荷。因此，在樣品保持電容器3 4 — 1 ，3 4 — 2 ....... 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）-114 - t-- (請先閲讀背面之注意事1.填寫本頁) 訂 經濟部中央樣準局員工消费合作社印製 A7 B7 五、發明説明（l!2) …中儲存出現於箱位節4 1 — 1 ，4 1 — 2 ..........之無 雜訊之電壓，並予以保持。 然後，在水平選擇電晶體12 — 1 ，12 - 2 ....... …上依次施加水平位址脈波而從信號輸出端（水平信號線 )15中讀出儲存於樣品保持電容器34_1 ，34 — 2 ..........之無雜訊之感光二極體6 2 a (或6 2 b )之信 號。 如此，先只讀出^雜訊成分〃，然後，讀出 ''信號成 分+雜訊成分^而只產生各每位晶胞之圖素信號成分，而 該圖素信號成分經由以水平位址電路13依照電視掃描之 順序之讀出順序控制其通斷之電晶體12 — 1 ，12 — 2 ..........輸出於信號輸出端1 5，故可產生無固定圖型雜 訊之圖素信號。 如此完成感光二極體6 2 a之信號讀出。 感光二極體6 2 a之信號之讀出後，係感光二極體 6 2 b之信號之讀出。 首先，在垂直（column)位址線6 - 1上施加高位準 之位址脈波。此時，在感光二極體選擇線2 4 _ 1上，而 非在感光二極體選擇線2 2 - 1上施加選擇脈波，從輸出 電路6 8中輸出感光二極體6 2 b之輸出信號。其他動作 與感光二極體6 2 a之讀出信號時之上述一連串之動作相^ 同。 以後’问樣的對水平位址線6 — 2 ，6 — 3 .......... 反復進行上述動作，即可取出配置成二次元狀之全部晶胞 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）-115 - 裝 II —訂 I 1 I I I 線 (請先閱讀背面之注意事反楱寫本頁) 一 經濟部中央樣準局貞工消費合作社印袈 A7 B7 五、發明説明（113) 之信號。 習用裝置中，單位晶胞相當於1個圖素，因此’在在 1個幀之期間內只進行一次晶位晶胞內之感光二極體之檢 測信號之讀出之動作步驟時，則不能如本發明中使用之 MO S型固體攝像裝置中，單位晶胞相當之許多圖素之結 構之單位晶胞之输出電路只讀出相當於1個圖素，亦即只 讀出1個感光二極體之檢測信號，不能在1個幀期間內讀 出單位晶胞內之許多感光二極體之各檢測信號。 然而，依照本發明之實施例之M〇 S型固體攝像裝置 之驅動方法，可在電視方式之1個幀期間內之奇數場與偶 數場之各水平熄滅期間內，分別使垂直選擇電晶體6 5導 通一次而使輸出電路6 8動作，第1次時（奇數場時對應 於本身圖素之回描線掃描位置之水平熄滅期間）可讀出感 光二極體6 2 a之檢測信號，第2次（偶數場時對應於本 身圖素之回描線掃描位置之水平熄滅期間）時讀出感光二 極體6 2 b之檢測信號，故可驅動單位晶胞微細化之 MO SM型固體攝像裝置。 如此，若不在1個幀期間內使輸出電路動作2次以上 ，則不能讀出全部感光二極體之檢測信號。若不在讀出一 次後下一次讀出之前復置輸出電路，則在從下一次開始之 讀出信號中重叠前次讀出時之信號。 本實施例之MO S型固體攝像裝置之特徵爲，充放電 用復置電晶體6 6連接於放大電晶體6 4之閘極，經由感 光二極體選擇電晶體6 3復置感光二極體之電位·此時， 本紙張尺度適用中國圃家標準（CNS)A4规格（ 210X297公釐）-116 - ^-- (請先閱讀背面之注意事1,填寫本頁) 訂 線 經濟部中央橾準局貝工消費合作社印製 A7 ______B7__ 五、發明説明（ll4) 與感光二極體6 2 a ，6 2 b分別連接1個放大電晶體 6 4之方式比較，可減少每單位晶胞之電晶體數量。 本實施例中，單位晶胞內有2個構成受光部之感光二 極體該2個感光二極體共有同一組之輸出電路》因此，將 本實施例之MO S型固體攝像裝置應用於電視攝像時，在 電視之1個水平熄滅期間內使用放大電晶體6 4讀出電荷 信號之次數爲1次，而且容易驅動。簡言之，本實施例之 特徵爲讀出方向與共有方向不相同。 以下說明第6 2圖所示時序之前後關係。其順序有如 下之3種》 (1 )垂直位址之上昇—復置脈波之下降·-箝位脈波 之下降—感光二極體選擇脈波之上昇-感光二極體選擇脈 波之下降—樣品保持脈波之下降—垂直位址之下降 (2)樣品保持脈波之上昇—感光二極體選擇脈波之 上昇 (3 )箝位脈波之上昇—感光二極體選擇脈波之上昇 垂直位址之上昇，樣品保持脈波之上昇，箝位脈波之 上昇，及復置脈波之上昇之前後關係可爲任意，但最好爲 如下之順序。 垂直位址之上昇-樣品保持脈波之上昇—箝位脈波之 上昇-復置脈波之上昇 如上所述，依照第6 2圖之動作，因爲在箝位節4 1 上出現被復置而無信號時（亦即無感光二極體輸出信號成 分，而只有雜訊成分時）’與有信號時（亦即感光二極體 本紙張尺度適用中國國家標準（CNS)A4規格（210χ297公釐）_ 117 - ---------^------、玎------^ (請先閱讀背面之注意事項' >寫本頁) ~ 經濟部中央標準局員工消費合作社印製 306073 at _B7____ 五、發明説明（ 輸出信號成分+雜訊成分）之差之電壓，故可補償因放大 電晶體6 4之閾值不均勻而產生之固定圖型雜訊。亦即由 箝位電晶體3 0，箝位電容器3 1 ，樣品保持電晶體4 0 ，及樣品保持電容器3 4所構成之電路成爲雜訊消除電路 〇 本實施例之雜訊消除電路經由源極跟隨電路所構成之 阻抗變換電路2 6，28連接於垂直信號線8。亦即垂直 信號線8連接於電晶體2 6之閘極。因爲該電晶體2 6之 閘極電容量非常小，故事實上晶胞之放大電晶體6 4只要 充電垂直信號線即可。因此，C R之時間常數短，可立即 成爲正常狀態。因此，可加快復置脈波，感光二極體選擇 脈波之施加時序，可在短時間內進行雜訊消除動作。 在電視信號時，雜訊消除動作必須在電視掃描之水平 熄滅期間內進行》因此，如本實施例之可在短時間內正確 的消除雜訊，具有極大之優點。又因爲包含於雜訊消除動 作中之雜訊'输出時與^信號+雜訊#输出時，從單位 晶胞觀察之雜訊消除電路之阻抗相同，故可正確的消除雜 訊。 亦即*在^雜訊成分^输出時，與~信號成分+雜訊 成分^输出時，從單位晶胞觀察時之雜訊消除電路之阻抗 大致上相同。因此，在該兩種输出時*雜訊成分成爲大致' 上相同，計算兩者之差值，即可正確的去除雜訊輸出而只 取出信號成分。因此，可疋確的消除雜訊。若從單位晶胞 觀察雜訊消除電路時，在阻抗上只能觀察到閘極電容器， 本紙張尺度逋用中國國家標準（CNS>A4規格（ 210X 297公釐）-118 - ---------^------1T------^ (請先閲讀背面之注意事反¼寫本頁) 一 經濟部中央標準局貝工消费合作社印製 A7 ______B7_ 五、發明説明（116) 而該電容器之電容量非常小，故可在短時間內確實的消除 雜訊。 以下說明本實施例之MO S型固體攝像裝置之構造。 由第5 7圖之電路結構可知，因爲箝位電容器3 2與 樣品保持電容器3 4直接連接而互相接近，故可在同一面 上層®，可將單位晶胞小型化· 具體言之，如第2 4圇所示，經由第1絕緣膜7 4在 矽基板7 2上形成第1電極7 6而構成樣品保持電容器 3 4，而經由第2絕緣膜7 8在第1電極76上形成第2 電極80而構成箝位電容器32。 由圖中可知，第1電極7 6成爲共同電極，箝位電容 器3 2與樣品保持電容器3 4靥叠而形成，故以分別形成 時之1/2面積即可產生相同之電容置。 本實施例中，單位晶胞P1 - 1一1 ，P1 — 1 — 2 ..........垂直位址電路5，水平位址電路1 3等周邊電路 係形成在P -型基板上設有P +型不純物層之半導體基板上 〇 第2 5A，2 5B圖爲這種半導體基板之斷面圖。如 圖中所示，在p-型基板8 1上設置p+型不純物層8 2之 半導體基板上形成感光二極體8 3等晶胞要素。 如此的形成半導體基板•即可利用P—/P+分界之擴' 散電位防止發生於P_型基板8 1之暗電流之一部分流入 P +側· 以下簡單說明詳細解析電子流動之結果。對於在P — 本紙張尺度適用中國國家梂準（CNS)A4規格（ 210X297公釐）-119 - ---------批衣------1T------.^ (請先閱讀背面之注意事^ 填寫本頁) * 經濟部中央標準局貝工消费合作社印裝 A7 _____B7 五、發明説明（in) 側發生之電子而言，p+不純物層8 2之厚度L成爲相當 於P +與p -之濃度之比之倍數，亦即L · p +/ p —。 亦即，如第2 5 B圖所示，暗電流發生源之p-基板 8 1至感光二極體8 3之距離成爲較遠p+/p-倍。暗電 流中，除了從基板深部流入之電流以外，又有發生於感光 二極體8 3附近之耗盡層內之電流。在耗盡層內發生之暗 電流之大小與從基板深部流入之暗電流之大小大致上相同 。耗盡層之厚度大約爲1 左右*從基板深部流入之暗 電流又從大約1 0 0 之深度流入。該深度被稱爲p型 半導體內部之電子擴散距離•暗電流與該厚度之差無關的 成爲相同之理由爲|耗盡層內部之每單位體稹之暗電流之 發生或然率提高。在耗盡層發生之暗電流原理上不能與信 號電流分離，故希望降低暗電流時，係減少從基板深部流 入之成分而達成。 因爲在P—型基板7 1上設置p+型不純物層7 2之半 導體基板上形成晶胞，故可防止因發生暗電流而產生之基 板電位之變動。結果，可正常的使雜訊去除電路動作。因 爲P型基板之厚度大，故電阻小，可確實的使雜訊去除電 路動作。 因爲元件溫度上昇後•來自基板深部之成分急速的增 加。此現象非常重要。其程度爲來自基板深部之成分充分 小於在耗盡層產生之成分。具體言之*來自基板深部之暗 電流小於來自耗盡層之成分大約1位數以下即可》亦即將 p+/p_設定爲1 0而使來自基板深部之成分成爲大約 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）-120 -~ 裝 訂 線 (請先閱讀背面之注意事^楱寫本頁) ~ 經濟部中央橾準局貝工消费合作社印製 A7 ____B7 五、發明説明（118) 1 / 1 〇即可。 來自基板深部之暗電流在由η型基板與p型阱所構成 之半導體基板中可謂完全不存在，但爲了使其位準與這種 半導體基板之位準相同，必須將Ρ+/Ρ-設定爲1 0 0而 使來自基板深部之暗電流成爲大約1/1 0。 在習用之有實績之C CD中，η型埋入通道之不純物 澳度大約爲1 0 iec m-3，而包圍安定的製造該埋入通道 之擴散層之埋入通道之P型層（在此爲P型基板）之不純 物濃度大約爲1 0 15c m_3。 P+/P_爲1 0時，P+層之濃度大約爲 1 Oiecm_3，ρ+/ρ-爲 1 〇 〇 時，大約爲 1 0 17c m-3左右，成爲與η型埋入通道之不純物濃度之 大約1 〇iecm_3大約相同或反轉1個位數。 因此，習用之有實練之C C D中完全未考慮使用這種 不純物濃度之P+層。若降低P-層之濃度時，基板之薄片 電阻增高。 然而，放大型MO S型攝像裝置因爲無C C D之埋入 通道故可不必降低P-層之濃度而可自由的設定P+/P 一 之數值。 降低P型阱之電阻，改善由η型基板及p型阱所構成 之半導體基板之構造，亦可構成晶胞。 ’ 第2 6圖爲在η型基板8 5上使用薄片電阻值低之 ρ+阱8 6之單位晶胞之斷面圖。第2 7圖爲C C D之單 位晶胞之斷面圖。 本紙張尺度遑用中國國家標準（CNS)A4規格（ 210X297公釐）-121 - ----------^------1Τ------^ (請先閲讀背面之注意事1 填寫本頁) ( 經濟部中央樣準局貝工消費合作社印製 A 7 B7 五、發明説明（119) 爲了穗定的製造，CCD之單位晶胞之η型基板8 7 ，ρ型阱8 6，η型埋入通道8 9之不純物濃度分別設定 爲大約1 014cm_3，大約1 〇13cm_3，大約 1 〇 iec m_3左右。 因爲η型感光二極體9 0之不純物濃度可在一定範圍 內自由的設定，故製造上無太大之限制。在上述不純物濃 度時，Ρ型阱86之薄片電阻值大約爲ΙΟΟΚΩ/Ο。 C C D即使在如此高之電阻值下，其雜訊仍非常小。 若在放大型Μ 0 S攝像裝置中使用雜訊去除電路時， 該Ρ型阱之薄片電阻值非常重要。其理由爲，因復置脈波 所造成之Ρ型阱8 6之電位之擾亂平定所需之時間必須配 合應用該裝置之系統。 電視方式時*設定水平回描線期間，在此期間內不傳 送畫像信號。因此，必須在此期間內，將上述復置脈波所 造成之Ρ型阱8 6之電位之擾亂減小至某一位準。因此， 在現行之電視方式之NT S C方式中，使雜訊去除電路動 作所容許之期間爲水平回描期間之大約1 1 〔# s〕之間 •必須在該期間內使P型阱8 6之電位之擾亂平定至 0 . 1 〔 m V〕左右。 β 該0 · 1 〔mV〕之極小值係CCD之雜訊電壓输出 大約爲此數值而設定。根據解析爲了在1 1 〔// s〕之非‘ 常短之時間內平定爲0·1 〔mV〕之極小值·必須將ρ 型阱8 6之薄片電阻值設定爲1 ΚΩ/□以下。該數值爲 習用之CCD之大約1/1 〇〇。 本紙張尺度遑用中國國家標準（CNS)A4规格（ 210X297公釐）-122 - I--------^-- (請先閲讀背面之注意事後梃寫本頁) 訂 經濟部中央樣準局貝工消費合作社印製 A7 B7 五、發明説明（12〇) 因此，必須將P型阱8 6之不純物濃度設定爲大約 100倍。如在P型基板之說明時所述，此濃度在CCD 上爲不可能應用之濃度。又因爲高解像度電視方式中，水 平回描線期間爲3·77〔#s〕，必須將p型阱86之 薄片電阻值設定爲3 0 0 Ω/□以下。 其他變更例有在基板上形成高濃度之P+三明治層， 而以澳度較低之P型層形成其表面之例。 第2 8圖爲在p-型基板9 1與P型厝9 3之間形成 P+型三明治層9 2之半導體基板之結構圖。第2 9圖爲 在η型基板9 5與P型層9 7之間形成P+型三明治層 9 6之半導體基板之結構圓。 這種ρ +型三明治層可利用高加速度之兆伏特離子注 入機實現。 在該Ρ型層上除了形成單位晶胞之構成要素之感光二 極體8 3，電晶體等之外，又形成水平位址電路，垂直位 址電路等周邊電路。 第3 0圖爲以高濃度Ρ型阱1 0 3包圍感光二極髖 8 3之周圍，以其他Ρ型阱1 〇 2形成η型基板1 0 1上 之其他部分而構成之半導體基板之結構圇。 因爲採用這種結構，故可防止暗電流洩漏至感光二極 體8 3中。半導體基板1 〇 1亦可爲Ρ-型基板。 形成晶胞周邊之水平位址電路及垂直位址電路之一部 分或全部之Ρ型阱之濃度係在電路設計時決定。因爲與晶 胞之最佳值不同，故亦可形成爲與形成攝像領域之Ρ型阱 本紙張尺度逋用中國國家橾準（CNS)A4規格（ 210X297公釐）-123 - 裝 訂 線 ί I. (請先閱讀背面之注意事成，填寫本頁) A7 B7 經濟部中央標準局員工消费合作社印製 五、 發明説明 ( 121) 分 開之P型 層 〇 第6 3 圖 爲在 η 型 基 板 1 0 5 上 形 成 構 成 攝 像 領 域 之 P 型阱1 0 6 ，而 且 分 別 形 成 構 成 周 邊 電 路 之 其 他 Ρ 型 阱 1 0 7之半 導 體基 板 之 結 構 圖 〇 如此構 成 ，即 可 形 成 適 合 於 各 構 成 要 素 之 Ρ 型 阱 〇 上 述 η型基板 1 0 5 亦 可 爲 Ρ -型基板 〇 第6 4 圖 爲在 η 型 基 板 1 0 5 上 形 成 構 成 攝 像 領 域 之 P +型三明治層1 0 8及形成濃度低之ρ型層] L 0 9 ，而 且 在周邊電 路 部形 成 其 他 Ρ 型 阱 1 0 7 之 結 構 圖 〇 如此構 成 ，即 可 形 成 適 合 於 各 構 成 要 素 之 Ρ 型 阱 可 防 止暗電流 洩 漏感 光 二 極 髖 中 〇 上 述 η 型 基 板 1 0 5 亦 可 爲 ρ _型基板 > 如上所 述 ，依 照 本 實 施 例 因 爲 使 用 以 在 垂 直 ( CO 1 umn )方 向 鄰接 之 許 多 ( 在 此 爲 2 個 ) 感 光 二 極 體 共 有 一 個輸出電 路 之單 位 晶 胞 故 可 將 單 位 晶 胞 之 面 積 微 細 化 0 共有输出 電 路之 感 光 二 極 體 之 數 量 不 限 定 爲 2 個 亦 可 爲 3個以上 0 輸出電 路 6 8 之 變 更 例 亦 可 爲 如 第 6 5 圖 所 示 » 設 置 垂 直選擇電 容 器6 9 以 取 代 垂 直 選 擇 電 晶 體 6 6 依 照 該 結 構，可更 減 少每 單 位 晶 胞 之 構 成 電 晶 體 之 數 童 » 故 可 減 少 每一圖素 所 需要 之 電 晶 體 數 量 » 故 對 晶 胞 之 微 細 化 更 爲 有 利。 在位址 線 6 — 1 上 施 加 高 位 準 電 壓 後 ♦ 放 大 電 晶 體 之 閘 極電壓移 位 至髙 電 壓 側 0 因 爲 鄰 接 之 單 位 圖 素 之 放 大 電 請 先 閱 讀 背 ιέ % 事 |裝 訂 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）_ 124 - A7 B7 經濟部中央標準局負工消费合作社印製 五、發明説明（I22) 晶體之閘極電壓繼 續 保 持 較 低 狀 態 > 故 在 垂 直 信 號 線 8 一 1上出現被定位址 之 放 大 電 晶 體 之 信 號 〇 又因爲經由雜 訊 消 除 電 路 輸 出 單 位 晶 胞 之 輸 出 故 可 去除配合單位晶胞 之 放 大 電 晶 體 之 閾 值 不 均 勻 之 固 定 圖 型 雜訊。本實施例中 > 因 爲 經 由 可 高 速 動 作 之 本 發 明 之 雜 訊 消除電路输出單位 晶 胞 之 输 出 9 故 即 使 將 Μ 0 S 偵 測 器 應 用於動畫像用攝像 裝 置 時 > 仍 可 在 每 一 幀 或 每 — 場 之 被 限 定之時間內去除配 合 單 位 晶 胞 之 放 大 電 晶 體 之 閾 值 不 均 勻 之固定圚型雜訊， 可 產 生 即 使 在 電 視 方 式 中 仍 可 充 分 利 用 之放大型MOS固 體 攝 像 裝 置 0 在 雜 訊 消 除 電 路 中 因 爲 箝位電容器3 2 — 1 3 2 — 2 … … … ( 以 後 將 之 總 稱 爲3 2。其他具有 添 加 字 之 雄 稱 件 亦 相 同 ) 與 樣 品 保 持 電 容 器3 4直接連接而 互 相 接 近 故 可 將 之 層 叠 於 同 — 面 上 形 成，可將單位晶胞 小 型 化 0 雜訊消除電路 具 有 阻 抗 變 換 電 路 而 且 經 該 阻 抗 變 換 電路輸入單位晶胞 之 輸 出 » 故 在 雜 訊 成 分 雜 輸 出 時 及 % 信號成分+雜訊成 分 輸 出 時 9 從 單 位 晶 胞 觀 察 之 雜 訊 消 除電路之阻抗大致 上 相 同 〇 因 此 » 在 該 兩 種 輸 出 時 y 雜 訊 成分成爲大致上相 同 » 計 算 兩 者 之 差 值 « 即 可 正 確 的 去 除 雜訊成分而只取出 信 號 成 分 0 因 此 t 可 正 確 的 消 除 雜 訊 0 從單位晶胞觀察雜 訊 消 除 電 路 時 在 阻 抗 之 觀 點 上 只 能 觀、 察到閘極電容器， 而 其 電 容 量 非 常 小 » 故 可 在 短 時 間 內 確 實的消除雜訊。 亦即，在本實 施 例 之 雜 訊 消 除 電 路 中 > 由 電 晶 體 2 6 本紙張尺度遑用中國國家標準（CNS>A4说格（ 210X 297公釐）-125 - _B7___ 五、發明説明（l23) —1 與 28-1 ，26 — 2 與 28-2，26 — 3 與 28 —3 ..........所構成之阻抗變換電路成爲電晶體2 8 — 1 ，2 8 - 2 ，2 8 — 3..........通斷阻抗變換電路之動作 之開關，而電晶體26 — 1 ，26 — 2 ，26 — 3 ....... …成爲傳送垂直信號線8 — 1 ，8 — 2，8 - 3 .......... 所產生之输出信號之構成。將電晶體26 — 1 ，26 -2 >26-3* .........微細化的形成於半導體基板上，即可 將閘極電容器之電容童減小，而減小該電容量之結果，可 縮短雜訊消除電路動作時之C R之時間常數•可加快復置 脈波，感光二極體選擇脈波之施加時序，可在短時間內完 成雜訊消除動作|應用於例如電視信號等必須在電視掃描 之水平熄滅期間內完成雜訊消除動作時，非常有效。 經濟部中央樣準局貝工消费合作社印製 本實施例之雜訊消除電路在I C化時，因爲使用由 p-型不純物基體與形成在P-型不純物基體上之P+型不 純物層所構成之基板做爲形成單位晶胞之半導體基板，故 可減少侵入單位晶胞中之暗電流，而且可使基板表面之電 位穗定，故可確實的使雜訊消除電路動作，確實的去除雜 訊。 因此，依照本實施例，可提供小型化，可進行高速動 作，雜訊消除性能確實，可靠性高之雜訊消除電路。將該 雜訊消除電路裝組於放大型MO S偵測器中’即可提供一' 種小型•高速，雜訊消除性能確實，可靠性高之放大型 MO S固體攝像裝置。 本紙張尺度適用中國國家梂準（CNS)A4規格（2丨0X297公釐>-126 - 經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明（I24) 第2 6實施例 以下說明第2 6實施例。本實施例係將第2 5實施例 之雜訊消除電路變更之實施例。 第6 6圖爲使用第2 6實施例之放大型MO S偵測器 之攝像裝置之電路結構圖。本實施例中，單位晶胞P 1 _ i — j附近之電路結構與第2 5實施例相同。 各垂直信號線8 — 1 ，8 — 2..........之另一端經由 其對應之箝位電容器131-1 ，131 — 2........... 箝位電晶體1 3 2 — 1 ，1 3 2 — 2..........，水平選擇 電晶體1 2 — 1 ，1 2-2 ..........連接於信號输出端（ 水平信號線）1 5。 與第0 A 1實施例之雜訊消除電路不同，本實施例中 ，箝位電容器1 3 1 - 1，1 3 1 — 2..........直接連接 於其對應之垂直信號線8 — 1，8_2...........在各箝 位電容器1 3 1 _ 1，1 3 1 — 2 ..........與其對應之各 樣品保持電晶體1 3 3 — 1，13 3 _ 2..........之間分 別連接對應之箝位電晶體1 3 2 - 1 ，13 2 - 2，…… …之吸極· 箝位電晶體132 — 1 ，132 — 2 ..........之源極 連接於共同源極端子1 4 1 ，閘極連接於共同端子1 4 2 。樣品保持電晶體1 3 3 — 1 ，1 3 3-2..........與水 平選擇電晶體12—1，12_2..........之連接點經由 樣品保持電容器1 3 4 — 1 ，1 3 4 — 2 ’ .........接地。 以下參照第6 7圖之時序圖說明上述MO S型固體攝 本紙張尺度適用中國國家標準（CNS>A4規格（ 210X297公釐）-127 - ^-- (請先閲讀背面之注意事ΐ 1填寫本頁) 訂 經濟部中央樣準局貝工消费合作社印製 A7 B7 五、發明説明（l25) 像裝置之動作。因爲負載電晶體9之共同吸極端子2 0 ’ 箝位電晶體之共同源極端子1 4 1係由D C驅動’故在時 序圖中未表示。 單位晶胞係使用第61圖所示之單位晶胞說明。 在水平位址線6 - 1上施加高位準之位址脈波後，連 接於該位址線6 — 1之單位晶胞Pl — l_l，P1 - 1 _ 2..........之垂直選擇電晶體6 6導通，由放大電晶體 6 2及負載電晶體9 — 1，9 — 2 ..........構成源極跟隨 電路。 使樣品保持電晶體133 — 1 ，133 - 2 .......... 之共同閘極1 4 3之電位成爲髙位準而使樣品保持電晶髖 133-1 ，133 — 2 ..........導通。然後，使箝位電 晶體132-1 ，132 — 2..........之共同閘極142 之電位成爲髙位準而使箝位電晶體1 3 2 — 1 ，1 3 2 — 2..........導通。 然後，在復置線7- 1上施加高位準之復置脈波後， 連接於該復置線7 - 1之單位晶胞P — l — 1 - 1 ，P — 1-1-2 ..........之復置雪晶體6 6導通，輸出電路 6 8之输入端子之電荷被復置。因此，從輸出電路6 8輸 出配合感光二極體6 2之無信號電荷時之放大電晶體6 4 之閾值不均勻之雜訊成分· 然後，使箝位電晶體132-1 · 132-2 ....... …之共同閘極1 4 2之電位成爲低位準而切斷箝位電晶體 132-1 * 132-2 ........... 本紙張尺度適用中國國家標準（CNS)A4规格（ 210X297公釐>-128 - 赛-- (請先閲讀背面之注意事t '填寫本頁) 訂 經濟部中央標準局員工消費合作社印裝 A7 _B7_ 五、發明説明（l26) 如此，出現於垂直信號線8 - 1 ，8 - 2 .........之 雜訊成分被儲存於箝位電容器13 1 — 1 ，131 - 2， .........。在單位晶胞 P 1 — 1 — 1 ’ P 1 — 1 — 2 ’ ...... …中，感光二極體6 2 a在復置後，儲存信號電荷，故將 之讀出。爲此，在感光二極體選擇線2 2 - 1上施加高位 準之選擇脈波。如此，從輸出電路6 8输出感光二極體 6 2 a之輸出信號（亦即·*信號電荷成分+雜訊成分# ) 0 , 如上所述，因爲在箝位電容器131 — 1*131 — 2..........中已儲存、雜訊成分*故在箝位節1 4 5上 只出現從垂直信號線8 — 1 ，8-2 .........之電壓變成 分中，亦即'信號成分+雜訊成分#中減去 ' 雜訊成分' 之無固定圖型雜訊之信號電壓。此時，樣品保持電晶體 133-1 ，133-2 ..........導通，而在樣品保持電 容器134 — 1 ，134 — 2 ..........端出現相同之信號 電壓β 然後，使樣品保持電晶體133 — 1 ，133 — 2， .........之共同閘極1 4 3之電位成爲低位準而切斷樣品保 持電晶體133 — 1 ’ 133-2 ...........因此，可將 出現於箝位節之無雜訊之電壓儲存於樣品保持電容器 134 — 1 1 134 — 2 * .........中。 然後，在水平選擇電晶體12 — 1，12 - 2....... …上依次施加水平位址脈波，即可從信號输出端（水平信 號線）1 5中讀出儲存於樣品保持電容器1 3 4 — 1 ， 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）_ 129 - ~ ---------批衣------ΐτ------0 (請先閱讀背面之注意事Is.-.填寫本頁) * 經濟部中央橾準局員工消费合作社印製 A7 _____B7_ 五、發明説明（127) 13 4 — 2，.........中之無雜訊之感光二極體6 2 a之信 號。 然後，於水平位址線6 _ 1上施加高位準之位址脈波 時，係在感光二極體選擇線2 4 - 1上而非感光二極體選 擇線2 2_ 1上施加髙位準之選擇脈波，從輸出電路6 8 供給输出信號於感光二極體6 2 b。其他動作與上述相同 〇 此後，同樣的對水平位址線6 — 2，6 — 3.......... 反復進行上述動作，即可取出配置成二次元狀之全部晶胞 之信號。 如上所述，本實施例之雜訊消除電路中，廢止第2 5 實施例中採用之阻抗變換電路》依照該結構亦可確實的消 除雜訊，而可去除固定園型雜訊而只取出信號成分。其電 路結構因爲廢止阻抗變換電路，故較簡化，電路結構變成 精小，對小型化更爲有利· 第2 7實施例 第6 8圖爲使用第2 7實施例之放大型MO S偵測器 之攝像裝置之電路結構圖。單位晶胞P 1 _ i — j附近之 電路結構與第2 5實施例相同。 第2 7實施例係將第2 5實施例之阻抗變換電路連接 於第2 6實施例之雜訊消除電路之例。本實施例中*箝位 電晶體1 3 2之共同源極係由DC驅動。 在第2 6實施例之雜訊消除電路中，若雜訊消除之精 本紙伕尺度逡用中國國家標準（CNS)A4说格（210X 297公釐）-130 - ---------^------1T------i (請先閱讀背面之注意ii「填寫本頁) 一 A7 B7 經濟部中央標準局負工消費合作社印氧 五、 發明説明 ( 128) 1 | 確 度 有 問 題 時 » 如 本 實 施 例 中 在 输 入 段 設 置 第 2 5 實 施 例 1 1 之 阻 抗 變 換 電 路 而 將 單 位 晶 胞 之 输 出 予 以 阻 抗 變 換 * 使 只 1 1 有 雜 訊 成 分 之 輸 出 時 » 與 % 信 號 成 分 + 雜 訊 成 分 之 1 I 輸 出 時 從 單 位 晶 胞 觀 察 之 雜 訊 消 除 電 路 之 阻 抗 成 爲 大 到 請 先 閲 1 I 上 相 同 * 使 兩 種 狀 態 下 之 雜 訊 成 分 皆 成 爲 大 致 上 相 同 讀 背 面 1 1 I » 形 成 可 進 行 高 精 確 度 雜 訊 消 除 之 雜 訊 消 除 電 路 〇 1 I 意 %, 1 第 2 8 資 施 例 k 寫 本 1 1 裝 第 6 9 圖 爲 使 用 第 2 8 實 施 例 之 放 大 型 Μ 0 S 偵 測 器 頁 1 I 之 攝 像 裝 置 之 電 路 結 構 圖 〇 該 裝 置 中 改 變 雜 訊 消 除 電 路 之 1 I 結 構 0 第 2 8 實 施 例 中 之 雜 訊 消 除 電 路 係 將 出 現 於 垂 直 信 1 1 I 號 線 8 — 1 8 — 2 … … … 之 亀 壓 經 由 限 幅 電 晶 體 1 訂 1 5 0 之 閘 極 電 容 器 變 換 成 電 荷 在 電 荷 領 域 內 進 行 減 法 1 1 而 抑 制 雜 訊 〇 1 1 亦 即 第 2 5 實施 例 中 係 在 電 壓 領 域 內 消 除 雜 訊 但 本 …- 1 | 實 施 例 中 係 在 電 荷 領 域 內 消 除 雜 訊 Ο 單 位 晶 胞 Ρ 1 一 i 線 I — j 附 近 之 電 路 結 構 與 第 2 5 實 施 例 相 同 9 I 1 如 第 6 9 圖 所 示 t 第 2 8 實 施 例 中 ， 雜 訊 消 除 電 路 包 1 1 括 * 限 幅 電 晶 體 1 5 0 — 1 1 5 0 — 2 * … … … » 限 幅 1 1 電 容 器 1 5 2 — 1 * 1 5 2 一 2 … • · · … t 限 幅 復 置 電 晶 1 1 體 1 5 6 — 1 t 1 5 6 — 2 … … … > 限 幅 電 荷 傳 送 電 容、 1 I 器 1 6 2 — 1 9 1 6 2 — 2 » … … … » 吸 極 復 置 電 晶 體 1 I 1 6 6 一 1 t 1 6 6 — 2 9 … … … 9 及 水 平 選 擇 電 晶 體 1 1 1 1 2 — 1 » 1 2 — 2 » … … … 〇 1 1 1 ¾. 紙 本 準 標 冢 釐 公 7 9 2 經濟部中央標準局負工消費合作社印裝 306G73 A7 B7 五、發明説明（129) 限幅電晶體1 5 0 — 1 ，1 5 0 — 2 ..........與垂直 信號線8 - 1 ’ 8 — 2..........成爲一對一的對應狀態設 置。限幅電晶體15 0 — 1 ’ 150 — 2..........之閘極 側連接於垂直信號線8 _ 1 ’ 8 — 2..........中對應之信 號線。其連接端爲垂直信號線8 - 1，8 — 2 ..........之 2個端部中，與負荷電晶體9 一 1 ，9 — 2 .........連連 接側相反之端部* 限幅電晶體1 5 0 — 1 ，1 5 0 — 2..........之源極 側分別連接限幅電容器1 5 2 - 1，1 5 2 — 2 .......... 中，各電晶體所對應之一個限幅電容器之一端。限幅電容 器1 5 2 — 1 ，1 5 2 — 2 ..........之另一端連接於限幅 脈波供給端子1 5 4。 限幅電晶體15 0 — 1 ，150 — 2..........之吸極 側經由水平（row)選擇電晶體1 2 — 1 · 1 2 — 2，… ……中對應之一個電晶體之源極與吸極連接於信號输出端 (水平信號線）15。水平選擇電晶體12 — 1 ，12 — 2..........係由水平位址電路1 3所供給之水平位址脈波 驅動。 爲了復置限幅電晶體1 5 0 — 1 ，1 5 0 — 2，…… …之源極電位，在限幅電晶體之源極與限幅電源電子 158之間設有限幅復置電晶體156-1 ，156 — ..........，而該電晶體1 5 6 — 1 ，1 5 6 — 2 .......... 之閘極連接於限幅復置端子1 6 0。亦即限幅電晶體 150-1 · 150-2 ..........之源極經由電晶體 本紙張尺度適用中國國家梂準（CNS> Μ规格（210X297公釐）-132 - ---------^ II (請先閲讀背面之注意事t ,填寫本頁) 丁 -* 線 經濟部中央標準局貝工消费合作社印裝 A7 _B7_ 五、發明説明（13()) 1 5 6 — 1 ，1 5 6 — 2..........中之對應之一個電晶髖 之源極與吸極連接於限幅電源端子1 5 8。限幅復置電晶 體15 6 — 1 ，156 — 2 ..........之閘極連接於限幅復 置端子1 6 0，以從該限幅復置端子1 6 0供給之限幅復 置脈波之時序使限幅復置電晶體15 6 - 1 ，156 — 2 ..........導通而復置限幅電晶體150 — 1 ，150 — 2 ..........之源極電位β 各限幅電晶體1 5 0- 1 ，1 5 0 — 2..........之吸 極連接於限幅電荷傳送電容量162 — 1，162 — 2 ’ .........中對應之一端。限幅電荷傳送電容器1 6 2 — 1 ， 16 2 — 2 ..........之另一端接地· 爲了復置各限幅電晶體150_1，150 — 2 ’… ……之吸極電位，在各限幅電晶體150 — 1，150 — 2 ..........之吸極與儲存吸極電源端子1 6 4之間連接吸 極復置電晶體166—1，166-2..........中對應之 電晶體•亦即，各限幅電晶體150 — 1 ，150 - 2 ’ .........之吸極由吸極復置電晶體1 6 6 — 1 ，1 6 6 — 2 ..........中，分別與其本身對應之一個吸極復置電晶體經 由該吸極復置電晶體之源極與吸極之間連接於儲存吸極電 源端子164。各電晶體166 — 1 ，166 - 2 ’ ...... …之閘極連接於吸極復置端子1 6 8。 如上所述，第2 8實施例之MO S偵測器之雜訊消除 電路之特徵爲*將出現於垂直信號線8 - 1，8 — 2 ’… ……之電壓經由限幅電晶體1 5 0 — 1 ，1 5 0 — 2，… 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）-133 - ---------#------1Τ------^ ^ I (請先閱讀背面之注意事填寫本頁) 經濟部中央標準局員工消費合作社印製 A 7 B7 五、發明説明（131) ......之閘極電容器變換成電荷，在電荷領域內進行減法而 抑制雜訊。將該在電荷領域內消除雜訊之方式之雜訊消除 電路連接於和第5 7圖所示之第0A 1實施例相同之單位 晶胞P 1 - i — j而構成固體攝像裝置。 以下說明本實施例之驅動方法。 第7 0圖爲表示本實施例之動作之時序圖。第7 1圖 爲限幅電晶體150 — 1 ，150 — 2..........之電位圖 。在此，限幅電晶體150 — 1 ，150 — 2..........爲 p通道型電晶體。 首先，在第1行之水平位址線6 - 1上施加高位準之 垂直位址脈波。然後，在該行之各單位晶胞中，該單位晶 胞所屬之垂直選擇電晶體6 6導通，由該單位晶胞所需之 放大電晶體6 4及負載電晶體9 一 1 ，9 — 2 ..........構 成源極跟隨電路。 然後，在雜訊消除電路之限幅復置端子1 6 0上施加 限幅復置脈波，使限幅復置電晶體156 — 1 ，156 — 2 ..........導通，將限幅電容器1 5 2 - 1 ，1 5 2 — 2 ..........之電荷初期化。 限幅復置端子1 6 0之限幅復置脈波消減後，限幅復 置電晶體156 - 1 ，156 - 2 ..........斷路，限幅電 容器1 5 2 — 1 ，1 5 2 — 2..........成爲可充電之狀態 。然後，在限幅脈波供給端子1 5 4上施加第1限幅脈波 s P 1 · 在限幅電容器1 5 2 - 1 ，1 5 2 — 2 ..........之初 本紙張尺度適用中國國家梂準（CNS)A4規格（210X297公釐）-134 - ---------批衣-- (請先閱讀背面之注意事填寫本頁) 、·ιτ 線 經濟部中央樣準局負工消费合作社印製 A7 ___B7_ 五、發明説明（132) 期化之前或之後，在復置線7 - 1上施加高位準之復置脈 波。如此，連接於該復置線7 — 1之單位晶胞P 1 — 1 — 1 ’ P 1 - 1 一 2..........之復置電晶體6 6接受該復置 脈波而成爲導通，復置输出電路6 8之輸入端子之電荷。 因此，從输出電路6 8輸出配合感光二極體6 2中無信號 電荷時之放大電晶體6 4之閾值不均勻之雜訊成分。在第 70圖之時序圖中，係在限幅電容器1 52 — 1 ，1 52 一 2..........之初期化之後進行上述動作，输出配合放大 電晶體6 4之閾值不均勻之雜訊成分。 因爲限幅復置電晶體1 5 6 — 1 ，1 5 6-2，…… …斷路，在限幅脈波供給端子1 5 4上施加第1限幅脈波 SP1 ，因此在各限幅電晶體150-1 ，150 — 2， .........中，超越無信號時（亦即只有雜訊成分時）之本身 之閘極下之通道電位V QCh將第1限幅電荷傳送至吸極。 此時，在吸極復置端子1 6 8上施加吸極復置脈波。如此 ，吸極復置電晶體1 6 6導通相當於該吸極復置脈波之時 間寬度之期間，故在該時間寬度之期間內，吸極電位固定 於電壓Vedd。因此，在該期間內，第1限幅電荷通過吸 極復置電晶體1 6 6被排出於儲存吸極電源端子1 6 4。 然後，在該感光二極體選擇線2 2 - 1上施加高位準 之選擇脈波後，從單位晶胞之输出電路6 8輸出該單位晶' 胞之感光二極6 2 a之輸出信號（亦即'信號電荷成分十 雜訊成分。 然後，在限幅脈波供給端子1 5 4上施加第2限幅脈 本紙張尺度逋用中國國家梂準（CNS)A4規格（ 210X297公釐）-135 - ---------^I (請先閲讀背面之注意事t .填寫本頁 訂 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（133) 波SP2。如此，各限幅電晶體150 - 1 ，150 — 2 ..........中，超越施加有信號電荷存在時之電壓（有"^信 號電荷成分+雜訊成分#存在時之電壓）之本身之閘極下 之通道電位VQCh，將第2限幅電荷傳送至吸極。此時， 因爲各吸極復置電晶體1 6 6 - 1 ’ 1 6 6 — 2 ’ ......... 成爲斷路，故第2限幅電荷被傅送至連接於本身之吸極復 置電晶體1 6 6 — 1，1 6 6 — 2 ..........之吸極之限幅 電荷傳送電容器1 6 2 - 1，1 6 2 - 2 ’ .......... 然後，從水平位址電路將水平選擇脈波依次施加於水 平選擇電晶體1 2 — 1，1 2 - 1 ’ .........從信號输出端 (水平信號線）15中依次取出相當於1條線之信號· 然後，從水平位址電路1 3將水平選擇脈波依次施加 於水平選擇電晶體1 2 - 1 ，1 2 - 2..........。如此， 水平選擇電晶體1 2 — 1 ，1 2-2 .........中，接受水 平選擇脈波之水平選擇電晶體成爲導通，將對應於限幅電 荷傳送電容器1 6 2 - 1 ，1 6 2 — 2 ..........之儲存電 荷之信號供給於信號輸出端（水平信號線）1 5。如此， 從水平位址電路13將水平選擇脈波依次施加於水平選擇 電晶體1 2 — 1 ，1 2 - 2 ..........因此將對應於儲存在 限幅電荷傳送電容器1 6 2 — 1 ，1 6 2 — 2..........之 電荷之信號依次供給於信號輸出端（水平位址電路）15' ，結果可從信號輸出端15依次取出相當於1條線之信號 〇 假設水平位址線6 - 1之高位準之垂直位址脈波前緣 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）-136 - I 裝 訂 線 (請先閱讀背面之注意事15-'填寫本頁) · 經濟部中央標準局貝工消费合作社印«. A7 B7 五、發明説明（134) 位Ϊ爲P1 ，後緣位置爲P2，復置線7 - 1之信號之前 綠1位S爲P 3，後緣位置爲P 4，施加於限幅復置端子 1 6 〇之限幅復置脈波之前緣位置爲P 5 ，後緣位置爲 P 6，施加於限幅脈波供給端子1 5 4之第1限幅脈波 Sp 1與第2限幅脈波SP2中，第1限幅脈波SP 1之 前緣位置爲P7，後緣位置P8，第2限幅脈波SP2之 前緣位置爲P 9，後緣位置爲P 10，施加於吸極復置端 子1 6 8之吸極復置脈波之前緣位置爲P 1 1 ，後緣位置 爲P 1 2時，各信號位置之時間上關係成爲 P1<P6<P7<P8<P3<P4<P9<P10< P 2 其中P8<P11<P12<P9 最好P11<P12<P3<P4 P 1與P 5前後關係可爲任意，P 3與P 1 1之位置 ，及P 4與P 1 2之位置關係亦可爲任意。 在下一條線，下下一條線依次繼績進行該動作，即可 讀出二次元狀之全部信號β 該裝置中，最後讀出於信號輸出端1 5之電荷（第2 限幅電荷）變成 C S 1 ^ ( V S C Η 一 Voch) 本紙張纽遑用中國®家縣（CNS > A4g (210x297公137 ---------MI — (請先閱讀背面之注意事填寫本頁) 訂 線 經濟部中央標準局員工消费合作社印製 A7 ΒΊ_ 五、發明説明（135) 結果出現與有輸出電荷時與被復置而無信號電荷時之差之 電荷，故可抑制因單位晶胞內之放大電晶體6 4之閾值不 均勻而產生之固定圖型雜訊。 如此，將出現於垂直信號線8 — 1 ’ 8 — 2 .......... 之電壓變換成電荷，在電荷領域進行減法之電路結構亦可 稱爲雜訊消除電路。 這種型式之電路之雜訊消除作用與第5 7圖所示之第 2 5實施例不同。在第2 5實施例中，於箝位節4 1之電 壓領域內消除雜訊。在第2 8實施例之型式中，於限幅電 晶體1 5 0之源極端之電壓領域內，雜訊被消除。施加第 2限幅脈波S Ρ 2時，方將已消除雜訊之電荷傅送至吸極 。亦即在電荷領域內消除雜訊。利用這種方式亦可高精確 的消除雜訊，可只取出信號成分。 如上所述，依照第2 8實施例•因爲經由雜訊消除髦 路輸出單位晶胞之輸出，故可去除配合單位晶胞之放大電 晶體之閾值不均匀之固定圖型雜訊。 本實施例中，又將單位晶胞之輸出經由限幅電晶體之 閘極電容器供給於雜訊消除電路•因此，無論在^雜訊成 分'之輸出時，或^信號成分+雜訊成分〃之输出時，從 單位晶胞觀察之雜訊消除電路之阻抗大致上相同，故在該 兩種輸出時，雜訊成分大致上成爲相同，計算兩者之差值^ ，即可正確的去除雜訊輸出，可只取出信號成分。 亦即可正確的消除雜訊而只取出信號成分•從單位晶 胞觀察雜訊消除電路時，在阻抗之觀點上只能觀察到閘極 本紙張尺度逍用中國國家標準（CNS)A4规格（ 210X297公釐）-138 - (請先閱讀背面之注意事填寫本頁) .裝· 訂 A7 B7 經濟部中央標準局属工消費合作社印製 五、發明説明（136) 1 1 電容 器， 而其電容 量 極 小 » 故 可 在 短時 間 內 確實 的 消 除 雜 1 1 訊》 1 I 第2 限幅脈波 S P 2 亦 可 能 受 到其 正 刖 方之 第 1 限 幅 1 I 脈波 S P 1之影響 〇 因 此 > 爲 了 使 第1 與 第 2限 幅 脈 波 對 請 先 閱 1 1 | 第1 與第 2電晶體 之 動 作 之 影 響 成 爲相 同 f 在第 1 限 幅 脈 讀 背 1 1 之 1 波 注 意 1 I S P 1之 正前方設 置 模 擬 限 幅 脈 波 最爲 有 效 9 4, 1 1 若第 1限幅脈 波 與 第 2 限 幅 脈 波之 振 幅 相同 時 • 在 微 填 寫 本 1 裝 1 秒之 電壓 條件下， 可 能 發 生 在 微 小 信號 領 域 內不 能 讀 出 信 頁 1 1 號電 荷， 或直線性 劣 化 之 問 題 故 將第 2 限 幅脈 波 之 振 幅 1 1 設定 爲大 於第1限 幅 脈 波 之 振 幅 在從 第 2 限幅 脈 波 讀 出 1 I 之電 荷上 相加偏壓 電 荷 其 動 作 較 穩定 〇 將 第2 限 幅 脈 波 訂 I 之寬 〇 度設 定爲大於 第 1 限 幅 脈 波 之 寬度 亦 爲有 效 之 方 法 1 1 1 1 I 第2 9實 施例 1 線 1 第7 2圖爲使 用 第 2 9 實 施 例 之放 大 型 Μ 0 S 偵 測 器 丨 之攝 像裝 置之電路 結 構 圖 0 單 位 晶 胞P 1 — i - j 附 近 之 1 I 電路 結構 與第0 A 1 實 施 例 相 同 〇 1 I 第2 9實施例 係 從 第 5 7 圖 所 示第 2 5 實施 例 中 省 略 1 1 1 由電 晶體 2 6-1 2 8 — 1 » 2 6 — 2 ...... … 及 電 晶、 1 1 體2 8 — 2 · 2 6 一 3 > 2 8 — 3 t · ♦« … … 所構 成 之 阻 抗 1 1 變換 電路 之實施例 φ 因 爲 在 第 2 5 實施 例 中 設置 之 阻 抗 變 1 1 換電 路之 電晶體2 6 之 閘 極 電 容 器 之電 容 量 小， 故 可 縮 短 1 1 本紙張尺度遑用中國國家梂準（CNS)A4规格（ 210X297公釐）-139 - 經濟部中央棣季局貝工消費合作社印製 A7 B7_ 五、發明説明（137) 雜訊消除電路動作時之C R之時間常數。因爲可縮短時間 常數，故可加快相當於該縮短時間之復置脈波，感光二極 體選擇脈波之施加時序，可在短時間內進行雜訊消除動作 。這種方式在例如電視信號等必須在電視掃描之水平熄滅 期間內進行雜訊消除動作時非常有效。然而，對於不要求 如此高速動作之用途則變成超過規格。 因此，若分配於雜訊動作之時間寬裕時，如第2 8實 施例中所述，省略阻抗變換電路之結構亦有充分之實用性 。因爲省略阻抗變換電路，可使電路結構更簡化，故可更 小型化。 第3 0實施例 第73，74圖爲使用第30實施例之放大型MOS 偵測器之攝像裝置之電路結構圖。單位晶胞P 1 — i 一 j 附近之電路結構與第25實施例相同》 本實施例中有許多與第6 6圖所示之第2 6實施例共 同之部分。其不同之處爲設置修正^信號成分+雜訊成分 〃輸出時與只輸出 ''雜訊成分'時從單位晶胞側觀察之雜 訊消除電路之阻抗之不同之修正電容器1 6 0 — 1 ， 16 0 — 2 ..........。各修正電容器分別具有C CMP之電 容量。各修正電容器160 — 1 ，160 — 2 ..........在 較箝位電容器1 3 1 - 1 ，1 3 1 — 2 ..........之設置位 置更靠近攝像領域（單位晶胞）側·而且經由開關1 6 2 -1 · 16 2-2 ..........並聯於垂直信號線8 - 1，8 本紙張尺度遥用中國國家標準（〇阳）八4规格（2丨0乂297公釐）-14〇- ---------1------1T------0 (請先閲讀背面之注意事i 1填寫本頁) ' _B7_ 五、發明説明（l38) 一 2 ...........以上爲與第2 6實施例不同之處。 在第73圖中，修正電容器160-1 ，160 — 2 ..........及對應的設置之開關162-1 ，162 — 2， .........係連接在箝位電容器1 3 1與攝像領域之間，在第 7 4圚中係連接在攝像領域與負載電晶體9之間》 第7 5圖表示本實施例之動作時序。開關1 6 2在箝 位電晶體1 3 2之箝位終了，從垂直信號線输出信號之期 間內接通。如此，在樣品保持對連接於垂直信號線8 — 1 • 8 - 2 * .........之電容器之電容量若假設樣品保持電容 器134之電容童爲CSH，箝位電容器131 - 1， 13 1-2 ..........電容量爲C <^時，變成如下， C = C c Μ P + C s Η · C c L / ( C c L + C s Η ) 因此，_若在 2 { C c L — C c L * Csh/ ( CcL + CsH) } > CcMP〉0 經濟部中央標準局貝工消費合作杜印製 之範圍內設定修正電容器cCMP之電容置時，與修正電容 器時比較，在樣品保持時連接於垂直信號線之電容器之電 容量接近箝位電容器1 3 1 - 1 ，1 3 1 - 2 ..........之 電容量Cclj。因此·因該電容量差而產生之電壓之差值 V Cli變成更小，故雜訊亦變小。 因此，從晶胞觀察之阻抗在信號傳送時與雜訊傳送時 本紙張尺度遑用中國國家橾準（CNS)A4規格（ 210X297公釐）-141 - 經濟部中央揉準局貝工消費合作社印«. A7 B7 五、發明説明（l39) 不會成爲不相同，與使樣品保持期間內之C接近Ccu，其 結果皆相同。 第7 6囫表不垂直信號線8 — 1，8 - 2..........之 電位與箝位節1 4 5之電位之時間變化。本實施例中，例 如在黑暗時信號變成0，當垂直信號線8_1 ，8 — 2 ， .........之電位復原成箝位時之電位，與復原成樣品保持時 之電位相同時，在樣品保持終了時刻之箝位節之電位不會 復原成接近之數值，但變成0。因此，不會發生雖 然爲黑暗而且信號爲〇，但出現相當於AVce之信號之問 題。因此，可防止因ΔΥπ之不均勻而造成之雜訊之發生 〇 如上所述，依照本實施例，在具有雜訊去除電路之 MO S型固體攝像元件中，於垂直信號線8上設置修正電 容量1 6 0 - 1，1 6 0 — 2..........，即可抑制成爲發 生雜訊之原因之雜訊去除動作中之電容置變化，可更促進 低雜訊化。亦即，在*信號成分+雜訊成分|输出時，與 %雜訊输出^•時，從晶胞觀察之阻抗變成相同，可正確的 消除雜訊》但復置終了時爲|雜訊成分〃输出時，PD ( 感光二極體）選擇後鳥、信號成分+雜訊成分〃輸出時。 本實施例中，在|雜訊成分〃输出時，與*信號成分 +雜訊成分〃输出時，從單位晶胞觀察之雜訊消除電路之' 阻抗大致上相同。因此，在該兩種輸出時，雜訊成分大致 上成爲相同，計算兩者之差值，即可正確的去除雜訊輪出 而只取出信號成分•因此*可正確的消除雜訊。 本紙張尺度遑用中國國家標準（CNS)A4規格（ 210X297公釐）-142 - g-- (請先閲讀背面之注意事t,填寫本頁) 訂 線 A7 B7 經濟部中央標準局貝工消費合作杜印製 五、 發明説明（140) 1 I 亦可將第3 0實施例變更 在第5 7 圖 所示第 2 5 施 1 1 例 ，第6 8圖所示之第2 7實 施例， 及 第 7 2圖 所示 之 第 1 1 2 9實施例之雜訊消除電路上 連接修 正 用 電容器 0 1 I 請 1 1 第2 6〜3 0實施例中係 說明與 第 2 5實施 例比 較 ) 先 閱 1 I 雜 訊消除電路不同之實施例。 以下說 明 與 第2 5 〜3 0 實 讀 背 ιδ 1 1 I 施 例比較，單位晶胞之結構不 同之第 3 1 實施例 1 第 3 1實施例 k 窍 本 1 裝 I 第3 1實施例與第2 5〜 3 0實 施 例 比較， 單位 晶 胞 頁 '—^ 1 1 之 結構不同。但整體結構與第 5 7圖 所 示 之第2 5實 施 例 1 1 相 同，故在此不再圖示。但本 實施例 之 特 徴爲使 用第 7 7 1 I 圖 所示之單位晶胞P 2取代第 5 7圖 所 示 之單位 晶胞 Ρ 1 1 訂 1 I 本實施例之單位晶胞P 2 之特徵 爲 第2 5 實施 例 中 1 1 1 之 感光二極體62a，62b 之方向 爲 垂 直方向 ，但 本 實 — 1 施 例中係朝水平方向鄰接的配 置。各 二 極 體經由 感光 二 極 線 1 體 選擇電晶體63a ，63b 連接於 復 置 電晶體 6 6 之 源 1 | 極 ，及放大電晶體6 4之閘極 ，而且 共 有 1個輸 出電 路 1 I 6 8。 1 1 1 以下參照第7 8圖之時序 圚說明 其 動 作。首 先， 在 水 1 1 平 媳滅期間內使水平位址線6 -1及 感 光 二極體 選擇 線 2 ' 1 1 2 - 1之電位成爲高位準，使 垂直選 擇 電 晶體6 5及 感 光 1 1 二 睡體選擇電晶體6 3 a導通 〇 1 1 結果，在放大電晶體6 4 之閘極 出 現 與感光 二極 體 1 1 本紙張尺度適用中國國家標準（CNS ) A4规格（2丨Ο X 297公釐> -143 - 經濟部中央標準局貝工消費合作社印製 A7 ___B7__ 五、發明説明（141) 6 2 a之電壓大致上相等之電壓。放大電晶體6 4及負載 電晶體9 - 1構成源極跟隨器，在垂直信號線8 - 1上出 現與放大電晶體6 4之閘極電壓大致上相等之電壓。 然後，使垂直位址脈波6 - 1之位準成爲低位準，使 垂直選擇電晶體6 5成爲斷路。結果，源極跟隨器不再動 作，但垂直信號線8 - 1之電位不會立即發生變化，可保 持與復置前放大電晶體6 4之閘極電壓大致上相等之電壓 〇 然後，使復置線7 — 1之電位成爲髙位準，使復置電 晶體6 6成爲導通，將放大電晶體6 4之閘極及感光二極 體6 2 a之電位初期化。 從水平位址電路13將水平位址脈波施加於水平選擇 電晶體1 2 — 1之閘極，從信號輸出端1 5取出感光二極 體6 3 a之信號。 然後，在同一水平熄滅期間內，於進行與上述相同動 作時，使感光二極體選擇電晶體6 3 b取代感光二極體選 擇電晶體6 3 a成爲導通。結果，可從信號输出端1 5取 出感光二極體6 3 b之信號。 圖中雖然未表示*但在該水平熄滅期間內，於相同垂 直位址之下依次變更水平位址而依次取出相當於1行之信 號》在下一個水平熄滅期間內對下一個垂直位址進行相同' 之動作*依次取出各行之信號· 如此，依照本實施例之MO S型固體攝像裝置，除了 具有第〇A 1實施例之效果之外，又因爲在某一幀之期間 本紙張尺度遑用中國國家梯準（CNS)A4规格（ 210X297公釐）-144 - (請先閲讀背面之注意事t '填寫本頁 •裝· 訂 線 A7 B7 306073 五、發明説明（142) 內垂直位址線成爲通斷係只在某一水平期間內，故可簡易 的控制垂直位址線。又因此可簡化垂直位址電路與多工電 路。 第3 1實施例亦可與第2 5實施例相同的變更雜訊消 除電路。亦即第5 7〜7 6圖之說明又可同樣的適用於第 31實施例。包含於第31實施例之單位晶胞中之在水平 方向鄰接之感光二極體之數置亦限定爲2個，亦可爲3個 以上。亦可如第6 5圖所示，其輸出電路以垂直選擇電容 器取代垂直選擇電晶體。 請 先 閱 讀 背 之 注 意 經濟部中央橾準局貝工消費合作社印製 第3 2實施例 第7 9圖爲第3 2 結構圖*單位晶胞P 3 元矩陣狀* 第80圖爲第79 結構圖。在只表示單位 單位晶胞P3—1—2 如圖中所示，本實 位晶胞係由4個感光二 極體選擇電晶體6 3 a 構成。4個感光二極體 感光二極體6 2 a 63a〜63d連接於 63a〜63d由從垂 實施例之Μ Ο S —i — j在縱向 型固體攝像裝置広 與橫向排列成二次 之單位晶胞P3 — 1 — 1之 圖所示 晶胞P ，〜亦採用相同 施例之Μ Ο S型 極體6 〜6 3 配置成 3 — 1 - 2 a〜6 訂 線 〜6 2 共同输 直位址 dll 2行2列 d分別經 出電路6 電路5朝 1之結構•但其他 之結構。 固體攝像裝置之單 2 d，4個感光二 個輸出電路6 8所 之矩陣狀。 由選擇電晶體 8。選擇電晶體 向水平方向配設之 本紙張尺度適用中國國家橾準（CNS)A4规格（2丨0><297公釐）_ 145 - B7 五、發明説明（143) 感光二極體選擇線22 — 1 ，24-1 ，172-1 , 1 7 4 — 1獨立的控制其通斷。 請 先 閣 讀 背 ΐέ 之 注 意 J裝 頁 如上所述，在4個感光二極體6 2 a〜6 2 d上連接 共同之输出電路6 4而構成單位晶胞P 1 _ 1 - 1 ,故與 習用之MO SM型固體攝像裝置之單位晶胞比較，可省略 三個输出電路。 如此，依照本實施例之MO S型固體攝像裝置，可產 生將第2 5實施例與第2 6實施例組合之效果。 訂 第〇 A 8實施例亦可與第2 5實施例相同的變更雜訊 消除電路·亦即第5 7〜7 6圖之說明又可適用於第 0A 8實施例。第3 2實施例之單位晶胞中包含之感光二 極體之數量亦不限定於2行2列，亦可爲3個以上之矩陣 ，不必爲正方形矩陣。如第6 5圚所示，輸出電路亦可使 用垂直選擇電容器取代垂直選擇電晶體。 線 經濟部中央標準局貝工消費合作社印装 本發明不受上述實施例之限制，可變更資施。例如只 要能製造無閾值不均勻之單位晶胞之放大電晶體，則因爲 不產生固定圖型雜訊，故可省略雜訊消除電路。或者即使 產生固定圖型雜訊，只要不影響畫質，則同樣的可省略雜 訊消除電路。 負載電晶體之閘極及源極不一定連接於同一電源線， 亦可分別連接於不同電源。如此，可控制通過之電流，可' 降低消耗功率。 在各實施例之雜訊消除電路中，因爲無输入信號時讀 出之信號電流（只有雜訊成分）小時雜訊較小，故最好使 t紙張尺度適用中國國家標準（CNS>A4规格（210X297公釐）_ 146 _ 一 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（144) 施加於儲存吸極電源端子之電壓與視頻偏壓成爲大致上相 等。所謂視頻偏壓係指從信號输出端1 5以電流方式讀出 信號時，信號输出端1 5大致上成爲固定之電壓。第4 5 圖表示將之實現之變更例。信號输出端1 5連接於運算放 大器1 7 6，在運算放大器1 7 6之输入输出端間連接負 載電阻1 7 8 ·如此，信號電流強制的流進負載電阻 1 7 8中，水平信號線1 5假想的被固定於某一電壓，亦 即視頻偏壓。 以上實施例中係說明將單位晶胞排列成二次元矩陣狀 之實施例•但本發明亦可應用於將單位晶胞排列成一次元 陣列狀之攝像裝置中。此時，單位晶胞內之感光二極體可 與單位晶胞之排列無關的朝向垂直方向與水平方向排列成 矩陣狀。 以上說明組合放大型MO S偵測器與雜訊消除器而產 生無雜訊之畫像信號之各種具體例* 然而，以上放大型M〇 S型偵測器中，包含於單位晶 胞之電晶體最少必須具有放大電晶體，垂直選擇電晶體， 及復置電晶體等3個電晶體》爲了晶胞之微細化，省電力 化，必須儘可能的減少構成晶胞之電晶體之數量。非放大 型之MO S偵測器中，晶胞係由感光二極體及1個電晶體 所構成，但與放大型比較，靂敏度較低。 以下說明放大型MO S偵測器中，可更微細化，而且 可更省電力化之MO S型固體攝像裝置（利用放大型 MO S偵測器之固體攝像裝置）之具體例。 本紙張尺度適用中國國家橾率（CNS ) A4規格（210X297公釐）_ 14了 - ---------^------iT------A (請先閲讀背面之注意事.^寫本頁) 經濟部中央標準局負工消費合作社印製 A7 __ _B7_ 五、發明説明（l45) 第3 3實施例 以下參照第8 1 ，82圇說明本發明之第3 3實施例 。第8 1圖表示第3 3實施例之MO S型固體攝像裝置之 結構。單位晶胞8 - i - j在縱向與橫向排列成二次元矩 陣狀•圖中只表示3 X 3，但實際上有數千個X數千個。 i爲水平（row)方 向之變數，j爲垂直（column)方向 之變數。 本發明之固體攝像裝置之應用領域爲視頻攝像機，電 子靜止攝像機，數位攝像機，電話傳真’複印機，及掃描 稷寺。 本實施例之基本晶胞Ρ 8 - i — j包括：檢測入射光 之感光二極體6 2 — i 一 j ;閘極連接於感光二極體6 2 一 i 一 j之陰極而放大其檢測信號之放大電晶體6 4 — i —j ;連接於感光二極體6 2 - i_j之陰極（放大電晶 體64—i-j之閘極），復置信號電荷之復置信號電荷 之復置電晶體6 0_i — j :及連接於放大電晶體6 4 — i — j之吸極與閘極間之位址電容器69 — i — j 。如此 ，本實施例中，可省略習用例（第1圖）中設置之垂直選 擇電晶體3 — i 一 j ’另外設置可產生相同功能之位址電 容器 6 9 — i — j β 從垂直位址電路5朝向水平方向配線之垂直位址線6 -1-6-2 ..........連接於各行之單位晶胞之放大電晶 體6 4 - i - j之吸極與復置電晶體6 0之吸極而決定讀 本紙浪尺度遗用中國國家標準（CNS ) A4規格（210X25(7公釐）_ 148 — ---------^------、玎------^ / I (請先閲讀背面之注意事項楱寫本頁) ____B7__ 五、發明説明（146) 出信號之水平線。同樣的，從垂直位址電路5朝向水平方 向配線之復置線7 — 1 ，7 - 2 ..........連接於各列之單 位晶胞之復置亀晶體6 6 _ i - j之閘極。 各列之單位晶胞之放大電晶體6 4 — i - j之源極連 接於朝向列方向配置之垂直信號線8 — 1 ，8 — 2 ，在垂 直信號線8 — 1 ，8 — 2..........之一端設有負載電晶體 9一1 ，9一2...........負載電晶體 9 — 1 ，9 — 2， .........之閘極與吸極共同的連接於吸極電壓端子2 0。 垂直信號線8 — 1，8 — 2 ..........之另一端經由箝 位電容器1 3 1 — 1，1 3 1 — 2..........，樣品保持電 晶體133 — 1 ，133 — 2..........，水平選擇電晶體 12-1 · 12-2 ..........連接於信號輸出端（水平信 號線）15。箝位電晶體132-1 ，132 — 2....... …之吸極連接於箝位電容器131 — 1 ，131 - 2，… ……與樣品保持電晶體1 3 3 - 1，1 3 3 — 2.......... 之連接點（箝位節1 4 5 — 1，1 4 5 - 2..........）。_ 箝位電晶體132 - 1 ，132 — 2 .........之源極連接 經濟部中央標準局貝工消費合作社印製 於共同源極1 4 1，閘極連接於共同閘極端子元1 4 2。 樣品保持電晶體133 - 1 ，133 - 2..........與水平 選擇電晶體1 2 — 1 ，1 2 — 2 ..........之連接點經由樣 品保持電容器1 3 4 — 1 ，1 3 4 — 2..........接地。水' 平選擇電晶體12 - 1，12-2，………之閘極水平位 址電路1 3接受住址脈波。 垂直位址電路5係將許多（在此爲2個）信號整合而 本紙張尺度適用中國國家標準（CNS)A4说格（ 210X297公釐）_ _ 經濟部中央樣準局員工消费合作社印製 A7 ________B7__^_ 五、發明説明（147) 移位之電路。該電路可利用第1 8，1 9或2 0圖中之任 一電路實現。第1 8圖之例中，多工器4 8將從許多輸出 端依次移位输入信號4 6而输出之位址電路4 4之輸出與 2個輸入信號5 0合成。第1 9圖之例中，多工器5 6將 編碼输入5 4解碼用解碼器5 2之輸出與2個輸入信號 58合成•第20圖之例中，將2個位址電路60a ， 6 0 b之输出整合成各行之控制信號線。 第8 2圖爲本實施例之動作時序圖。在水平熄滅期間 內，於垂直位址線6 - 1上施加高位準之位址脈波後，該 高位準之位址脈波經由位址電容器6 9供給於連接在該線 之單位晶胞之放大電晶體6 4之閘極上，該閘極下之通道 之電位變成高於連接在其他線之單位晶胞之放大電晶體 6 4之閘極下之通道電位而成爲導通。因此，由連接於垂 直位址線6 — 1之單位晶胞之放大電晶體6 4及負載電晶 體9構成源極跟隨電路。然後，在垂直信號線8上出現與 放大電晶體6 4之閘極電壓，亦即感光二極體6 4之電壓 大致上相等之電壓。如此，在垂直信號線8 — 1 ，8 — 2 ..........上只出現被定位址之線之放大電晶體6 4之閘極 電位，而不會出現其他線之放大電晶體6 4之閘極電位。 因此即使省略垂直選擇電晶體，仍可設定垂直位址線之位 址。 在箝位電晶體1 3 2 — 1，1 3 2 — 2 ..........之共 同閛極142上施加箝位脈波’使箝位電晶體1 32 — 1 ，132 - 2..........成爲導通。將箱位節14 5 — 1， 本紙張尺度A用中國國家樣準（CNS>A4说格（_210x297公羡〉-150 - ---------#------1T------^ (請先閱讀背面之注意事m~丨填寫本页) 一 經濟部中央標準局負工消費合作社印製 A7 B7MO S transistor 2 6 — 1, 2 6-2. . . . . . . . . . With MOS transistor 28-1, 28-2. . . . . . . . . . The connection point is through a sample holding transistor 3 0-1, 3 0-2 which is also a constituent element of the noise cancellation circuit. . . . . . . . . . Connected to clamp capacitors 32-1, 32-2. . . . . . . . . . One end. Clamp capacitors 3 2-1, 3 2-2 in the components of the noise cancellation circuit . . . . . . . . . One end of the parallel sample holding capacitors 34-1, 34-2. . . . . . . . . . With clamp transistors 40-1, 4 0-2. Sample holding capacitor 3 4-1 * 3 4-2 of the components of the noise cancellation circuit. . . . . . . . . . The other end is grounded. Tank capacitor 3 2 — 1 • 32-2. . . . . . . . . . The other end through the horizontal selection transistor 1 2 — 1 * 12-2 · .. . . . . . . . . Connected to the signal output (horizontal signal line)-1 5 β level (row) selection transistor 1 2 _ 1, 1 2 — 2. . . . . . .  … Through the circuit that switches the row address in turn, that is, choose the level --------- ^ ------, order -------- ^ (please read the notes on the back first Matter 1 \ write this page) * This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) -1〇4-V. Description of invention (l〇2) The horizontal address provided by the address circuit A7 B7 The selected row (row) of the pulse wave selects the transistor 1 2 _ 1 2-2 V · · «· ·« · · · Connected to the signal output terminal (horizontal signal line) 1 5. The vertical address circuit 5 is a circuit that shifts the signals of many lines, in this example, the signals of four lines. That is, the vertical address circuit 5 has 4 X η groups of terminals, and sequentially switches 4 groups of terminal groups to make each group become active each time. This action is realized by any of the circuits in Figures 58, 59, or 60. Please read the back first. * Matters printed by the Ministry of Economic Affairs, Central Standards Bureau, Beigong Consumer Cooperative, 5th input input signal 5 5th input decoding 6th shift In the potential electric crystal, it is the same as the sixth structural example. The number of other unit crystals 8 8 4 0 0 Synthesizer 9 Figure 5 5 2 0 Figure body 6 0-In the terminal example, the multiplexer 4 8 will sequentially shift from many output terminals and output the shift register 4 4 In the example of the output and the four inputs, the multiplexer 56 synthesizes the output of the decoder encoder 54 with the four input signals 58. In the embodiment, four a, 60b, 60c, 60d with many terminals are used, and the output of the output position is integrated as a control signal line for each row. The unit cell P 1 _ 1-1 shown in FIG. 5 7 represents the structure of the unit cell P 1-1-1, but its figure 1 shows that only the cell P 1-1-2 is used here. The structure is as shown in the figure, the unit cell of the MO S-type hip fixed camera device of this embodiment includes: two photodiodes 62a, 62b adjacent in the vertical direction (column): select any one of the photodiodes The detection signals of the body 62a, 6 2 b are used as the output of the unit cell 2 photodiode selection transistors 6 3 a, 6 3 b; and the output from the unit cell is selected by the paper size used in China. National Rubbing Standard (CNS) A4 (210X297 mm) _ 1〇5-i Binding Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperation Du Yin «.  A7 B7__ V. Description of the invention (103) The output circuit 6 8 of the output signal of the photodiode 62a and 6 2 b selected by the transistors 63a and 63b. The selection switches 63a and 63b are turned on and off independently. Turning on the selection switches, the electric charge stored in the photodiodes 6 2 a, 6 2 b can be supplied to the output circuit 68 in a time-division manner. The output circuit 6 8 is composed of the following components, that is, the amplified transistor 6 4 that receives the charge signal supplied from the photodiode 6 2 a, 6 2 b at the gate and amplifies it, and selects the read signal The vertical selection transistor 65 of the unit cell is composed of a reset transistor 6 6 that charges and discharges the charge applied to the gate of the amplifier transistor 6 4. The horizontal address line 6-1 wired from the vertical address circuit 5 toward the horizontal direction (row direction) is connected to the gate of the vertical selection transistor 6 5 to select the line for reading out the signal. Similarly, the reset line 7-1 wired from the vertical address circuit 5 to the horizontal direction, the photodiode selection lines 22-1, 24-1 are respectively connected to the gate of the reset transistor 66, the photodiode Select the gates of transistors 63a and 63b. In this way, the unit cell of the MOS solid-state imaging device of this embodiment is different from the conventional one photodiode / unit cell, and has many photodiode / unit cell structures. Here, the two photodiodes adjacent in the vertical direction share a single output circuit 6 8. That is, in the structure of one photosensitive diode / unit cell, each unit cell corresponds to one pixel, but many photosensitive diodes / unit cell structures have many of them as light-receiving parts. Photodiodes, so the number of light-receiving parts can be used as pixels, therefore, each unit cell becomes many pixels. The paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210X 297 mm) _ 1〇6 --------- 1 ------ 1T ------ line (please read the precautions on the back to write this page first) (Printed by the Ministry of Economic Affairs Bureau of Central Standards Staff Consumer Cooperative A7 __B7 Fifth, the structure of the invention (104). In this embodiment, the unit cell system is composed of two photosensitive diodes, and each unit cell has two electric cells for selecting the photosensitive diodes. There are a total of 5 transistors in the crystal. That is, the structure of the unit cell of the MOS solid-state imaging device according to this embodiment is equivalent to only 2.5 pixels per 1 photodiode for 1 pixel Transistors. Therefore, compared with the conventional structure shown in Figure 1 where one photodiode requires three transistors, the number of transistors per pixel The number of transistors in this embodiment is 2 · 5. The number of transistors can be reduced by 0.5 · *. Therefore, the occupation area of each pixel can be reduced. If it is a solid-state imaging device with the same pixel number *, it can be Making a more compact solid-state imaging device * The unit cell of the MO S-type solid-state imaging device of this embodiment is characterized by two photosensitive diodes 6 2 a, 6 2 b through selection transistors 6 3 a, 6 3 b respectively It is connected to the output circuit 68. That is, the photodiodes 62a and 62b are connected in parallel. Of course, in addition to the above method, there are many methods for sharing the output circuit 6 8 with many photodiodes 62. For example, only One photosensitive diode is connected to the output circuit 68, and other photosensitive diode systems are connected to the output circuit 6 8 through the above one photosensitive diode connected to the output circuit 68. Using the method of serial connection is not easy to read out the output signals of many photosensitive diodes independently without destroying the detection signals stored in other photosensitive diodes. Therefore, it is best to use the structure shown in the embodiment . Generally, in the enlarged type M In the O S-type solid-state imaging device, it is equivalent to the light-receiving part of the element in each unit crystal, that is, the output signal t (CNS) Λ4 ^ (2. 0X297 ^) _ 1〇? _ ---------- ^ ------ ίτ ------ 0 (Please read the notes on the back ^ ,. (Write this page) ~ A7 B7 306073 V. Description of invention (1〇5) Please read the notes on the back first. The item number is taken out by the amplifier transistor 6 4 set in the unit cell. Therefore, during amplification, the unevenness of the threshold voltage of the amplifying transistor 65 overlaps the signal. Therefore, even if the potentials of the photodiodes 6 2 in each unit cell are the same, because the amplifying transistors of the unit cell that the photodiode is in are separated, and the threshold voltage of each amplifying transistor 64 Not the same, so the output signals are not the same. If the captured image is reproduced, noise corresponding to the uneven threshold of the amplifier transistor 64 is generated. As mentioned above, the threshold voltages of the amplified transistors 64 of each unit cell are different, and there is an inherent voltage in each unit cell, so it becomes a noise distributed in position fixed to the regenerated image, that is, Second-element noise. Because the position of the noise is fixed on the screen in the second-dimensional space, it is called fixed pattern noise. In the above description, it has been stated that the Central Sample Bureau of the Ministry of Economics and Technology Beigong Consumer Cooperative Cooperative System. Therefore, in this embodiment, a noise removal circuit that suppresses fixed pattern noise is provided to replace the conventional circuit diagram of Figure 1. Shown is the circuit formed by the signal transmission transistor and storage capacitor of the output section. The noise removal circuit in Figure 5 7 is a double sampling type circuit that calculates the difference between the signal and noise in the voltage domain. However, noise removal "The type of the road is not limited to the relevant double sampling type, and various other noise removal circuits can also be used. The following description will refer to the timing chart in FIG. 6 2 to illustrate the use of the invention with the above noise cancellation circuit. The action of the MO S solid-state imaging device. Because the common sink terminal 20 of the load transistor 9, the common gate terminal 36 of the transistor 28 of the impedance conversion circuit, and the common source terminal 38 of the clamp transistor are driven by DC, so at this timing Not shown in the chart. That is, the transistors that make up the impedance conversion circuit 2 8-1, · 2 8 — This paper uses the Chinese National Standard (CNS> A4 specification (210X297 mm) _ 1〇8 _ Male Worker, Central Central Bureau of Economic Affairs Printed by consumer cooperatives A7 _B7__ V. Description of invention (l〇6) 2, . . . . . . . . The voltage of the common gate terminal 36 is in a high-level state when the MOS solid-state imaging device is in operation, and is often turned on. Clamp transistor 4 0 — 1, 4 0 — 2. . . . . . . . . . The voltage of the common source terminal 3 8 often becomes a low potential when the MOS solid-state imaging device operates. Since the potential of the common source terminal 3 6 becomes a high level, the transistors 2 8 — 1, 2 8 — 2 of the impedance conversion circuit . . . . . . . . . It often becomes continuity ’with vertical signal lines 8-1, 8-2. . . . . . . . . . The transmitted signal level (voltage level) becomes the corresponding driving transistor 26 — 1 ’26 — 2. . . . . . . . . . . Therefore, the vertical signal line 8-1, 8-2. . . . . . . . . .  From transistor 26 — 1, 26-2. . . . . . . . . . And transistor 28-1, 2 8 — 2. . . . . . . . . . The signal level transmitted by the circuit becomes the corresponding output voltage signal. As shown in the figure, transistors 26-1, 26-2, ... . . . . . And transistor 2 8 _ 1, 2 8 — 2. . . . . . . . . . In each case, the corresponding pair of transistors are connected in series with their source and sink connected to the positive side of the system power supply (a positioning standard DC voltage) and the ground level side. If the transistors 28-1, 28-2 . . . . . . . . . . When conducting, it is connected with the vertical signal line 8 -1 * 8-2. . . . . . . . . . The signal level sent by Fu becomes the corresponding driving transistor 26-1, 26-2. . . . . . . . . And it can output voltage within a range of direct voltage. In other words, transistor 26-1 · 26-2. . . . . . . . . . And transistor 2 8 — 1, 2 8 — 2. . . . . . . . . . The impedance conversion will correspond to the vertical signal lines 8_1, 8-2. . . . . . . . . . The voltage signal of the transmitted signal level is supplied to the noise cancellation circuit. From the transistor 2 6 — 1, 2 6-2. . . . . . . . . . And transistors 2 8 a 1, 2 8 — 2. . . . . . . . . . The paper format of the input paper produced by the impedance conversion circuit is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -109 — (please read the precautions on the back side to write this page) -Binding A7 A7 Central Ministry of Economic Bureau of Standards and Staff Consumer Cooperative Seal ___B7_ V. Description of the invention (107) via the corresponding vertical signal lines 8-1, 8-2. . . . . . . . . . The set sample holding transistor 3 0 — 1, 3 0 — 2. . . . . . . . . Transmitted to the same corresponding to the vertical signal line 8-1, 8-2. . . . . . . . . Clamp capacitors set 3 2 — 1, 3 2 — 2. . . . . . . . . . . When the sample holds the transistor 30-1 * 30-2. . . . . . . . . . When turned on, the output from the impedance conversion circuit is transferred to the corresponding clamp capacitor 3 2-1, 3 2-2. . . . . . . . . . And stored in it. If the sample holding capacitor 3 0 — 1, 3 0-2. . . . . . . . . . When it becomes an open circuit, the transmission from the vertical signal line 8-1, 8-2 can be stopped. . . . . . . . . . The output produced. In the imaging operation of this device, the transistors constituting the impedance conversion circuit 28-1 * 28-2 «. . . . . . . . . The voltage of the common gate terminal 36 becomes a high-level state, and often becomes an on-state • Clamp transistor 4 0-1, 40-2. . . . . . . . . . The voltage of the common source terminal 38 often becomes a low level. In this state, after applying an address pulse wave of a high level (logic signal level) to the horizontal address line 6 _1, the unit cell P1-1-connected to the horizontal address line 6-1 1, P1 — 1-2,. . . . . . . . . The vertical selection transistor 6 5 becomes conductive, and the amplification transistor 6 4 and the load transistor 9-1, 9-1. 2. . . . . . . . . . Form the source follower circuit. The voltage of any photodiode selected by the selection transistor 6 3 a and 6 3 b in the photodiode 6 2 a 6 2 b can be applied to the gate electrode of the amplifying transistor 64. The amplifying transistor 64 amplifies the voltage applied to the gate electrode and supplies it to the sink electrode, so the selection of the transistor 6 3 a, 6 3 b selects the size of the paper and the Chinese National Standard (CNS> A4 specification 210X297mm) _ HQ _ II III Pack II I Order II cable (please read the notes on the back first *. . . (This page) 1. The Central Standards Bureau of the Ministry of Economic Affairs cooperates with the industrial and consumer cooperation to print A7 B7. 5. Description of the invention (1〇8) The photodiodes 62a, 62b can correspond to their own units The voltage of the light-receiving diode is supplied to the vertical (row) signal lines 8-1, 8-2. . . . . . . . . . , Corresponds to the vertical signal line of the unit cell. In the noise cancellation circuit, the samples of its constituent elements hold transistors 3 0-1, 3 0-2. . . . . . . . . . The common gate 3 7 becomes the high level to keep the sample 3 0-1, 3 0-2. . . . . . . . . . Become continuity. In this way, the vertical signal lines 8-1, 8-2. . . . . . . . . . The resulting output is, strictly speaking, a vertical signal line 8-1, 8-2 that transforms the impedance through an impedance conversion circuit. . . . . . . . . . The output is transferred to the clamp capacitor 3 2 — 1, 3 2-2. The noise cancellation circuit uses the clamp transistors 4 0-1, 4 0-2 of its constituent elements. . . . . . . . . The potential of the common gate 4 2 becomes a high level within a certain period of time in a certain period, so that each clamp transistor 4 0-1, 4 0-2. . . . . . . . . . Become continuity. In this way, the clamp transistor 4 0 — 1, 4 0 _ 2. . . . . . . . . . Clamp capacitors 3 2-1, 3 2 _ 2. Clamping capacitors that make up the noise cancellation circuit . . . . . . . . . With sample holding capacitor 34 — 1 * 34 — 2. . . . . . . . . . The potential of the connection point becomes the low level of the applied voltage level of the common source terminal 38 between the certain time width, and the sample holding capacitors 34-1, 34-2. . . . . . . . . . The potential drops to the voltage level of the common source terminal 38. That is, the sample remains electric 'container 3 4 — 1.  ’3 4-2’. . . . . . . . . One end is grounded and becomes the ground level. "In this state, the sample holding capacitor 34-1, 34-2. . . . . . . . . . The charge becomes the low level of the common source terminal 3 8 voltage level -----------------. 玎 ------ ^ / (Please read the precautions on the back first, > write this page) This paper scale is applicable to China National Standard (CNS) A4 specification (210X 297mm) -HI-Central Standard of the Ministry of Economic Affairs Bureau staff consumer cooperatives printed policy A7 B7 V. Invention description (1〇9) standard, so the sample holding capacitor 3 4-1, 3 4-2. . . . . . . . . . Among them, the stored charge is discharged and becomes a stable state at a low level. This level is the level in the reset state. After a time equivalent to the certain time width, the reset state is released. Then, after applying a reset pulse wave of a high level on the reset line 7_1, the unit cell P1 — 1—1, P1 — 1 — 2 connected to the reset line 7_1. . . . . . . . . . The reset transistor 66 becomes conductive. Since the reset transistor 6 6 is a circuit that resets the charge on the input side of the amplifying transistor 64, the charge of the input terminal of the output circuit 68 is reset due to the reset. That is, the input of the output circuit 68 becomes zero. Therefore, the output circuit 68 outputs only the output component of the amplifying transistor 64 of its constituent elements. In this state, the output component of the amplifying transistor 64 is a noise component corresponding to the threshold unevenness of the amplifying transistor 64. As such, due to the unit cell Pl-l-l, P1-1-2,. . . . . . . . . After resetting, the output circuit 6 8 generates the output component of the amplifier transistor 6 4 when there is no signal charge in the photosensitive diode 6 2, that is, the noise component corresponding to the uneven threshold value of the amplifier transistor 6 4 , Is the output signal. Then, the clamp transistor that makes up the noise cancellation circuit is 4 0 -1 > 40-2. . . . . . . . . . The potential of the common gate 4 2 becomes a low level (logic signal level), so that the clamping transistor 40 — 1, 4 0-2-. . . . . . . . . Become open. Because the clamp transistor 40-1 > 40-2. . . . . . . . . . Becomes a broken circuit, so the composition of the noise cancellation circuit is based on the paper standard of China National Standard (CNS) A4 (210X297mm) -112---------- ^ ------ lτ- ----- ^ ί · '' (Please read the precautions on the back to write this page) A7 ___B7_ printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs 5. Description of the invention (110) Clamping capacitors for elements 3 2 — 1, 3 2 — 2. . . . . . . . . . Hold the capacitor 34-1, 34-2 with the sample. . . . . . . . . . The connection point is separated from the common source terminal, and the sample holding capacitors 34-1, 34-2. . . . . . .  … Becomes vertical signal lines 8-1, 8-2. . . . . . . . . . The state of the generated output. Therefore, the noise components appearing on the vertical signal lines 8-1, 8-2 are stored in the clamping capacitors 32-1, 32-2. . . . . . . . . . Hold the capacitor with the sample 3 4 — 1, 3 4 — 2. . . . . . . . . . In the formed series capacitor. The timing of the clamp is when the clamp pulse is cut off, that is, between the reset pulse and the PD selection pulse. After the noise component is stored in this way, the process of reading out the signal component is started. The unit cell P1 — 1 — 1 ’P1 — 1 — 2’. . . . . . . . . In the middle, after resetting, signal charges are stored in the photodiodes 62a, 62b, and then read out. At the time of reading, at each step of storage of the noise component, the photodiode 6 2 a is read out first, and then the photodiode 6 2 b is read out after the end of the storage step of the next noise component. After the storage step of the noise component is finished, the photodiode 6 2 a is read out. Proceed alternately. When reading the signal charge stored in the photodiode 6 2 a, a high-level selection pulse wave is applied to the photodiode selection line 2 2 _1. So, from the unit cell P 1 — 1-1, P 1 — 1 — 2. . . . . . . . . The output signal of the photodiode 6 2 a in the “output circuit 6 8” (that is, the “signal charge component + noise component * "), and each unit cell P1 — 1—1, PI — 1 - 2. . . . . . . . . . Enlarged transistor 64 inside to enlarge the size of this paper, using the Chinese standard (CNS) A4 (210X297mm) -113---------- approved clothing ------ 1T- ----- ^ (Please read the notes on the back Ϊ5. . . (Fill in this page) 1. A7 B7 printed by the Beigong Consumer Cooperative of the Central Department of Economics of the Ministry of Economic Affairs 5. Description of the invention (m) and supplied to the vertical signal line 8-1, 8-2 9 corresponding to the unit cell · ○ As mentioned above, because the clamping capacitors 32 — 1, 32_2. . . . . . . . . . With sample holding capacitors 3 4 — 1, 3 4 — 2. . . . . . . . . .  Noise components are already stored in the formed series capacitor, so the clamping nodes 41-1 and 41-2 at the connection point of the series capacitor . . . . . . . . . Only the vertical signal lines 8 _ 1, 8 _ 2 appear. . . . . . . . . . The voltage change component, that is, the signal that subtracts the noise component from the 'signal component + noise component ^, that is, the detection output corresponding to the light receiving amount of the photodiode 6 2 a without fixed pattern noise , That is, the voltage of the signal component * As such, first read ^ noise component ', and then read the' signal component + noise component # ', then you can remove the random noise caused by the reset action at the same time. Then, the sample holding transistor 30-1, 30-2, ..., the potential of the common gate 3 7 becomes a low level. In this way, each sample holds transistors 30-1, 30-2. . . . . . . . . . It becomes an open circuit, and the vertical signal lines 8-1, 8-2 are cut off due to the open circuit. . . . . . . . . . The output signal supplied to the noise cancellation circuit. Therefore, the clamp capacitor 3 2 — 1, 3 2 — 2. . . . . . . . . . With sample holding capacitor 3 4 — 1, 34-2. . . . . . . . . . The sampling performed by the tandem capacitor formed is ended, and each clamping capacitor 3 2-1_ * 32-2 ·. . . . . . . . . With sample holding capacitors 34-1, 34-2. . . . . . . . . . The series capacitor formed constitutes the previously stored charge. Therefore, in the sample holding capacitor 3 4-1, 3 4-2. . . . . . .  This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) -114-t-- (Please read the notes on the back first 1. (Fill in this page) Order A7 B7 Printed by the Employees Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economy V. Description of invention (l! 2)… The storage appears in the box section 4 1 — 1, 4 1 — 2. . . . . . . . . . No noise voltage, and keep it. Then, select transistors 12-1, 12-2 at the level. . . . . . .  ... the horizontal address pulse wave is applied in sequence and read from the signal output terminal (horizontal signal line) 15 and stored in the sample holding capacitors 34_1, 34-2. . . . . . . . . . The noise-free photodiode 6 2 a (or 6 2 b) signal. In this way, only the ^ noise component is read out first, and then, the `` signal component + noise component '' is read out and only the pixel signal component of each unit cell is generated, and the pixel signal component is passed through the horizontal address Circuit 13 controls the on-off transistors 12-1, 12-2 according to the reading sequence of the TV scanning sequence. . . . . . . . . . It is output at the signal output terminal 15 so it can generate pixel signals without fixed pattern noise. In this way, the signal reading of the photodiode 6 2 a is completed. After the signal of the photodiode 6 2 a is read, it is the signal of the photodiode 6 2 b. First, a high-level address pulse is applied to the vertical address line 6-1. At this time, instead of applying a selection pulse on the photodiode selection line 2 4 -1 instead of the photodiode selection line 2 2-1, the photodiode 6 2 b is output from the output circuit 6 8 output signal. Other actions are the same as the above series of actions when the photodiode 6 2 a reads the signal. In the future, ask questions about the horizontal address lines 6-2, 6-3. . . . . . . . . .  By repeating the above operations, you can take out all the unit cells configured in the form of a second element. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) -115-Pack II-order I 1 III line (please read the back first Please pay attention to this article) (1) The Central Sample Bureau of the Ministry of Economic Affairs, Zhengong Consumer Cooperative Co., Ltd. A7 B7 5. Signal of the invention (113). In the conventional device, the unit cell is equivalent to one pixel, so 'when the operation step of reading out the detection signal of the photodiode in the cell is only performed once in a frame period, it cannot As in the MO S type solid-state imaging device used in the present invention, the output circuit of the unit cell with a structure of many pixels corresponding to the unit cell can only read out one pixel, that is, only one photosensitive two The detection signal of the polar body cannot read out the detection signals of many photosensitive diodes in the unit cell within one frame period. However, according to the driving method of the MOS solid-state imaging device according to the embodiment of the present invention, the vertical selection transistors 6 can be respectively selected in the horizontal extinction periods of the odd field and the even field within one frame period of the television mode. 5 Turn on once to operate the output circuit 68. At the first time (the period when the odd-numbered field corresponds to the horizontal extinction period of the retrace line scanning position of its own pixels), the detection signal of the photodiode 6 2 a can be read out. The detection signal of the photodiode 6 2 b is read out at the time of the even field (corresponding to the horizontal extinction period of the scanning position of the retrace line of its own pixels), so it can drive the MO SM solid-state imaging device with unit cell miniaturization. In this way, if the output circuit is not operated twice or more within one frame period, the detection signals of all the photosensitive diodes cannot be read. If the output circuit is not reset after reading once and before the next reading, the signal from the previous reading is superimposed on the reading signal from the next reading. The MOS solid-state imaging device of this embodiment is characterized in that the reset transistor 66 for charging and discharging is connected to the gate electrode of the amplifying transistor 64, and the selection transistor 6 3 is reset by the photosensitive diode to reset the photosensitive diode Potential · At this time, this paper scale is applicable to China Pujia Standard (CNS) A4 specification (210X297mm) -116-^-(please read the note 1 on the back first, fill in this page). A7 ______B7__ printed by the Beigong Beigong Consumer Cooperative. V. Description of the invention (ll4) Compared with the way that the photosensitive diodes 6 2 a and 6 2 b are connected to one amplifying transistor 6 4 respectively, the electricity per unit cell can be reduced Number of crystals. In this embodiment, there are two photosensitive diodes in the unit cell that constitute the light-receiving part. The two photosensitive diodes share the same set of output circuits. Therefore, the MO S solid-state imaging device of this embodiment is applied to a TV During imaging, the charge signal is read out by the amplifying transistor 64 during one horizontal extinction period of the TV, and it is easy to drive. In short, this embodiment is characterized in that the readout direction is different from the common direction. The following describes the relationship between the timing shown in Figure 62. The sequence is as follows: (1) The rise of the vertical address-the fall of the reset pulse wave-the fall of the clamp pulse wave-the rise of the pulse wave selected by the photodiode-the choice of the pulse wave by the photodiode Decrease-sample hold pulse drop-vertical address drop (2) sample hold pulse wave rise-photodiode select pulse wave rise (3) clamp pulse rise-photodiode select pulse wave The rise of the vertical address, the sample keeps the rise of the pulse wave, the rise of the clamp pulse wave, and the rise and fall of the reset pulse wave can be arbitrary, but it is preferably in the following order. Vertical address rise-sample hold pulse rise-clamp pulse rise-reset pulse rise as described above, follow the action in Figure 6 2 because the clamp node 4 1 appears to be reset When there is no signal (that is, there is no output signal component of the photodiode, but only noise components) 'and when there is a signal (that is, the photodiode The paper standard applies to the Chinese National Standard (CNS) A4 specification (210χ297 PC) _ 117---------- ^ ------, 玎 ------ ^ (please read the notes on the back first '> write this page) ~ Central Standard of the Ministry of Economic Affairs Printed at 306073 at _B7____ by the Consumer Cooperative of the Bureau. V. Invention description (output signal component + noise component) The voltage of the difference, so it can compensate for the fixed pattern noise caused by the uneven threshold of the amplifier transistor 64. That is, the circuit formed by the clamp transistor 30, the clamp capacitor 3 1, the sample holding transistor 40, and the sample holding capacitor 3 4 becomes a noise cancellation circuit. The noise cancellation circuit of this embodiment follows through the source The impedance conversion circuit 26, 28 formed by the circuit is connected to the vertical signal line 8. That is, the vertical The wire 8 is connected to the gate of the transistor 26. Because the capacitance of the gate of the transistor 26 is very small, in fact, the amplified transistor 64 of the cell only needs to charge the vertical signal line. Therefore, the CR The short time constant can immediately become a normal state. Therefore, it can speed up the reset pulse, and the photosensitive diode selects the timing of the pulse wave application, which can perform noise elimination in a short time. In the case of TV signals, noise elimination It must be carried out within the horizontal extinction period of the TV scan. Therefore, as in this embodiment, the noise can be correctly eliminated in a short time, which has great advantages. And because the noise included in the noise elimination action is output and ^ Signal + noise # When output, the impedance of the noise cancellation circuit observed from the unit cell is the same, so the noise can be eliminated correctly. That is, * when ^ noise component ^ is output, it is the same as ~ signal component + noise When the component ^ is output, the impedance of the noise cancellation circuit when viewed from the unit cell is approximately the same. Therefore, the * noise component becomes approximately the same at both outputs, and the difference between the two can be calculated correctly Removal of impurities Only the signal components are taken out. Therefore, the noise can be eliminated accurately. If the noise cancellation circuit is observed from the unit cell, only the gate capacitor can be observed in the impedance. This paper scale uses the Chinese National Standard (CNS >; A4 specification (210X 297mm) -118---------- ^ ------ 1T ------ ^ (please read the notes on the back to write this page) 1. A7 ______B7_ printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economy V. Invention description (116) The capacitance of this capacitor is very small, so it can eliminate noise in a short time. The following describes the MO S in this embodiment The structure of the solid-state imaging device. It can be seen from the circuit structure in FIG. 57 that the clamp capacitor 32 and the sample holding capacitor 34 are directly connected to each other, so they can be layered on the same surface, and the unit cell can be miniaturized. As shown in FIG. 24, a first electrode 76 is formed on the silicon substrate 72 via the first insulating film 74 to form a sample holding capacitor 34, and a second electrode 76 is formed on the first electrode 76 via the second insulating film 78 The electrode 80 constitutes a clamp capacitor 32. As can be seen from the figure, the first electrode 76 becomes a common electrode, and the clamping capacitor 32 and the sample holding capacitor 34 are formed by stacking, so that the same capacitance can be generated with 1/2 area when they are formed separately. In this embodiment, the unit cell P1-1-1, P1-1-2. . . . . . . . . . Peripheral circuits such as the vertical address circuit 5, the horizontal address circuit 13 and the like are formed on a semiconductor substrate provided with a P + -type impurity layer on a P-type substrate. Figures 25A and 25B show the cross-section of such a semiconductor substrate Figure. As shown in the figure, a cell element such as a photodiode 83 is formed on a semiconductor substrate provided with a p + type impurity layer 8 2 on a p-type substrate 81. In this way, the semiconductor substrate can be formed. The diffusion potential of the P- / P + boundary can be used to prevent a part of the dark current that occurs on the P_ type substrate 81 from flowing into the P + side. The following briefly explains the results of detailed analysis of the electron flow. For P — This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) -119---------- approved clothes ----- 1T ------. ^ (Please read the notes on the back ^ fill in this page) * A7 _____B7 printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. For the electrons on the invention description (in) side, the thickness of p + impurity layer 8 2 2 Become a multiple of the ratio of the concentration of P + and p-, that is, L · p + / p —. That is, as shown in Fig. 25B, the distance from the p-substrate 81 of the dark current generation source to the photodiode 83 becomes a farther p + / p-fold. In the dark current, in addition to the current flowing from the deep part of the substrate, there is also a current occurring in the depletion layer near the photodiode 83. The magnitude of the dark current occurring in the depletion layer is approximately the same as the magnitude of the dark current flowing from the deep part of the substrate. The thickness of the depletion layer is about 1 * The dark current flowing from the deep part of the substrate flows again from a depth of about 100. This depth is called the electron diffusion distance in the p-type semiconductor. The dark current has nothing to do with the difference in thickness. The reason for the same is that the probability of occurrence of dark current per unit volume in the depletion layer increases. The dark current generated in the depletion layer cannot be separated from the signal current in principle. Therefore, when it is desired to reduce the dark current, it is achieved by reducing the components flowing from the deep part of the substrate. Since a cell is formed on the semiconductor substrate provided with the p + -type impurity layer 7 2 on the p-type substrate 7 1, it is possible to prevent the fluctuation of the substrate potential due to the occurrence of dark current. As a result, the noise removal circuit can be operated normally. Because the thickness of the P-type substrate is large, the resistance is small, and the noise removal circuit can be surely operated. Because the component temperature rises, the components from the deep part of the substrate increase rapidly. This phenomenon is very important. The degree is that the composition from the deep part of the substrate is sufficiently smaller than the composition generated in the depletion layer. Specifically, * the dark current from the deep part of the substrate is less than about 1 digit less than the component from the depletion layer. That is, the p + / p_ is set to 10 so that the deep part of the substrate becomes approximately the paper size. Standard (CNS) A4 specification (210X297mm) -120-~ binding line (please read the notes on the back ^ 楱 write this page) ~ Printed by the Ministry of Economic Affairs Central Bureau of Industry and Commerce Beigong Consumer Cooperative A7 ____B7 V. Description of invention (118) 1/1 〇. The dark current from the deep part of the substrate can be said to be completely absent in the semiconductor substrate composed of the n-type substrate and the p-type well, but in order to make it the same level as this semiconductor substrate, it is necessary to set Ρ + / Ρ- It is 1 0 0 so that the dark current from the deep part of the substrate becomes about 1/10. In the conventional C CD with practical performance, the impurity of the n-type buried channel is about 10 iec m-3, and the P-type layer of the buried channel surrounding the stable diffusion layer that manufactures the buried channel (in the This is a P-type substrate) The impurity concentration is about 1 0 15cm_3. When P + / P_ is 10, the concentration of the P + layer is about 1 Oiecm_3, and when ρ + / ρ- is 100, it is about 1017cm-3, which becomes the concentration of impurities in the n-type buried channel. About 10 cm_3 is about the same or inverted by 1 digit. Therefore, the practiced CCD does not consider the use of this impurity concentration P + layer at all. If the concentration of the P-layer is reduced, the sheet resistance of the substrate increases. However, the magnification type MO S-type camera device can freely set the value of P + / P-1 without reducing the concentration of the P-layer because there is no buried channel of CCD. Lowering the resistance of the P-type well and improving the structure of the semiconductor substrate composed of the n-type substrate and the p-type well can also constitute a unit cell. Fig. 26 is a cross-sectional view of a unit cell using a ρ + well 86 with a low sheet resistance on an n-type substrate 85. Figure 27 is a cross-sectional view of the unit cell of CC D. This paper uses the Chinese National Standard (CNS) A4 specification (210X297mm) -121----------- ^ ------ 1Τ ------ ^ (please read first Matters needing attention on the back 1 fill in this page) (printed A 7 B7 by the Beigong Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs 5. Description of the invention (119) For the manufacturing of Sui Ding, the n-type substrate of the unit cell of the CCD 8 7, The impurity concentration of the ρ-type well 86 and the n-type buried channel 8 9 are set to about 1 014 cm_3, about 1 〇13 cm_3, and about 1 〇iec m_3. Because the impurity concentration of the n-type photodiode 90 can be a certain It can be set freely within the range, so there is not much limitation in manufacturing. At the above impurity concentration, the sheet resistance value of the P-well 86 is about ΙΟΚΩ / Ο. Even with such a high resistance value, the noise of the CCD is still very high If the noise removal circuit is used in the amplified MOS imaging device, the sheet resistance value of the P-well is very important. The reason is that the potential of the P-well 856 caused by the reset pulse The time required to disturb the settling must be coordinated with the system to which the device is applied. When in TV mode * Set the horizontal retrace period During this period, the image signal is not transmitted. Therefore, it is necessary to reduce the disturbance of the potential of the P-well 86 caused by the reset pulse wave to a certain level during this period. Therefore, in the current TV In the NT SC mode of the method, the period allowed for the operation of the noise removal circuit is approximately 1 1 [# s] during the horizontal retrace period. • The disturbance of the potential of the P-well 856 must be settled to 0.  1 Around [m V]. β The minimum value of 0 · 1 [mV] is that the noise voltage output of the CCD is approximately set to this value. According to the analysis, in order to set the minimum value of 0 · 1 [mV] in a non-normal time of 1 1 [// s], the sheet resistance value of the ρ-type well 8 6 must be set to 1 KΩ / □ or less. This value is about 1/100 of the conventional CCD. This paper uses the Chinese National Standard (CNS) A4 (210X297mm) -122-I -------- ^-(please read the notes on the back and write this page afterwards). Sample A7 B7 printed by the Beigong Consumer Cooperative. V. Description of the invention (12〇) Therefore, the impurity concentration of the P-type well 8 6 must be set to about 100 times. As mentioned in the description of the P-type substrate, this concentration is impossible to apply on the CCD. Also, in the high-resolution TV method, the horizontal retrace period is 3.77 [#s], and the sheet resistance value of the p-type well 86 must be set to 3 0 0 Ω / □ or less. Other modifications include the formation of a high-concentration P + sandwich layer on the substrate and the formation of its surface with a P-type layer with a relatively low degree. Figure 28 is a structural diagram of a semiconductor substrate in which a P + type sandwich layer 9 2 is formed between a p-type substrate 91 and a P-type substrate 93. Figure 29 shows the structure of a semiconductor substrate in which a P + sandwich layer 96 is formed between an n-type substrate 95 and a P-type layer 97. This ρ + type sandwich layer can be realized by a high acceleration megavolt ion implanter. On the p-type layer, in addition to the photodiode 83, transistor, etc., which form the unit cell, peripheral circuits such as a horizontal address circuit and a vertical address circuit are formed. Figure 30 is the structure of a semiconductor substrate formed by surrounding the photosensitive diode hip 8 3 with a high-concentration p-well 1 0 3 and forming other parts on the n-type substrate 1 0 1 with other p-wells 1 0 2囵. Because of this structure, it is possible to prevent dark current from leaking into the photodiode 83. The semiconductor substrate 101 may also be a P-type substrate. The concentration of a part or all of the P-well forming the horizontal address circuit and the vertical address circuit around the cell is determined at the time of circuit design. Because it is different from the optimal value of the cell, it can also be formed into a P-type well that forms the imaging field. This paper standard uses the Chinese National Standard (CNS) A4 specification (210X297 mm) -123-binding line ί I.  (Please read the notes on the back and fill in this page) A7 B7 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of the Invention (121) Separate P-type layer 〇 No. 6 3 The picture shows the η-type substrate 1 0 5 A P-type well 106 forming the imaging field is formed, and a structure diagram of a semiconductor substrate separately forming other P-type wells 107 forming a peripheral circuit. With such a configuration, a P-type well suitable for each constituent element can be formed 〇 The above n-type substrate 1 0 5 may also be a p-type substrate. The sixth picture 6 shows the formation of a p + type sandwich layer 1 0 8 constituting the imaging field and the formation of a low concentration p-type layer on the n-type substrate 1 0 5 ] L 0 9, and the structure diagram of forming another P-type well 1 0 7 in the peripheral circuit part. In this way, a P-type well suitable for each component can be formed to prevent dark current leakage in the photosensitive diode hip. Type substrate 1 0 5 can also be ρ _ type substrate > As described above, according to this embodiment, since many (two in this case) adjacent to the vertical (CO 1 umn) direction are used, the unit cell of the output diode shares an output circuit. Area miniaturization 0 The number of photodiodes in the common output circuit is not limited to 2 but can also be more than 3 0 The modification example of the output circuit 6 8 can also be as shown in Figure 6 5 »Install vertical selection capacitor 6 9 Instead of vertically selecting transistors 6 6 According to this structure, the number of transistors constituting the unit cell per unit cell can be reduced »so the number of transistors required per pixel can be reduced» so the miniaturization of the cell is more advantageous. After applying a high level voltage on the address line 6-1, the gate voltage of the amplifying transistor is shifted to the high voltage side 0. Because the amplifying power of the adjacent unit pixels, please read the back% first thing. China National Standards (CNS) A4 specification (210X297mm) _ 124-A7 B7 Printed by the Ministry of Economic Affairs Central Standards Bureau Negative Consumer Cooperative V. Invention description (I22) The gate voltage of the crystal continues to remain low > The signal of the amplified transistor that is located on the vertical signal line 8-1 appears. Because the output of the unit cell is output through the noise cancellation circuit, the fixed pattern of the uneven threshold value of the amplified transistor that matches the unit cell can be removed Noise. In this embodiment > because the output of the unit cell is output through the noise cancellation circuit of the present invention capable of high-speed operation, even when the MOS detector is applied to a video camera device for animation, it can still be used in each Frame or per-field within a limited period of time to remove the fixed unit noise of the unit cell's amplified transistor threshold is not uniform, can produce an amplified MOS solid-state imaging device that can be fully utilized even in television mode In the noise cancellation circuit, because the clamping capacitors 3 2 — 1 3 2 — 2… (hereinafter collectively referred to as 3 2. The other male parts with added words are also the same) and the sample holding capacitor 3 4 are directly connected to each other Close to it, it can be formed by stacking on the same surface, and the unit cell can be miniaturized. The noise cancellation circuit has an impedance conversion circuit and the output of the unit cell is input through the impedance conversion circuit »Therefore, the noise component At output and% signal component + noise component at output 9 The impedance of the noise cancellation circuit observed from the unit cell is approximately the same. Therefore »y the noise component becomes approximately the same at both outputs» Calculate the two The difference «can remove the noise component correctly and only take out the signal component 0. Therefore t can correctly remove the noise 0. Observing the noise cancellation circuit from the unit cell can only observe and observe the gate capacitor from the point of view of impedance , And its electric capacity is very small »So it can eliminate noise in a short time. That is, in the noise canceling circuit of this embodiment > from the transistor 26, the paper size is not in accordance with the Chinese National Standard (CNS> A4 said grid (210X 297mm) -125-_B7___ V. Invention description (l23 ) —1 and 28-1, 26-2 and 28-2, 26-3 and 28-3. . . . . . . . . . The impedance conversion circuit formed becomes transistors 2 8-1, 2 8-2, 2 8-3. . . . . . . . . . The switch that turns on and off the operation of the impedance conversion circuit, and the transistors 26-1, 26-2, 26-3. . . . . . .  … Becomes a vertical signal line 8-1, 8-2, 8-3. . . . . . . . . .  The composition of the generated output signal. Transistor 26 — 1, 26 -2 > 26-3 *. . . . . . . . . Finely formed on the semiconductor substrate, the capacitance of the gate capacitor can be reduced, and as a result of reducing the capacitance, the time constant of CR when the noise cancellation circuit operates can be shortened • The reset pulse can be accelerated The light-sensitive diode selects the application timing of the pulse wave and can complete the noise elimination action in a short time. It is very effective when it is used to eliminate noise action within the horizontal extinction period of the TV scan, such as TV signals. When the noise cancellation circuit of this embodiment was printed by the Central Sample Bureau of the Ministry of Economic Affairs, the noise cancellation circuit of this embodiment was ICized, because it was composed of a p-type impurity matrix and a P + type impurity layer formed on the P-type impurity matrix. The substrate is used as a semiconductor substrate to form a unit cell, so it can reduce the dark current invading into the unit cell, and the potential on the surface of the substrate can be fixed, so that the noise elimination circuit can be reliably operated, and the noise can be reliably removed. Therefore, according to the present embodiment, it is possible to provide a noise reduction circuit that is miniaturized, can perform high-speed operation, has reliable noise elimination performance, and has high reliability. Install the noise cancellation circuit in the amplified MO S detector to provide a compact and high-speed, high-reliability, high-reliability amplified MO S solid-state imaging device. This paper scale is applicable to the Chinese National Standard (CNS) A4 (2 丨 0X297mm> -126-Printed A7 B7 by the Employees ’Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention Description (I24) The following description Embodiment 26. This embodiment is an embodiment in which the noise cancellation circuit of Embodiment 25 is modified. Figure 6 is a circuit of an imaging device using the amplified MOS detector of Embodiment 26 Structure diagram. In this embodiment, the circuit structure near the unit cell P 1 — i — j is the same as in the 25th embodiment. Each vertical signal line 8 — 1, 8 — 2. . . . . . . . . . The other end via its corresponding clamping capacitor 131-1, 131-2. . . . . . . . . . .  Clamp transistor 1 3 2 — 1, 1 3 2 — 2. . . . . . . . . . , Level selection Transistor 1 2 — 1, 1 2-2. . . . . . . . . . Connect to the signal output (horizontal signal line) 1 5. Unlike the noise cancellation circuit in the 0 A 1 embodiment, in this embodiment, the clamping capacitors 1 3 1-1, 1 3 1-2. . . . . . . . . . Directly connected to its corresponding vertical signal line 8 — 1, 8_2. . . . . . . . . . . In each clamp capacitor 1 3 1 _ 1, 1 3 1 — 2. . . . . . . . . . The corresponding samples hold transistors 1 3 3 — 1, 13 3 _ 2. . . . . . . . . . Connect the corresponding clamp transistors 1 3 2-1, 13 2-2, ... ... the sucker · clamp transistors 132-1, 132-2. . . . . . . . . . The source is connected to the common source terminal 1 4 1, and the gate is connected to the common terminal 1 4 2. Sample holding transistor 1 3 3 — 1, 1 3 3-2. . . . . . . . . . Transistor selection level 12-1, 12_2. . . . . . . . . . The connection point is via the sample holding capacitor 1 3 4 — 1, 1 3 4 — 2 ’. . . . . . . . . Ground. The following refers to the timing chart in Figure 6 7 to illustrate that the above MO S-type solid camera paper size is applicable to the Chinese national standard (CNS> A4 specification (210X297mm) -127-^-(please read the notes on the back first 1 fill in This page) Order A7 B7 printed by the Beigong Consumer Cooperative of the Central Bureau of Samples of the Ministry of Economy V. Description of the invention (l25) The action of the image device. Because the common sink terminal of the load transistor 9 is the common source of the clamping transistor The terminals 1 4 1 are driven by DC ', so they are not shown in the timing diagram. The unit cell system is described using the unit cell shown in Figure 61. The high-level address pulse is applied to the horizontal address line 6-1 After the wave, the unit cell Pl — l_l, P1-1 _ 2 connected to the address line 6 — 1 . . . . . . . . . The vertical selection transistor 6 6 is turned on by the amplification transistor 6 2 and the load transistor 9-1, 9-2. . . . . . . . . . Form the source follower circuit. Keep the sample transistor 133-1, 133-2. . . . . . . . . .  The potential of the common gate 1 4 3 becomes a high level to keep the sample 133-1, 133-2. . . . . . . . . . Turn on. Then, clamp the transistors 132-1, 132-2. . . . . . . . . . The potential of the common gate 142 becomes a high level to clamp the transistors 1 3 2 — 1, 1 3 2 — 2. . . . . . . . . . Turn on. Then, after applying the reset pulse wave of high level on the reset line 7-1, the unit cell P — l — 1-1, P — 1-1-2 connected to the reset line 7-1. . . . . . . . . . The resetting snow crystal 6 6 is turned on, and the charge of the input terminal of the output circuit 6 8 is reset. Therefore, the output circuit 6 8 outputs the noise component of the amplified transistor 6 4 with a non-uniform threshold value in conjunction with the no-signal charge of the photodiode 6 2. Then, the clamp transistor 132-1 · 132-2 is made. . . . . . .  The potential of the common gate 1 4 2 becomes a low level and cuts off the clamping transistor 132-1 * 132-2. . . . . . . . . . .  This paper scale applies the Chinese National Standard (CNS) A4 specification (210X297mm > -128-Sai-(please read the notes on the back first t fill in this page) Order A7 printed by the Ministry of Economy Central Standards Bureau Staff Consumer Cooperative _B7_ V. Description of the invention (l26) As such, it appears on the vertical signal lines 8-1, 8-2. . . . . . . . . The noise components are stored in the clamping capacitor 13 1-1, 131-2,. . . . . . . . . . In the unit cell P 1 — 1 — 1 ’P 1 — 1 — 2’. . . . . .  In ..., the photodiode 6 2 a stores the signal charge after reset, so it is read out. For this purpose, a high-level selection pulse wave is applied to the photodiode selection line 2 2-1. In this way, the output signal of the photodiode 6 2 a is output from the output circuit 6 8 (that is, * signal charge component + noise component #) 0, as described above, because the clamp capacitor 131 — 1 * 131 — 2 . . . . . . . . . . The stored and noise components in * are displayed on the clamping section 1 4 5 only from the vertical signal lines 8-1, 8-2. . . . . . . . . The voltage becomes cent, that is, the signal voltage of the "signal component + noise component #" minus the "noise component" without the fixed pattern noise. At this time, the sample holds transistors 133-1, 133-2. . . . . . . . . . Turn on, and hold the capacitor 134-1, 134-2 in the sample. . . . . . . . . . The same signal voltage β appears at the terminal. Then, the sample is held in the transistor 133-1, 133-2,. . . . . . . . . The potential of the common gate 1 4 3 becomes a low level and cuts off the sample holding transistor 133 — 1 ’133-2. . . . . . . . . . . Therefore, the noise-free voltage appearing in the clamp node can be stored in the sample holding capacitor 134 — 1 1 134 — 2 *. . . . . . . . . in. Then, select transistors 12-1, 12-2 at the level. . . . . . .  … Horizontal address pulses are applied in sequence to read from the signal output (horizontal signal line) 1 5 and stored in the sample holding capacitor 1 3 4 — 1. 210X297mm) _ 129-~ --------- approved clothing ------ 1τ ------ 0 (please read the notes on the back first Is. -. (Fill in this page) * Printed by the Employee Consumer Cooperative of the Central Department of Economic Affairs of the Ministry of Economic Affairs A7 _____B7_ V. Description of Invention (127) 13 4 — 2, . . . . . . . . The noise-free photodiode 6 2 a signal. Then, when a high-level address pulse is applied to the horizontal address line 6 _1, a high level is applied to the photosensitive diode selection line 2 4-1 instead of the photosensitive diode selection line 2 2_1 The selected pulse wave supplies the output signal from the output circuit 6 8 to the photodiode 6 2 b. Other actions are the same as above. After that, the same to the horizontal address lines 6-2, 6-3. . . . . . . . . .  By repeating the above operations, the signals of all the cells arranged in a quadratic shape can be taken out. As described above, in the noise cancellation circuit of this embodiment, the impedance conversion circuit adopted in the 25th embodiment is abolished. According to this structure, the noise can be reliably eliminated, and the fixed circular noise can be removed and only the signal is taken out. ingredient. The circuit structure is simplified because the impedance conversion circuit is abolished, and the circuit structure becomes smaller, which is more beneficial to miniaturization. The second 7th embodiment and the sixth and eighth images are the amplified MOS detectors using the second and seventh embodiments. Circuit diagram of the camera device. The circuit structure in the vicinity of the unit cell P 1 — i — j is the same as in the 25th embodiment. The 27th embodiment is an example in which the impedance conversion circuit of the 25th embodiment is connected to the noise cancellation circuit of the 26th embodiment. In this embodiment, the common source of the clamp transistors 1 3 2 is driven by DC. In the noise cancellation circuit of the 26th embodiment, if the fine paper size of the noise cancellation uses the Chinese National Standard (CNS) A4 specification (210X 297 mm) -130--------- -^ ------ 1T ------ i (please read the notes on the back ii first "fill in this page") A7 B7 Oxygen printing by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economy V. Description of the invention (128) 1 | When there is a problem with the accuracy »If the impedance conversion circuit of the second embodiment is provided in the input section of the second embodiment in this embodiment and the impedance of the unit cell is converted by impedance 1 * Only 1 1 is output with noise components» It is the same as the% signal component + 1 I of the noise component. The impedance of the noise cancellation circuit observed from the unit cell at the time of output becomes so large that please read 1 I. The same * makes the noise component in both states substantially the same Read the back 1 1 I »Form a noise cancellation circuit that can perform high-precision noise cancellation. 〇 I I%, 1 2 8 Example k Writing book 1 1 installed No. 6 9 The figure is the circuit structure diagram of the imaging device using the amplified MOS detector page 1 I of the 28th embodiment. The structure of the 1 I with the noise cancellation circuit changed in this device 0 The noise canceling circuit in the 2nd 8th embodiment will appear on the vertical signal 1 1 I line 8 — 1 8 — 2....... The charge is subtracted in the charge field by 1 1 to suppress noise. In the second 5th embodiment, the noise is eliminated in the voltage field, but this ...- 1 | In the embodiment, the noise is eliminated in the charge field. Ο The unit cell P 1 -i line I-j circuit structure is the same as in the second 5th embodiment 9 I 1 as shown in Figure 6 9 t In the second 8 8th embodiment, the noise cancellation circuit package 1 1 includes * Limiting transistor 1 5 0 — 1 1 5 0 — 2 *… …… »Limiter 1 1 Capacitor 1 5 2 — 1 * 1 5 2 — 2… t Limit reset transistor 1 1 Body 1 5 6 — 1 t 1 5 6 — 2…… > Limiting charge transfer capacitors, 1 I device 1 6 2 — 1 9 1 6 2 — 2 »……» Sink reset transistor 1 I 1 6 6-1 t 1 6 6 — 2 9…… 9 and Level selection transistors 1 1 1 1 2 — 1 »1 2 — 2»…… 〇1 1 1 ¾.  Printed standard on paper. 7 9 2 Printed by the Consumer Labor Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs 306G73 A7 B7 V. Description of Invention (129) Limiting Transistor 1 5 0 — 1, 1 5 0 — 2. . . . . . . . . . With vertical signal lines 8-1 ’8 — 2. . . . . . . . . . Become a one-to-one corresponding state setting. Limiting transistor 15 0 — 1 ’150 — 2. . . . . . . . . . The gate side is connected to the vertical signal line 8 _ 1 ’8 — 2. . . . . . . . . . The corresponding signal line in. The connecting end is the vertical signal line 8-1, 8-2. . . . . . . . . . Among the two ends, the load transistors 9 1 1, 9 2 . . . . . . . . The opposite end of the connecting side * Limiting transistor 1 5 0 — 1, 1 5 0 — 2. . . . . . . . . . The source side is connected to limiting capacitors 1 5 2-1, 1 5 2 — 2. . . . . . . . . .  In one, one end of a limiting capacitor corresponding to each transistor. Limiting capacitors 1 5 2 — 1, 1 5 2 — 2. . . . . . . . . . The other end is connected to the limiting pulse wave supply terminal 1 5 4. Limiting transistors 15 0 — 1, 150 — 2. . . . . . . . . . The source side and source side of the corresponding one of transistors 1 2-1 · 1 2-2,... Are selected by horizontal (row) transistors connected to the signal output terminal (horizontal signal line) 15. Level selection transistor 12-1, 12-2. . . . . . . . . . It is driven by the horizontal address pulse supplied by the horizontal address circuit 13. In order to reset the source potential of the limiting transistor 1 5 0-1, 1 5 0-2, ..., a limiting reset transistor is provided between the source of the limiting transistor and the limiting power supply electron 158 156-1, 156 —. . . . . . . . . . , And the transistor 1 5 6 — 1, 1 5 6 — 2. . . . . . . . . .  The gate is connected to the limiting reset terminal 160. That is, the limiting transistor 150-1 · 150-2. . . . . . . . . . The source of the paper is based on the transistor. The paper standard is applicable to the Chinese National Standard (CNS > M specifications (210X297 mm) -132---------- ^ II (please read the notes on the back t, fill in Page) D- * Line A7 _B7_ printed by Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (13 ()) 1 5 6 — 1, 1 5 6 — 2. . . . . . . . . . The source electrode and the sink electrode of the corresponding one of the electric crystal hips are connected to the limiting power terminal 1 5 8. Limiting reset electric crystal 15 6-1, 156-2. . . . . . . . . . The gate is connected to the limiting reset terminal 160, and the timing of the limiting reset pulse supplied from the limiting reset terminal 160 makes the limiting reset transistor 15 6-1, 156-2 . . . . . . . . . . Turn on and reset the limiter transistors 150-1, 150-2. . . . . . . . . . The source potential β each limiting transistor 1 5 0-1, 1 5 0-2. . . . . . . . . . The sink is connected to the limit charge transfer capacitance 162-1, 162-2 ’. . . . . . . . . Corresponding to the end. Limiting charge transfer capacitors 1 6 2 — 1, 16 2 — 2. . . . . . . . . . The other end is grounded · In order to reset the limiting potential of each limiting transistor 150_1, 150 — 2……, at each limiting transistor 150 — 1, 150 — 2. . . . . . . . . . The connection between the sink and the storage sink power terminal 1 6 4 is connected to the sink reset transistor 166-1, 166-2. . . . . . . . . . Corresponding transistors in Chinese • That is, each limiting transistor 150 — 1, 150-2 ’. . . . . . . . . The sucker consists of a reset transistor 1 6 6 — 1, 1 6 6 — 2. . . . . . . . . . In this case, one sink transistor corresponding to itself is connected to the storage sink power terminal 164 via the source and the sink of the sink transistor. Each transistor 166 — 1, 166-2 ’. . . . . .  The gate of… is connected to the reset terminal 1 6 8 of the sink. As described above, the characteristic of the noise cancellation circuit of the MOS detector of the 28th embodiment is that the voltage that will appear on the vertical signal line 8-1, 8-2 '......... through the limiting transistor 1 5 0 — 1, 1 5 0 — 2,… This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) -133---------- # ------ 1Τ-- ---- ^ ^ I (please read the notes on the back and fill out this page) A 7 B7 printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of Invention (131). . . . . . The gate capacitor is converted into a charge, and subtraction is performed in the charge field to suppress noise. The noise elimination circuit in the noise elimination method in the charge field is connected to the same unit cell P 1-i-j as in the 0A 1 embodiment shown in FIG. 57 to constitute a solid-state imaging device. The driving method of this embodiment will be described below. FIG. 70 is a timing chart showing the operation of this embodiment. Figure 7 1 shows the limiting transistors 150-1, 150-2. . . . . . . . . . The potential diagram. Here, the limiting transistors 150-1, 150-2. . . . . . . . . . It is a p-channel transistor. First, apply the high-level vertical address pulse on the horizontal address line 6-1 in the first row. Then, in each unit cell of the row, the vertical selection transistor 6 6 to which the unit cell belongs is turned on, and the amplification transistor 6 4 and the load transistor 9-1, 9-2 required by the unit cell are turned on . . . . . . . . . . Constitute the source follower circuit. Then, apply the limiting reset pulse wave to the limiting reset terminal 1 6 0 of the noise cancellation circuit to make the limiting reset transistor 156-1, 156-2. . . . . . . . . . Turn on, the limiting capacitor 1 5 2-1, 1 5 2 — 2. . . . . . . . . . The initial charge. Limiting reset terminal 1 6 0 After the limiting reset pulse is reduced, the limiting reset transistor 156-1, 156-2. . . . . . . . . . Open circuit, limiting capacitor 1 5 2 — 1, 1 5 2 — 2. . . . . . . . . . Become rechargeable. Then, the first limiting pulse wave s P 1 is applied to the limiting pulse wave supply terminal 1 5 4 · in the limiting capacitor 1 5 2-1, 1 5 2-2. . . . . . . . . . At the beginning, the paper standard is applicable to China National Standards (CNS) A4 (210X297mm) -134---------- Approved Clothing-(please read the notes on the back and fill in this page), · ιτ Line A7 printed by the Consumer Labor Cooperative of the Central Bureau of Standards of the Ministry of Economy ___B7_ V. Description of Invention (132) Before or after the periodization, a high-level reset pulse is applied to the reset line 7-1. In this way, the unit cell P 1 — 1 — 1 ’P 1-1-2 connected to the reset line 7-1 2. . . . . . . . . . The reset transistor 6 6 receives the reset pulse and becomes conductive, and resets the charge of the input terminal of the output circuit 68. Therefore, the noise component in which the threshold value of the amplifying transistor 6 4 is uneven when the signal charge in the photodiode 6 2 is matched is output from the output circuit 68. In the timing diagram of Figure 70, it is in the limiting capacitor 1 52 — 1, 1 52-2. . . . . . . . . . After the initialization, the above operation is performed to output the noise component in accordance with the uneven threshold of the amplifier transistor 64. Since the limiting reset transistor 1 5 6 — 1, 1 5 6-2, ... is broken, the first limiting pulse wave SP1 is applied to the limiting pulse wave supply terminal 1 5 4. Crystal 150-1, 150-2,. . . . . . . . . In the middle, the channel potential V QCh under the gate of itself beyond the no signal (that is, when there is only noise component) transfers the first limiting charge to the sink. At this time, a sink reset pulse wave is applied to the sink reset terminal 168. In this way, the conduction of the sink reset transistor 1 6 6 corresponds to the period of the time width of the reset pulse of the sink, so during the period of the time width, the sink potential is fixed at the voltage Vedd. Therefore, during this period, the first clipped charge is discharged to the sink-supply power supply terminal 164 through the sink reset transistor 166. Then, after applying a high-level selection pulse wave to the photosensitive diode selection line 2 2-1, the output signal of the unit cell's photosensitive diode 6 2 a is output from the unit cell output circuit 6 8 ( That is, the signal charge component and the noise component. Then, the second limiting pulse is applied to the limiting pulse wave supply terminal 1 5 4 and the paper standard adopts the Chinese National Standard (CNS) A4 specification (210X297mm)- 135---------- ^ I (Please read the notes on the back first t. Fill in this page Order Printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of Invention (133) Wave SP2. In this way, each limiting transistor 150-1, 150-2. . . . . . . . . . In the middle, the channel potential VQCh under the gate of the voltage beyond the voltage when the signal charge is present (the voltage with " ^ signal charge component + noise signal # present) is applied, and the second limit charge is transferred to the sink . At this time, because each absorber resets the transistor 1 6 6-1 ’1 6 6 — 2’. . . . . . . . .  Becomes an open circuit, so the second limiting charge is sent to the reset transistor 1 6 6 — 1, 1 6 6 — 2 connected to itself. . . . . . . . . . Limit of the absorption pole of the charge transfer capacitor 1 6 2-1, 1 6 2-2 ’. . . . . . . . . .  Then, horizontal selection pulses are sequentially applied to the horizontal selection transistors 1 2 — 1, 1 2-1 ’from the horizontal address circuit. . . . . . . . . From the signal output terminal (horizontal signal line) 15, sequentially extract a signal equivalent to one line. Then, apply the horizontal selection pulse wave to the horizontal selection transistors 1 2-1, 1 2-from the horizontal address circuit 13 2. . . . . . . . . . . In this way, the horizontal selection transistors 1 2-1, 1 2-2. . . . . . . . . In the receiving level selection pulse wave level selection transistor becomes conductive, which will correspond to the limiting charge transfer capacitor 1 6 2-1, 1 6 2-2. . . . . . . . . . The stored charge signal is supplied to the signal output terminal (horizontal signal line) 15. In this way, from the horizontal address circuit 13, the horizontal selection pulse wave is sequentially applied to the horizontal selection transistors 1 2-1, 1 2-2. . . . . . . . . . Therefore it will correspond to the charge storage capacitors 1 6 2 — 1, 1 6 2 — 2 stored in the limiter. . . . . . . . . . The signal of the electric charge is sequentially supplied to the signal output terminal (horizontal address circuit) 15 ', and as a result, a signal corresponding to one line can be sequentially extracted from the signal output terminal 15. Assume that the vertical bit of the high level of the horizontal address line 6-1 The front edge of the address pulse wave is based on the Chinese National Standard (CNS) A4 specification (210X297mm) -136-I binding line (please read the notes on the back 15-'fill this page) · Central Ministry of Economic Affairs Industrial and consumer cooperatives printed «.  A7 B7 5. Description of the invention (134) The bit Ϊ is P1, the trailing edge position is P2, the green 1 bit S is P 3 before the signal of the reset line 7-1, the trailing edge position is P 4, applied to the limiting reset The leading edge position of the limiting reset pulse wave of terminal 1 6 〇 is P 5, and the trailing edge position is P 6, which is applied to the first limiting pulse wave Sp 1 and the second limiting pulse of the limiting pulse wave supply terminal 1 5 4 In the pulse wave SP2, the leading edge position of the first limiting pulse wave SP 1 is P7, the trailing edge position P8, the leading edge position of the second limiting pulse wave SP2 is P 9, and the trailing edge position is P 10, which is applied to the suction pole complex If the position of the leading edge of the reset pulse of terminal 1 6 8 is P 1 1 and the position of the trailing edge is P 1 2, the time relationship of each signal position becomes P1 < P6 < P7 < P8 < P3 < P4 < P9 < P10 < P 2 where P8 < P11 < P12 < P9 best P11 < P12 < P3 < P4 The relationship between P 1 and P 5 can be arbitrary, the position relationship between P 3 and P 1 1, and the position relationship between P 4 and P 1 2 can also be arbitrary. In the next line, the next line will perform this action in sequence, so that all signals in the quadratic form can be read out. In this device, the charge from the signal output terminal 15 (the second limit charge) is finally read as CS 1 ^ (VSC Η 一 Voch) This paper is used in New Zealand China County (CNS> A4g (210x297 公 137 --------- MI — (please read the precautions on the back and fill in this page first) Printed by the Ministry of Economic Affairs, Central Bureau of Standards, Employee and Consumer Cooperatives A7 ΒΊ_ V. Description of the invention (135) The resulting charge is the difference between when there is output charge and when it is reset without signal charge, so it can be suppressed due to Amplify the fixed pattern noise generated by the uneven threshold value of the transistor 64. In this way, the voltage appearing on the vertical signal line 8-1'8-2 ... The circuit structure for subtraction in the charge field can also be called a noise cancellation circuit. The noise cancellation effect of this type of circuit is different from the 25th embodiment shown in Fig. 57. In the 25th embodiment, in Eliminate noise in the voltage field of the clamping section 41. In the type of the 28th embodiment, in In the voltage domain of the source terminal of the amplitude transistor 1 50, the noise is eliminated. When the second limiting pulse S ρ 2 is applied, the noise-eliminated charge is sent to the sink. That is, in the charge domain Internal noise elimination. With this method, noise can also be eliminated with high accuracy, and only signal components can be taken out. As described above, according to the 28th embodiment It can remove the fixed pattern noise with the uneven threshold value of the amplification transistor of the unit cell. In this embodiment, the output of the unit cell is supplied to the noise cancellation circuit through the gate capacitor of the limiting transistor , Regardless of the output of ^ noise component ', or the output of ^ signal component + noise component' ', the impedance of the noise cancellation circuit observed from the unit cell is approximately the same. The signal components are almost the same. Calculate the difference between the two ^, you can correctly remove the noise output, you can take out only the signal components. You can also correct the noise and take out only the signal components Message cancellation circuit From the point of view of impedance, we can only observe that the paper size of the gate electrode is compliant with the Chinese National Standard (CNS) A4 specification (210X297mm) -138-(please read the notes on the back and fill in this page). Pack · Order A7 B7 Printed by the Industrial and Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (136) 1 1 Capacitors, and their capacitance is extremely small »Therefore, it is possible to eliminate impurities in a short period of time 1 1 News 1 1 2nd amplitude limiting pulse wave SP 2 may also be affected by the 1st limiter 1 I pulse SP 1 of its square root. Therefore, in order to match the 1st and 2nd limit pulses, please read 1 1 | 1st and 2nd The effect of the crystal action becomes the same f. Reading the 1st 1st pulse of the 1st limiting pulse 1 Note 1 It is most effective to set the analogue limiting pulse just in front of ISP 1 9 4, 1 1 If the 1st limiting pulse is equal to When the amplitude of the second limiting pulse wave is the same • Under the condition of micro-filling this 1 pack for 1 second, it may occur in WeChat Page 1 cannot be read in the number field, or the charge of No. 1 is degraded, or the linearity is degraded. Therefore, the amplitude of the second limiting pulse wave 1 1 is set to be greater than the amplitude of the first limiting pulse wave from the second limiting pulse The operation of reading the charge of 1 I and adding bias charge is more stable. It is also effective to set the width of the second limiting pulse wave to be larger than the width of the first limiting pulse wave. 1 1 1 1 I 2 9th Example 1 Line 1 7 2 Figure 2 is the circuit structure of the imaging device using the amplified Μ 0 S detector of the 2 9th embodiment 0 Unit cell P 1 — 1 near i-j I The circuit structure is the same as the 0th A 1th embodiment. The 1st 2nd 9th embodiment is omitted from the 2nd 5th embodiment shown in Fig. 5 7 1 1 1 By transistor 2 6-1 2 8 — 1 »2 6 — 2…… and transistors, 1 1 body 2 8 — 2 · 2 6-3 > 2 8 — 3 t ·…… Because in the first 2 5 The impedance change set in the embodiment 1 1 Transistor transistor 2 6 The gate capacitor has a small capacitance, so it can be shortened 1 1 This paper size adopts China National Standards (CNS) A4 specification (210X297mm ) -139-A7 B7_ printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs. V. Description of Invention (137) The time constant of CR when the noise cancellation circuit operates. Since the time constant can be shortened, the reset pulse wave corresponding to the shortened time can be accelerated. The photosensitive diode selects the timing of pulse wave application and can perform noise elimination in a short time. This method is very effective when noise removal operations must be performed during the horizontal extinction period of the TV scan, such as TV signals. However, for applications that do not require such high-speed operation, it becomes more than the specification. Therefore, if the time allocated to the noise operation is wide, as described in the 28th embodiment, it is also sufficient to omit the structure of the impedance conversion circuit. Since the impedance conversion circuit is omitted, the circuit structure can be more simplified, so it can be more compact. Embodiment 30 Embodiments 73 and 74 are circuit configuration diagrams of an imaging device using the amplified MOS detector of Embodiment 30. The circuit structure near the unit cell P 1-i-j is the same as in the 25th embodiment. There are many parts in this embodiment that are common to the 26th embodiment shown in FIG. The difference is that the correction capacitor 1 6 0 — 1 is set to correct the difference between the impedance of the noise cancellation circuit observed from the unit cell side when outputting the ^ signal component + noise component 〃 and when only the `` noise component '' is output. , 16 0 — 2 ........... Each correction capacitor has a capacitance of C CMP. The correction capacitors 160 — 1, 160 — 2... Are located more than the clamp capacitors 1 3 1-1, 1 3 1-2 .... Close to the side of the camera field (unit cell) · And through the switch 1 6 2 -1 · 16 2-2 .......... in parallel with the vertical signal line 8-1, 8 This paper standard is used remotely in China Standard (〇yang) 8.4 specifications (2 丨 0 侂 297mm) -14〇- --------- 1 ------ 1T ------ 0 (please read the back first Attention i 1 fill in this page) '_B7_ V. Description of the invention (l38) 1 2....... The above is the difference from the 26th embodiment. In Figure 73, the correction capacitors 160-1, 160-2 ... and the corresponding set switches 162-1, 162-2, ... are connected Between the clamp capacitor 1 3 1 and the imaging field, it is connected between the imaging field and the load transistor 9 in the 7th image. FIG. 75 shows the operation timing of this embodiment. The switch 1 6 2 is turned on during the output of the signal from the vertical signal line after the clamping of the transistor 1 3 2 ends. In this way, if the capacitance of the sample holding pair connected to the vertical signal line 8-1 • 8-2 * ......... If the capacitance of the sample holding capacitor 134 is assumed to be CSH, the clamping capacitor 131- 1, 13 1-2 .......... capacitance is C < ^, becomes as follows, C = C c Μ P + C s Η · C c L / (C c L + C s Η) Therefore, if _ if in 2 {C c L — C c L * Csh / ( CcL + CsH)} > CcMP> 0 The setting of the correction capacitor cCMP is set within the scope of the DuPont Printing Co., Ltd. of the Central Standards Bureau of the Ministry of Economic Affairs. Compared with the correction capacitor, it is connected to the vertical signal line when the sample is held. The capacitance of the capacitor is close to the capacitance Cclj of the clamp capacitor 1 3 1-1, 1 3 1-2 .......... Therefore, the voltage difference V Cli due to the difference in capacitance becomes smaller, so the noise becomes smaller. Therefore, the impedance observed from the cell is used for signal transmission and noise transmission. This paper uses the Chinese National Standard (CNS) A4 specification (210X297mm) -141-Printed by Beigong Consumer Cooperatives, Ministry of Economic Affairs «. A7 B7 V. Invention description (l39) will not be different, and the result of keeping C close to Ccu during the sample holding period is the same. The 7th 囫 indicates the time change of the potential of the vertical signal line 8 — 1, 8-2 .......... and the potential of the clamp node 1 4 5. In this embodiment, for example, the signal becomes 0 in the dark, when the potential of the vertical signal lines 8_1, 8-2, ... is restored to the potential when clamped, and to the potential when the sample is held At the same time, the potential of the clamping node at the end of the sample retention will not return to a close value, but will become 0. Therefore, although there is no darkness and the signal is 0, the signal equivalent to AVce does not occur. Therefore, it is possible to prevent the occurrence of noise caused by the unevenness of ΔΥπ. As described above, according to this embodiment, in the MO S type solid-state imaging device having a noise removal circuit, a correction circuit is provided on the vertical signal line 8 Capacity 1 6 0-1, 1 6 0 — 2 ............., which can suppress the change of the capacitance setting in the noise removal operation that causes noise, which can further promote low noise . That is, when * signal component + noise component | output, the impedance observed from the unit cell becomes the same as when% noise is output ^ •, the noise can be eliminated correctly, but when resetting is finished | noise component 〃When outputting, PD (Photodiode) selects rear bird, signal component + noise component 〃output. In this embodiment, when the noise component is output, and the * signal component + noise component is output, the impedance of the noise cancellation circuit observed from the unit cell is substantially the same. Therefore, in these two outputs, the noise components become approximately the same. Calculating the difference between the two, the noise can be correctly removed and only the signal components can be taken out. Therefore * the noise can be correctly eliminated. This paper uses the Chinese National Standard (CNS) A4 specification (210X297mm) -142-g-- (please read the notes on the back first and fill in this page). A7 B7 Ministry of Economic Affairs Bureau of Central Standards Cooperative Duprinting 5. Description of the invention (140) 1 I can also change the 30th embodiment to the 5th to 11th example shown in Figure 5 7 and the 27th to the 27th example shown in Figure 6 and 8, And the capacitor for correction connected to the noise cancellation circuit of the first 1 2 9 embodiment shown in FIG. 7 2 0 1 I please 1 1 The second 2 6 ~ 3 0 embodiment is explained in comparison with the second 5 embodiment) First read 1 I different embodiments of the noise cancellation circuit. The following description compares with the second 5 ~ 3 0 actual reading ιδ 1 1 I embodiment, the structure of the unit cell is different. The first 3 1 embodiment 1 The third 3 1 embodiment k Tip 1 installed I The third 1 1 embodiment and Compared with the second 5 ~ 30 embodiments, the structure of the unit cell page ^^ 1 1 is different. However, the overall structure is the same as that of the 25th embodiment 11 shown in Fig. 57, so it is not shown here. However, the feature of this embodiment is to replace the unit cell P 1 shown in FIG. 5 7 with the unit cell P 2 shown in FIG. 7 7 1 I. The characteristics of the unit cell P 2 in this embodiment The direction of the photodiodes 62a, 62b of 1 1 1 in the 25th embodiment is the vertical direction, but in this embodiment-1, the arrangement is adjacent to the horizontal direction. Each diode is connected to the source 1 | pole of the reset transistor 6 6 and the gate of the amplifying transistor 6 4 through the photosensitive diode 1 body selection transistors 63a and 63b, and there are a total of 1 output circuit 1 I 6 8. 1 1 1 The operation will be described with reference to the timing diagram in Figure 7-8. First, during the period when the water 1 1 level is extinguished, the potential of the horizontal address line 6 -1 and the photodiode selection line 2 ′ 1 1 2-1 is set to a high level, so that the vertical selection transistor 6 5 and the photoreceptor 1 1 The second sleeping body selects the transistor 6 3 a to turn on 〇1 1 As a result, the gate of the amplifying transistor 6 4 appears and the photosensitive diode 1 1 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 Ο X 297 Mm > -143-A7 ___B7__ printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (141) 6 2 a The voltage is approximately equal to the voltage. Amplifying transistor 6 4 and load transistor 9-1 A source follower is formed, and a voltage substantially equal to the gate voltage of the amplifying transistor 64 appears on the vertical signal line 8-1. Then, the level of the vertical address pulse 6-1 becomes a low level, so that The vertical selection transistor 6 5 becomes an open circuit. As a result, the source follower no longer operates, but the potential of the vertical signal line 8-1 does not change immediately, and the gate voltage of the amplifier transistor 6 4 can be maintained approximately the same as before the reset. Apply an equal voltage. Then, The potential of the reset line 7-1 becomes the high level, and the reset transistor 6 6 is turned on, and the potentials of the gate of the amplifying transistor 6 4 and the photodiode 6 2 a are initialized. From the horizontal address circuit 13 Apply the horizontal address pulse wave to the gate of the horizontal selection transistor 1 2-1, and take out the signal of the photodiode 6 3 a from the signal output terminal 15. Then, during the same horizontal extinction period, proceed with In the same operation as described above, the photodiode selection transistor 6 3 b is turned on instead of the photodiode selection transistor 6 3 a. As a result, the signal of the photodiode 6 3 b can be taken out from the signal output terminal 15. Although * is not shown in the figure, during this horizontal extinction period, the horizontal address is sequentially changed under the same vertical address and signals corresponding to one line are sequentially extracted. 'Operation * Take out the signals of each line in sequence. So, in addition to the effect of the 〇A 1 embodiment, the MOS solid-state imaging device according to this embodiment, because the paper size is not used during a certain frame Chinese National Standard CNS) A4 specification (210X297mm) -144-(please read the notes on the back first t 'fill in this page • install · binding line A7 B7 306073 V. Description of the invention (142) The internal vertical address line becomes the on-off system only During a certain horizontal period, the vertical address line can be easily controlled. Therefore, the vertical address circuit and the multiplex circuit can be simplified. The third embodiment can also change the noise cancellation circuit in the same way as the second embodiment. . That is, the descriptions in Figs. 5 7 to 7 6 are equally applicable to the 31st embodiment. The number of photodiodes adjacent in the horizontal direction included in the unit cell of the 31st embodiment is also limited to two, and may be three or more. As shown in Fig. 65, the output circuit is replaced with a vertical selection capacitor instead of a vertical selection transistor. Please read the notes first. Printed by the Ministry of Economic Affairs, Central Bureau of Customs and Excise, Beigong Consumer Cooperative, 3rd Example 2 of Example 7 9 The picture is the 3rd 2 Structure diagram * Unit cell P 3 element matrix shape * The 80th picture is the 79th structure Figure. In the unit cell P3-1-2, which only represents the unit, as shown in the figure, the real unit cell system is composed of four photosensitive diode selection transistors 6 3 a. 4 photosensitive diodes photosensitive diode 6 2 a 63a ~ 63d connected to 63a ~ 63d from the vertical embodiment of the M Ο S — i — j in the vertical type solid-state imaging device 広 and horizontally arranged into a second unit crystal Cell P3 — unit cell P shown in the diagram of 1-1, ~ also uses the same embodiment of ΜΟ S-type polar body 6 ~ 6 3 is configured to 3-1-2 a ~ 6 line ~ 6 2 common input straight position Address dll 2 rows and 2 columns d through the circuit 6 circuit 5 toward 1 structure • but other structures. The solid-state imaging device has a single 2 d, four light-sensitive two output circuits in a matrix of 68. Selection of transistors 8. Select the transistor to be arranged horizontally. The paper size is applicable to China National Standard (CNS) A4 (2 丨 0 > < 297mm) _145-B7 V. Description of the invention (143) Photodiode selection lines 22-1, 24-1, 172-1, 1 7 4-1 independently control their on-off. Please read the note on the back page. As mentioned above, connect the common output circuit 6 4 to the four photodiodes 6 2 a ~ 6 2 d to form the unit cell P 1 _ 1-1, so Compared with the unit cell of the conventional MO SM solid-state imaging device, three output circuits can be omitted. In this manner, according to the MOS solid-state imaging device of this embodiment, the effect of combining the 25th embodiment with the 26th embodiment can be produced. The 0th 8th embodiment can also be modified with the same noise cancellation circuit as the 25th embodiment. That is, the descriptions in FIGS. 5 7 to 76 can be applied to the 0A 8th embodiment. The number of photosensitive diodes included in the unit cell of the third embodiment is not limited to 2 rows and 2 columns, and may be a matrix of more than 3, not necessarily a square matrix. As shown in Chapter 65, the output circuit can also use vertical selection capacitors instead of vertical selection transistors. Printed by Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs The present invention is not limited by the above-mentioned embodiments, and the funding can be changed. For example, as long as amplifying transistors with unit cells without threshold unevenness can be manufactured, since no fixed pattern noise is generated, the noise cancellation circuit can be omitted. Or even if fixed pattern noise is generated, as long as the image quality is not affected, the noise cancellation circuit can be omitted. The gate and source of the load transistor are not necessarily connected to the same power line, but can also be connected to different power sources separately. In this way, the passing current can be controlled, and the power consumption can be reduced. In the noise canceling circuit of each embodiment, since the signal current (only the noise component) read out when there is no input signal is small, the noise is small, so it is best to make the t paper scale applicable to the Chinese national standard (CNS> A4 specification ( 210X297mm) _ 146 _ Printed by the Ministry of Economic Affairs, Central Bureau of Standards, Employee Consumer Cooperatives A7 B7 V. Description of the invention (144) The voltage applied to the power terminal of the storage sink becomes approximately equal to the video bias voltage. The so-called video bias system It means that when the signal is read out from the signal output terminal 15 by current, the signal output terminal 15 becomes a substantially fixed voltage. Figure 4 5 shows a modified example of the realization. The signal output terminal 15 is connected to the operational amplifier 17 6. Connect the load resistor 1 7 8 between the input and output terminals of the operational amplifier 1 7 6. In this way, the signal current flows into the load resistor 1 7 8 forcibly, and the horizontal signal line 15 is assumed to be fixed to a certain voltage. That is, video bias. The above embodiments describe embodiments in which the unit cells are arranged in the form of a two-dimensional matrix. However, the present invention can also be applied to an imaging device in which the unit cells are arranged in the form of a one-dimensional array. At this time, the photodiodes in the unit cell can be arranged in a matrix in the vertical and horizontal directions regardless of the arrangement of the unit cell. The above description combines the amplified MOS detector and the noise canceller. Various specific examples of generating noise-free image signals * However, in the above-mentioned amplified MOS detector, the transistor included in the unit cell must have at least an amplified transistor, a vertically selected transistor, and a reset In order to miniaturize the unit cell and save power, the number of transistors that constitute the unit cell must be reduced as much as possible. In the non-amplified MO S detector, the unit cell is composed of a photosensitive diode It is composed of a body and a transistor, but the pin sensitivity is lower than the magnification type. The following illustrates the MO S type solid-state imaging device that can be more miniaturized and more power-saving in the magnification type MO S detector (Specific example of solid-state imaging device using magnified MO S detector). This paper scale is applicable to China National Atomic Rate (CNS) A4 specification (210X297mm) _ 14 了---------- ^ ------ iT ------ A (Please read the notes on the back first. ^ write This page) Printed A7 __ _B7_ by the National Bureau of Standards, Ministry of Economic Affairs, Consumer Labor Cooperative V. Description of the invention (l45) The third 33rd embodiment The following describes the third 33rd embodiment of the present invention with reference to Articles 8 1 and 82. Article 8 1 The figure shows the structure of the MO S type solid-state imaging device of the third and third embodiments. The unit cells 8-i-j are arranged in the form of a two-dimensional matrix in the vertical and horizontal directions • The figure only shows 3 X 3, but there are actually thousands Thousands of X. I is a variable in the horizontal direction, and j is a variable in the vertical direction. The application fields of the solid-state imaging device of the present invention are video cameras, electronic still cameras, digital cameras, telephone fax 'copiers , And scan Jiji Temple. The basic unit cell P 8-i-j of this embodiment includes: a photodiode 6 2-i-j that detects incident light; a gate electrode connected to the cathode of the photodiode 6 2-i-j to amplify its detection Signal amplification transistor 6 4 — i — j; connected to the cathode of the photodiode 6 2-i_j (amplification transistor 64—ij gate), reset signal charge reset signal charge reset transistor 6 0_i — j: and an address capacitor 69 — i — j connected between the sink and gate of the amplifier transistor 6 4 — i — j. In this way, in this embodiment, the vertical selection transistor 3-i-j 'provided in the conventional example (Figure 1) can be omitted. An address capacitor 6 9-i-j β that can produce the same function can also be provided from the vertical address The vertical address line 6 of the circuit 5 wired in the horizontal direction 6 -1-6-2... ....... The amplifier transistors connected to the unit cells of each row 6 4-i-j Set the absorber of the transistor 60 to determine the size of the reader. The size of the paper is left to the Chinese National Standard (CNS) A4 specification (210X25 (7mm) _ 148 — --------- ^ ------ 、 玎 ------ ^ / I (Please read the precautions on the back to write this page) ____B7__ V. Description of the invention (146) The horizontal line of the signal. Similarly, the wiring from the vertical address circuit 5 toward the horizontal direction The reset line 7-1, 7-2.. ....... is connected to the reset gate of the unit cell of each row 6 6 _ i-j. The unit cell of each row The source of the amplifying transistor 6 4-i-j is connected to the vertical signal lines 8-1, 8-2 arranged in the column direction, and the vertical signal lines 8-1, 8-2 .... .. one end is equipped with load transistors 9-1, 9-2. ..... the load transistors 9-1, 9-2, ......... The gate electrode and the sink electrode are connected to the sink voltage terminal 20. Vertical signal line 8 — 1, 8 — 2 ..... The other end is via the clamping capacitor 1 3 1 — 1, 1 3 1 — 2 ...., the sample holding transistor 133 — 1, 133 — 2 ...., horizontal selection transistor 12-1 · 12-2 .......... connected to the signal output (horizontal signal line) 15 . Clamp transistor 132-1, 132-2 .... The collector of the clamp is connected to the clamp capacitor 131-1, 131-2, ... ... hold the transistor with the sample 1 3 3-1, 1 3 3 — 2 .......... connection point (clamping section 1 4 5 — 1, 1 4 5-2 ..........) ._ Clamping transistor 132-1, 132-2... The source is connected to the common source 1 4 1 and the gate is connected to the common gate terminal 1 4 2. Sample holding transistors 133-1, 133-2 .......... and level selection transistors 1 2-1, 1 2-2 ..... The sample holding capacitors 1 3 4 — 1, 1 3 4 — 2 .......... are grounded. The horizontal selection gates of the transistors 12-1, 12-2, ......... horizontal address circuit 1 3 accept the address pulse wave. The vertical address circuit 5 series integrates many (here 2) signals and this paper standard is applicable to the Chinese National Standard (CNS) A4 grid (210X297 mm) _ _ A7 printed by the Employees Consumer Cooperative of the Central Bureau of Samples ________ B7 __ ^ _ V. Description of the invention (147) Shifting circuit. This circuit can be implemented with any of the circuits in Figures 18, 19 or 20. In the example of Fig. 18, the multiplexer 48 sequentially synthesizes the output of the address circuit 4 4 which is output by shifting the input signal 46 from many output terminals, and the two input signals 50. In the example of FIG. 19, the multiplexer 5 6 synthesizes the output of the encoding input 5 4 decoding decoder 5 2 with the two input signals 58. • In the example of FIG. 20, the two address circuits 60a, 6 The output of 0 b is integrated into the control signal lines of each row. FIG. 8 2 is an operation timing chart of this embodiment. During the horizontal extinction period, after applying the high-level address pulse on the vertical address line 6-1, the high-level address pulse is supplied to the unit cell connected to the line through the address capacitor 69 On the gate of the amplifying transistor 64, the potential of the channel under the gate becomes higher than the potential of the channel under the gate of the amplifying transistor 6 4 of the unit cell connected to other lines and becomes conductive. Therefore, the source follower circuit is constituted by the amplifier transistor 64 and the load transistor 9 connected to the unit cell of the vertical address line 6-1. Then, a voltage substantially equal to the gate voltage of the amplifying transistor 64, that is, the voltage of the photodiode 64, appears on the vertical signal line 8. In this way, only the gate potential of the amplified transistor 6 4 of the line of the located address appears on the vertical signal lines 8-1, 8-2 ..., and no amplification of other lines occurs The gate potential of transistor 64. Therefore, even if the vertical selection transistor is omitted, the address of the vertical address line can be set. Clamp pulses are applied to the common transistor 142 of the clamp transistor 1 3 2 — 1, 1 3 2 — 2 ... to clamp the transistor 1 32 — 1, 132- 2 .......... become conductive. Set the box section 14 5-1, the paper size A is based on the Chinese national standard (CNS> A4 said grid (_210x297 公 En> -150---------- # ------ 1T- ----- ^ (Please read the precautions on the back m ~ 丨 Fill in this page) A7 B7 printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs

五、發明説明（148D 14 5-2 * .........之電壓固定爲與箝位電源1 4 1相同 之電壓。 然後，切斷箝位電晶體132-1 ，132 - 2，… ……後，在復置線7 1 -上施加髙位準之復置脈波，使復 置電晶體6 6 — 1 ，6 6 — 2 ’ .........導通而復置感光二 極體62之信號電荷。如此，在箝位節145-1 ， 14 5 — 2 ..........上出現將感光二極體6 2上有信號電 荷時與被復置而無信號電荷時之垂直信號線8 - 1 ’ 8 -2 ..........之電壓差相加於箝位電源1 4 1 一之電壓· 然後，在樣品保持電晶體133 — 1 ，133 — 2， .........之共同鬧極1 4 3上施加樣品保持脈波*使樣品保 持電晶體133 — 1 ，133-2 ..........成爲導通*將 該信號傅送至樣品保持電容器134 — 1 ，134 — 2， • · · · · · · · · 0 然後，從水平位址電路1 3將水平位址脈波依次施加 於水平選擇電晶體1 2 — 1 ，12 - 2 ...........從水平 信號線1 5中依次取出相當於1條線之信號。 在下一條線，下下一條線依次繼續進行該動作，即可 讀出2次元狀之全部信號。 通常在放大型MO S型固體攝像裝置中，因爲放大電 晶體6 4之閾值電壓之不均勻重叠於信號上，故即使感光 二極體6 2之電位相同，其輸出信號不會成爲相同，若再 生攝像之畫像時，則產生對應於放大電晶體6 4之閩值不 均勻之二次元狀雜訊（因爲其位置固定，故稱爲固定圖型 本紙張尺度逍用中國國家標準（CNS)A4規格（ 210X297公釐）-151 - ---------^------1T------0 # I (請先閱讀背面之注意事'4填寫本頁) 經濟部中央標準局負工消费合作杜印製 A7 _____B7_ 五、發明説明（149) 雜訊）。然而，如上所述，依照本實施例，因爲在箝位節 145 — 1 ，145-2 ..........上終究會出現單位晶胞 中有信號電荷與被復置而無信號電荷時之差之電壓，故可 抑制因放大電晶體6 4之閾值不均勻而產生之固定圇型雜 訊。亦即由箝位電容器131 ，箝位電晶體132，樣品 保持電晶體1 3 3，及樣品保持電容器1 3 4所構成之電 路成爲雜訊消除電路》 以下說明本實施例之構造· 本實施例中，單位晶胞P8 — 1 — 1 ，P8 — 1_2 ..........垂直位址電路5，水平位址電路1 3等周邊電路 係形成在p-型基板設有P+型不純物靥之半導體基板上。 如第2 5 A圖所示，在p-型基板8 1上設置P+型不 純物層8 2之半導體基板上形成感光二極體8 3等晶胞要 素。 如此的形成半導體基板，則由於存在於P+/P-分界 之擴散電位，可防止產生於p-型基板8 1之暗電流之一 部分流入P +側。 以下簡單說明詳細解析電子流之結果•對於產生於 P—側之電子而言，P+不純物層8 2之厚度似乎成爲P + 與P —之濃度比倍，亦即L · p +/ p -。 亦即，如第2 5 B圖所示，從暗電流發生源之p-基' 板8 1至感光二極體8 3之距離似乎變成較遠p+/p-倍 。暗電流除了從基板深部流入之暗電流以外，又有產生於 感光二極體8 3附近之耗盡層內之暗電流。在耗盡內產生 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐）_ 152 _ ---------批衣------iT------# (請先閲讀背面之注意事項V寫本頁) - 經濟部中央橾準局貝工消費合作杜印装 A7 __B7_ 五、發明説明（150) 之暗電流大小與從基板深部流入之暗電流之大小大致上相 同。耗盡層之厚度大約爲1 ，從基板深部流入之暗電 流又從大約1 0 0 之深度流入。該深度被稱爲P型半 導體內部之電子之擴散距離。雖然而該厚度，但暗電流仍 成爲相等之理由爲耗盡層內部之毎單位體積之暗電流之發 生或然率較髙。原理上，發生於耗盡層之暗電流不可能與 信號電流分離，故希望降低暗電流必須降低從基板深部流 入之暗電流成分· 又因爲在p-型基板7 1上形成P+型不純物餍7 2之 半導體基板上形成晶胞，故可防止因發生暗電流而造成基 板電位之變動。因爲p型基板之厚度大，電阻小，故如後 文中所述，可使雜訊去除電路確實的動作。 因爲若元件溫度上昇時，來自基板深部之暗電流成分 急速的增加，這種現象非常重要。其程度爲來自基板深部 之成分充分小於在耗盡層發生之成分。具體言之，只要來 自基板深部之暗電流小於來自耗盡層內部之暗電流大約1 個位數以下即可。亦即只要將p+/p-設定爲1 0而將來 自基板深部之暗電流設定爲1/10即可。 來自基板深部之暗電流在由η型基板與p型阱所構成 之半導體基板中幾乎不存在。但爲了使其與該半導體基板 成爲相同位準，必須將Ρ+/Ρ-設定爲1 0 0而將來自基 板深部之暗電流設定爲大約1/1 0 0 · 在習用之具有實績之C CD中，η型埋入通道之不純 物濃度大約爲1 0 lec m-3，而包圍穩定的製造該埋入通 本紙張尺度逋用中國國家橾隼（CNS)A4規格（210X297公釐）_ 153 _ ---------私衣------，訂------0 (請先閲讀背面之注意事項r'·'. ‘寫本頁) 一 經濟部中央標準局貝工消費合作社印製 A 7 B7__ 五、發明説明（151) 道之擴散層之埋入通道之P型層（在此爲P型基板）之不 純物濃度大約爲1 0 15c m-3。 假設口+/〇_爲1 0時，ρ+層之澳度大約爲 1 Oiecm_3左右，p+/p-爲1 〇 〇時，大約爲 1 017c m-3，成爲與η型埋入通道之不純物澳度之大約 1 Oiecm-3大約相等或反轉1個位數。 因此，在具有實練之習用C C D中從考慮可以使用這 種不純物漉度之P+層。降低p-層之澳度後，基板之薄片 電阻值增大。 然而，放大型MO S攝像裝置中無C C D之埋入通道 ，故可不必降低p-層之澳度而在某一程度內自由的設定 P +/ P ~之數值· 因此，降低P型阱之電阻值，並且改善由η型基板與 Ρ型阱所構成之半導體基板之構造，亦可構成晶胞。 第2 6圖爲在η型基板8 5上使用薄片電阻值小之 Ρ+阱8 6之單位晶胞之斷面圖*第2 7圖爲C CD之單 位晶胞之斷面圖。 爲了穩定的製造，C C D之單位晶胞之η型基板8 7 ，η型阱8 6，η型埋入通道8 9之不純物濃度係設定爲 大約 1014cm_3，1015cm_3，10lecm-3 左右。 因爲η型感光二極體9 0之不純物濃度可在某一程度 內自由設定，故製造上無太大之限制*在上述不純物澳度 時，Ρ型阱86之薄片電阻值大約爲ΙΟΟΚΩ/C]· C C D即使具有如此髙之電阻，其雜訊仍極小。 本紙張尺度逋用中國國家標準（CNS)A4規格（ 210X297公釐）_ 154 - ---------^------ΐτ------.^- (請先閱讀背面之注意事.¼寫本頁) 一 A7 B7 經濟部中央標準局員工消費合作社印製 五 、發明説明 (152) 1 | 在放大 型Μ 0 S攝像 裝 置 中 使 用 雜 訊去除電路時， 該 1 1 P 型阱之薄 片電阻非常重 要 0 其 理 由 爲 ，復置脈波所造 成 1 1 之 P型阱8 6之電位擾亂 平 靜 之 時 間 必 須匹配應用該裝 置 1 | 請 1 I 之 系統。 先 閲 1 I 在現行 電視方式之Ν Τ S C 方 式 中 ，使雜訊去除電 路 背 1 之 1 動 作之時間 係水平回描線 期 間 之 大 約 1 1 〔以S〕之期 間 注 意 1 I 內 。P型阱 8 6之電位擾 亂 必 須 在 該 期 間內平靜至0 . 1 事 項 1 1 C m V〕左 右。 寫 本 1 裝 該0 · 1〔 m V〕之 極 小 數 值 係 因 c C D之雜訊電 壓 頁 1 1 输 出大約爲 此數值而設定 〇 爲 了 在 1 1 〔从s〕之極短 時 1 1 間 內平靜成 0 · 1〔 m V 之 極 小 數 值 *依照詳細解析 結 1 | 果 ，必須將 P型阱8 6之 薄 片 電 阻 值 設 定爲1 Κ Ω /□ 以 訂 I 下 •此數值 大約爲從用之 C C D 之 大 約 1/10 0。 1 1 1 因此， P型阱8 6之 不 純 物 濃 度 必 須大約爲1 0 0 時 1 1 I 〇 在上述P 型基板中已說 明 此 數 值 C c D不可能實現 0 ..氣 1 1 在 高解像度 電視方式中， 水 平 回 掃 線 期 間爲 線 1 3 • 7 7〔 β S ]，故 Ρ 型 阱 8 6 之 薄 片電阻必須爲 1 1 3 0 0 Ω / □以下。 1 I 其他變 更例可在基板 上 形 成 髙 濃 度 Ρ +型三明治層， 1 1 I 以 濃度更低 之Ρ型層形成 其 表 面 0 1 1 I 第2 8 圖爲在Ρ -型基板S 1 與Ε >型層9 3之間形成' 1 1 P +層三明技 ί層9 2之半導體基板之結構圖。第2 9圖爲 1 1 在 η型基板 9 5與Ρ型層 9 7 之 間 形 成 Ρ +型三明治層 1 1 9 6之半導 體基板之結構 圖 1 1 本紙張尺度遑用中國國家梂準（CNS)A4規格（2丨0X297公釐）_ 155 - 五、發明説明（153) 道種p +型三明治層可利用高加速度兆伏特離子注入 器實現。 在該P型層上除了形成單位晶胞之構成要素之感光二 極體8 3，電晶體等之外，又形成水平位址電路’垂直位 址電路等周邊電路。 第3 0圖爲以高濃ip型阱1 0 3包圍感光二極體 8 3之周圍，以其他P型阱1 0 2形成η型基板1 0 1上 之其他部分而構成之半導體基板之結構圖。 採用這種結構，故可防止暗電流流入感光二極髖8 3 。半導體基板1 0 1亦可爲Ρ_型基板· 形成晶胞周邊之水平位址電路及垂直位址電路之一部 分或全部之Ρ型阱之濃度係在電路設計時決定。因爲與晶 胞之最佳值不同，故可形成爲與構成攝像領域之Ρ型阱分 開之Ρ型層。 第6 3圇爲在η型基板1 〇 5上形成構成攝像領域之 ρ型阱1 0 6，而分開的形成構成周邊電路之其他Ρ型阱 1 0 7之半導體基板之結構圖。 經濟部中央標準局員工消費合作社印製 如此構成，即可形成適合於各構成要素之Ρ型阱。該 η型基板1 0 5亦可爲ρ—型基板。 第6 4圓爲在η型基板1 〇 5上形成構成攝像領域之 Ρ+型三明治層1 0 8及濃度低之ρ型層1 0 9 ，並且在' 周邊電路中形成其他Ρ型阱1 0 7之裝置。 如此構成，即可形成適合於各構成要素之Ρ型阱，可 防止暗電流洩漏至感光二極體。該η型基板1 〇 5亦可爲 本紙張尺度適用中國國家標率（CNS ) Α4規格（210X 297公釐）_ 156 _ 306073 A7 B7___ 五、發明説明（154) P -型基板。 如上所述，依照本實施例，因爲將放大電晶體6 4之 源極直接連接於垂直位址線6上，又在垂直位址線6與放 大電晶體6 4之閘極之間裝設位址電容器6 9以取代垂直 選擇電晶體，故可使被設定位址之放大電晶體6 4之導通 ，只將其閘極電位取出於垂直信號線8中。亦即，即使垂 直選擇電晶體，仍可設定垂直位址線之位址，因此，可將 晶胞微細化。 又因爲將單位晶胞之輸出經由雜訊消除電路輸出，故 可抑制配合單位晶胞之放大電晶體之閾值不均匀之固定圖 型雜訊。 因爲使用由P -型不純物基板與形成在P _型不純物基 板上之P +型不純物層所構成之基板做爲形成單位晶胞之 半導體基板，故可降低侵入單位晶胞中之暗電流，而且可 使基板表面之電位穩定，故可使雜訊去除電路確實動作。 以下說明第3 3實施例中變更雜訊消除電路之實施例 第3 4實施例 以下參照第8 3圖，第8 4圚說明第3 4實施例•第 8 3圖爲使用第3 4實施例之放大型MO S偵測器之攝像' 裝置之電路結構圖。單位晶胞P 8 - i - j附近電路結構 與第3 3實施例相同· 垂直信號線8 — 1 ，8 - 2..........之另一端連接於 裝I ί I訂— I I I 線 (請先閱讀背面之注意事項i 寫本頁) 一 經濟部中央標隼局貝工消費合作社印製 本紙張尺度遑用中國國家標率（CNS ) A4規格（210X297公釐）_ 157 - A7 B7 經濟部中央標準局貝工消费合作社印製 五、 發明説明 ( 155) 1 | Μ 0 S 電 晶 體 2 6 — 1 > 2 6 — 2 * … … … 之 閘 極 1 1 Μ 0 S 電 晶 體 2 6 — 1 * 2 6 — 2 9 … … … 之 源 極 連 接 於 1 1 Μ 0 S 電 晶 體 2 8 — 1 2 8 — 2 9 … … … 之 吸 極 而 S 1 I 請 1 I Μ 0 S 電 晶 體 2 6 — 1 t 2 6 — » 2 … … … 2 8 — 1 t 先 閱 1 I 讀 1 2 8 一 2 ， • · · … •«· 成 爲 源 極 跟 隨 電 路 動 作 0 Μ 0 S 電 晶 體 背 ιέ 1 1 之 1 2 8 一 1 » 2 8 一 2 * … … … 之 閘 極 連 接 於 共 同 閘 極 端 子 注 意 1 I 事 1 3 6 〇 罗 1 I Μ 0 S 電 晶 體 2 6 — 1 2 6 — 2 » … … … 與 Μ 0 S % 裝 頁 1 電 晶 體 2 8 — 1 2 8 一 2 … … … 之 連 接 點 經 由 樣 品 保 1 持 電 晶 體 3 0 一 1 3 0 — 2 … … … 連 接 於 箝位 電 容 器 1 1 3 2 一 1 > 3 2 — 2 … … … 之 — 端 0 箝 位 電 容 器 3 2 一 1 1 1 » 3 2 — 2 … … … 之 另 — 端 並 聯 樣 品 保 持 電 容 器 3 4 訂 1 — 1 3 4 — 2 … … … 與 箝 位 電 晶 體 4 0 — 1 4 0 一 1 | 2 » … 〇 樣 品 保 持 容 器 3 4 — 1 3 4 一 2 9 1 I … 之 — 端 接 地 0 箝 位 電 容 器 3 2 一 1 3 2 一 2 9 … … 一， 1 1 線 … 之 另 —， 端 經 由 水 平 選 擇 電 晶 體 1 2 一 1 1 2 — 9 2 … 1 … … 連 接 於 信 號 输 出 端 ( 水 平 信 號 線 ) « 1 1 以 下 說 明 本 實 施 例 之 構 造 〇 1 1 由 第 8 3 圖 之 電 路 結構 可 知 因 爲 箝 位 電 容 器 3 2 與 1 1 樣 品 保 持 電 容 器 3 4 直 接 連 接 而 且 互 相 接 近 故 可 層 疊 形 1 I 成 於 同 一 面 上 » 可 將 單 位 晶 胞 小 型 化 〇 1 I 具 體 言 之 9 如 第 2 4 圖 所 示 * 在 矽 基 板 7 2 上 經 由 第 1 1 1 1 絕 緣 膜 7 4 形 成 第 1 電 極 7 6 而 構 成 樣 品 保 持 電 容 器 1 1 3 4 > 又 在 第 1 電 極 7 6 上 經 由 第 2 絕 緣 膜 7 8 形 成 第 2 1 1 本紙伕尺度適用中國國家橾隼（CNS ) A4規格（210X 297公釐）_ 158 經濟部中央標隼局貝工消費合作社印製 A7 B7 五、發明説明（l56) 電極8 0而構成箝位電容器3 2。 由圖中可知，第1電極7 6成爲共同電極，而箝位電 容器3 2與樣品保持電容器3 4層叠的形成，故以分別形 成時之1/2面積即可形成相同之電容量。 以下參照第8 4圖之時序圖說明如此構成之MO S型 固體攝像裝置之動作。因爲負載電晶體9之共同吸極端子 2 0，阻抗變換電路之電晶體2 8之共同閘極端子3 6， 及箝位電晶體4 0之共同源極端子3 8係由D C驅動，故 在時序圖中不表示· 在水平熄滅期間內，於垂直位址線6 — 1上施加髙位 準之位址脈波後，連接於該垂直位址線6 - 1之單位晶胞 P8 — 1 - 1 ，P8 — 1 — 2..........之放大電晶體64 導通，由放大電晶體64與負載電晶體9 一 1 ，9一2， .........構成源極跟隨電路。 使樣品保持電晶體3 0 — 1 ，3 0 — 2..........之共 同閘極3 7之電位成爲高位準而使樣品保持電晶體3 0 — 1*30-2 ..........導通。然後，使箝位電晶體40 — 1*40-2*.........之共同閘極42之電位成爲高位準 而使箝位電晶體40 — 1 ，40 — 2 ’ .........導通。 然後，使箝位電晶體40 — 1 ，40 — 2 ..........之 共同閘極4 2之電位成爲低位準而使箝位電晶體4 0 — 1' •40-2*.........斷路。因此，出現於垂直信號線8— 1 ，8 — 2..........之信號加雜訊成分被儲存於箝位電容 器 3 2 — 1 ，32 — 2 ..........中· 本紙張尺度遑用中國國家標準（〇吣>八4規格（2丨0乂297公釐）-159- I I 111 I 裝^ I 11 訂— I I 線 (請先閲讀背面之注意事項一、寫本頁) 為 A7 B7 經濟部中央標準局貝工消費合作社印笨 五、 發明説明 ( 157) 1 | 然 後 在 復 置 線 7 — 1 上 施 加 高 位 準 之 復 置 脈 波 > 則 1 1 連 接 於 該 復 置 線 7 — 1 之 單 位 晶 胞 P 8 — 1 — 1 P 8 — 1 1 1 一 2 * … … 之 復 置 電 晶 體 6 6 導 通 輸 出 電 路 6 8 之 1 信 號 線 請 1 输 入 端 子 之 電 荷 被 復 置 0 如 此 » 在 垂 直 8 一 1 t 8 先 閱 1 1 之 雜 訊 讀 1 一 2 » … … • · « 上 只 出 現 信 號 成 分 被 復 置 成 分 0 背 面 1 之 1 如 上 所 述 * 因 爲 在 箝 位 電 容 器 3 2 1 > 3 2 — 2 » ί 1 | … … … 中 儲 存 信 號 加 雜 訊 成 分 * 故 在 箝 位 節 4 1 — 1 事 1 1 1 4 1 — 2 ♦ … … … 上 只 出 現 垂 直 信 號 線 8 — 1 9 8 — 2 9 % 本 1 裝 … … 之 電 壓 變 化 » 亦 即 從 信 號 成 分 加 雜 訊 成 分 中 減 去 雜 頁 '—^ 1 1 訊 成 分 之 撕 固 定 圖 型 雜 訊 之 信 號 電 壓 〇 1 1 然 後 » 使 樣 品 保 持 電 晶 體 3 0 一 1 9 3 0 — 2 » « · · … 1 | … 之 共 同 閘 極 3 7 之 電 位 成 爲 低 位 準 而 切 斷樣 品 保 持 電 晶 訂 I 體 3 0 — 1 3 0 一 2 … … … « 因 此 9 出 現 於 箝 位 節 1 1 | 4 1 — 1 4 1 一 2 … … … 之 Atr m 雜 訊 之 電 壓 被 儲 存 於 樣 1 1 1 品 保 持 電 容 器 3 4 — 1 3 4 一 2 … … … 中 〇 1 1 線 1 然 後 在 水 平 選 擇 電 晶 體 1 2 一 1 9 1 2 — 2 9 … … … 上 依 次 施 加 水 平 位 址 脈 波 而 從 输 出 端 子 ( 水 平 信 號 線 ) 1 1 1 5 讀 出 儲 存 於 樣 品 保 持 電 容 器 3 4 — 1 9 3 4 — 2 f … 1 I … … 中 之 JrrT. 脓 雜 訊 感 光 二 極 體 6 2 之 信 號 〇 1 1 以 後 * 同 樣 的 對 垂 直 位 址 線 6 — 2 9 6 — 3 > … … … 1 1 I 反 復 進 行 上 述 動 作 9 即 可 取 出 配 置 成 二 次 元 狀 之 全 部 晶 胞， 1 1 之 信 號 〇 1 1 以 下 說 明 第 8 4 圖 之 時 序 之 ,i t. 刖 後 關 係 〇 其 所 需 之 順 序 1 1 有 如 下 2 種 〇 1 1 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐）_ ι6〇 _ B7____ 五、發明説明（158) · (1 )樣品保持脈波之上昇箝位脈波之下降—第1 個垂直位址脈波之下降—復置脈波之下降-第2個垂直位 址脈波之上昇—樣品保持脈波之上昇—第2個垂直位址脈 波之下降 (2 )箝位脈波之下降—復置脈波之上昇—復置脈波 之下降 第1個垂直位址脈波之上昇，樣品保持脈波之上昇， 箝位脈波之上昇之前後關係可爲任意，但最好爲依照上述 關係。第1個垂直位址脈波之下降與復置脈波之上昇之前 後關係亦可爲任意，但最好爲依照上述關係β 如上所述，依照第8 4圖之動作，在箝位節4 1上出 現有信號（加雜訊）時，與放大電晶體被復置而無信號時 之差之電壓，故可補償因放大電晶體6 4之閾值不均勻所 造成之固定圖型雜訊•亦即由箝位電晶體3 0 *箝位電容 器3 1 ，樣品保持電晶體4 0，樣品保持電容器3 4所構 成之電路成爲雜訊消除電路。 經濟部中央樣準局貝工消費合作社印製 本實施例之雜訊消除電路經由源極跟隨電路所構成之 阻抗變換電路2 6，28連接於垂直信號線8。亦即垂直 信號線連接於電晶體2 6之閘極。因爲該閘極電容器之電 容童非常小，故晶胞之放大電晶體6 4只充電垂直信號線 8 — 1 ，8 — 2 ...........故C R之時間常數小，可立即' 成爲正常狀態。因此，可加快復置脈波之施加時序，可在 短時間內進行雜訊消除動作·若爲電視信號時•雜訊消除 動作必須在水平熄滅期間內進行，故可在短時間內正確的 本紙張尺度適用中國國家橾隼（CNS)A4現格（210Χ297公釐161 - 306G73 A7 _____B7_ 五、發明説明（159) 消除雜訊爲其特徼•又因爲在包含於雜訊消除動作中之信 號加雜訊輸出時，與雜訊输出時，從單位晶胞觀察之雜訊 消除電路之阻抗相同，故可正確的消除雜訊。 亦即，在％雜訊成分^输出時，與 ''信號成分加雜訊 成分^輸出時，從單位晶胞觀察之雜訊消除電路之阻抗大 致上相同。因此，在該兩種输出時，雜訊成分大致上成爲 相同，計算兩者之差值，即可正確的去除雜訊成分輸出而 可只取出信號成分。因此，可正確的消除雜訊。從單位晶 胞觀察雜訊消除電路時，在阻抗之觀點上只能觀察到閘極 «容器，而且其電容量極小，故可在短時間內確實的消除 雜訊。 如上所述，依照本實施例，在雜訊消除電路中，箝位 電容器3 2 — 1 ，3 2 — 2..........與樣品保持電容器 3 4直接連接而且互相接近，故可在同一面上層叠形成， 可將電容器小型化。從單位晶胞觀察雜訊消除電路時，在 阻抗之觀點上只能觀察到閘極電容器，而其電容量極小， 故可在短時間內確實的消除雜訊。 經濟部中央標準局貝工消费合作社印裝 (請先閲讀背面之注意事".%寫本頁) 第3 5實施例 第8 5圖爲使用第3 5實施之放大型MOS偵測器之 攝像裝置之電路結構圖。單位晶胞P 8 - i - j附近之電 路結構與第3 3實施例相同。 將分離電晶體202 — 1 ，202-2 ..........串聯 於垂直信號線8 - 1 ，8 — 2 ’ .........並在分離電晶體 本紙張尺度遑用中囷國家標準（CNS)A4現格（ 210X297公釐）_ 162 _ A7 B7 經濟部中央棟準局員工消费合作社印裝 五’ *發明説明 ( 160) 1 2 0 2 — 1 » 2 0 2 — 2 » … … … 與 水 平 選 擇 電 晶 體 1 2 1 1 一 1， 1 2 — 2 9 … … 之 間 設 置 放 大 電 容 器 2 0 6 一 1 1 1 » 2 0 6 — 2 … … … 〇 亦 即 本 實 施 例 中 9 在 水 平 選 擇 電 1 I 請 1 I 晶 體之 前 不 設 置 雜 訊 消 除 電 路 而 設 置 調 整 放 大 係 數 之 放 大 先 閱 1 I 電 容器 〇 it 背 1 δ I 之 1 注 I 意 古 I 第 3 6 實 施 例 ¥ ^. 1 1 第 8 6 ΓΒ1 圚 爲 使 用 第 3 6 實 施 例 之 放 大 型 Μ 0 S 偵 測 器 窝 本 1 裝 之 攝像 裝 置 之 電 路 結 構 圖 0 單 位 晶 胞 P 8 一 i — j 附 近 之 頁 —^ 1 1 番 路結 構 與 第 3 3 實 施 例 相 同 0 1 1 第 3 6 實 施 例 係 在 第 3 3 實 施 例 之 雜 訊 消 除 電 路 上 連 1 | 接 第3 4 資 施 例 之 阻 抗 變 換 電 路 之 實 施 例 0 本 實 施 例 中 • 訂 I 箝 位電 晶 體 1 3 2 之 共 同 源 極 係 以 D C 驅 動 〇 1 1 1 1 第 3 7 實 施 例 1 1 1 以 下 參 照 第 8 7 8 8 圖 說 明 本 發 明 之 第 3 7 實 施 例 線 1 0 第8 7 圖 爲 使 用 第 3 7 實 施 例 之 放 大 型 Μ 0 S 偵 測 器 之 1 1 攝 像裝 置 之 電 路 結 構 圖 〇 單 位 晶 胞 P 8 — i — j 附 近 之 電 1 1 路 結構 與 第 3 3 實 施 例 相 同 0 1 1 I 負 載 電 晶 體 9 一 1 9 9 一 2 9 … … … 之 相 反 側 之 垂 直 1 1 I 信 號線 8 — 1 » 8 — 2 … … … 之 端 部 分 別 連 接 於 限 幅 電、 1 1 晶 體1 5 0 一 1 • 1 5 0 一 2 ♦ … … … 之 閘 極 〇 限 幅 電 晶 1 1 體 15 0 — 1 1 1 5 0 — 2 » … … … 之 源 極 連 接 於 限 幅 電 1 1 容 器1 5 2 一 1 > 1 5 2 — 2 … … … 之 — 端 〇 限 幅 電 容 1 1 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐）_ 163 - 經濟部中央標準局貝工消費合作社印製 A7 _B7_ 五、發明説明（161) 器1 5 2 — 1 ，1 5 2 - 2..........之另一端連接於限幅 脈波供給端子154。爲了復置限幅電晶體150_1 ， 15 0-2 ..........之源極電位，在限幅電晶體之源極與 限幅電源端子1 5 8之間設置限幅復置電晶體1 5 6 — 1 * 15 6 — 2 * .........而電晶體 156 — 1 ，156 — 2 ..........之閘極連接於限幅復置端子1 6 0。 限幅電晶體1 50 — 1 ，1 50 — 2..........之吸極 連接於限幅電荷傳送電容器162 — 1，162 — 2，… .......爲了復置限幅電晶體150 — 1 ，150 - 2，… ……之吸極電位，在其吸極與儲存吸極電源端子1 6 4之 間設置吸極復置電晶體166 — 1 ，166 — 2.......... 。電晶體166 — 1 ，166-2..........之閘極連接於 吸極復置端子168。限幅電晶體150 — 1 ，150 — 2..........之吸極經由從水平位址電路1 3供給之水平位 址脈波所驅動之水平選擇電晶體1 2 — 1 ，1 2 — 2，… ……連接於信號輸出端1 5。 如上所述，第3 7實施例之MO S偵測器與第8 1圓 所示之第3 3實施例比較，其單位晶胞P 8 - i — j之結 構相同，但雜訊消除電路之構成不同。第3 7實施例之雜 訊消除電路之特徵爲，將出現於垂直信號線8_1 ，8 — 2..........之電壓經由限幅電晶體1 5 0之閘極電容器變 換成電荷，在電荷領域內進行減法而抑制雜訊。 以下說明本實施例之驅動方法。第8 8爲本實施例之 動作之時序圖。第4 8圖表示限幅電晶體1 5 0 — 1 ， 本紙張尺度逋用中國國家橾隼（CNS>A4说格（210X297公釐）_ 164 - ---------批衣------IT------A (請先閱讀背面之注意事項一，4'寫本頁) A7 B7 經濟部中央標準局員工消費合作社印裝 五 •發明説明 ( 162) 1 1 1 5 0- 2 … ......之 電 位圖 〇 1 1 首先， 在 第 1 條垂直 位 址線 6 — 1 上 施 加 高 位 準 之 垂 1 1 直 位址脈 波 後 1 只有該 行 之單 位晶胞 之 垂 直 選 擇 電 晶 體 1 | 6 6導通 * 由 該 行之放 大 電晶 體6 4 與 負 載 電 晶 體 9 一 1 請 先 閲 1 I » 9 — 2 … … …構成 源 極跟 隨電路 0 讀 背 Λ 1 1 1 然後 贅 在 限 幅復置 端 子1 6 0上 施 加 限 幅 復 置 脈 波 » 意 1 1 使 限幅復 置 電 晶 體1 5 6 -1 ，15 6 — 2 9 … … … 導 通 事 項 1 1 > 將限幅 電 容 器 15 2 — 1， 15 2 — 2 9 … … … 之 電 荷 % 1 裝 初 期化。 頁 '—* 1 1 然後 贅 使 限 幅復置 電 晶體 15 6 斷 路 9 此 時 在 垂 直 1 1 信 號線8 一 1 9 8-2 • 4 · · _ · …上出 現 對 應 於 被 設 定 位 址 1 I 之 第1行 之 感 光 二極體 之 信號 «荷信 號 電 壓 〇 訂 I 在限 幅 脈 波 供給端 子 15 4上施 加 第 1 限 幅 脈 波 1 1 I S P 1 » 如 此 超越有 信 號時 (亦即 信 號 成 分 + 雜 訊 成 1 1 分 '之輸 出 時 ) 之限幅 電 晶體 15 0 之 閘 極 下 之 通 道 電 位 1 1 V ech將第1限幅電荷傳送至吸極。此時 在限幅復置端 線 1 子 16 8 上 施 加 吸極復 置 脈波 ，吸極 復 置 電 晶 體 1 6 6 導 1 I 通 ，故吸 極 電 位 被固定 於 儲存 吸極電 源 端 子 1 6 4 之 電 壓 1 I V Sdd。因此， 第1限幅電荷通過吸極復置電晶體1 e 6 1 1 I 被 排出於 儲 存 吸 極電源 端 子1 6 4。 1 1 I 然後 » 在 復 置線7 — 1上 施加復 置 脈 波 後 » 在 晶 胞 之、 1 1 感 光二極 體 被 復 置之垂 直 信號 線8 - 1 9 8 — 2 > … … … 1 1 上 只输出 無 信 號 之雜訊 成 分。 在限幅 脈 波 供 給 端 子 1 5 4 1 1 上 施加第 2 限 幅 脈波S P 2 · 如此， 超 越 施 加 m 信 號 電 荷 1 1 本紙張尺度遑用中國國家標準（CNS)A4規格（ 210X297公釐）-165- 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（l63) 時之電壓之限幅電晶體1 5 0之閘極下之通道電位VQCh ，將第2限幅電荷傳送至吸極。此時，因爲吸極復置電晶 體1 6 6斷路，故第2限幅電荷被傳送至連接於吸極之限 幅電荷傳送電容器1 6 2中。 然後，從水平位址電路1 3將水平選擇脈波依次施加 於水平選擇電晶體1 2 — 1，1 2 -，2 .........，從水平 信號線1 5依次取出相當於1條線之信號•在下一條線， 下下一條線時依次繼績進行該動作，即可讀出2次元狀之 全部信號。 該裝置中，假設限幅電容器1 5 2之電容量爲CS1時 ，最後在水平信號線1 5上讀出之電荷（第2限幅電荷） 癉成 C SlX ( V" sch_ V osc) 出現與有信號時，與被復置而無信號時之差成比例之電荷 ，故可抑制因爲單位晶胞內之放大電晶體6 4之閾值偏差 所產生之固定圖型雜訊。如此，將出現於垂直信號線8之 電壓變換成電荷，在電荷領域內進行減法之電路結構亦可 稱爲雜訊消除電路。 這種型式之雜訊消除電路之方法與第8 1圖之第3 3 實施例不相同。第3 3實施例中之箝位節1 4 5在其電壓 領已無雜訊之存在，而在電領域內消除雜訊。這種型式之 限幅電晶體1 5 0之源極端上，在電壓領域內未消除雜訊 本紙張尺度適用中國國家橾準（CNS)A4規格（ 210X297公釐>_ 166 _ ---------^------1T------^ (請先鬩請背面之注意事1 楱寫本頁) 一 A7 B7 經濟部中央標準局員工消費合作社印製 五’ •發明説明 ( 164) 1 1 t 但 施 加 第 3 4 個 限 幅 脈 波 S P 2 時 9 方 將 消 除 雜 訊 之 電 1 1 荷 傳 送 至 吸 極 〇 亦 即 在 電 荷 領 域 內 消 除 雜 訊 9 1 I 如 上 所 述 » 依 照 第 3 7 實 施 例 t 因 爲 經 由 雜 訊 消 除 電 1 I 路 输 出 單 位 晶 胞 之 輸 出 t 故 可 去 除 配 合 單 位 晶 胞 之 放 大 電 請 先 閱 1 I 晶 體 之 閾 值 不 均 勻 之 固 定 ΓΒΊ 圖 型 雜 訊 〇 讀 背 面 1 1 | 又 因 爲 將 單 位 晶 胞 之 輸 出 經 由 限 幅 電 晶 體 之 閘 極 電 容 之 注 意 1 1 1 器 供 給 於 雜 訊 消 除 電 路 « 故 在 雜 訊 輸 出 時 與 信 Dffe m 加 雜 訊 输 事 1 1 出 時 9 從 單 位 晶 胞 觀 察 之 雜 訊 消 除 電 路 之 阻 抗 大 致 上 成 爲 % 寫 1 裝 相 同 1 故 在 該 兩 種 輸 出 時 9 雜 訊 成 分 大 致 上 成 爲 相 同 » 計 頁 1 1 算 兩 者 之 差 值 9 即 可 正 確 的 去 除 雜 訊 可 以 只 取 出 信 號 成 1 I 分 可 正 確 的 消 除 雜 訊 0 從 單 位 晶 胞 *11 1 觀 察 雜 訊 消 除 電 路 時 1 I 9 在 阻 抗 之 觀 點 上 只 能 觀 察 到 閘 極 電 容 器 而 且 其 電 容 量 訂 I 極 小 故 可 在 短 時 間 內 確 實 的 消 除 雜 訊 〇 1 1 1 第 2 個 限 幅 脈 波 S P 2 可 能 受 到 正 刖 方 之 第 1 個 限 幅 1 1 脈 波 S P 1 之 影 響 0 因 此 爲 了 使 第 1 第 2 限 幅 脈 波 對 1 1 第 1 第 2 電 晶 體 之 動 作 之 影 響 成 爲 相 同 在 第 1 限 幅 脈 線 1 波 S P 1 之 正 .> 1. 刖 方 設 置 模 擬 脈 波 最 爲 有 效 〇 若 第 1 限 幅 脈 1 I 波 與 第 2 限 幅 脈 波 之 振 幅 相 同 時 t 在 微 妙 之 電 壓 條 件 下 1 I 可 能 在 微 小 信 號 領 域 內 不 能 讀 出 信 號 電 荷 或 直 線 劣 化 y 故 1 1 I 將 第 2 限 幅 脈 波 之 振 幅 設 定 爲 大 於 第 1 限 幅 脈 波 之 振 幅 9 1 1 I 在 由 第 2 限 幅 脈 波 讀 出 之 電 荷 上 相 加 偏 壓 電 荷 > 其 動 作 較、 1 1 穩 定 〇 將 第 2 限 幅 脈 波 之 寬 度 設 定 爲 大 於 第 1 限 幅 脈 波 之 1 1 寬 度 亦 爲 有 效 之 方 法 0 1 1 1 1 本紙張尺度適用中國國家揉準（CNS)A4規格（ 210X297公釐）-167- A7 B7 經濟部中央標準局員工消費合作社印製 五 發明説明 (165) I 1 第 3 8 實 施 例 1 1 以 下 參 照 第 8 9 圔 說 明 第 3 8 實 施 例 0 第 8 9 1 〇.1 圖 爲 使 I 1 用 第 3 8 實 施 例 之 放 大 型 Μ 0 S 偵 測 器 之 攝 像 裝 置 之 電 路 1 I 請 1 I 結 JMt 稱 圖 〇 單 位 晶 胞 P 8 — 1 一 j 附 近 之 電 路 結 構 Cbs3 與 第 3 3 先 閱 1 1 資 施 例 相 同 〇 讀 背 1 第 之 1 3 8 實 施 例 係 從 第 8 3 圖 所 示 之 第 3 4 實 施 例 中 省 注 意 1 I 略 由 源 極 跟 隨 電 晶 體 所 構 成 之 阻 抗 變 換 電 路 實 施 例 〇 事 1 1 1 % 本 S* 1 裝 I 第 3 9 實 施 例 η 1 1 以 下 參 照 第 9 0 » 9 1 及 9 2 圚 說 明 第 3 9 實 施 例 0 1 1 第 9 0 9 1 圓 爲 使 用 第 3 9 實 施 例 之 放 大 型 Μ 0 S 偵 測 1 1 器 之 攝像裝 置 之 電 路 結 構 圖 〇 單 位 晶 胞 P 8 一 i — j 附近 訂 I 之 電 路 結構 與 第 3 3 實 施 例 相 同 1 1 I 本 實 施 例 中 有 許 多 部 分 與 第 8 1 圖 所 示 之 第 3 3 實 施 1 1 I 例 共 同 其 不 同 之 處 爲 將 用 來 修 正 在 % 信 wt 成 分 + 雜 訊 成 -ν· 1 1 線 1 分 • 输 出 時 與 只 输 出 % 雜 訊 成 分 /r 時 之 從 單 位 晶 胞 觀 察 之 雜 訊 消 除 電 路 之 阻 抗 值 之 不 同 之 電 容 器 C CM P 1 6 0 - -] 1 1 > 1 6 0 — 2 … … … 在 較箝 位 電 容 器 1 3 1 — 1 1 I 1 3 1 — 2 ♦ … … … 更 靠 近 攝 像 領 域 ( 單 位 晶 胞 側 ) 經 1 I 由 開 關 1 6 2 — 1 » 1 6 2 — 2 • · … • · 並 聯 於 垂 直 信 號 1 1 I 線 8 — 1 » 8 — 2 * … … … 〇 在 第 9 0 圖 中 • 修 正 電 容 器、 1 1 1 1 6 0 及 開 關 1 6 2 係 連 接 於 箝 位 電 容 器 1 3 1 與 攝 像 領 1 1 域 之 間 在 第 9 1 圖 中 ， 係 連 接 於 攝 像 領 域 與 負 載 電 晶 體 1 1 9 之 間 〇 1 1 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐）_ 168 _ 經濟部中央標準局貝工消費合作杜印製 A7 ___B7 五、發明説明（166) 第9 2圖爲本實施例之動作時序圚。開關1 6 2在箝 位電晶體1 3 2之箝位終了，在垂直信號線上只輸出感光 二極體復置後之雜訊之期間內成爲導通狀態》因此，假設 樣品保持電容器1 3 4之電容量爲CSH，箝位電容器 1 3 1之電容置爲C &時，在樣品保持時連接於垂直信號 線8之電容量成爲 C = CCMp+CsH· Ccl/ (CcL+CsH) 若將修正電容器之電容置C CMP在 2 { C c U _ C c L * C sh/ ( C CL+ C SH) }〉C CMP〉0 之範圍內設定時，與無修正電容器時比較，在樣品保持時 連接於垂直信號線之電容量接近箝位電容器131之電容 量Ccl·因此，其差值Vet變成更小，故雜訊亦變小。 第5 5圖表示垂直信號線8之電位與箝位節1 4 5之 電位之時間變化。本實施例中，例如在信號爲〇之暗時’ 當垂直信號線8之電位復原至箝位時之電位與復原樣品保 持時之電位相同時，在樣品保持終了時之箝位節之電位不 會復原至接近之數值，但變成0。因此，不會發生 雖然爲暗時而信號爲〇 ’但出現相當於u之信號之問 題。因此，可防止因之不均勻而造成之雜訊之產生 本紙張尺度適用中國國家標準（CNS)A4说格（210Χ 297公釐）_ 169 - 裝 I II訂——IIII線 (請先閱讀背面之注意事項广4·寫本頁) 經濟部中央樣準局貝工消费合作社印製 A7 B7 五、發明説明（l67) 如上所述，依照本實施例之具有雜訊去除電路之 MO S型固髖攝像元件，因爲在垂直信號線8上設置修正 電容器1 6 0，故可抑制造成發生雜訊之原因之雜訊去除 動作中之電容量變化，可更進一步降低雜訊。亦即，選擇 感光二極體後之信號加雜訊输出時，與復置終了後之雜訊 输出時，從晶胞觀察之阻抗成爲相同，可正確的消除雜訊 第3 9實施例之變更例可例如在第8 3圖所示之第 3 4實施例，第8 5圖所示之第3 5實施例，第8 6圖所 示之第3 6實施例，第8 7圖所示之第3 7資施例，第 8 9圖所示之第3 8實施例之雜訊消除電路連接修正用電 容器。 第3 4〜3 9實施例係說明雜訊消除電路與第3 3實 施例不同之實施例。以下說明單位晶胞之結構與第3 3〜 39實施例不同之其他資施例· 第4 0實施例 以下參照第9 3圖說明第4 0實施例•第9 3圇爲使 用第4 0實施例之放大型MO S偵測器之固體攝像裝置之 全部電路圖。本實施例之單位晶胞P 9 - i _ j係從第 3 3實施例之單位晶胞中省略位址電容器6 9之單位晶胞 本實施例中，當垂直位址電路5設定放大電晶體6 4 之吸極後，爲了變動放大電晶體6 4之閘極下之通道之電 本紙張尺度遑用中國國家橾準（CNS)A4規格（210X297公釐）_ 170 - ί I I I I I 裝 I 訂—— II 線 (請先閲讀背面之注意事項寫本頁) 一 經濟部中央標準局員工消費合作社印製 A7 ____B7___ 五、發明説明（I68) 位而利用短路通道效果。亦即利用當放大電晶體6 4之吸 極電位增高時，耗盡層從吸極延伸至閘極下之通道，閾值 電壓變化至負方向之現象。只有被設定位址之線之單位晶 胞之感光二極體6 2之輸出信號出現於垂直信號線8之理 由與第3 3實施例完全相同。 如上所述’依照本實施例，不僅是無垂直選擇電晶體 時，即使無位址霄容器時，仍可設定垂直位址線，因此其 元件數置比第3 3實施例少，可實現晶胞之微細化。 第4 0實施例亦與第3 3實施例相同的可變更雜訊消 除電路。亦即第8 1〜9 2圓，及第5 5圖之說明亦可同 樣的應用於第4 0實施例。 第4 1實施例 以下參照第9 4圖說明第4 1實施例。第9 4圖爲使 用第4 1實施例之放大型MO S偵測器之固體攝像裝置之 全部電路圖。本實施例之單位晶胞P 1 0 - i - j係將垂 直選擇電晶體設在晶胞外，在1條垂直位址線上只設置1 個之單位晶胞•亦即單位晶胞P 1 0 - i 一 j包括感光二 極體62— i — j ，感光二極體62 - i — j之檢測信號 放大用放大電晶體6 4 — i — j ，復置感光二極體6 2 — i_j之信號電荷之復置電晶體66—i—j 。 從垂直位址電路5朝向水平方向配線之垂直位址線6 -1*6-2 ..........連接於垂直選擇電晶體3 0 2 - 1 •302-2*.........之閘極，垂直選擇電晶體302— 本紙張尺度適用中國國家梯準（CNS)A4規格（ 210X297公釐）-171 - 111 I 裝 I I —訂— I 11 I 線 (請先閱讀背面之注意事虱 k寫本頁) ί 306G73 A7 B7 五、發明説明（169) 1*3 0 2 -2 之源極連接於各單位晶胞之放大 電晶體6 4之源極，及復置電晶體6 6之源極。垂直選擇 • · · · · · 電晶體3 0 2 — 1 接於吸極端子3 0 依照本實施例 得由垂直位址電路 爲共同吸極電源3 址之垂直位址線在 定位址之垂直位址 作，只有連接於被 光二極體6 2之檢 序與第8 2圓所示 第4 1實施例 除電路。亦即第8 樣的應用於第41 3 0 2 -1 4。 ，因爲 5設定 0 4之 電氣上 線上之 設定位 測信號 第3 3 亦與第 1〜9 實施例 垂直選擇電晶 位址之1條垂 位準（高位準 成爲漂浮。因 單位晶胞之放 址之垂直位址 出現於垂直信 實施例之動作 3 3實施例相 2圖，及第5 之吸極共同的連 體3 0 直位址 )，但 此，連 大電晶 線之單 號線8 時序相 同的可 5圖之 2導通，使 線之®位成 未被設定位 接於未被設 體6 4不動 位晶胞之感 。其動作時 同。 變更雜訊消 說明亦可同 請 閱 讀 背 之 注 意 事 % 4、I裝 頁 訂 線 經濟部中央標準局貝工消费合作社印製 第4 2實施例 第9 5圖爲用來說明第4 2實施例之圖，亦即使用放 大型MO S偵測器之固體攝像裝置之全部電路圖。本實施 例之單位晶胞PI l — i — j係從第81圖所示第33實 施例之基本晶胞中省略復置電晶體6 6及復置線7之晶胞、 。亦即單位晶胞P 1 1 — i — j包括感光二極體6 2 — i 一j ，放大感光二極體62—i-j之檢測信號之放大電 晶體 64_i — j * 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）-172 - 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（no) 從垂直位址電路5朝向水平方向配線之垂直位址線6 —1 ，6 — 2..........連接於放大電晶體6 4之吸極，而 且經由位址電容器6 9連接於放大電晶體6 4之閘極。 第9 6圖表示本實施例之動作時序圖·該圖除了在施 加於垂直位址線6 _ 1，6 - 2..........之位址脈波中途 插入負信號電荷排出脈波P d以外，其他與第8 2圖所示 之第3 3實施例之時序圖相同。 以下說明第9 6圖之時序之前後關係。其所必須之順 序如下* 垂直位址脈波之第1次上昇—箝位脈波之下降—信號 電荷排出脈波之上昇—信號電荷排出脈波之下降—樣品保 持脈波之下降-垂直位址脈波之第2次下降 垂直位址脈波之第1次上昇，樣品保持脈波之上昇， 及箝位脈波之上昇之前後關係可爲任意。但最好依照上述 順序β 第9 7圖表示本實施例之基本晶胞之斷面構造與信號 電荷之排出狀態。其基本動作與第3 3實施例相同。因爲 具有位址電容器6 9，故即使無垂直選擇電晶體，仍可設 定垂直位址線之位址。信號讀出終了之後，在垂直位址線 6 — 1 ，6 — 2 ..........上施加負信號電荷排出脈波P d ，經由結合電容器將感光二極體6 2之電位偏壓至負方向、 ，將內部之信號電荷排出於P型基板上。如此’可復置信 號電荷。雜訊去除電路之動作與第3 3實施例完全相同。 如上所述，依照本實施例，可用感光二極體6 2 ’放 本紙張尺度適用中困國家標準（CNS)A4規格（210X297公釐）-173 - I I I I I 裝 I I —訂 線 (請先閱讀背面之注意事項‘ j..寫本頁) 一 A7 B7 經濟部中央標準局貝工消費合作社印袈 五 發明説明 ( 171) 1 I 大 電 晶 體 6 4 及 位 址 電 容 器 6 9 構 成 基 本 晶 胞 故 可 將 1 1 單 位 晶 胞 大 幅 度 的 微 細 化 〇 1 1 第 4 2 實 施 例 亦 與 第 3 3 實 施 例 相 同 的 可 變 更 雜 訊 消 1 I 請 1 1 除 電 路 0 亦 即 > 第 8 1 9 2 圖 1 及 第 5 5 圖 之 說 明 亦 可 先 閱 1 I 讀 1 同 樣 的 應 用 於 第 4 2 實 施 例 0 背 1 之 1 注 | 意 重 第 4 3 實 施 例 Ψ 項 jr — 1 第 9 8 圖 爲 用 來 說 明 第 4 3 實 施 例 之 圚 〇 亦 即 使 用 放 寫 本 1 裝 大 型 Μ 0 S 偵 測 器 之 固 體 攝 像 裝 置 之 全 部 電 路 圖 0 本 實 施 頁 ^ 1 1 例 之 單 位 晶 胞 Ρ 1 2 — i 一 j 係 在 第 8 1 圖 所 示 之 第 3 3 1 1 實 施 例 之 晶 胞 結 構 中 » 於 感 光 二 極 體 6 2 與 放 大 電 晶 體 1 | 6 4 之 閘 極 之 間 附 加 傳 送 電 晶 體 3 0 6 之 例 傅 送 電 晶 體 訂 I 3 0 6 之 共 同 閘 極 3 0 8 連 接 於 垂 直 位 址 電 路 5 〇 1 1 1 1 第 4 4 實 施 例 1 1 1 第 9 9 圖 爲 用 來 說 明 第 4 4 實 施 例 之 圖 〇 亦 即 使 用 放 線 1 大 型 Μ 0 S 偵 測 器 之 固 體 攝像 裝 置 之 全 部 電 路 圇 9 本 實 施 1 1 例 之 單 位 晶 胞 Ρ 1 3 — i — j 係 在 第 9 3 圖 所 示 之 第 4 0 1 I 實 施 例 之 晶 胞 結 構 中 於 感 光 二 極 體 6 2 與 放 大 電 晶 體 1 1 1 6 4 之 閘 極 之 間 附 加 傅 送 電 晶 體 3 0 6 之 例 « 1 1 1 第 4 5 實 施 例 1 1 1 第 1 0 0 圖 爲 用 來 說 明 第 4 5 實 施 例 之 圖 〇 亦 即 使 用 1 1 放 大 型 Μ 0 S 偵 測 器 之 固 體 攝 像 裝 置 之 全 部 電 路 圚 9 本 實 1 1 本紙張尺度適用中國國家標率（匸阳）八4規格（2丨0乂297公釐）-174- A7 B7 經濟部中央標準局貝工消費合作社印製 五、 發明説明 ( 172) 1 I 施 例 之 單 位 晶 胞 P 1 4 一 1 — j 係 在 第 9 4 圖 所 示 之 第 1 1 4 1 實 施 例 之 晶 胞 結 構 中 t 於 感 光 二 極 體 6 2 與 放 大 電 晶 1 1 體 6 4 之 閘 極 之 間 附 加 傳 送 電 晶 體 3 0 6 之 晶 胞 〇 1 | 請 1 1 先 閲 1 1 第 4 6 實 施 例 背 1 | 第 1 0 1 圖 爲 使 用 第 4 6 實 施 例 之 放 大 型 Μ 0 S 偵 測 1 1 1 1 器 之 固 體 SJ5L 攝 像 裝 置 之 全 部 電 路 圖 0 本 實 施 例 之 單 位 晶 胞 事 項 再一: 1 1 P 1 5 — i — j 係 在 第 9 5 圖 所 示 第 4 2 實 施 例 之 晶 胞 結 本 1 裝 稱 中 » 於 感 光 二 極 體 6 2 與 放 大 電 晶 體 6 4 之 閘 極 之 間 附 頁 •—^ 1 1 加 傳 送 電 晶 體 3 0 6 之 晶 胞 0 1 1 第 1 0 2 圖 爲 本 實 施 例 之 動 作 時 序 圖 〇 在 水 平 熄 滅 期 1 | 間 內 於 垂 直 位 址 線 6 — 1 上 施 加 髙 位 準 之 位 址 脈 波 後 * 訂 I 該 高 位 準 之 位 址 脈 波 經 由 位 址 電 容 器 6 9 供 給於 連 接 在 該 1 1 I 線 之 單 位 晶 胞 之 放 大 電 晶 體 6 4 之 閘 極 該 閘 極 下 之 通 道 1 1 I 之 電 位 變 成 高 於 連 接 於 其 他 線 之 單 位 晶 胞 之 放 大 電 晶 體 1 1 6 4 之 閘 極 下 之 通 道 電 位 而 成 爲 導 通 〇 因 此 由 連 接 於 垂 線 1 直 位 址 線 6 — 1 之 單 位 晶 胞 之 放 大 電 晶 體 6 4 及 負 載 電 晶 1 1 體 9 構 成 源 極 跟 隨 電 路 Q 然 後 在 垂 直 信 號 線 8 上 出 現 放 1 1 大 電 晶 體 6 4 之 閘 極 電 壓 亦 即 與 感 光 二 極 體 6 4 之 電 壓 1 1 大 致 上 相 等 之 電 壓 〇 1 I 如 此 » 在 垂 直 信 號 線 8 一 1 8 — 2 … … … 上 只 出 1 1 I 現 被 設 定 位 址 之 線 之 放 大 電 晶 體 6 4 之 閘 極 電 位 而 不 出 1 1 現 其 他 線 之 放 大 電 晶 體 6 4 之 閘 極 電 位 0 因 此 即 使 省 略 1 1 垂 直 選 擇 電 晶 體 » 仍 可 設 定 垂 直 位 址 線 之 位 址 〇 1 1 本紙張尺度遑用中國國家橾準（CNS) A4規格（210X29*7公釐）_ 175 - A 7 B7 經濟部中央標隼局員工消費合作社印製 五、發明説明（173) 然後，在垂直位址線6 — 1上施加大振幅之負電荷排 出脈波C D而復置感光二極體6 2之電荷。然後，在樣品 保持電晶體13 3 — 1 ，133 — 2 .........之共同閘極 1 4 3上施加高位準之樣品保持脈波後，在箝位電晶體 132-1*132-2' .........之共同閘極142上施 加箝位脈波，使箝位電晶體132 - 1 ，132 — 2，… ......成爲導通，將辩位節1 4 5 — 1 ，1 4 5 - 2....... …之電壓固定爲與箝位電壓141相同之電壓。 然後，使箝位電晶體132 — 1，132-2 ....... …斷路後，在電荷傳送線3 0 8 - 1上施加髙位準之傳送 脈波，使電荷傳送電晶體306 - 1 ，306 - 2 ....... …導通。如此，在箝位節1 4 5 - 1，1 4 5 — 2 ...... …上出現將感光二極體6 2中有信號電荷時與被復置而無 信號電荷時之垂直信號線8 - 1 ，8 — 2 .........之電壓 之差相加於箝位電源1 4 1之電壓•然後，完成樣品保持 脈波之施加* 然後，從水平位址電路1 3將水平位址脈波依次施加 於水平選擇電晶體1 2 - 1 ，1 2 — 2 ...........從水平 信號線1 5依次取出相當於1條線之信號。 以下說明第9 6圖之時序之前後關係β其必須之順序 如下· 、 垂直位址脈波之第1次上昇—垂直位址脈波之第1次 下降—垂直位址脈波之第2次上昇—箝位脈波之下降—電 荷傳送脈波之上昇—電荷傳送脈波之下降—樣品保持脈波 (請先閱讀背面之注意事項4:¾本頁) 、νβ Γ 本紙張尺度適用中國國家橾率（CNS ) Α4規格（210X297公釐）_ 176 - A7 B7 經濟部中央標準局貝工消費合作社印装 五， •發明説明 ( 174) 之 下 降 —> 垂 直 位 址 脈 波 之 第 2 次 下 降 垂 直 位 址 脈 波 之 第 2 次 上 昇 t 樣 品 保 持 脈 波 之 上 昇 t 箝 位 脈 波 之 上 昇 • 及 箝 位 脈 波 之 下 降 之 前 後 關 係 可 爲 任 意 9 但 最 好 爲 依 照 上 述 順 序 0 依 照 第 4 3 4 6 實 施 例 之 結 構 ♦ 因 爲 將 感 光 二 極 體 6 2 與 放 大 電 晶 體 6 4 分 離 9 故 可 減 小 檢 測 電 荷 之 電 容 量 而 提 高 靈 敏 度 0 亦 可 使 傳 送 電 晶 體 3 0 6 斷 路 先 將 相 當 於 4rrt: 撕 信 號 電 荷 時 之 雜 訊 成 分 之 電 壓 输 出 於 垂 直 信 8 * 然 後 使 傳 送 電 晶 體 3 0 6 斷路 而 输 出 相 當 於 有 信 wt 電 荷 時 之 信 號 成 分 加 雜 訊 成 分 之 電 壓 « 如 此 先 復 置 之 結 果 又 可 同 時 去 除 因 復 置 動 作 而 產 生 之 隨 意 雜 訊 〇 第 4 3 4 6 實 施 例 亦 興 第 3 3 實 施 例 相 同 的 可 變 更 雜 訊 消 除 電 路 0 亦 即 第 8 1 9 2 圖 及 第 5 5 圖 之 說 明 又 可 同 樣 的 ntg 應 用 於 第 4 3 4 6 實 施 例 〇 本 發 明 不 受 上 述 實 施 例 之 限 制 可 在 不 超 越 其 要 旨 之 範 圍 內 變 更 實 施 〇 例 如 若 可 製 造 Jtvr 撕 閾 值 不 均 勻 之 單 位 晶 胞 之 放 大 電 晶 體 則 因 爲 不 產 生 固 定 圖 型 雜 訊 故 可 省 略 雜 訊 消 除 電 路 〇 或 者 即 使 產 生 固 定 圖 型 雜 訊 » 只 要 畫 質 不 受 影 響 y 則 可 同 樣 的 省 略 雜 訊 消 除 電 路 〇 在 各 實 施 例 之 雜 訊 消 除 電 路 中 jhrr 撕 输 入 信 號 時 讀 出 之 信 號 電 流 ( 只 有 雜 訊 成 分 ) 愈 小 t 雜 訊 亦 愈 少 » 故 最 好 使 施 加 於 儲 存 吸 極 電 源 端 子 之 電 壓 與 視 頻 偏 壓 成 爲 大 致 上 相 等 〇 所 謂 視 頻 偏 壓 係 指 從 水 平 信 號 線 1 5 中 以 電 流 方 式 讀 出 信 號 時 水 平 信 號 線 1 5 被 固 定 之 電 壓 〇 第 9 5 圖 表 示 請 閲 讀 背 面 項 再 本 頁 本紙張尺度適用t國國家標準（ 經濟部中央標準局員工消費合作社印装 A 7 B7 五、發明説明（175) 該變更例。输出信號線1 5連接於運算放大器1 7 6 ’運 算放大器1 7 6之输入输出端之間連接負載電阻1 7 8 » 如此，信號電流強制的流入負載電阻1 7 8，水平信號線 1 5被固定爲假想之電壓，亦即視頻偏壓。 以上實施例中，單位晶胞係排列成二次元矩陣狀’但 本發明亦可應用於將單位晶胞排列成一次元陣列狀之攝像 裝置。亦即，除了可形成爲將單位晶胞排列成mx η之二 次元矩陣狀之區域偵測器之結構以外，亦可形成爲將單位 晶胞排列成一列之一次元排列之線偵測器》 第4 7實施例 希望隨意存取MO S偵測器中之矩陣狀排列之受光部 分，亦即MO S晶胞矩陣時，包括晶胞在內之周邊電路之 結構成爲如第1 0 3圖所示之結構。 第1 0 3圖中· MOS偵測器係將mx η個感光二極 體排列成矩陣狀之mx η圖素結構之MO S偵測器。該偵 測器包括具有將m X η個感光二極體排列成矩陣狀之受光 部（輸入部）I ，從構成該受光部I之各感光二極體中依 次讀出信號之讀出控制部CONT，及雜訊消除電路NC 之處理部m，输出該處理部m讀出之信號之輸出部。 讀出控制部CONT係由垂直位址電路5，及水平位 址電路1 3所構成，垂直位址電路5被垂直位址緩衝器 Bv A及垂直解碼電路Dv取代•而水平位址電路1 3被水 平位址緩衝器B HA及水平解碼電路D H取代》位址信號a 本紙張尺度適用中國國家揉率（CNS)A4現格（ 210X297公釐）-Π8 - (請先閱讀背面之注意事項再填Α ，頁) -·一9 B7 經濟部中央揉準局貝工消费合作社印装 五， 發明説明 (176) 1 A i 输 入 垂 直 位 址 仲 衝 器 B V A ‘中 » 位 址 信 號 A - A n 輸 入 水 平 位 址 緩 衝 器 B H A 中 y 由 各 位 址 選 擇 特 定 之 晶 胞 〇 經 由 位 址 緩 衝 器 B V A 9 B Η A 输 入 之 位 址 信 號 使 垂 直 解 碼 電 路 D V及水平解碼電路Dh 選 定 特 定 之 線 〇 第 1 0 4 圖 表 示 位 址 緩 衝 器 B V A > B Η A 及 解 碼 電 路 D V ，D Η 之 具 體 結 構 〇 爲 了 說 明 之 方 便 % 表 示 只 使 用 位 址 信 號 A 1 « A 2 A 3 時 之 例 〇 通 過 對 應 於 位 址 信 號 A 1 A 2 » A 3 之 倒 相 器 I N V 1 I N V 2 » I N V 3 被 反 轉 之 信 號 與 原 來 之 信 號 成 爲 平 行 的 配 置 成 縱 方 向 之 線 選 擇 —· 個 不 同 之 信 號 而 配 置 输 入 上 述 三 個 信 號 之 N 0 R 電 路 N 0 R 1 N 0 R 2 9 N 0 R 3 0 N 0 R 電 路 N 0 R 1 > N 0 R 2 N 0 R 3 輸 入 上 述 rr 個 输 入 信 號 之 N 0 R 邏 輯 只 從 全 部 输 入 信 號 爲 L 位 準 之 電 路 輸 出 Η 位 準 之 信 號 而 選 定 特 定 之 線 〇 選 擇 垂 直 線 之 位 址 信 號 與 選 擇 水 平 線 之 位 址 信 號 亦 可 從 其 他 位 址 端 子 输 入 但 亦 可 使 用 多 工 器 t 將 位 址 信 號 做 爲 行 位 址 信 號 ( 垂 直 方 向 之 位 址 信 號 ) 輸 入 之 R A S 信 號 及 將 位 址 信 號 做 爲 列 位 址 信 號 ( 水 平 方 向 之 位 址 信 號 ) 輸 入 之 C A S j 從 同 一 位 址 端 子 輸 入 〇 如 上 所 述 » 依 照 本 發 明 * 可 提 供 -- 種 可 消 除 雜 訊 而 產 生 完 美 之 晝 像 信 號 » 而 且 以 單 —. 電 源 即 可 驅 動 之 放 大 型 Μ 0 S 型 固 體 攝 像 裝 置 0 又 可 以 提 供 — 種 可 將 單 位 晶 胞 微 細 化 9 因 而 可 將 全 部 外 型 小 型 化 之 放 大 型 Μ 0 S 型 固 體 攝 像 裝 置 〇 又 因 爲 使 用 該 放 大 型 Μ 0 S 型 固 體 攝 像 裝 置 t 故 本紙張尺度適用中國國家橾率（CNS)A4規格（ 210X297公釐）-179 - 經濟部中央樣準局員工消费合作杜印製 A7 ________B7_____ 五*、發明説明（177) 可提供一種小型，節省電力，高畫質之MO S型固體攝像 #置應用系統》 圖式： 第1圖爲MO S型固體攝像裝置之習用例之電路圖； 第2圖爲第1圖所示習用例之動作時序圖； 第3圖爲固定攝像元件之基本結構圚； 第4爲使用MO S偵測器做爲畫像檢測部之裝置之一 般結構圖； 第5圖爲本發明第2實施例之說明圖，使用本發明之 M〇 S偵測器之視頻攝像機之實施例之結構圖； 第6圖爲將彩色過濾器陣列1 〇 4與MO S偵測器 1 〇 5 —體化之MO S攝像裝置之一實施例之斷面圖； 第7圓爲本發明第3實施例之說明圖，使用本發明之 M〇 S偵測器之另一視頻攝像機之實施例之結構圖； 第8圖爲本發明第4資施例之說明圓，本發明之放大 型M〇 S偵測器在網路系統中之應用例之圖； 第9圇爲本發明第5實施例之說明圖，本發明之放大 型MO S偵測器應用於靜止攝像機之實施例之說明圖： 第1 0圖爲本發明第6實施例之說明圖*使用本發明 之MOS偵測器之電話傳真裝置之實施例之圖； 、 第1 1圖爲本發明第7實施例之說明圖，使用本發明 之MO S偵測器之電子複印機之實施例之圖； 第1 2圖爲本發明第8實施例之說明圖，使用本發明 本紙張尺度適用中國國家標準（CNS}A4規格（210Χ297公釐）_ _ 1111 . I 訂 線 (請先閱讀背面之注意事項#-....鳥本頁) ( 306073 A7 B7 經濟部中央標準局員工消费合作社印«. 五、 發明説明 (178) 1 1 之 Μ 0 S 偵 測 器 之 手 提 式 圖 像 掃 描 器 之 實 施 例 之 圖 1 I 第 1 3 圖 爲 本 發 明 第 9 實 施 例 之 說 明 蹁 • 使 用 機械 切 1 1 換 式彩 色 過 濾 器 之 放 大 型 Μ 0 S 偵測 器 之 結構 例 之 圖 1 I 請 1 I 第 1 4 圚 爲 本 發 明 第 1 0 實 施 例 之 說 明 圖 * 本 發 明 之 先 Μ 1 I 讀 1 放 大型 Μ 0 S 偵 測 器 nhs 應 用 於 薄 膜 掃 描 裝 置 之 說 明 圖 背 1 I 之 1 第 1 5 圖 爲 本 發 明 第 1 1 實 施 例 之 說 明 圓 使 用 本 發 注 意 1 I 明 之Μ 0 S 偵 測 器 之 具 有 白 動 對 焦 機 構 之 單 眼 反 射 式 照 相 事 1 1 I 機 之實 施 例 之 圖 % 本 1 裝 第 1 6 A 1 6 B 1 6 C 圃 爲 用 來 說 明 白 動 對 焦 機 頁 1 1 構 之對 焦 原 理 之 圖 1 1 第 1 7 圖 爲 本 發 明 第 1 2 實 施 例 之 說 明 圔 Μ 0 S 型 I 1 固 體攝 像 裝 置 之 結 構 例 之 電 路 圖 1 訂 I 第 1 8 圖 爲 第 1 2 實 施例 之 垂 直 位 址 電 路 之 電 路 圖 t 1 1 I 第 1 9 圖 爲 第 1 2 實 施 例 之 垂 直 位 址 電 路 之 其 他 電 路 1 1 圓 * 1 1 第 2 0 圖 爲 第 1 2 實 施 例 之 垂 直 位 址 電 路 之 另 — 電 路 線 1 圔 1 1 第 2 1 圖 爲 第 1 2 實 施 例 之 單 位 晶 胞 之 電 路 圖 t 1 I 第 2 2 A 2 2 B 2 2 C 圖 爲 用 來 說 明 修 正 第 1 2 1 1 實 施例 之 單 位 晶 胞 之 放 大 電 晶 體 之 閾 值 電 壓 不 均 勻 之 原 理 1 1 之 圖： - 1 1 第 2 3 圖 爲 第 1 2 實 施 例 之 動 作 時 序 圖 » 1 1 第 2 4 圖 爲 第 1 2 實 施 例 之 雜 訊 消 除 電 路 裝 置 之 構 造 1 I 斷 面圖 » 1 1 本紙張尺度適用中國國家標準（CNS> Μ規格（ 210X297公釐）-181 - 306073 經濟部中央標準局貝工消費合作社印製 五Λ 發明説明 ( 179) 1 I 第2 5 A » 2 5 B 圖 爲 第 1 2 實 施 例 之 單ί 立晶 胞 之 裝 1 1 置 構 造之 斷 面 圖 1 1 第2 6 圖 爲 第 1 2 實 施 例 之 單 位 晶 胞 之 半導體 基 板 變 1 1 更 例 之圖 * 請 先 1 閲 1 第2 7 圖 爲 C C D 型 固 體 攝 像 裝 置 之 習 用例之 晶 胞 之 •Λ 背 1 I 斷 面 ΡΒΠ 圖， 之 1 1 意 I 第2 8 圖 爲 第 1 2 實 施 例 之 單 位 晶 胞 之 半導體 基 板 之 事 1 1 其 他 變更 例 之 圖 寫 本 1 第2 9 圖 爲 第 1 2 實 施 例 之 單 位 晶 胞 之 半導體 基 板 之 頁 1 1 其 他 變更 例 之 圚 1 l 第3 0 圓 爲 第 1 2 資 施 例 之 單 位 晶 胞 之 半導體 基 板 之 1 1 其 他 變更 例 之 圖 1 訂 1 第3 1 圖 爲 第 1 2 實 施 例 之 單 位 晶 胞 之 半導體 基 板 之 1 1 I 其 他 變更 例 之 圖 t 1 1 第3 2 圖 爲 第 1 2 實 施 例 之 單 位 晶 胞 之 半導體 基 板 之 ««i. 1 1 其 他 變更 例 之 圖 1 線 1 第3 3 圇 爲 本 發 明 第 1 3 實 施 例 之 說 明 圖 Μ 0 S 型 1 I 固 體 攝像 裝 置 之 電 路 圓 1 I 第3 4 圚 爲 第 1 3 實 施 例 之 動 作 時 序 圖 f 1 1 I 第3 5 圖 爲 本 發 明 第 1 4 實 施 例 之 說 明 圖 Μ 0 S 型 1 1 固 體 攝像 裝 置 之 電 路 圖 1 1 第3 6 圚 爲 第 1 4 實 施 例 之 動 作 時 序 圖 t 1 1 第3 7 圚 爲 本 發 明 第 1 5 實 施 例 之 說 明 圖 Μ 0 S 型 1 1 固 體 攝像 裝 置 之 電 路 圖 1 1 1 本紙張尺度適用中國國家標率（CNS ) A4規格（210X 297公釐）_ 182 A7 B7 306G73 五、發明説明（180) 第3 8圖爲本發明第1 6實施例之說明圖，MO S型 固體攝像裝置之電路圖； 第3 9圖爲本發明第1 7實施例之說明圖，MOS型 固體攝像裝置之電路圖； 第4 0圖爲本發明第1 8實施例之說明圖，第1 8實 施例之MO S型固體攝像裝置之第1結構例之電路圖； 第4 1圖爲本發明第1 8實施例之說明圖，第1 8實 施例之MO S型固體攝像裝置之第2結構例之電路圇； 第4 2圖爲本發明第1 9實施例之說明圖，MO S型 固體攝像裝置之單位晶胞之結構例之電路圖； 第4 3圈爲本發明第2 0實施例之說明圖，MOS型 固體攝像裝置之單位晶胞之結構例之電路圖； 第4 4圚爲本發明第2 1實施例之說明圖，MO S型 固體攝像裝置之單位晶胞之結構例之電路圖； 第4 5爲本發明之變更例中，連接於水平信號線之視 視頻放大器之電路圖； 第4 6圖爲本發明第2 2實施例之說明圖，使用本實 施例之放大型MO S偵測器之固體攝像裝置之電路結構圖V. Description of the invention (148D 14 5-2 *. . . . . . . . . The voltage is fixed to the same voltage as the clamp power supply 1 4 1. Then, cut off the clamp transistors 132-1, 132-2, ... After applying the reset pulse wave of the high level on the reset line 7 1-, the reset transistors 6 6-1, 6 6 — 2 '. . . . . . . . . Turning on and resetting the signal charge of the photodiode 62. So, in the clamping section 145-1, 14 5-2. . . . . . . . . . A vertical signal line 8-1 ’8 -2 appears when there is a signal charge on the photodiode 6 2 and when it is reset without signal charge. . . . . . . . . . The voltage difference is added to the voltage of the clamp power supply 1 4 1 one. Then, the sample holding transistors 133-1, 133-2,. . . . . . . . . A common pulse 1 4 3 is applied to the sample holding pulse wave * so that the sample holds the transistor 133 — 1, 133-2. . . . . . . . . . Become on * This signal is sent to the sample holding capacitors 134-1, 134-2, 0, 0, and then, the horizontal address pulse wave is sequentially applied to the horizontal selection from the horizontal address circuit 1 3 Transistor 1 2 — 1, 12-2. . . . . . . . . . . The signals corresponding to one line are sequentially taken out from the horizontal signal lines 15. In the next line, the next line continues to perform this action in sequence, and all the signals of the 2nd dimension can be read out. Generally, in the amplified MOS solid-state imaging device, because the threshold voltage of the amplified transistor 64 is unevenly superimposed on the signal, even if the potential of the photodiode 62 is the same, the output signal will not become the same. When reproducing the image of the camera, the second-element noise corresponding to the uneven threshold value of the amplifying transistor 64 is generated (because its position is fixed, it is called a fixed pattern. The paper standard is used in the Chinese National Standard (CNS) A4 Specifications (210X297mm) -151---------- ^ ------ 1T ------ 0 # I (please read the notes on the back '4 fill in this page) Economy The Ministry of Central Standards Bureau undertook consumer cooperation to print A7 _____B7_ V. Description of Invention (149) Noise). However, as described above, according to this embodiment, because in the clamp section 145-1, 145-2. . . . . . . . . . After all, there will be a voltage difference between the signal charge in the unit cell and when it is reset without signal charge, so the fixed noise caused by the uneven threshold of the amplifier transistor 64 can be suppressed. That is, the circuit formed by the clamp capacitor 131, the clamp transistor 132, the sample holding transistor 1 3 3, and the sample holding capacitor 1 3 4 becomes a noise cancellation circuit. The structure of this embodiment will be described below. In the unit cell P8 — 1 — 1, P8 — 1_2. . . . . . . . . . Peripheral circuits such as the vertical address circuit 5, the horizontal address circuit 13 and the like are formed on a p-type substrate provided with a semiconductor substrate having a P + type impurity. As shown in FIG. 25 A, a cell element such as a photodiode 8 3 is formed on a semiconductor substrate provided with a p + type impurity layer 8 2 on a p-type substrate 8 1. By forming the semiconductor substrate in this way, a part of the dark current generated on the p-type substrate 81 can be prevented from flowing into the P + side due to the diffusion potential existing at the P + / P- boundary. The following is a brief description of the results of detailed analysis of the electron flow. For the electrons generated on the P-side, the thickness of the P + impurity layer 8 2 appears to be the concentration ratio of P + and P −, that is, L · p + / p-. That is, as shown in Fig. 25B, the distance from the p-based plate 81 of the dark current generation source to the photodiode 83 appears to be farther p + / p-fold. In addition to the dark current flowing from the deep part of the substrate, the dark current also occurs in the depletion layer near the photodiode 83. The paper standard produced within the exhaustion is applicable to China National Standard (CNS) A4 specification (210X297mm) _ 152 _ --------- approved clothing ------ iT ------ # (Please read the precautions V on the back to write this page)-The Central Bureau of Economic Affairs of the Ministry of Economic Affairs Beigong Consumer Cooperation Du Printed A7 __B7_ V. Invention description (150) The size of the dark current and the dark current flowing from the deep part of the substrate The size is roughly the same. The thickness of the depletion layer is about 1, and the dark current flowing from the deep part of the substrate flows from the depth of about 100. This depth is called the diffusion distance of electrons inside the P-type semiconductor. Despite this thickness, the reason why the dark current becomes equal is that the probability of occurrence of dark current per unit volume inside the depletion layer is relatively high. In principle, the dark current occurring in the depletion layer cannot be separated from the signal current, so it is necessary to reduce the dark current component flowing from the deep part of the substrate in order to reduce the dark current. And because the p + type impurity 7 is formed on the p-type substrate 7 1 The unit cell is formed on the semiconductor substrate of 2, so that the variation of the substrate potential due to dark current can be prevented. Because the thickness of the p-type substrate is large and the resistance is small, as described later, the noise removal circuit can be surely operated. This phenomenon is very important because the dark current component from the deep part of the substrate increases rapidly when the device temperature rises. The degree is that the composition from the deep part of the substrate is sufficiently smaller than the composition occurring in the depletion layer. Specifically, it is sufficient if the dark current from the deep part of the substrate is less than the dark current from the inside of the depletion layer by about one digit or less. That is, as long as p + / p- is set to 10 and the dark current from the deep part of the substrate is set to 1/10. The dark current from the deep part of the substrate hardly exists in the semiconductor substrate composed of the n-type substrate and the p-type well. However, in order to achieve the same level as the semiconductor substrate, it is necessary to set Ρ + / Ρ- to 100 and the dark current from the deep part of the substrate to about 1/1 0 0 The concentration of impurities in the η-type buried channel is about 10 lec m-3, and the stable manufacturing of this buried paper uses the Chinese National Falcon (CNS) A4 specification (210X297 mm) _ 153 _ --------- private clothes --------, order ------ 0 (please read the notes r '·' on the back first.  'Write this page) A 7 B7__ printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (151) Impurity concentration of the P-type layer (here P-type substrate) of the buried channel of the diffusion layer It is about 1 0 15cm-3. Assuming that the port + / 〇_ is 10, the degree of the ρ + layer is about 1 Oiecm_3, and when the p + / p- is 100, it is about 1 017cm-3, which becomes an impurity with the n-type buried channel. About 1 Oiecm-3 is approximately equal to or inverted by 1 digit. Therefore, it is considered that the P + layer of such impure matter can be used in the practical practice C CD. After decreasing the p-layer thickness, the sheet resistance of the substrate increases. However, there is no embedded channel of CCD in the magnification type MO S camera device, so it is possible to freely set the value of P + / P ~ within a certain degree without reducing the degree of p-layer. Therefore, reduce the P-well Resistance value, and improve the structure of the semiconductor substrate composed of n-type substrate and p-type well, can also constitute a unit cell. Fig. 26 is a cross-sectional view of a unit cell using a P + well 8 6 with a small sheet resistance value on an n-type substrate 85. Fig. 27 is a cross-sectional view of a unit cell of CD. For stable production, the impurity concentration of the n-type substrate 8 7 of the unit cell of C C D, the n-type well 86, the n-type buried channel 89 is set to about 1014cm_3, 1015cm_3, and 10lecm-3. Because the impurity concentration of the η-type photodiode 90 can be set freely within a certain degree, there is not much limitation in manufacturing. * At the above-mentioned degree of impurity, the sheet resistance value of the P-well 86 is about 100 KΩ / C ] · Even if the CCD has such a high resistance, the noise is still very small. This paper uses the Chinese National Standard (CNS) A4 specification (210X297mm) _ 154---------- ^ ------ lτ ------. ^-(Please read the notes on the back first. ¼Write this page) 1. A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy 5. Description of Invention (152) 1 | When using a noise removal circuit in an enlarged Μ 0 S camera device, the 1 1 P-type well The sheet resistance is very important. The reason is that the time when the potential of the P-well 8 6 caused by the reset pulse wave disturbs the calm must match the system using the device 1 | Please 1 I. First read 1 I In the current TV mode Ν Τ S C mode, the time for the noise removal circuit back 1 1 is about 1 1 during the period of the horizontal retrace line. Note during 1 1 [with S]. The disturbance of the potential of the P-well 8 6 must be calmed down to 0 during this period.  1 Event 1 1 C m V] Left to right. Writing book 1 Install the minimum value of 0 · 1 [m V] due to the noise voltage on the CD page 1 1 The output is approximately set to this value. In order to be calm for a very short period of 1 1 [from s] 1 1 Becomes 0 · 1 [the minimum value of m V * According to the detailed analysis of junction 1 | result, the sheet resistance value of P-well 8 6 must be set to 1 Κ Ω / □ to order I. This value is about the CCD used. It is about 1/10 0. 1 1 1 Therefore, the impurity concentration of the P-type well 8 6 must be approximately 100 0 1 1 I 〇 It has been stated in the above P-type substrate that this value C c D cannot be achieved 0. . Gas 1 1 In the high-resolution TV mode, the horizontal retrace line is line 1 3 • 7 7 [β S], so the sheet resistance of the P-well 8 6 must be 1 1 3 0 0 Ω / □ or less. 1 I Other modified examples can form a high-density P + -type sandwich layer on the substrate. 1 1 I Form a surface with a lower-concentration P-type layer. 0 1 1 I Page 2 8 The picture shows the P-type substrates S 1 and E > A structure diagram of a semiconductor substrate in which a 1 1 P + layer Sanming layer 9 2 is formed between the type layers 9 3. Figure 2 9 shows the structure of a semiconductor substrate with a p + type sandwich layer 1 1 9 6 formed between an n-type substrate 9 5 and a p-type layer 9 7 1 1 This paper scale uses the Chinese National Standard (CNS ) A4 specification (2 丨 0X297mm) _ 155-V. Description of the invention (153) Dao p + type sandwich layer can be realized by high acceleration megavolt ion implanter. On this P-type layer, in addition to the photodiode 83, transistor, etc., which form the constituent elements of the unit cell, peripheral circuits such as a horizontal address circuit and a vertical address circuit are formed. Figure 30 is the structure of a semiconductor substrate formed by surrounding the photosensitive diode 8 3 with a high-concentration ip well 1 0 3 and forming other parts on the n-type substrate 1 0 1 with other p-type wells 102 Figure. With this structure, it is possible to prevent dark current from flowing into the photosensitive dipole hip 8 3. The semiconductor substrate 101 may also be a P-type substrate. The concentration of the P-type well forming part or all of the horizontal address circuit and the vertical address circuit around the cell is determined at the time of circuit design. Since it is different from the optimal value of the cell, it can be formed as a P-type layer separate from the P-type well constituting the imaging field. No. 6 3 is a structure diagram of a semiconductor substrate in which a p-type well 106 constituting an imaging field is formed on an n-type substrate 105, and other p-type wells 107 constituting a peripheral circuit are separately formed. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs In this way, a P-well suitable for each component can be formed. The n-type substrate 105 may also be a p-type substrate. The sixth circle is the formation of a p + -type sandwich layer 1 0 8 and a low-concentration p-type layer 1 0 9 on the n-type substrate 105, and other p-type wells 1 0 are formed in the peripheral circuit 7 device. With this configuration, a P-well suitable for each component can be formed, and dark current leakage to the photodiode can be prevented. The η-type substrate 105 can also be the Chinese standard rate (CNS) Α4 specification (210X 297 mm) _ 156 _ 306073 A7 B7___ for this paper scale. 5. Description of the invention (154) P-type substrate. As described above, according to this embodiment, since the source of the amplifying transistor 6 4 is directly connected to the vertical address line 6, a bit is installed between the vertical address line 6 and the gate of the amplifying transistor 6 4 The address capacitor 69 replaces the vertical selection transistor, so that the amplifying transistor 64 of the set address can be turned on, and only its gate potential is taken out in the vertical signal line 8. That is, even if the transistor is selected vertically, the address of the vertical address line can be set, so that the unit cell can be miniaturized. Also, because the output of the unit cell is output through the noise cancellation circuit, it is possible to suppress the fixed pattern noise in which the threshold value of the amplification transistor matching the unit cell is not uniform. Since the substrate composed of the P-type impurity substrate and the P + type impurity layer formed on the P _ type impurity substrate is used as the semiconductor substrate forming the unit cell, the dark current invading the unit cell can be reduced, and The potential on the surface of the substrate can be stabilized, so that the noise removal circuit can be surely operated. The following describes an embodiment of changing the noise canceling circuit in the third and third embodiments. The third and fourth embodiments are described below with reference to FIGS. 8 and 3, and the fourth and fourth embodiments are described in the third and fourth embodiments. The third and fourth embodiments are illustrated in the third and fourth embodiments. The circuit diagram of the “MOS detector camera” device. The circuit structure near the unit cell P 8-i-j is the same as that in the third and third embodiments. Vertical signal lines 8-1, 8-2. . . . . . . . . . The other end is connected to the line I lining I-III (please read the precautions on the back side first to write this page) 1. The Central Standard Falconry Bureau of the Ministry of Economic Affairs printed this paper. The paper scale uses the Chinese National Standard Rate (CNS ) A4 specification (210X297 mm) _ 157-A7 B7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of the invention (155) 1 | The gate of… 1 1 Μ 0 S transistor 2 6 — 1 * 2 6 — 2 9…… the source of which is connected to the 1 1 Μ 0 S transistor 2 8 — 1 2 8 — 2 9…… Sink and S 1 I please 1 I Μ 0 S transistor 2 6 — 1 t 2 6 — »2…… 2 8 — 1 t first read 1 I read 1 2 8 one 2, • · ·… •« · Become source follow circuit action 0 Μ 0 S Transistor back 1 1 of 1 2 8 one 1 »2 8 one 2 * The gate of… is connected to the common gate terminal Note 1 I 1 3 6 〇 Luo 1 I Μ 0 S transistor 2 6 — 1 2 6 — 2 »… and Μ 0 S% page 1 1 transistor 2 8 — 1 2 8 a 2…… the connection point through the sample Protect 1 holding transistor 3 0 1 1 3 0 — 2…… connected to the clamping capacitor 1 1 3 2 1 1 > 3 2 — 2…… of — terminal 0 clamping capacitor 3 2 1 1 1 1 » 3 2 — 2…… the other — the end of the parallel sample holding capacitor 3 4 order 1 — 1 3 4 — 2…… and clamp transistor 4 0 — 1 4 0 1 1 | 2 »… 〇 sample holding container 3 4 — 1 3 4 one 2 9 1 I… the ground of the terminal 0 clamp capacitor 3 2 a 1 3 2 a 2 9…… one, 1 1 line… the other of the terminal, through the horizontal selection transistor 1 2 a 1 1 2 — 9 2… 1…… connected to the signal output (horizontal signal line) «1 1 The structure of this embodiment will be described below. 1 1 It can be seen from the circuit structure in Figure 8 3 that the clamping capacitor 3 2 and the sample holding capacitor 3 4 are directly connected and close to each other, so they can be stacked 1 I on the same surface »Unit cells can be miniaturized. 1 I Specifically 9 as shown in Figure 2 4 * A first electrode 7 6 is formed on the silicon substrate 7 2 via the first 1 1 1 1 insulating film 7 4 to form a sample holding capacitor 1 1 3 4 > 1 The second electrode 7 6 is formed on the electrode 7 6 through the second insulating film 7 8 to form the first 2 1 1 The paper scale is applicable to the Chinese National Falcon (CNS) A4 specification (210X 297 mm) A7 B7 5. Description of the invention (l56) The electrode 80 constitutes a clamping capacitor 32. As can be seen from the figure, the first electrode 76 becomes a common electrode, and the clamp capacitor 32 and the sample holding capacitor 34 are formed by lamination. Therefore, the same capacitance can be formed with half the area when formed separately. The operation of the MOS solid-state imaging device thus constructed will be described below with reference to the timing chart of FIG. 84. Because the common sink terminal 20 of the load transistor 9, the common gate terminal 36 of the transistor 28 of the impedance conversion circuit, and the common source terminal 38 of the clamp transistor 40 are driven by DC, Not shown in the timing diagram. During the horizontal extinction period, after applying the address pulse wave of the high level on the vertical address line 6-1, the unit cell P8-1-connected to the vertical address line 6-1 1, P8 — 1 — 2. . . . . . . . . . The amplifier transistor 64 is turned on by the amplifier transistor 64 and the load transistor 9 1 1, 9 2,. . . . . . . . . Form the source follower circuit. Keep the sample holding transistors 3 0 — 1, 3 0 — 2. . . . . . . . . . The potential of the common gate 3 7 becomes a high level to keep the sample 3 0 — 1 * 30-2. . . . . . . . . . Turn on. Then, make the clamp transistor 40 — 1 * 40-2 *. . . . . . . . . The potential of the common gate 42 becomes a high level to clamp the transistors 40-1, 40-2 ’. . . . . . . . . Turn on. Then, make the clamping transistors 40-1, 40-2. . . . . . . . . . The potential of the common gate 4 2 becomes a low level to make the clamp transistor 4 0 — 1 ′ • 40-2 *. . . . . . . . . Open circuit. Therefore, it appears on the vertical signal lines 8-1, 8-2. . . . . . . . . . The signal plus noise components are stored in the clamping capacitors 3 2-1, 32-2. . . . . . . . . . Medium · This paper scale uses the Chinese National Standard (〇 吣 > 8 4 specifications (2 丨 0 297 mm) -159- II 111 I installed ^ I 11 order-II line (please read the note 1 on the back first , Write this page) for the A7 B7, the Central Standards Bureau of the Ministry of Economic Affairs, Beigong Consumer Cooperative, printed stupid five, invention description (157) 1 | Then apply a high level reset pulse on the reset line 7-1> then 1 1 The unit cell P 8-1-1 P 8-1 1 1 1 2 *… connected to the reset line 7-1 reset transistor 6 6 turns on the output circuit 6 8 1 signal line 1 input terminal The charge is reset to 0 so »In the vertical 8 1 1 t 8 read first 1 1 noise read 1 1 2»…… • Only signal components appear on the «reset component 0 back 1 1 as above * Because the clamping capacitor 3 2 1 > 3 2 — 2 »ί 1 |…… stores the signal plus noise components * Only the vertical signal line 8 — 1 9 8 — 2 9% appears in the clamping section 4 1 — 1 event 1 1 1 4 1 — 2…… the voltage change of the device 1 is added from the signal component The noise component is subtracted from the noise component '— ^ 1 1 The signal voltage of the signal component is fixed and the signal voltage 〇1 1 Then »keep the sample transistor 3 0 1 1 9 3 0 — 2» «· ·… 1 | The potential of the common gate 3 7 becomes a low level and the sample is cut off to hold the transistor 3 0 — 1 3 0 1 2…… therefore 9 appears in the clamping section 1 1 | 4 1 — 1 4 The voltage of the Atr m noise of 1 1 2… is stored in the sample 1 1 1 product holding capacitor 3 4 — 1 3 4 1 2… in the middle 〇 1 1 line 1 and then the transistor 1 2 1 1 is selected horizontally 9 1 2 — 2 9 ... apply horizontal address pulses to the output terminal (horizontal signal line) 1 1 1 5 read out and store in the sample Container 3 4 — 1 9 3 4 — 2 f… 1 I… Among JrrT.  Pussy noise photodiode 6 2 signal 〇1 1 and later * The same for the vertical address line 6 — 2 9 6 — 3 >…… 1 1 I Repeat the above actions 9 to take out and configure it as a secondary element All the unit cells of the shape, the signal of 1 1 〇1 1 The timing of Figure 8 4 is described below, i t.  After the relationship 〇The required order 1 1 There are the following two kinds 〇1 1 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) _ ι6〇_ B7____ V. Description of the invention (158) · (1 ) Sample hold pulse rise Clamp pulse drop-1st vertical address pulse drop-reset pulse wave drop-2nd vertical address pulse wave rise-sample hold pulse wave rise- 2nd vertical address pulse drop (2) Clamp pulse drop—Reset pulse rise—Reset pulse drop 1st vertical address pulse rise, the sample keeps the pulse rise The relationship between the rise and fall of the clamp pulse can be arbitrary, but it is best to follow the above relationship. The relationship between the fall of the first vertical address pulse and the rise and fall of the reset pulse can also be arbitrary, but it is best to follow the above relationship β as described above, according to the operation of Figure 8 4 in the clamp section 4 When there is a signal (plus noise) on 1, the voltage difference between the amplifier and the reset transistor without the signal, so it can compensate the fixed pattern noise caused by the uneven threshold of the amplifier transistor 64 That is, the circuit formed by the clamp transistor 3 0 * clamp capacitor 3 1, the sample holding transistor 40, and the sample holding capacitor 3 4 becomes a noise cancellation circuit. Printed by Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs. The noise cancellation circuit of this embodiment is connected to the vertical signal line 8 via an impedance conversion circuit 26, 28 formed by a source follower circuit. That is, the vertical signal line is connected to the gate of the transistor 26. Because the capacitance of the gate capacitor is very small, the amplifying transistor 64 of the unit cell charges only the vertical signal lines 8-1, 8-2. . . . . . . . . . . Therefore, the time constant of CR is small, and it can immediately become a normal state. Therefore, the application timing of the reset pulse wave can be accelerated, and the noise elimination operation can be performed in a short time. If it is a TV signal, the noise elimination operation must be performed within the horizontal extinction period, so the correct cost can be corrected in a short time The paper scale is applicable to the Chinese National Falcon (CNS) A4 format (210Χ297mm 161-306G73 A7 _____B7_ V. Description of the invention (159) It is unique to eliminate noise. When the noise is output, the impedance of the noise cancellation circuit observed from the unit cell is the same as the noise output, so the noise can be correctly eliminated. That is, when the% noise component ^ is output, it is the same as the `` signal component '' When adding the noise component ^ output, the impedance of the noise cancellation circuit observed from the unit cell is approximately the same. Therefore, the noise component becomes approximately the same in the two outputs, and the difference between the two can be calculated The noise component can be output correctly and only the signal component can be taken out. Therefore, the noise can be correctly eliminated. When observing the noise cancellation circuit from the unit cell, only the gate «container can be observed from the viewpoint of impedance And its capacitance is very small, it can indeed eliminate noise in a short time as described above, according to the present embodiment, the noise cancellation circuit, a clamp capacitor 3 2 - 1, 32--2. . . . . . . . . . The sample holding capacitors 34 are directly connected and close to each other, so they can be stacked on the same surface to reduce the size of the capacitor. When observing the noise elimination circuit from the unit cell, only the gate capacitor can be observed from the impedance point of view, and its capacitance is extremely small, so it can be surely eliminated in a short time. Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the notes on the back first). % Write this page) 3rd 5th embodiment Fig. 8 5 is a circuit configuration diagram of an imaging device using the amplified MOS detector implemented in the 35th embodiment. The circuit structure near the unit cell P 8-i-j is the same as in the third to third embodiments. Will separate transistors 202-1, 202-2. . . . . . . . . . In series with the vertical signal line 8-1, 8-2 ’. . . . . . . . . And use the Chinese National Standard (CNS) A4 standard (210X297mm) for the separation of the transistors on the paper. 2 0 2 — 1 »2 0 2 — 2» ... and the level selection transistor 1 2 1 1 1 1, 1 2 — 2 9 ... Amplifier capacitors are set between 2 0 6 1 1 1 »2 0 6 — 2… …… that is, 9 in this embodiment, the level selection circuit 1 I, please 1 I, without setting up the noise canceling circuit before the crystal, and setting up the amplification to adjust the amplification factor. 1 I capacitor 〇it back 1 δ I 1 Note I Italian ancient I 36th Example ¥ ^.  1 1 8 8 ΓΒ1 圚 is the circuit structure diagram of the imaging device equipped with the magnified Μ 0 S detector base of the 3rd 6th embodiment 0 unit cell P 8 — i — j nearby page — ^ 1 1 The fan circuit structure is the same as the third 3rd embodiment 0 1 1 The third 6th embodiment is connected to the noise canceling circuit of the third 3rd embodiment 1 | Connected to the third embodiment of the impedance conversion circuit of the fourth embodiment 0 In this embodiment, the common source of the clamp transistor 1 3 2 is driven by DC. 1 1 1 1 3 7 Embodiment 1 1 1 The following describes the third 7 of the present invention with reference to the 8 7 8 8 figure. Example line 10 0 8 8 The picture shows the circuit structure of a 1 1 imaging device using the amplified Μ 0 S detector of the 3 7th embodiment. The unit cell P 8 — i — j near the circuit 1 1 The structure is the same as the third 3rd embodiment. 0 1 1 I Load transistors 9-1 9 9-2 9...... The side of the vertical 1 1 I signal line 8 — 1 »8 — 2 ... is connected to the limiter, 1 1 crystal 1 5 0 one 1 • 1 5 0 one 2 ♦…… the gate of the gate. Limiting transistor 1 1 body 15 0 — 1 1 1 5 0 — 2 »…… The source of the source is connected to the limiter 1 1 container 1 5 2 1 1 > 1 5 2 — 2…… at the end 〇Limiting capacitance 1 1 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) — 1, 1 5 2-2. . . . . . . . . . The other end is connected to the limiting pulse wave supply terminal 154. In order to reset the limiting transistor 150_1, 15 0-2. . . . . . . . . . The source potential of the limiting transistor is set between the source of the limiting transistor and the limiting power terminal 1 5 8 1 5 6 — 1 * 15 6 — 2 *. . . . . . . . . And transistors 156-1, 156-2. . . . . . . . . . The gate is connected to the limiting reset terminal 160. Limiting transistor 1 50 — 1, 1 50 — 2. . . . . . . . . . The sink is connected to the limiting charge transfer capacitor 162-1,162-2, ... . . . . . . In order to reset the sucker potential of limiter transistors 150-1, 150-2, ..., a sink reset transistor 166-1, 166 is provided between its sink and storage sink power terminal 1 6 4 - 2. . . . . . . . . .  . Transistor 166 — 1, 166-2. . . . . . . . . . The gate is connected to the sink reset terminal 168. Limiting transistor 150 — 1, 150 — 2. . . . . . . . . . The sink electrode is connected to the signal output terminal 15 via the horizontal selection transistors 1 2-1, 1 2-2, ... driven by the horizontal address pulse supplied from the horizontal address circuit 13. As described above, the MO S detector of the 37th embodiment is compared with the 33rd embodiment shown in the circle 81. The unit cell P 8-i-j has the same structure, but the noise cancellation circuit The composition is different. The noise cancellation circuit of the 37th embodiment is characterized by appearing on the vertical signal lines 8_1, 8-2. . . . . . . . . . The voltage is converted into electric charge through the gate capacitor of the limiting transistor 150. Subtraction is performed in the electric charge field to suppress noise. The driving method of this embodiment will be described below. The 8th is a timing chart of the operation of this embodiment. Figure 4 8 shows the limiter transistor 1 5 0 — 1, the size of the paper uses the Chinese National Falcon (CNS> A4 said grid (210X297 mm) _ 164---------- ----- IT ------ A (please read the note 1 on the back first and write this page at 4 ') A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention Instructions (162) 1 1 1 5 0- 2…. . . . . . Potential diagram 〇1 1 First, apply a high level droop on the first vertical address line 6-1 1 After the straight address pulse 1 Only the vertical selection transistor of the unit cell of the row 1 | 6 6 Continuity * Amplifier transistor 6 4 and load transistor 9 1 in this line are read first 1 I »9 — 2…… constitute the source follower circuit 0 Read back Λ 1 1 1 and then reset the limit reset terminal 1 6 0 applies the limiting reset pulse »meaning 1 1 makes the limiting reset transistor 1 5 6 -1, 15 6 — 2 9…… conduction matters 1 1 > the limiting capacitor 15 2 — 1 , 15 2 — 2 9... The charge% 1 is initialized. Page '— * 1 1 and then reset the limiting reset transistor 15 6 open circuit 9 At this time on the vertical 1 1 signal line 8 1 1 9 8-2 • 4 · · _ ·… corresponding to the set address 1 The signal of the photodiode in the first row of I «charge signal voltage setting I I apply the first limiting pulse wave 1 1 ISP 1 on the limiting pulse wave supply terminal 15 4» so when there is a signal (that is, a signal When the component + noise becomes 1 1 minute's output), the channel potential 1 1 V ech under the gate of the limiting transistor 15 0 transmits the first limiting charge to the sink. At this time, the reset pulse of the sink is applied to the 1 16 8 of the limiting reset terminal line. The sink reset transistor 1 6 6 conducts 1 I, so the potential of the sink is fixed to the storage sink power terminal 16 4 Voltage 1 IV Sdd. Therefore, the first limiting charge is discharged through the sink reset transistor 1 e 6 1 1 I to the storage sink power supply terminal 1 6 4. 1 1 I Then »After applying the reset pulse on the reset line 7-1» The vertical signal line 8-1 9 8 — 2 >…… 1 1 Only the noise components with no signal are output. Apply the second limiting pulse wave SP 2 to the limiting pulse wave supply terminal 1 5 4 1 1 · In this way, the m signal charge is applied beyond 1 1 This paper standard uses the Chinese National Standard (CNS) A4 specification (210X297 mm) -165- A7 B7 printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economy V. Invention description (l63) Voltage limiter Transistor channel potential VQCh under the gate of 1 50 0, transfers the second limit charge To the sucker. At this time, since the reset transistor 1 6 6 of the sink is disconnected, the second limit charge is transferred to the limit charge transfer capacitor 1 6 2 connected to the sink. Then, the horizontal selection pulse wave is sequentially applied to the horizontal selection transistors 1 2 — 1, 1 2-, 2 from the horizontal address circuit 13. . . . . . . . . , From the horizontal signal line 15 in order to take out the signal equivalent to one line • In the next line, the next successive line to perform this action in sequence, you can read all the signals of the second dimension. In this device, assuming that the capacitance of the limiting capacitor 15 2 is CS1, the last charge (second limiting charge) read on the horizontal signal line 15 will appear as C SlX (V " sch_ V osc) and When there is a signal, the charge is proportional to the difference when it is reset without a signal, so the fixed pattern noise generated by the threshold deviation of the amplified transistor 64 in the unit cell can be suppressed. In this way, the circuit structure that converts the voltage appearing in the vertical signal line 8 into electric charge and performs subtraction in the electric charge field can also be called a noise canceling circuit. The method of this type of noise cancellation circuit is different from the third embodiment in FIG. 81. The clamp section 1 4 5 in the third embodiment has no noise in its voltage collar, but eliminates noise in the electrical field. This type of limiting transistor has no noise elimination in the source terminal of 150. This paper standard applies to China National Standard (CNS) A4 (210X297mm > _ 166 _ ---- ----- ^ ------ 1T ------ ^ (Please note the first thing on the back 1) Please write this page) 1 A7 B7 Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs • Description of the invention (164) 1 1 t but when the 3rd 4th limiting pulse SP 2 is applied, the 9 side will transfer the noise-removing electricity 1 1 to the sink. That is, the noise will be eliminated in the charge field 9 1 I As mentioned above »According to the third 7th embodiment t Because the output of the unit cell is output through the noise elimination circuit 1 I, the amplified power of the unit cell can be removed. Please read 1 I The threshold of the crystal is uneven and fixed ΓΒΊ Pattern noise 〇Read the back 1 1 | Also because the output of the unit cell is passed through the gate capacitance of the limiting transistor 1 1 1 The device is supplied to the noise cancellation circuit «Therefore, when the noise is output, it is the same as the letter Dffe m plus the noise input 1 1 when it is out 9 The impedance of the noise cancellation circuit observed from the unit cell becomes roughly%. Write 1 and install the same 1 so when the two outputs are 9 The noise components are roughly the same »Page 1 1 Calculate the difference between the two to get rid of the noise correctly. You can only take out the signal into 1 I points to get rid of the noise correctly 0 From the unit cell * 11 1 Observe the noise In the case of the signal cancellation circuit, 1 I 9 can only observe the gate capacitor from the viewpoint of impedance and its capacitance is set to be very small, so it can reliably eliminate noise in a short period of time. 1 1 1 2nd limiting pulse SP 2 May be affected by the first limiter 1 1 pulse SP 1 of the square side. Therefore, in order to make the effect of the first 2nd limit pulse on the action of the 1 1 1st 2nd transistor become the same at the 1st limit Amplitude 1 wave SP 1 is positive. > 1.  It is most effective to set the analog pulse wave. If the amplitude of the 1st limiting pulse 1 I wave is the same as the amplitude of the 2nd limiting pulse wave t Under subtle voltage conditions 1 I may not be able to read the signal charge in the field of small signals Or the straight line degrades y, so 1 1 I sets the amplitude of the second limiting pulse to be greater than the amplitude of the first limiting pulse 9 9 1 1 I adds a bias charge to the charge read by the second limiting pulse > The action is relatively stable, 1 1 is stable. Setting the width of the second limiting pulse wave to be greater than 1 1 of the first limiting pulse wave is also an effective method. 0 1 1 1 1 This paper size is suitable for Chinese national standards. (CNS) A4 specification (210X297 mm) -167- A7 B7 Printed five invention descriptions by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (165) I 1 3rd 8th Example 1 1 The following refers to the 8th 9th description of the 3rd 8th Example 0 No. 8 9 1 〇. 1 The picture shows the circuit of the imaging device using the amplified MOS detector of the third 8th embodiment for I 1 1 I please 1 I junction JMt scale diagram. Circuit structure Cbs3 near unit cell P 8-1-j It is the same as the first 3 3 first reading 1 1 information embodiment. Read the back 1 first 1 3 8 The embodiment is from the third 3 4 embodiment shown in FIG. 8 3 Note 1 I is slightly followed by the source follower transistor Example of the structure of the impedance conversion circuit 1 thing 1 1 1% of this S * 1 installed I No. 3 9 Example η 1 1 The following refers to No. 9 0 »9 1 and 9 2 description 3 9 Example 0 1 1 9 0 9 1 circle is the circuit structure of the imaging device using the amplified MOS detection 1 1 of the 39th embodiment. The circuit structure of the unit cell near the unit cell P 8 i-j and the implementation of the third 3 Same example 1 1 I There are many The multi-part is the same as the 3rd 3rd implementation 1 1 I example shown in Fig. 8 1 The difference is that it will be used to correct the% letter wt component + noise into -ν · 1 1 line 1 point Capacitor C CM P 1 6 0--] 1 1 > 1 6 0 — 2…… in comparison clamp when outputting% noise component / r when the impedance value of the noise cancellation circuit observed from the unit cell is different Bit capacitor 1 3 1 — 1 1 I 1 3 1 — 2 ♦……… closer to the camera field (unit cell side) via 1 I by switch 1 6 2 — 1 »1 6 2 — 2 • ·… • · parallel In the vertical signal 1 1 I line 8 — 1 »8 — 2 *…… in Figure 9 0 • Correction capacitor, 1 1 1 1 6 0 and switch 1 6 2 are connected to the clamping capacitor 1 3 1 and Between the camera collar 1 1 and the field in Figure 9 1, it is connected between the camera field and the load transistor 1 1 9 〇1 1 This paper scale is applicable to the Chinese National Standard (CNS) A 4 Specifications (210X297 mm) _ 168 _ Printed by Beigong Consumer Cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs A7 ___B7 V. Description of the invention (166) The 9th 2nd figure is the sequence of actions of this embodiment. The switch 1 6 2 ends at the clamping of the clamping transistor 1 3 2 and becomes conductive during the period when only the noise after resetting the photosensitive diode is output on the vertical signal line. Therefore, it is assumed that the sample holding capacitor 1 3 4 When the capacitance is CSH and the capacitance of the clamp capacitor 1 3 1 is C & the capacitance connected to the vertical signal line 8 when the sample is held becomes C = CCMp + CsH · Ccl / (CcL + CsH) When the capacitance of the capacitor is set to C CMP within 2 {C c U _ C c L * C sh / (C CL + C SH)}> C CMP> 0, compared with the case without correction capacitor, it is connected when the sample is held. The capacitance of the vertical signal line is close to the capacitance Ccl of the clamp capacitor 131. Therefore, the difference Vet becomes smaller, so the noise becomes smaller. Fig. 55 shows the time variation of the potential of the vertical signal line 8 and the potential of the clamp node 1 4 5. In this embodiment, for example, when the signal is dark, when the potential of the vertical signal line 8 is restored to the clamped potential and the restored sample is held at the same potential, the clamped node at the end of the holding of the sample is not Will revert to a close value, but becomes 0. Therefore, there is no problem that a signal equivalent to u occurs even when it is dark and the signal is 0 '. Therefore, it can prevent the noise caused by the unevenness. This paper standard is applicable to the Chinese National Standard (CNS) A4 standard (210Χ 297 mm) _ 169-Pack I II-IIII line (please read the back The matters needing attention are wide 4. Write this page) A7 B7 is printed by the Beigong Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs. 5. Description of the invention (l67) As mentioned above, the MO S type with noise removal circuit according to this embodiment Since the hip camera element is provided with a correction capacitor 160 on the vertical signal line 8, it is possible to suppress the capacitance change in the noise removal operation that causes noise, and to further reduce noise. That is, when the signal after the photodiode is selected plus the noise output, the impedance observed from the cell becomes the same as the noise output after the reset is completed, and the noise can be correctly eliminated. The change of the 39th embodiment For example, the third and fourth embodiments shown in Figures 8 and 3, the third and fifth embodiments shown in Figures 8 and 5, the third and sixth embodiments shown in Figures 8 and 6, and the examples shown in Figures 8 and 7 The third to seventh embodiments, and the third to eighth embodiments shown in Figures 8 to 9 are connected to a correction capacitor. The 3rd to 3rd 9th embodiments illustrate different embodiments of the noise canceling circuit from the 3rd to 3rd embodiment. The following describes other examples of the structure of the unit cell that are different from the 3rd to 39th embodiments. The 40th embodiment. The 40th embodiment will be described below with reference to the 9th and 3rd figures. Example of the overall circuit diagram of the solid-state imaging device of the amplified MOS detector. The unit cell P 9-i _ j of this embodiment is a unit cell in which the address capacitor 6 9 is omitted from the unit cell of the third and third embodiments. In this embodiment, when the vertical address circuit 5 sets an amplification transistor After the 6 4 sucking pole, in order to change and enlarge the electric paper size of the channel under the gate of the 6 4 transistor, the Chinese National Standard (CNS) A4 specification (210X297 mm) is used _ 170-ί IIIII 装 I 設定- — Line II (please read the precautions on the back to write this page) 1. A7 ____B7___ printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. The invention description (I68) bit uses the short-circuit channel effect. That is, when the sink potential of the amplifying transistor 64 increases, the depletion layer extends from the sink to the channel under the gate, and the threshold voltage changes to the negative direction. The reason that only the output signal of the photodiode 6 2 of the unit cell of the line of the set address appears on the vertical signal line 8 is the same as that of the third embodiment. As described above, according to this embodiment, not only when there is no vertical selection transistor, but also when there is no address container, the vertical address line can be set, so the number of elements is set less than in the third and third embodiments, and the crystal can be realized. The miniaturization of cells. The 40th embodiment is also the same as the 33rd embodiment with a changeable noise canceling circuit. That is, the descriptions of the 8th to 9th circles, and the 5th and 5th figures can also be applied to the 40th embodiment. Embodiment 41 The following describes Embodiment 41 with reference to Figure 94. Fig. 94 is the entire circuit diagram of the solid-state imaging device using the amplified MOS detector of the 41st embodiment. The unit cell P 1 0-i-j of this embodiment sets the vertical selection transistor outside the unit cell, and only one unit cell is set on one vertical address line • That is, the unit cell P 1 0 -i-j includes photodiode 62-i-j, photodiode 62-i-j detection signal amplification amplifier transistor 6 4-i-j, reset photodiode 6 2-i_j Reset of signal charge transistor 66-i-j. Vertical address line 6 -1 * 6-2 wired from vertical address circuit 5 to the horizontal direction. . . . . . . . . . Connected to the vertical selection transistor 3 0 2-1 • 302-2 *. . . . . . . . . Gate, vertical selection transistor 302-This paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) -171-111 I installed II-ordered-I 11 I line (please read the notes on the back first Licek write this page) ί 306G73 A7 B7 V. Description of the invention (169) 1 * 3 0 2 -2 The source is connected to the source of the amplified transistor 6 4 of each unit cell, and the reset transistor 6 6 Source. Vertical selection • Transistor 3 0 2 — 1 is connected to the sink terminal 3 0 According to this embodiment, the vertical address line from the vertical address circuit to the common sink power source 3 address is the vertical position of the positioning address For addressing, only the inspection sequence connected to the photodiode 6 2 and the circuit shown in the 4th embodiment shown in circle 8 2 are excluded. That is, the 8th kind is applied to the 41st 3 0 2 -1 4th. , Because 5 is set to 0, 4 is set on the electrical upper line, and the 3rd 3rd signal is also vertically selected with the 1st to 9th embodiments. The vertical level of the electrical crystal address is selected (the high level becomes floating. Due to the unit cell release The vertical address of the address appears in the action of the vertical letter embodiment 3 3 embodiment phase 2 figure, and the 5th common common junction 3 0 straight address), but this, even the single line of the large crystal line 8 The same timing can be turned on in Fig. 2 to make the ® position of the line feel as if the unset position is connected to the unset body 6 4 the fixed position cell. The action is the same. The instructions for changing the noise elimination can also be read in the same way as the following. 4. I Binding and Binding Line Printed by the Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperative Co., Ltd. Printed No. 4 2 Example 9 9 Picture 5 is used to explain the implementation The example diagram is the entire circuit diagram of the solid-state imaging device using the magnifying MOS detector. The unit cell PI l-i-j of this embodiment is a unit cell in which the reset transistor 6 6 and the reset line 7 are omitted from the basic unit cell of the 33rd embodiment shown in FIG. 81. That is, the unit cell P 1 1 — i — j includes the photodiode 6 2 — i — j and the amplified transistor 64_i — j that amplifies the detection signal of the photodiode 62 — ij (CNS) A4 specification (210X297mm) -172-A7 B7 printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (no) Vertical address line 6 wired from the vertical address circuit 5 to the horizontal direction — 1, 6, 2 . . . . . . . . . It is connected to the sink of the amplifying transistor 6 4 and is connected to the gate of the amplifying transistor 6 4 via an address capacitor 69. Figure 9 6 shows the operation timing chart of this embodiment. This figure is applied to the vertical address line 6 _ 1, 6-2. . . . . . . . . . In the middle of the address pulse wave, the negative signal charge is inserted to discharge the pulse wave P d, and the others are the same as the timing chart of the third and third embodiments shown in FIG. The following describes the relationship between the timing of Figure 96. The necessary sequence is as follows: The first rise of the pulse wave of the vertical address—the fall of the clamp pulse wave—the rise of the signal charge discharge pulse wave—the fall of the signal charge discharge pulse wave—the sample holding pulse wave fall—the vertical position The 2nd fall of the address pulse wave The 1st rise of the vertical address pulse wave, the sample keeps the rise of the pulse wave, and the relationship between the before and after the rise of the clamp pulse wave can be arbitrary. However, it is preferable to show the sectional structure of the basic unit cell of this embodiment and the state of discharge of signal charges in accordance with the above sequence β FIG. 97. The basic operation is the same as the third to third embodiments. Since the address capacitor 69 is provided, the address of the vertical address line can be set even if there is no vertical selection transistor. After the signal readout ends, the vertical address lines 6-1, 6-2. . . . . . . . . . A negative signal charge is applied to discharge the pulse wave P d, and the potential of the photodiode 62 is biased to the negative direction through the coupling capacitor to discharge the internal signal charge on the P-type substrate. In this way, the signal charge can be reset. The operation of the noise removal circuit is exactly the same as in the third to third embodiments. As described above, according to the present embodiment, the photodiode 6 2 'can be used to place the paper. The size of the paper is applicable to the national standard (CNS) A4 specification (210X297 mm) -173-IIIII Pack II-binding line (please read the back side first Notes' j. . (Write this page) 1. A7 B7 Description of the Invention of the Fifth Invention of the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (171) 1 I Large Transistor 6 4 and Address Capacitor 6 9 Form a basic unit cell, so 1 1 unit cell can be large Refinement of amplitude 〇1 1 The 4th 2nd embodiment is also the same as the 3rd 3rd embodiment. The noise cancellation can be changed. 1 I please 1 1 divide the circuit 0, which is > 8th 9 9 2 Figure 1 and Figure 5 5 The description can also be read first 1 I read 1 The same applies to the 4th 2nd Example 0 Back 1 of 1 Note | It is important to focus on the 4th 3rd Example Ψ Item jr — 1 9th 9 8 The picture is used to explain the 4th 3 implementation The case of the example is to use the copybook 1 The full circuit diagram of the solid-state imaging device equipped with a large Μ 0 S detector 0 This implementation page ^ 1 1 The unit cell of the example P 1 2 — i a j It is in the unit cell structure of the third 3 1 1 embodiment shown in FIG. 8 1 »Between the photodiode 6 2 and the gate of the amplifying transistor 1 | 6 4 a transmission transistor 3 0 6 is added Example: The common gate 3 0 8 of the power transmission crystal I 3 0 6 is connected to the vertical address circuit 5 〇1 1 1 1 4th 4th embodiment 1 1 1 9th 9 9 The figure is for explaining the 4th embodiment Figure 〇 That is to say, the full circuit of the solid-state imaging device using the pay-off 1 large-scale M 0 S detector 9 The unit cell P 1 3 — i — j of this example of implementation 11 is the fourth shown in FIG. 9 3 0 1 I In the unit cell structure of the embodiment, a power-transmitting crystal 3 is added between the photosensitive diode 6 2 and the gate of the amplifying transistor 1 1 1 6 4 3 0 6 Example «1 1 1 4th Example 1 1 1 The first 1 0 0 is a diagram for explaining the 4th 5th embodiment. That is, the 1 1 magnified Μ 0 S detection is used. The full circuit of the solid-state camera device 9 The real 1 1 The paper scale is applicable to the Chinese national standard (匸 阳) 84 specifications (2 丨 0 297 mm) -174- A7 B7 Beigong consumption of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the cooperative V. Description of the invention (172) 1 I The unit cell P 1 4-1-j of the embodiment is in the unit cell structure of the 1 1 4 1 embodiment shown in FIG. Transistor 6 2 and the gate of the amplifier transistor 1 1 body 6 4 are additionally transmitted with a transistor 3 0 6 cell 〇1 | please 1 1 read first 1 1 4 4 Example back 1 | first 1 0 1 The picture shows the overall circuit diagram of the solid-state SJ5L camera device using the amplified Μ0S detection 1 1 1 1 of the 4th 6th embodiment. The unit cell matters of this embodiment are one more: 1 1 P 1 5 — i — j It is in the unit cell structure of the 4th and 2nd embodiment shown in Figure 9 5. Attached to the gate of the amplifying transistor 6 4 • — ^ 1 1 plus the unit cell of the transmitting transistor 3 0 6 0 1 1 The first 1 0 2 The operation timing chart of the present embodiment. During the horizontal extinction period 1 | After applying the address pulse of the high level on the vertical address line 6-1 * Order I The address pulse of the high level is supplied to the unit connected to the 1 1 I line through the address capacitor 6 9 The gate of the amplifying transistor 6 4 of the unit cell The potential of the channel 1 1 I under the gate becomes higher than the channel potential under the gate of the amplifying transistor 1 1 6 4 of the unit cell connected to other lines Turn on. Therefore, the source follower circuit Q is formed by the amplifying transistor 6 4 of the unit cell connected to the vertical line 1 straight address line 6-1 and the load transistor 1 1 body 9 and then appears on the vertical signal line 8 1 1 The gate voltage of the large transistor 6 4 and the photosensitive diode The voltage of 6 4 1 1 is approximately equal to the voltage 〇1 I so »On the vertical signal line 8 a 1 8 — 2…… only the gate of the amplifier transistor 6 4 of the line whose address is now set is 1 1 I The polar potential does not appear 1 1 Amplification transistors of other lines 6 4 The gate potential of 0 4 So even if 1 1 is omitted Vertical selection transistor »The address of the vertical address line can still be set 〇1 1 This paper size is not used in China National Standard (CNS) A4 specification (210X29 * 7mm) _ 175-A 7 B7 Printed by the Central Standard Falcon Bureau Employee Consumer Cooperative of the Ministry of Economy V. Invention description (173) Then, on the vertical address line 6-1 A negative charge with a large amplitude is applied to discharge the pulse wave CD and reset the charge of the photodiode 62. Then, hold the transistor 13 3-1, 133-2 in the sample. . . . . . . . . After applying a high level sample to the common gate 1 4 3 to maintain the pulse wave, clamp the transistor 132-1 * 132-2 '. . . . . . . . . A clamping pulse wave is applied to the common gate 142 to clamp the transistors 132-1, 132-2, ... . . . . . Become a continuity, will debate the position 1 4 5 — 1, 1 4 5-2. . . . . . .  The voltage of ... is fixed to the same voltage as the clamping voltage 141. Then, make the clamping transistor 132-1, 132-2. . . . . . .  … After the circuit breaks, a high level transmission pulse is applied to the charge transfer line 3 0 8-1 to make the charge transfer transistors 306-1, 306-2. . . . . . .  … On. So, in the clamp section 1 4 5-1, 1 4 5-2. . . . . .  … The vertical signal lines 8-1, 8-2 will appear when there is signal charge in the photodiode 6 2 and when it is reset without signal charge. . . . . . . . . The difference in voltage is added to the voltage of the clamping power supply 1 4 1 • Then, the application of the sample holding pulse wave is completed * Then, the horizontal address pulse wave is sequentially applied to the horizontal selection transistor 1 2 from the horizontal address circuit 1 3 -1, 1 2 — 2. . . . . . . . . . . The signals corresponding to one line are sequentially taken from the horizontal signal lines 15. The following describes the relationship between the timing of Figure 9 6 and the relationship β. The necessary sequence is as follows. · The first rise of the vertical address pulse wave-the first fall of the vertical address pulse wave-the second time of the vertical address pulse wave Ascent—Clamping pulse wave fall—Charge transfer pulse wave rise—Charge transfer pulse wave fall—Sample hold pulse (please read Note 4 on the back of the page first: ¾ this page), νβ Γ This paper size applies to China Rate (CNS) Α4 specification (210X297 mm) _ 176-A7 B7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, Fifth, • Description of the invention (174) — > 2nd time of vertical address pulse Decrease the 2nd rise of the pulse wave of the vertical address t The sample keeps the rise of the pulse wave t The rise of the clamp pulse wave and the relationship between the before and after the fall of the clamp pulse wave can be any 9 but it is best to follow the above sequence 0 According to the 4 3 4 6 The structure of the embodiment ♦ Because the photodiode 6 2 and the amplifying transistor 6 4 are separated 9 Reducing the capacitance of the detected charge and increasing the sensitivity 0 can also cause the transmission transistor 3 0 6 to be disconnected. First output the voltage equivalent to 4rrt: the noise component when tearing the signal charge to the vertical signal 8 * Then make the transmission transistor 3 0 6 Open circuit and output the voltage equivalent to the signal component plus noise component when there is a wt charge «The result of the first reset can also remove the random noise caused by the reset action. The 4th 4 4 6 embodiment also Xing No. 3 3 The same changeable noise cancellation circuit 0, that is, the descriptions of Figs. 8 1 9 2 and 5 5 can also be applied to the same ntg in the 4 3 4 6 embodiment. The present invention is not subject to the above The limitation of the embodiment can be changed within the scope that does not exceed its gist. For example, if a Jtvr tearing unit unit cell with an uneven tearing threshold can be manufactured, a fixed pattern is not generated. Therefore, the noise cancellation circuit can be omitted. Or even if a fixed pattern noise is generated »as long as the image quality is not affected y, the noise cancellation circuit can be similarly omitted. In the noise cancellation circuit of each embodiment, jhrr tears off the input signal The signal current (only the noise component) read out is smaller t and the noise is less »It is best to make the voltage applied to the storage sink power terminal and the video bias voltage become approximately equal. The so-called video bias voltage is from the horizontal When the signal is read out in the signal line 1 5 by the current method, the horizontal signal line 1 5 is the fixed voltage. The 9th figure shows that please read the back item and then this page. The paper standard is applicable to the national standard of the t country (Ministry of Economic Affairs Central Standards Bureau staff consumption Cooperative cooperative printing A 7 B7 V. Description of invention (175) This modification example. The output signal line 15 is connected to the operational amplifier 1 7 6 'the input and output terminals of the operational amplifier 1 7 6 are connected to the load resistance 1 7 8 »In this way, the signal current flows into the load resistance 1 7 8 forcibly, and the horizontal signal line 15 is It is fixed to the imaginary voltage, which is the video bias. In the above embodiments, the unit cell system is arranged in the form of a two-dimensional matrix. However, the present invention can also be applied to an imaging device in which the unit cells are arranged in a form of a one-dimensional array. That is, in addition to the structure of the area detector that can be formed as a quadratic matrix array in which unit cells are arranged in mx η, it can also be formed as a line detector in which the unit cells are arranged in a row. The 47th embodiment wishes to randomly access the light-receiving portion arranged in a matrix in the MO S detector, that is, the MO S cell matrix, the structure of the peripheral circuit including the cell becomes as shown in FIG. The structure shown. Figure 1 0 3 · The MOS detector is a MOS detector of mx η pixel structure in which mx η photodiodes are arranged in a matrix. The detector includes a light-receiving portion (input portion) I having m X η photodiodes arranged in a matrix, and a readout control portion that sequentially reads signals from each photodiode constituting the light-receiving portion I CONT, and the processing section m of the noise cancellation circuit NC, output the output section of the signal read by the processing section m. The read control section CONT is composed of a vertical address circuit 5 and a horizontal address circuit 1 3, the vertical address circuit 5 is replaced by a vertical address buffer Bv A and a vertical decoding circuit Dv, and the horizontal address circuit 1 3 Replaced by the horizontal address buffer B HA and the horizontal decoding circuit DH. "Address signal a. This paper scale is applicable to the Chinese National Crushing Rate (CNS) A4 format (210X297mm) -Π8-(Please read the notes on the back Fill in Α, page)-· 1-9 B7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs V. Description of the invention (176) 1 A i Enter the vertical address BVA 'Middle »Address signal A-A n Input to the horizontal address buffer BHA. Y Select a specific cell from each address. The address signal input through the address buffer BVA 9 B H A causes the vertical decoding circuit DV and the horizontal decoding circuit Dh to select a specific line. 1st 0 4 The figure shows the specific structure of the address buffer BVA> B H A and the decoding circuit DV, D H. For the convenience of explanation% The example when only the address signal A 1 «A 2 A 3 is used. The signal inverted by the inverter INV 1 INV 2» INV 3 corresponding to the address signal A 1 A 2 »A 3 and the original signal Become parallel and select the line in the vertical direction-a different signal and configure the input of the above three signals N 0 R circuit N 0 R 1 N 0 R 2 9 N 0 R 3 0 N 0 R circuit N 0 R 1 > N 0 R 2 N 0 R 3 The N 0 R logic that inputs the above rr input signals only outputs the signal of H level from the circuits whose all input signals are L level and selects a specific line. Selects the address of the vertical line The signal and the address signal of the selected horizontal line can also be input from other address terminals. However, the multiplexer t can also be used to use the address signal as a row address signal (address signal in the vertical direction). The signal is used as the column address signal (horizontal Address signal) input of C A S j input square as seen from the same one access terminal on said »by according the present invention * can provide - species can be eliminated heteroaryl information and producing finished green beauty day image signal» Moreover a single -.  The magnification type M 0 S solid-state imaging device that can be driven by the power supply can also provide a kind of magnification type M 0 S type solid-state imaging device that can miniaturize the unit cell 9 and thus can reduce the overall appearance. The magnification type Μ 0 S type solid-state camera device t so the paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -179-Employee's consumer cooperation du printing A7 _____ B7 _____ 5 *, Description of the invention (177) A small, power-saving, high-quality MO S-type solid-state camera #setting application system can be provided. Schema: Figure 1 is a circuit diagram of a conventional example of the MO S-type solid-state camera device; Figure 2 is Figure 1 shows the operation timing diagram of the conventional example; Figure 3 is the basic structure of the fixed imaging element; Figure 4 is the general structure of the device that uses the MO S detector as the image detection section; Figure 5 is based on An explanatory diagram of the second embodiment of the invention, a structural diagram of an embodiment of a video camera using the MOS detector of the present invention; Array 1 〇4 and MO S detector 1 〇5-a sectional view of one embodiment of the integrated MO S camera device; circle 7 is an explanatory diagram of the third embodiment of the present invention, using the M of the present invention 〇S detector of another video camera embodiment of the structural diagram; Figure 8 is the fourth embodiment of the present invention, the invention's amplified MOS detector application in the network system Fig. 9 is an explanatory diagram of a fifth embodiment of the present invention, and an explanatory diagram of an embodiment in which the enlarged MO S detector of the present invention is applied to a still camera: Fig. 10 is a sixth embodiment of the present invention Explanatory drawing * An illustration of an embodiment of a telephone facsimile device using the MOS detector of the present invention; FIG. 11 is an explanatory diagram of a seventh embodiment of the present invention, an electronic copier using the MO S detector of the present invention Figures of the embodiment; Figure 12 is an explanatory diagram of the eighth embodiment of the present invention, using the present invention, the paper scale is applicable to the Chinese National Standard (CNS} A4 specification (210Χ297 mm) _ _ 1111.  I Threading (please read the notes on the back #-. . . . (Bird page) (306073 A7 B7 Printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs «.  5. Description of the invention (178) Figure 1 of the embodiment of the portable image scanner of the Μ 0 S detector of 1 1 Figure 1 I Figure 1 3 is a description of the ninth embodiment of the present invention • Use mechanical cutting 1 1 The structure example of the magnification type M 0 S detector of the changeable color filter is shown in FIG. 1 I, please 1 I, the 1st, 4th, and 4th embodiments of the present invention. FIG. 1 is the first embodiment of the present invention. Description of the large-scale M 0 S detector nhs applied to the thin-film scanning device. Back 1 1 of 1 1 5 FIG. 15 is a description of the first embodiment of the present invention. Note the use of the 1 M M 0 S detector. Single-eye reflex camera with white dynamic focusing mechanism 1 1 I I Figure of the embodiment of the machine% This 1 installed 1 6 A 1 6 B 1 6 C The garden is used to explain the focusing principle of the white dynamic focusing machine page 1 1 structure Picture 1 1 FIG. 17 is a description of the 12th embodiment of the present invention. Circuit diagram of the structural example of the M 0 S type I 1 solid-state imaging device 1 Order I FIG. 18 is a circuit diagram of the vertical address circuit of the 12 embodiment t 1 1 I Figure 1 9 shows the other circuits of the vertical address circuit of the 1st 2nd embodiment 1 1 circle * 1 1 second 2 0 shows the other of the vertical address circuit of the 1st 2nd embodiment-circuit line 1 圔1 1 The second 2 1 is the circuit diagram of the unit cell of the first 2 embodiment t 1 I The second 2 2 A 2 2 B 2 2 C The diagram is used to explain the modification of the unit cell of the first 1 2 1 1 embodiment The principle of uneven threshold voltage of the transistor 1 1 Figure:-1 1 The second 2 3 is the operation timing chart of the first 2 embodiment »1 1 The second 2 4 is the noise cancellation circuit device of the first 2 embodiment Of the structure 1 I cross section » 1 1 This paper scale is applicable to the Chinese National Standard (CNS> M Specification (210X297mm) -181-306073 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Beigong Consumer Cooperatives. 5 Invention Description (179) 1 I 2 5 A »2 5 B is a sectional view of the unit structure of the single unit cell of the 1st and 2nd embodiments. Fig. 1 1 2nd 6 6 is a diagram of a more example of the change of the semiconductor substrate of the unit cell of the 1st and 2nd embodiments 1 1 * Please read 1 first 1 2 7 The picture shows the unit of the cell of the conventional example of CCD solid-state imaging device • Λ back 1 I cross-section PBΠ diagram, 1 1 meaning I 2 8 The picture shows the unit of the first 2 embodiments The matter of the semiconductor substrate of the unit cell 1 1 The diagram of other modified examples 1 Page 2 9 The picture shows the page of the semiconductor substrate of the unit cell of the first embodiment 1 1 The other modified examples of the page 1 l The 3 0 circle is the first 1 2 Example 1 of the semiconductor substrate of the unit cell 1 1 Other modified examples of FIG. 1 1 3 1 The figure is the semiconductor substrate of the unit cell of the first embodiment 1 1 1 I of the other modified examples t 1 1 3 3 The picture shows the «« i.  1 1 FIG. 1 of other modified examples Line 1 3rd 3rd is an illustration of the 1st 3rd embodiment of the present invention Μ 0 S type 1 I circuit circle of the solid-state imaging device 1 I 3rd 4th is the first 3rd embodiment Operation timing diagram f 1 1 I Figure 3 5 is an explanatory diagram of the 14th embodiment of the present invention Μ 0 S type 1 1 circuit diagram of a solid-state imaging device 1 1 3 3 6 is the operation timing diagram of the 1 4 embodiment 1 1 3 7th is an illustration of the 15th embodiment of the present invention. Μ 0 S type 1 1 Circuit diagram of a solid-state imaging device 1 1 1 This paper scale is applicable to China ’s National Standard Rate (CNS) A4 specification (210X 297 mm) _ 182 A7 B7 306G73 V. Description of the invention (180) Figure 3 8 is an explanatory diagram of the 16th embodiment of the present invention, a circuit diagram of the MO S type solid-state imaging device; FIG. 39 is a 17th embodiment of the present invention Explanatory drawing, a circuit diagram of the MOS solid-state imaging device; FIG. 40 is an explanatory view of the 18th embodiment of the present invention, the 18th implementation Circuit diagram of the first configuration example of the MO S-type solid-state imaging device; FIG. 41 is an explanatory diagram of the eighteenth embodiment of the present invention, and the circuit of the second configuration example of the MO S-type solid-state imaging device of the eighteenth embodiment Fig. 4 2 is an explanatory diagram of the 19th embodiment of the present invention, a circuit diagram of a structural example of the unit cell of the MO S type solid-state imaging device; 4th and 3rd circles are explanatory diagrams of the 20th embodiment of the present invention, Circuit diagram of a structural example of the unit cell of the MOS solid-state imaging device; Chapter 4 is an explanatory diagram of the 21st embodiment of the present invention, and a circuit diagram of a structural example of the unit cell of the MO S solid-state imaging device; It is a circuit diagram of a video amplifier connected to a horizontal signal line in a modified example of the present invention; FIG. 46 is an explanatory diagram of the 22nd embodiment of the present invention, using the solid of the amplified MOS detector of this embodiment Circuit diagram of camera device

I 第4 7圖爲第4 6圖所示固體攝像裝置之動作時序圖 t 第4 8圖爲第4 6圖所示固體攝像裝置之限幅電晶體 之電位圚； 第4 9圖爲使用傳送電晶體之晶胞之電路圚； 本紙張尺度適用中國國家橾孪（CNS ) A4規格（210X297公釐）-183 - ' ~ ----------装------，訂------ii (請先閱讀背面之注意事項厂〜寫本頁) 一 經濟部中央標準局貝工消費合作社印製 A7 經濟部中央標準局貝工消费合作杜印製 五、 發明説明 ( 181) B7 1 第 5 0 圖 爲 使 用 第 2 3 實 施 例 之 放 大 型 Μ 0 S 偵 測 器 1 1 之 固 體 攝 像 裝 置 之 電 路 圖 ; 1 I 第 5 1 圖 爲 第 5 0 圖 所 示 固 體 攝 像 裝 置 之 動 作 時 序 ΓΕΠ 圖 1 I 請 1 » 先 1 閲 | 第 5 2 圖 爲 使 用 本 發 明 第 2 4 實 施 例 之 放 大 型 Μ 0 S 漬 背 1 I 偵 測 器 之 固 體 攝像 裝 置 之 電 路 圖 « 冬 | '意 I 第 5 3 圖 爲 本 發 明 第 2 4 實 施 例 之 固 體 攝像 裝 置 之 電 事 項 ^S..η. 1 1 路 圚 I 將 第 5 2 圖 所 示 之 —* 部 分 變 更 之 固 體 攝 像 裝 置 之 電 % 大 1 裝 路 圖 » 令 頁 1 1 第 5 4 圖 爲 第 5 2 9 5 3 圖 所 示 第 2 4 實 施 例 之 固 體 1 | 攝 像 裝 置 之 動 作 時 序 圖 1 I 第 5 5 圖 爲 垂 直 信 號 線 電 位 與 箝 位 節 電 位 之 時 間 變 化 1 訂 | 之 圖 1 1 1 第 5 6 圖 爲 垂 直 信 wt 線 電 位 與 箝 位 節 電 位 之 時 間 變 化 1 1 之 圖 1 1 第 5 7 圖 爲 本 發 明 第 2 5 實 施 例 之 說 明 圖 本 發 明 之 線 1 Μ 0 S 型 固 體 攝 像 裝 置 之 電 路 圖 t 1 | 第 5 8 圖 爲 第 2 5 實 施 例 之 電 路 中 之 垂 直 位 址 電 路 5 1 I 之 電 路 圖 • 1 1 I 第 5 9 圖 爲 第 2 5 實 施 例 之 電 路 中 之 垂 直 位 址 電 路 5 1 1 1 之 其 他 電 路 圖 1 - 1 1 第 6 0 圓 爲 第 2 5 實 施 例 之 電 路 中 之 垂 直 位 址 電 路 之 1 1 其 他 電 路 圖 * 1 1 第 6 1 圖 爲 第 2 5 實 施 例 之 電 路 中 之 單 位 晶 胞 之 電 路 1 1 本紙張尺度遴用中國國家標準（CMS) A4規格（ 210X297公釐）-184- 306G73五、發明説明（l82) 圖 經濟部中央標準局員工消費合作社印11 導 導出型 型型 電型實·，實： 半半输 s s S 之 so 圖 0圖 之 之 之 ο ο ο 體 ο 3 路 3 路 胞胞胞 Μ MM 晶 Μ 第電第電 晶 晶晶， ， ， 電， ,之’之 .，位 位 位 圖 ·，圓 圖 .，幅 圖 圖例圖例 圖單 單 單 明 圖明 明 圖限 明 明構明構 序之 之 之 說 序說 說 序之 說 說結說結 時中 中 中 之 時之 之 時中 之 之1之 2 作路 路 路 例 作例 例 作路 例 例第例第 動電 電 電 施 動施 施 動電 施 施之施之 之之 之 之 實 之實 實 之之 實 實置實置 例例 例 例 6 例 7 8 例例 9 ο 裝 ο 裝 施施.，施·，施 2 施 2 2 施施 2 3像 3 像 實實圖實圖實；第：實第；第；實實 第：第攝第攝 55 之 5 之 5 圖明圖 6 明圖明圖 88 明圖明體明體 22 例 2 例 2 路發路 2 發路發路 22 發路發固發固 第第更第形第電本電第本電本電第第 本電本型本型 爲爲變爲變爲之爲之爲爲之爲之爲爲 爲之爲 S 爲 S 圖圚他圖他圖例圖置圖圖置圖置圖圓 圖置圖0圖0 23 其 4 其 5 更 6 裝 78 裝 9 裝 οι 2 裝 3Μ4Μ 66 之 6 之 6 變 6 像 66 像 6 像 77 7 像 7 之 7 之 第第板第板第之第攝第第攝第攝第第；第攝第中第中 基 基路體 體體 .圖 體例例 體 體電固 固固 位 固施施 裝------訂------線 (請先閱讀背面之注意事現 嚷寫本頁) 本紙張尺度逋用中國國家標準（CNS)A4規格（ 210X297公釐〉-185 - A7 B7 經濟部中央標準局員工消費合作社印袈 五、發明説明（183) 第7 5圖爲第3 0實施例之動作時序圖； 第7 6圖爲第3 0實施例之電路中之雜訊消除電路之 電位圖； 第7 7圖爲本發明第3 1實施例之說明圖，MO S型 固體攝像裝置之結構例之電路圖： 第7 8圖爲第3 1實施例之動作時序圖； 第7 9圖爲本發明第3 2實施例之說明圖，MO S型 固體攝像裝置之電路圖； 第8 0圖爲第3 2實施例之電路中之單位晶胞之電路 圃’ 第8 1圖爲本發明第3 3實施例之說明圖，MO S型 固體攝像裝置之電路圖； 第8 2圖爲第3 3實施例之動作時序圖； 第8 3圖爲本發明第3 4實施例之說明圖，MO S型 固體攝像裝置之電路圖； 第84圖爲第34實施例之動作時序圖： 第8 5圖爲本發明第3 5實施例之說明圖，MOS型 固體攝像裝置之電路圖； 第8 6圖爲本發明第3 6實施例之說明圖，MO S型 固體攝像裝置之電路圖； 第8 7圖爲本發明第3 7賁施例之說明圖，MO S型 固體攝像裝置之電路圖； 第8 8圖爲第3 7實施例之動作時序圖： 第8 9圖爲本發明第3 8實施例之說明圖，MO S型 本紙浪尺度逋用中國國家梂準（CNS>A4規格（210X297公釐>_ 186 - ---------抑衣------、玎------0 (請先閲讀背面之注意事1 k寫本頁) 3〇6 A7 經濟部中夬梂準局員工消費合作社印製 五 Β7 ‘發明説明 (184) 1 固 鳗磙 像裝 置之 電路圖； 1 1 第 9 0 圖爲 本發明第3 9實施例 之 說明 圚， 第 3 9 實 1 1 施 例中 之Μ 0 S 型固體攝像裝置之第 1 結構 例之 電 路 圖 f 1 第 請 1 9 1 圖爲 本發明第3 9實施例 之 說明 圖， 第 3 9 實 先 閱 1 I 施 例中 之Μ 0 S 型固體攝像裝置之第 2 結構 例之 電 路 圖 * 讀 背 ιέ 1 1 | 第 9 2 圖爲 第3 9實施例之動作 時 序圖 ·· 之 注 意 1 1 I 第 9 3 圖爲 本發明第4 0實施例 之 說明 圖， Μ 0 S 型 事 項 1 1 固 鳆攝 像裝 置之 單位晶胞之結構例之 電 路圖 馬 本 1 裝 第 9 4 圖爲 本發明第41實施例 之 說明 圖， Μ 0 S 型 頁 1 1 固 贈攝 像裝 置之 單位晶胞之結構例之 電 路圖 • 1 I 第 9 5 圖爲 本發明第4 2實施例 之 說明 圖， Μ 0 S 型 1 I 固 贈攝 像裝 置之 單位晶胞之結構例之 電 路圖 » 1 訂 I 第 9 6 圖爲 第4 2實施例之動作 時 序圖 t 1 1 I 第 9 7 圖爲 第4 2實施例之裝置 構 iM- tar m圖 ; 1 1 第 9 8 圖爲 本發明第4 3實施例 之 說明 圖， Μ 0 S 型 1 1 固 贈攝 像裝 置之 單位晶胞之結構例之 電 路圖 線 1 第 9 9 圖爲 本發明第4 4資施例 之 說明 圖， Μ 0 S 型 1 1 固 體攝 像裝 置之 單位晶胞之結構例之 電 路圇 t 1 I 第 10 〇圚 爲本發明第4 5實施 例 之說 明圖 » Μ 0 S 1 1 I 型 固體 攝像 裝置 之單位晶胞之結構例 之 電路 圖； 1 1 1 第 10 1圖 爲本發明第4 6實施 例 之說 明圚 * Μ 0 S、 1 1 型 固體 攝像 裝置 之單位晶胞之結構例 之 電路 圖； 1 1 第 10 2圖 爲第4 6實施例之動 作 時序 圔， 1 1 第 10 3圖 爲本發明第4 7實施 例 之說 明圖 t 包 含 隨 1 1 用 適 度 尺 張 紙 本 準 標 家 國 國 規 % A7 B7 五、發明説明（l85) 意存取本發明之MO S晶胞矩陣時之晶胞之周邊電路之結 構例之方塊圖： 第1 0 4圖爲第1 0 3圖之結構中之位址緩衝器 B VA，B HA及解碼電路Dv，DH之具體結構例之電路圖。 (請先閲讀背面之注意事項ί^,寫本頁) .裝. 訂 經濟部中央標準局員工消費合作社印製 本紙張尺度遑用中國國家梯準（〇他）八4規格（2丨0乂297公釐）_188_I Figure 4 7 is the operation timing chart of the solid-state imaging device shown in Figure 4 6 Figure 4 8 is the potential of the limiting transistor of the solid-state imaging device shown in Figure 4 6; Figure 4 9 is the use of transmission The circuit of the unit cell of the transistor; The standard of this paper is applicable to the China National Twin (CNS) A4 specification (210X297 mm) -183-'~ ---------- installed ------, Order ------ ii (please read the precautions on the back of the plant ~ write this page) 1. Printed by the Ministry of Economic Affairs, Central Standards Bureau, Beigong Consumer Cooperative, A7 Printed by the Ministry of Economic Affairs, Central Standards Bureau, Beigong Consumer Co., Ltd. V. Inventions Description (181) B7 1 Figure 5 0 is the circuit diagram of the solid-state imaging device using the amplified Μ 0 S detector 1 1 of the second 3rd embodiment; 1 I The fifth 5 1 Figure is the solid-state imaging shown in Figure 50 The operation sequence of the device ΓΕΠ Figure 1 I Please 1 »First 1 Read | Page 5 2 The picture shows an enlarged Μ 0 S stain back 1 I using the second 4th embodiment of the present invention The circuit diagram of the solid-state imaging device of the detector «Winter | 'I I 5th Figure 3 shows the electrical matters of the solid-state imaging device according to the 24th embodiment of the present invention ^ S..η. 1 1 Lu Ji I will be the 5th Figure Shown-* Partially changed electricity of solid-state imaging device% Big 1 Installation diagram »Order page 1 1 5th 4 The picture shows the 5th 2 9 5 3 The solid 2 of the embodiment shown in Figure 2 4 | Operation timing diagram 1 I Page 5 5 The graph shows the time variation of the potential of the vertical signal line and the potential of the clamping node 1 Set | Figure 1 1 1 The graph 5 6 shows the time variation of the potential of the vertical signal line and the potential of the clamping node 1 1 Figure 1 1 Figure 5 7 is an illustration of the 25th embodiment of the present invention. The circuit diagram of the line 1 Μ 0 S type solid-state imaging device of the present invention t 1 | FIG. 5 8 is the circuit in the 2 5th embodimentThe circuit diagram of the vertical address circuit 5 1 I • 1 1 I No. 5 9 The picture shows the other circuit diagram of the vertical address circuit 5 1 1 1 in the circuit of the second 5th embodiment 1-1 1 The 6th circle is the 2nd 5th The vertical address circuit in the circuit of the embodiment 1 1 Other circuit diagrams * 1 1 The sixth 6 1 The picture shows the circuit of the unit cell in the circuit of the second embodiment 1 1 The paper standard is selected by China National Standard (CMS) A4 specification (210X297mm) -184-306G73 V. Description of the invention (l82) Figure 11 of the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative Printed 11 Derivative type electric type real, real: half and half lost ss S so picture 0 Of ο ο ο body ο 3-way 3-way cell MM MM crystalline second electric crystal Jingjing,,, electric,, of ,, bit, bitmap, circle, figure legend Legend, picture, picture, picture, picture, picture, picture, picture, picture, picture, picture, picture, picture, picture, picture, picture, picture, picture, picture 1 of 2 at the time of making an example of making an example of making an example of making an example Example Example Example 6 Example 7 8 Example Example 9 ο Equipment ο Shi Shi., Shi ·, Shi 2 Shi 2 2 Shi Shi 2 3 like 3 like real image real image; first: real first; first; real Practical: Photograph 55-5 of 5 Pictured picture 6 Pictured picture 88 Pictured body and body 22 Example 2 Example 2 Lufalu 2 Falufalu 22 Falufa Gufadi The first form, the second form, the second form, the second form, the type, the type, the type, the type, the type, the type, the type, the type, the type, the type, the type, the type, the type, the type, the type, the type. Image layout image layout image circle image layout 0 image 0 23 its 4 its 5 more 6 pack 78 pack 9 pack 2 2 pack 3Μ4Μ 66 of 6 6 change 6 image 66 image 6 image 77 7 image 7 of 7th plate The first plate, the second photo, the second photo, the second photo; the second base, the base road body body. ---- Line (please read the notes on the back first and write now This page uses the Chinese National Standard (CNS) A4 specifications (210X297mm) -185-A7 B7. The printed version of the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention description (183). Timing diagram of the operation of the 0th embodiment; FIG. 76 is the potential diagram of the noise canceling circuit in the circuit of the 30th embodiment; FIG. 77 is the explanatory diagram of the 31st embodiment of the present invention, MO S type solid Circuit diagram of the configuration example of the imaging device: Figure 7.8 is the operation timing chart of the 31st embodiment; Figure 799 is the explanatory diagram of the 32nd embodiment of the present invention, the circuit diagram of the MO S type solid-state imaging device; 0 is a circuit diagram of a unit cell in the circuit of the third embodiment. FIG. 8 1 is an explanatory diagram of the 33rd embodiment of the present invention, a circuit diagram of the MO S type solid-state imaging device; FIG. 8 2 is the first 33. Operation timing diagram of the 3rd embodiment; FIG. 8 3 is an explanatory diagram of the 34th embodiment of the present invention, a circuit diagram of the MO S type solid-state imaging device; FIG. 84 is an operation timing diagram of the 34th embodiment: No. 8 5 Figures are explanatory diagrams of the 35th embodiment of the present invention, a circuit diagram of the MOS solid-state imaging device; This is an explanatory diagram of the 36th embodiment of the present invention, a circuit diagram of the MO S type solid-state imaging device; FIG. 8 7 is an explanatory diagram of the 37th embodiment of the present invention, a circuit diagram of the MO S type solid-state imaging device; The figure is the operation timing chart of the 37th embodiment: Fig. 89 is the explanatory diagram of the 38th embodiment of the present invention. The MO S-type original paper wave scale adopts the Chinese National Standard (CNS> A4 specification (210X297mm> ; _ 186---------- Yiyi --------, 玎 ------ 0 (please read the notes on the back first to write this page) 3〇6 A7 Ministry of Economic Affairs Printed 5B7's description of the invention by the Chinese Consumers Cooperative Association (184) 1 Circuit diagram of the solid eel-like image device; 1 1 9 9 The figure is a description of the 39th embodiment of the invention, No. 3 9 Actual 1 1 The circuit diagram of the first structural example of the Μ 0 S type solid-state imaging device in the embodiment f 1 The first request 1 9 1 is an explanatory diagram of the 39th embodiment of the present invention. Circuit diagram of the second structure example of the Μ 0 S type solid-state imaging device * Read back 1 1 | Page 9 2 The photo shows the third 9 Operation Timing Diagram of the First Embodiment · Note 1 1 I 9th Figure 3 is an explanatory diagram of the 40th embodiment of the present invention, Μ 0 S type matters 1 1 Circuit diagram of a structural example of the unit cell of the solid-field camera device Maben 1 installed No. 9 4 is an explanatory diagram of the 41st embodiment of the present invention, a circuit diagram of a structural example of the unit cell of the MU 0 S type page 1 1 fixed camera device • 1 I 9th FIG. 5 is the present invention 4 An explanatory diagram of the 2nd embodiment, a circuit diagram of a structural example of the unit cell of the MOS type 1 I fixed camera device »1 Order I page 9 6 The operation timing chart of the 42nd embodiment t 1 1 I page 9 7 is the iM-tar m diagram of the device configuration of the 42nd embodiment; 1 1 9 9 is the explanatory diagram of the 43rd embodiment of the present invention, the unit cell of the MOS type 1 1 fixed camera device Circuit diagram of the structure example 1 Figure 9 9 is an explanatory diagram of the fourth to fourth embodiments of the present invention, the circuit example of the structure example of the unit cell of the MOS type 1 1 solid-state imaging device t 1 I 10th 圚for Explanation of the 45th embodiment of the invention »Circuit diagram of a structural example of the unit cell of the MOS 0 1 1 I type solid-state imaging device; 1 1 1 10 1 is a description of the 46th embodiment of the invention * Μ Circuit diagram of a structural example of a unit cell of a 0 S, 1 1 type solid-state imaging device; 1 1 FIG. 10 2 is the operation timing of the 46th embodiment, and 1 1 10 3 is the 47th embodiment of the present invention The explanatory diagram t contains the paper with the appropriate ruler of the standard size of the national standard% 1 A7 B7. 5. Description of the invention (l85) The structure of the peripheral circuit of the cell when accessing the MO S cell matrix of the present invention Example block diagram: Figure 104 is a circuit diagram of a specific structural example of the address buffers B VA, B HA and decoding circuits Dv, DH in the structure of Figure 103. (Please read the precautions on the back ^ first, and write this page). Packing. Order this paper to be printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Use the Chinese National Standard (Ota) 84 specifications (2 丨 0 乂297mm) _188_

Claims (1)

ABCD 經濟部中央標準局員工消費合作社印製 六、申請專利範圍 1 .—種畫像系統*其特徵爲包括：具有從被攝體接 受光學像，將該光學像導引至一定位置之光學系統，及將 被導引至上述一定位置之光學像以圖素單位光電變化成對 應於上述光學像之光量之偵測器之畜像處理裝置；及將該 畫像處理裝置之输出加工成一定型態而輸出之信號加工部 ，上述偵測器包括：設在上述一定位置之光電變換元件： 含有連接於該光電變換元件之放大MO S電晶體，在第1 時序時放大上述光電變換元件之输出，在第2時序時输出 與上述光電變換元件之輸出無關之雜訊之輸出電路；連接 於該輸出電路之輸出端，從上述第1及第2時序時之上述 输出電路觀察之阻抗相等，產生在上述第1及第2時序時 之上述輸出電路之输出之差值之雜訊去除電路。 2. —種畫像系統，其特徵爲包括：具有從被攝體接 受光學像，將該光學像導引至一定位置之光學系統，及將 被導引至上述一定位置之光學像以圖素單位光電變化成對 應於上述光學像之光置之電氣信號之偵測器之奎像處理裝 置：及將該畫像處理裝置之输出加工成一定型態而輸出之 信號加工部，上述偵測器包括：設在上述一定位置之光電 變換元件；含有連接於該光電變換元件之放大MO S電晶 體，在第1時序時放大上述光電變換元件之輸出而將之輸 出，在第2時序時输出與上述光電變換元件之输出無關之、 雜訊之輸出電路；連接於上述输出電路之信號線：及具有 一端連接於上述信號線之箝位電容器•連接在該箝位電容 器之另一端與一定電位之間之樣品保持電容器，及將小於 本紙張尺度適用中國國家標隼（CNS)A4規格（210X297公釐）-189 - ---------^------、1T------0 (請先聞讀背面之注意事項寫本頁) 經濟部中央揉隼局員工消費合作社印策 306G73 it C8 D8 々、申請專利範圍 上述箝位電容器與上述樣品保持電容器之串聯電容量之2 倍之電容量選擇性的施加於上述信號線與一定電位之間之 阻抗修正電路，並產生在上述第1及第2時序時之上述输 出電路之输出之差值之雜訊去除電路。 3 . —種畫像系統，其特徵爲包括：具有從被攝體接 受光學像，將該光學像導引至一定位置之光學系統，及將 被導引至上述一定位置之光學像以圖素單位光電變化成對 應於上述光學像之光量之電氣信號之偵測器之畫像處理裝 置：及將該查像處理裝置之输出加工成一定形態输出之信 號加工部，上述偵測器包括：設在上述一定位置之光電變 換元件；含有連接於該光電變換元件之放大MO S電晶體 ，在第1時序時放大上述光電變換元件之輸出並將之輸出 ，在第2時序時輸出與上述光電變換元件之输出無關係之 雜訊之輸出電路；連接於該輸出電路之輸出端之信號線； 輸入端連接於該信號線之源極跟隨電路：一端連接於該源 極跟隨電路之輸出端之箝位電容器：連接在該箝位電容器 之另一端與第1 一定電位之間之樣品保持電容器；及連接 於上述箝位電容器之另一端與第2 —定電位之間，選擇性 的箝位上述樣品保持電容器之箝位電晶體。 4 .—種畫像系統，其特徵爲包括：具有從被攝體接 受光學像，將該光學像導引至一定位置之光學系統，及將' 被導引至上述一定位置之光學像以圚素單位光電變化成對 應於上述光學像之光量之電氣信號之偵測器之畫像處理裝 置：及將該畫像處理裝置之輸出加工成一定形態而輸出之 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）_ 190 - ---------1------,訂------^ (請先閲讀背面之注意事項*·..寫本頁) 、 A8 B8 C8 D8 六、申請專利範圍 信號加工部，上述偵測器包括：設在上述一定位置之光電 變換元件；含有連接於該光電變換元件之放大MO S電晶 體，在第1時序時放大上述光電變換元件之输出而將之輸 出，在第2時序時輸出與上述光電變換元件之输出無關之 雜訊之輸出電路；連接於該输出電路之输出端之信號線； 一端連接於該信號線之箝位電容器；連接在該箝位電容器 之另一端與第1 一定電位之間之樣品保持電容器；及連接 在上述箝位電容器之另一端與第2 —定電位之間，在一定 之時序時箝位上述樣品保持電容器之箝位電晶體。 經濟部中央標隼局負工消費合作社印聚 (請先閱讀背面之注意事項寫本頁) 5 . —種畫像系統，其特徵爲包括：具有從被攝體接 受光學像，將該光孿像導引至一定位置之光學系統，及將 被導引至上述一定位置之光學像以圖素單位光電變換成對 應於上述光學像之光量之電氣信號之偵測器之畫像處理裝 置；及將該畫像處理裝置之输出加工成一定形態而输出之 信號加工部，上述偵測器包括：在第1時序時输出對應於 雜訊及上述光量之電壓，在第2時序時输出對應於上述雜 訊之電壓之圖素；含有由接受該圖素之输出之第1節，儲 存電荷之第2節*及從第2節接受根據第1節之電位控制 之一定量之電荷之第3節所構成之3端子元件，產生上述 第1與第2時序時之上述圖素之输出之差值之雜訊去除電 路。 6 . —種畫像系統，其特徵爲包括：具有從被攝體接 受光學像，將該光學像導引至一定位置之光學系統，及將 被導引至上述一定位置之光學像以圖素單位光電變換成對 本紙張尺度適用中國國家標準（CNS)A4*Jl格（ 210X297公釐）_ 191 - 經濟部中央標準局員工消费合作社印袈 A8 B8 C8 D8 六、申請專利範圍 應於上述光學像之光量之電氣信號之偵測器之畫像處理裝 置；將該畫像處理裝置之輸出加工成一定形態而输出之信 號加工部，上述偵測器包括：在第1時序時輸出對應於雜 訊及上述光量之電壓，在第2時序時输出對應於上述雜訊 之電壓之圖素；及输出配合在上述第1時序時之上述圖素 之输出電壓之電荷量•與配合在上述第2時序時之上述圖 素之輸出電壓之電荷量之差之雜訊去除電路。 7 . —種畫像系統，其特徴爲包括：具有從被攝體接 受光學像，將該光學像導引至一定位置之光學系統，及將 被導引至上述一定位置之光學像以圖素單位光電變換成對 應於上述光學像之光量之電氣信號之偵測器之畫像處理裝 置：將該畫像處理裝置之输出加工成一定形態而输出之信 號加工部，上述偵測器包括：在第1時序時輸出對應於雜 訊及上述光量之第1電氣信號，在第2時序時輸出對應於 上述雜訊之第2電氣信號之圖素；及以相同之输入阻抗输 入上述第1及第2電氣信號，輸出上述第1與第2電氣信 號之差值之雜訊去除電路。 8 .—種畫像系統*其特徵爲包括：具有從被攝體接 受光學像，將該光學像導引至一定位置之光學系統，及將 被導引至上述一定位置之光學像以圖素單位光電變換成對 應於上述光學像之光量之電氣信號之偵測器之畫像處理裝、 置：及將該畫像處理裝置之输出加工成一定形態而输出之 信號加工部，上述畫像處理裝置之输出之動態範圍爲7 0 d B以上。 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）-192 - ---------^------,訂------^ (請先閱讀背面之注意事項JS--_寫本頁) 气 經濟部中央標準局員工消費合作社印裝 A8 B8 C8 D8 ~、申請專利範圍 9.如申請專利範圍第1 · 2，3，4，5，6，7 或8項之系統，其中上述偵測器之输出爲類比信號，上述 畫像處理裝置又包括將上述偵測器之輸出變換成數位信號 之A/D變換電路，及將控制上述偵測器之動作之時序信 號供給於上述偵測器之時序信號產生電路。 1 0 .如申請專利範圍第9項之系統，其中上述時序 信號之電源位準與供給於上述偵測器之電源位準相同。 1 1.如申請專利範圍第1 ，2，3 ，4，5，6， 7或8項之系統，其中上述偵測器之输出爲電壓信號，上 述畫像處理裝置又包括：接受上述偵測器之輸出之電壓-電流變換電路：接受該電壓-電流變換電路之輸出之電流 _m壓變換電路：將該電流一電壓變換電路之輸出放大成 對應於所需靈敏度之增益之放大電路；及箝位該放大電路 之输出之箝位電路。 1 2 .如申請專利範圍第9項之系統，其中上述偵測 器之輸出爲電壓信號，上述畫像處理電路又包括：接受上 述偵測器之輸出之電壓-電流變換電路；接受該電壓一電 流變換電路之輸出之電流-電壓變換電路；將該電流-電 壓變換電路之输出放大成對應於所需靈敏度之增益之放大 電路；及箝位該放大電路之输出而將之供給於上述A/D 變換電路之箝位電路。 1 3.如申請專利範圔第1 ，2 ，3 ，4，5 ，6 ， 7或8項之系統，其中上述信號加工部包括對上述畫像處 理裝置之输出實施一定之製程處理之製程電路，及將該製 本紙張尺度適用中國國家標準（〇邶）八4現格（210\297公釐）_193_ ---------g------、訂------^ (請先閱讀背面之注意事項舄本頁) β S06G7S_^_ 六、申請專利範圍 程電路之输出變換成複合影像信號之編碼電路。 1 4.如申請專利範圍第1 ，2，3，4，5，6， 7或8項之系統，其中上述光學系統包括：將上述光學像 聚焦之透鏡；調整射入上述畫像處理裝置中之入射光量之 光圈調整裝置；調整上述透鏡與上述畫像處理裝置間之距 離之焦距調整裝置；及設在上述圖素上之顔色過濾器》 1 5.如申請專利範圍第1 ，2，3，4，5，6， 7或8項之系統，其中配合上述光學像之波長設置許多個 上述畫像處理裝置，上述光學系統包括：將上述光學像聚 焦之透鏡：調整射入上述畜像處理裝置中之入射光量之光 圈調整裝置；調整上述透鏡與許多上述畫像處理裝置間之 距離之焦距調整裝置；及以波長將經由上述透鏡聚焦之光 學像分光成許多光學像，將被分光之光學像供給於許多上 述畫像處理裝置之分光裝置。 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）_ 194 - ---------批衣------1T------0 (請先閱讀背面之注意事項_s,.^本頁) ’ 處 處 -處’ 6 像 ，像 6 像 6 ’ 畫 6 畫 ，畫 ， 5 述 ，述 5 述 5 ’ 上 5 上 ’上 ， 4 將 ，將 4 將 4 ， 有 · 4 有 ，有 。’ 3 具置 ， 具。 3 具置 3 ， 部裝 3 部器，部裝 -2 工億，工視 2 工刷 2 , 加記 2 加監，加印 ， 1 號之，號之 1 號之 1 第信億 1 信示第信刷第 圍述記第述顯圍述印圍 範上態圍上態範上態範 利中形範中形利中形利 專其定利其定專其定專 請，一 專，一 請，一請 申統以請統以申統以申 如系出申系出如系出如 •之輸如之輸.之輸 6 項之 7 項之 8 項之 9 18 置 18 置 18 置 1 或裝 或裝 或裝 7 理 7 理 7 理 經濟部中央標準局員工消费合作社印製 ABCD 經濟部中央標準局員工消費合作社印製 六、申請專利範圍 7或8項之系統，其中又包括：接受上述信號加工部之输 出之介面電路；接受該介面電路之輸出之信號匯流排；及 連接於該信號匯流排之資訊處理裝置。 20.如申請專利範圍第9項之系統，其中又包括： 記億上述A/D變換電路之输出之幀記憶器；及壓縮記億 於該幀記憶體中之信號之壓縮裝置。 2 1 _如申請專利範圍第2 0項之系統，其中又包括 記億上述壓縮裝置之输出之記憶裝置。 22.如申請專利範圍第20項之系統，其中又包转 :接受上述畫像壓縮裝置之输出之介面電路；及接受該介 面電路之輸出之信號匯流排。 2 3_如申請專利範困第1 ，2，3，4，5，6， 7或8項之系統，其中又包括在上述被攝體上照射光線之 光源，上述信號加工部包含根據上述畫像處理裝置之输出 印刷對應於上述被攝體之畫像之印刷裝置，上述光學像爲 從上述光源射出之光線照射在上述被攝體上而反射之反射 光。 24. 如申請專利範圍第23項之系統，其中又包括 使上述被攝體與上述光源相對的移動之移動裝置· 25. 如申請專利範圍第1 ，2，3，4，5，6， 7或8項之系統，其中又包括在上述被攝體之照射光線之、 光源，上述信號加工部包括爲了將上述畫像處理裝置之輸 出發送至電話線路而進行信號變換之數據機，上述光學像 爲從上述光源射出之光線在上述被攝體上反射之反射光。 本紙張尺度遥用中國國家標牟（CNS>A4規格（ 210X297公釐）-195 - ---------I------、玎-----1^ (請先閱讀背面之注意事項*'寫本頁) 、 經濟部中央標隼局員工消費合作社印默 A8 II ‘ __D8 々、申請專利範圍 2 6 .如申請專利範圍第2 5項之系統，其中又包括 使上述被攝體與上述光源相對的移動之移動裝置。 27. 如申請專利範圍第1 ，2 ，3 ，4，5 ，6 ， 7或8項之系統，其中又包括：在上述被攝體上照射光線 之光源；使上述被攝體與上述光源相對的移動之移動裝置 :及檢測上述被攝體與上述光源之位置關係之位置檢測裝 置，上述信號加工部以上述位置檢測裝置之輸出加工上述 畫像處理裝置之輸出，上述光學像爲從上述光源射出之光 線照射在上述被攝體上而反射之反射光。 28. 如申請專利範圍第1 ，2，3，4，5，6， 7或8項之系統，其中上述光學系統包括可由移動裝置移 動之透鏡，與該透鏡相距某距離設在上述偵測器側，將透 鏡上述透鏡之光線2分割成上述一定方向之光線而供給於 上述偵測器之一對分離透鏡•上述信號加工部檢測透過上 述分離透鏡之被2分割之光線之焦點位置間之距離，根據 該檢測結果產生驅動上述移動裝置之信號。 29. 如申請專利範圍第1 ，2，3 ，4，5，6， 7或8項之系統，其中又包括在上述被攝體上照射光線之 光源，上述被攝體爲設在上述光源與上述偵測器間之攝影 到影像之薄膜* 3 0 . —種固體攝像裝置，其特徵爲包括：光電變換' 元件；含有連接於該光電變換元件之放大MO S電晶體， 在第1時序時放大上述光電變換元件之輸出而將之輸出， 在第2時序時输出與上述光電變換元件之输出無關係之雜 本紙張尺度通用中國國家標準（CNS)A4規格（210X297公釐U 196 - (請先閱讀背面之注意事項為本頁) -裝. 訂 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 訊之輸出電路；及連接於該输出電路之輸出端，從在上述 第1及第2時序時之上述输出電路觀察之阻抗相等，產生 上述第1時序與第2時序時之上述輸出電路之输出之差值 之雜訊去除電路。 3 1 .如申請專利範圍第3 0項之裝置*其中又包括 連接上述输出電路與上述雜訊去除電路之信號線。 3 2 .如申請專利範圍第3 1項之裝置，其中上述雜 訊去除電路包括：一端連接於上述信號線之箝位電容器： 連接在該箝位電容器之另一端與箝位電位之間•選擇性的 成爲導通之箝位電晶體；連接在上述箝位電容器之另一端 與一定電位之間之樣品保持電容器；及連接在上述信號線 與一定電位之間之阻抗修正電路· 3 3 .如申請專利範圍第3 2項之裝置，其中上述阻 抗修正電路包括：當上述箝位電晶體成爲非導通時選擇性 的成爲導通之開關元件；及串聯於該開關，而具有與上述 箝位電容器與上述樣品保持電容器之串聯電容置相等之電 容置之修正電容器。 34.如申請專利範圍第31項之裝置，其中上述雜 訊去除電路具有連接於上述信號線之阻抗變換電路，從上 述輸出電路觀察之阻抗爲該阻抗變換電路之輸入阻抗。 3 5.如申請專利範圍第3 4項之裝置，其中上述阻、 抗變換電路具有閘極連接於上述信號線，源極連接於一定 電位之輸入MO S電晶體，及連接在該第2M0 S電晶體 之吸極與電源電位之間之負載。 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐）_ 197 _ ---------^------,訂------0 (請先閱讀背面之注意事項1 ,舄本頁) ( 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 3 6 ·如申請專利範圍第3 1項之裝置，其中上述雜 訊去除電路具有閘極連接於上述信號線之限幅電晶體，從 上述输出電路觀察之阻抗爲該限幅電晶體之閘極電容置。 37.如申請專利範圍第36項之裝置，其中上述雜 訊去除電路又包括：連接在上述限幅電晶體之源極與限幅 脈波供給端子之間之限幅電容器：及連接在上述限幅電晶 體之吸極與一定電位之間，將上述差值充電之限幅傅送電 容器。 3 8 . —種固體攝像裝置*其特徵爲包括：光電變換 元件；含有連接於該光電變換元件之放大型MO S電晶體 ，在第1時序時放大上述光電變換元件之输出而將之输出 ，在第2時序時輸出與上述光電變換元件之输出無關係之 雜訊之输出電路：連接於上述输出電路之信號線；將一端 連接於上述信號線之箝位電容器之電容量，連接在該箝位 電容器之另一端與一定電位之間之樣品保持電容器之電容 置，及小於上述箝位電容器之電容量與上述樣品保持電容 器之電容童之串聯電容量與上述箝位電容器之電容置之差 之2倍之電容量選擇性的施加於上述信號線與一定電位之 間之阻抗修正電路；及產生在上述第1與第2時序時之上 述輸出電路之輸出之差值之雜訊去除電路。 3 9 種固體攝像裝置，其特徵爲包括：光電變換、 元件：含有連接於該光電變換元件之放大MO S電晶體， 在第1時序時放大上述光笔變換元件之輸出而將之輸出， 在第2時序時輸出與上述光電變換元件之输出無關之雜訊 本紙張尺度適用十國國家標準（CNS)A4規格（ 210X297公釐）_ J98 - ---------g------、訂------0 (請先閱讀背面之注意事項-&,.½本頁) < A8 B8 C8 · D8 ^、申請專利範圍 之输出電路：連接於該輸出電路之输出端之信號線：输入 端連接於該信號線之源極跟隨電路：一端連接於該源極跟 隨電路之輸出端之箝位電容器；連接在該箝位電容器之另 一端與第1一定電位之間之樣品保持電容器；及連接在上 述箝位電容器之另一端與第2 —定電位之間，選擇性的箝 位上述樣品保持電容器之箝位電晶體。 40.如申請專利範圍第39項之裝置，其中 位電容器與上述樣品保持電容器在同一基板上成爲 重叠。 4 1.—種固體攝像裝置，其特徴爲包括：光 元件；含有連接於該光電變換元件之放大MO S電 在第1時序時放大上述光電變換元件之输出而將之 在第2時序時输出與上述光電變換元件之输出無關 訊之输出電路；連接於該输出電路之输出端之信號 端連接於該信號線之箝位電容器；連接在該箝位電 上述箝 平面的 電變換 晶體， 输出， 係之雜 線；一 容器之 請 先 閱 讀 背 之 注 意 事 項 I裝 頁 訂 另一端與第1 一定電位之間之樣品保持電容器：及連接在 上述箝位電容器之另一端與第2 —定電位之間，在一定時 間時箝位上述樣品保持電容器之箝位電晶體· 4 2 . —種固體攝像裝置，其特徵爲包括：在第1時 序時输出配合雜及入射光之電壓，在第2時序時输出配合 上述雜訊之電壓之圖素；含有具備接受該圚索之輸出之第 1節，儲存電荷之第2節，及從第2節接受根據上述第1 節之電位控制之一定量之電荷之第3節之3端子元件，產 生在上述第1與第2時序時之上述圖素之輸出之差值之雜 本紙張尺度通用中國國家標準（CNS)A4規格（2丨0X297公釐）_ 199 - 線 經濟部中央標準局員工消费合作社印製 經濟部中央標準局員工消費合作社印裝 A8 B8 C8 · D8 六、申請專利範圍 訊去除電路。 43.如申請專利範圍第42項之裝置，其中上述3 端子元件係以上述第1節做爲閘極，以上述第2節爲源極 •以上述第3節做爲吸極之MO S電晶體。 4 4.—種固體攝像裝置，其特徴爲包括：在第1時 序時输出配合雜訊及入射光之電壓，在第2時序時輸出配 合上述雜訊之電壓之圖素；及輸出配合在上述第1時序時 之上述圖素之输出電壓之電荷置，與配合在上述第2時序 時之上述圖素之輸出電壓之電荷量之差之雜訊去除電路。 4 5 ·—種固體攝像裝置，其特徴爲包括：在第1時 序時输出配合雜訊及入射光之第1電氣信號*在第2時序 時输出配合上述雜訊之第2電氣信號之圖素；及以相同之 输入阻抗輸入上述第1及第2電氣信號，输出上述第1與 第2電氣信號之差值之雜訊去除電路。 4 6 . —種固體攝像裝置，其特徴爲包括：許多水平 選擇線：與上述水平選擇線交叉之許多垂直信號線：設在 上述水平選擇線與上述垂直信號線之各交叉位置，配合上 述水平選擇線之電位選擇性的成爲活化，在該活化期間內 之第1時序時將配合雜訊及入射光之第1電氣信號供給於 對應之上述垂直信號線，在上述活化期間內之第2時序時 將配合上述雜訊之第2電氣信號供給於對應之上述垂直信， 號線之許多圚素；及設在上述許多垂直信號線之各一端， 以相同之阻抗輸入上述第1及第2電氣信號，輸出上述第 1與第2電氣信號之差值之許多雜訊去除電路。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）_ goo _ ---------^------,訂------0 (請先閱讀背面之注意事項1:%本頁) 一 ABCD 經濟部t央標準局員工消費合作社印裝 々、申請專利範圍 4 7 . —種固體攝像裝置，其特徵爲包括：許多水平 選擇線：與上述水平選擇線交叉之許多垂直信號線；設在 上述水平選擇線與上述垂直信號線之各交叉位置，配合上 述水平選擇線之電位選擇性的成爲活化，在該活化期間內 之第1時序時將配合雜訊及入射光之第1電氣信號供給於 對應之上述垂直信號線，在上述活化期間內之第2時序時 將配合上述雜訊之第2電氣信號供給於對應之上述垂直信 號線之許多圖素；及含有具備連接於上述許多垂直信號線 之各一端之第1節，儲存電荷之第2節，及從第2節接受 根據上述第1節之電位控制之一定置之電荷之第3節之3 端子元件，產生在上述第1與第2時序時之上述圖素之输 出之差值之許多雜訊去除電路。 4 8 .—種固體攝像裝置，其特徽爲包括：許多水平 選擇線：與上述水平選擇線交叉之許多垂直信號線：設在 上述水平選擇線與上述垂直信號線之各交叉位置*配合上 述水平選擇線之電位選擇性的成爲活化，在上述活化期間 內之第1時序時將配合雜訊及入射光之第1電應输出於對 應之上述垂直信號線，在上述活化期間內之第2時序時將 配合上述雜訊之第2電壓输出於對應之上述垂直信號線之 許多圓素：及設在上述許多垂直信號線之各一端，输出配 合上述第1電壓之電荷量與配合上述第2電壓之電荷量之、 差之許多雜訊去除電路。 4 9 . 一種固體攝像裝置，其特撤爲包括··許多水平 選擇線：與上述水平選擇線交叉之許多垂直信號線；設在 本紙張尺度適用申國國家橾準（CNS)A4規格（210X297公釐）-201 - ^-- (請先閱讀背面之注意事項ί 、寫本頁) 訂 經濟部中央標隼局員工消費合作杜印製 A8 ?88 . D8 六、申請專利範圍 上述水平選擇線與上述垂直信號線之各交叉位置，配合上 述水平選擇線之電位選擇性的成爲活化，在該活化期間內 之第1時序時將配合雜訊及入射光之第1電氣信號输出於 對應之上述垂直信號線，在上述活化期間內之第2時序時 將配合上述雜訊之第2電氣信號輸出於對應之上述垂直信 號之許多圖素：及具有連接於上述許多垂直信號線之各一 端之許多箝位電容器，連接在許多箝位電容器之各另一端 與第1 一定電位之間之許多樣品保持電容器，及連接在上 述許多箝位電容器之各另一端與第2 —定電位之間，以一 定時序將對應之上述樣品保持電容器箝位之許多箝位電晶 體之許多雜訊去除電晶體。 50. 如申請專利範團第46，47，48 *或49 項之裝置，其中又包括：使上述許多水平選擇線選擇性的 依次活化之第1移位電晶體；输出端子；一端連接於上述 許多雜訊去除電路之各输出端，另一端共同連接於上述输 出端子之許多轉換元件：及依次输出使上述許多轉換元件 選擇性的成爲導通之控制信號之第2移位電晶體· 51. 如申請專利範圍第46，47，48或49項 之裝置，其中又包括：输出端子：一端連接於上述許多雜 訊去除電路之各输出端，另一端共同連接於上述输出端之 許多轉換元件；輸入位址信號之位址端子；及將上述位址、 信號解碼，根據其結果使上述許多水平選擇線選擇性的成 爲活化，而且輸出使上述許多轉換元件選擇性的成爲導通 之控制信號之位址解碼器。 本紙張尺度逋用中國國家標準（CNS)A4規格（210X297公釐）_ 202 - ---------1------，訂------0 (請先閲讀背面之注意事項*'·-.寫本頁) 《 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 5 2 ·如申請專利範圍第5 0項之裝置，其中又包括 :產生用來驅動上述第1及第2移位暫存器之時序信號之 時序產生器；及输入端結合於上述輸出端子之數比數位（ A / D )變換電路。 5 3 .如申請專利範圍第5 1項之裝置，其中又包括 输入端連接於上述输出端之A/D變換電路。 54.如申請專利範圍第53項之裝置，其中又包括 放大上述输出端子之信號而將之供給於上述A/D變換電 路之输入端之類比放大電路。 5 5 .如申請專利範圍第5 2項之裝置，其中又包括 放大上述输出端子之信號而供給於上述A/D變換電路之 输入端之類比放大電路。 5 6 · —種固體攝像裝置，其特徴爲包括：許多垂直 信號線；分別對應於許多垂直信號線設置，在第1時序時 將配合雜訊及入射光之第1電氣信號供給於對應之上述垂 直信號，在第2時序時將配合上述雜訊之第2電氣信號供 給於對應之上述垂直信號線之許多圖素；及設在上述許多 垂直信號之各一端，以相同之阻抗輸入上述第1及第2電 氣信號，輸出上述第1與第2電氣信號之差值之許多雜訊 去除電路。 5 7 · —種固體攝像裝置，其特徵爲包括：許多垂直、 信號線；分別對應於許多垂直信號線設置，在第1時序時 將配合雜訊及入射光之第1電氣信號供給於對應之上述垂 直信號線，在第2時序時將配合上述雜訊之第2電氣信號 本紙張尺度逋用中國國家標準（CNS)A4規格（ 210X297公釐）_ 2〇3 _ ^— (請先閱讀背面之注意事項1.:¾¾本頁) 訂 線- 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 供給於上述垂直信號線之許多圖素：及包含具有連接於上 述許多垂直信號線之各一端之第1節*儲存電荷之第2節 ，從該第2節接受根據上述第1節之電位控制之一定量之 電荷之第3節之3端子元件，產生在上述第1與第2時序 時之上述圖素之輸出之差值之許多雜訊去除電路。 5 8 . —種固體攝像裝置，其特徴爲包括：許多垂直 信號線；分別對應於許多垂直信號線設置，在第1時序時 將配合雜訊及入射光之第1電壓供給於對應之上述垂直信 號線*在第2時序時將配合上述雜訊之第2電壓供給於對 應之上述垂直信號線之一端，產生配合上述第1電壓之電 荷量與配合上述第2電壓之電荷量之差之許多雜訊去除電 路。 5 9 . —種固體攝像裝置，其特徵爲包括：許多垂直 信號線；分別對應於許多垂直信號線設置，在第1時序時 將配合雜訊及入射光之第1電氣信號供給於對應之上述垂 直信號，在第2時序時將配合上述雜訊之第2電氣信號供 給於對應之上述垂直信號線之許多圖素；及連接於上述許 多垂直信號線之各一端之許多箝位電容器，連接在許多箝 位電容器之各另一端與第1 一定電位之間之許多樣品保持 電容器，及連接在上述許多箝位電容器之各另一端與第2 一定電位之間，在一定時序時將對應之上述樣品保持電容、 器箝位之許多箝位電晶體。 6 0 . —種固體攝像裝置，其特徴爲包括：許多水平 選擇線；與該水平選擇線交叉之垂直信號線：設在上述水 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐）_ 204 - ^-- (請先閲讀背面之注意事項I ,舄本頁) 訂 線 A8 B8 C8 β _ D8 ^、申請專利範圍 請 先 閲 背 ιέ 之 注 意 事 項 寫裝· 本衣 頁 平選擇線與上述垂直信號線之各交叉位置，配合上述水平 選擇線之電位選擇性的成爲活化，在該活化期間內之第1 時序時將配合雜訊及入射光之第1電氣信號供給於上述垂 直信號線，在上述活化期間內之第2時序時將配合上述雜 訊之第2電氣信號供給於上述垂直信號線之許多圖素；及 設在上述垂直信號線之一端*以相同之輸入阻抗输入上述 第1及第2電氣信號，產生上述第1與第2電氣信號之差 值之雜訊去除電路· 6 1 種固體攝像裝置，其特徵爲包括：許多水平 訂 線 經濟部中央標準局貝工消費合作社印製 選擇線：與該水平選擇線交叉之垂直信號線：設在上述水 平選擇線與上述垂直信號線之各交叉位置，配合上述水平 選擇線之電位選擇性的成爲活化，在該活化期間內之第1 時序時將配合雜訊及入射光之第1電氣信號供給於上述垂 直信號線，在上述活化期間內之第2時序時將配合上述雜 訊之第2電氣信號供給於上述垂直信號線之許多圖素：及 包含具有連接於上述垂直信號線之一端之第1節，儲存電 荷之第2節，及從該第2節接受根據上述第1節之電位控 制之一定量之電荷之第3節之3端子元件，產生在上述第 1與第2時序時之上述圖素之输出之差值。 6 2 .—種固體攝像裝置，其特徴爲包括：許多水平 選擇線；與上述水平選擇線交叉之垂直信號線；設在上述' 水平選擇線與上述垂直信號線之各交叉位置，配合上述水 平選擇線之電位選擇性的成爲活化，在該活化期間內之第 1時序時將配合雜訊及入射光之第1電壓供給於上述垂直 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐）_ 205 - 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 信號線，在上述活化期間內之第2時序時將配合上述雜訊 之第2電壓供給於上述垂直信號線之許多圖素；及設在上 述垂直信號線之一端，產生配合上述第1電壓之電荷置與 配合上述第2電壓之電荷量之差之雜訊去除電路。 6 3 . —種固體攝像裝置，其特徵爲包括：許多水平 選擇線；與上述水平選擇線交叉之垂直信號線：設在上述 水平選擇線與上述垂直信號線之各交叉位置，配合上述水 平選擇線之電位選擇性的成爲活化，在該活化期間內之第 1時序時將配合雜訊及入射光之第1電氣信號供給於上述 垂直信號線，在上述活化期間內之第2時序時將配合上述 雜訊之第2電氣信號供給於上述垂直信號線之許多圖素； 及具有連接於上述垂直信號線之一端之箝位電容器，連接 在該箝位電容器之另一端與第1 一定電位之間之樣品保持 電容器，及連接在上述箝位電容器之另一端與第2 —定電 位之間，在一定時序時將上述樣品保持電容器箝位之箝位 電晶體之雜訊去除電路· 6 4 .—種半導體稹體電路，其特徴爲包括：半導體 基板；形成於該半導體基板上之申請專利範圍第4 6至 6 3項中之任一項所述之固體攝像裝置；及形成在該固體 攝像裝置上，具有對應於上述許多圖素之許多開口之遮光 膜。 65. 如申請專利範圍第64項之電路，其中又包括 選擇性形成於上述開口上之顏色過濾器。 66. 如申請專利範團第64項之電路，其中又包括 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐>_ 206 - ---------^------,玎------^ (請先閲讀背面之注意事項®--.%'本頁) 一 經濟部中央標準局員工消費合作社印装 A8 B8 C8 . D8々、申請專利範圍 形成於上述開口上之微透鏡。 6 7 . —種差值信號输出方法，其特徴爲包括：在 MO S電晶體之閘極上施加第1電壓之步驟；將充電於一 連接在上述MO S電晶體之源極之電容器中之電荷復置之 步驟；在上述電容器之另一端施加第1脈波，將一定電荷 從上述MO S電晶體之源極經由吸極放電之步驟；在上述 MO S電晶體之閘極上施加第2電壓之步驟；及在上述電 容器之另一端施加振幅與上述第1脈波之振幅相等之第2 脈波，將相當於上述第1電壓與第2電壓之差值之電荷從 上述Μ 0 S電晶體之源極傅送至吸極之步驟* 68.—種差值输出方法，其特徴爲包括在第1電容 器之一端施加第1電壓，在上述第1電容器之另一端施加 箝位電荷之步驟：及在上述第1電容器之一端施加第2電 壓而將上述第1電壓與第2電壓之差值充電於一端直接連 接於上述第1電容器之另一端之第2電容器之步驟。 6 9 .如申請專利範圍第6 8項之方法，其中上述第 1電容器之一端連接於阻抗變換電路之輸出端子，上述第 1及第2電壓爲該阻抗變換電路之输出。 70.如申請專利範圍第67，68或69項之方法 ，其中上述第1及第2電壓中，一方係對應於射入固體攝 像元件之圖素中之入射光之输出電壓與從上述圖素中產生、 之固定圖型雜訊電壓之和，另一方係上述固定圖型雜訊。 ---------^------iT------^ - ™ (請先閱讀背面之注意事項V w寫本頁) 本紙張尺度遑用中國國家橾隼（CNS>A4規格（2丨0X297公釐）-207 -Printed by ABCD Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy 6. Scope of patent application 1. A kind of image system * which is characterized by including: an optical system that receives an optical image from a subject and guides the optical image to a certain position And an animal image processing device that photoelectrically changes the optical image guided to the above-mentioned certain position into a pixel unit photoelectrically into a detector corresponding to the light quantity of the above-mentioned optical image; and processes the output of the image processing device into a certain type and The output signal processing section, the detector includes: a photoelectric conversion element provided at the above-mentioned fixed position: contains an amplified MOS transistor connected to the photoelectric conversion element, and amplifies the output of the photoelectric conversion element at the first timing, An output circuit that outputs noise unrelated to the output of the photoelectric conversion element at the second timing; connected to the output end of the output circuit, the impedance observed from the output circuit at the first and second timings is equal, resulting in the above The noise removal circuit of the difference between the outputs of the above-mentioned output circuits at the first and second timings. 2. A picture system, which includes: an optical system that receives an optical image from a subject and guides the optical image to a certain position, and the optical image that is guided to the above-mentioned certain position is in pixel units A photo image processing device that changes the photoelectricity into a detector corresponding to the electrical signal of the optical image: and a signal processing section that processes the output of the image processing device into a certain type of output, the detector includes: The photoelectric conversion element set at the above-mentioned fixed position; contains the amplified MOS transistor connected to the photoelectric conversion element, amplifies and outputs the output of the photoelectric conversion element at the first timing, and outputs the photoelectric conversion element at the second timing The output circuit of the conversion element has nothing to do with noise; the signal line connected to the above output circuit: and a clamping capacitor with one end connected to the signal line • connected between the other end of the clamping capacitor and a certain potential Sample holding capacitor, and will be smaller than the size of this paper, suitable for China National Standard Falcon (CNS) A4 specification (210X297 mm) -189---------- ^ ------, 1T ------ 0 (please read the precautions on the back and write this page) 306G73 it C8 D8, the consumer consumer cooperative of the Central Falcon Bureau of the Ministry of Economic Affairs 々, the scope of patent application. A capacitance twice that of the series capacitance is selectively applied to the impedance correction circuit between the signal line and a certain potential, and generates noise at the difference between the output of the output circuit at the first and second timings Remove the circuit. 3. A picture system, which is characterized by including: an optical system that receives an optical image from a subject, guides the optical image to a certain position, and the optical image that is guided to the above-mentioned certain position is in pixel units An image processing device of a detector that changes photoelectricity into an electrical signal corresponding to the light quantity of the optical image: and a signal processing section that processes the output of the image processing device into a certain form of output, the detector includes: A photoelectric conversion element at a certain position; contains an amplified MOS transistor connected to the photoelectric conversion element, which amplifies the output of the photoelectric conversion element at the first timing and outputs it, and outputs the output of the photoelectric conversion element at the second timing An output circuit that outputs irrelevant noise; a signal line connected to the output end of the output circuit; an input follower connected to the source follower circuit of the signal line: one end connected to a clamp capacitor at the output end of the source follower circuit : Sample holding capacitor connected between the other end of the clamping capacitor and the first certain potential; and connected to the above clamping capacitor One end of the 2 - constant potential between the clamp in the sample holding clamp selective crystal capacitor. 4. A type of image system, which includes: an optical system that receives an optical image from a subject, guides the optical image to a certain position, and guides the optical image to a certain position The image processing device of the detector whose unit photoelectricity changes into the electrical signal corresponding to the light quantity of the above optical image: and the paper standard output by processing the output of the image processing device into a certain form is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) _ 190---------- 1 ------, order -------- ^ (please read the notes on the back first * · .. write this page), A8 B8 C8 D8 VI. Patent application signal processing section, the detector includes: the photoelectric conversion element set at the above-mentioned certain position; contains the amplified MOS transistor connected to the photoelectric conversion element, and amplifies the above at the first timing The output of the photoelectric conversion element and the output of the output circuit that outputs noise that is not related to the output of the photoelectric conversion element at the second timing; the signal line connected to the output end of the output circuit; one end connected to the signal line Clamp capacitor; connected A sample holding capacitor connected between the other end of the clamping capacitor and the first certain potential; and connected between the other end of the above clamping capacitor and the second fixed potential, clamping the sample holding at a certain timing Clamp transistor of capacitor. Printed by the Consumer Labor Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs (please read the precautions on the back to write this page) 5. A kind of image system, which is characterized by including: receiving an optical image from the subject, and twinning the light An optical system guided to a certain position, and an image processing device of a detector for photoelectrically converting the optical image guided to the certain position into electrical signals corresponding to the light quantity of the optical image in pixel units; and The output of the image processing device is processed into a certain shape and output to a signal processing section. The detector includes: outputting a voltage corresponding to noise and the light quantity at the first timing, and outputting a voltage corresponding to the noise at the second timing A pixel of voltage; consisting of a section 1 that accepts the output of the pixel, a section 2 that stores charge *, and a section 3 that receives a quantified charge from section 2 based on one of the potential controls of section 1 The 3-terminal element generates a noise removal circuit that generates the difference between the outputs of the pixels at the first and second timings. 6. A picture system, which is characterized by including: an optical system that receives an optical image from a subject, guides the optical image to a certain position, and the optical image that is guided to the above-mentioned certain position is in pixel units The photoelectric conversion is applied to the Chinese paper standard (CNS) A4 * Jl grid (210X297 mm) _ 191-Employee Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A8 B8 C8 D8 VI. The scope of patent application should be within the above optical image The image processing device of the detector of the electrical signal of the light quantity; the signal processing unit that processes the output of the image processing device into a certain form and outputs the above-mentioned detector includes: outputting the noise and the above-mentioned light quantity at the first timing The voltage corresponding to the voltage of the noise is output at the second timing; and the charge amount corresponding to the output voltage of the pixel at the first timing is matched with the output at the second timing A noise removal circuit for the difference in the amount of charge of the pixel's output voltage. 7. A kind of portrait system, which includes: an optical system that receives an optical image from a subject, guides the optical image to a certain position, and the optical image that is guided to the above-mentioned certain position is in pixel units An image processing device of a detector for photoelectric conversion into an electrical signal corresponding to the light quantity of the above optical image: a signal processing section that processes the output of the image processing device into a certain form and outputs it, the detector includes: at the first timing Output the first electrical signal corresponding to the noise and the above-mentioned light quantity, and output the pixels of the second electrical signal corresponding to the above-mentioned noise at the second timing; and input the above-mentioned first and second electrical signals with the same input impedance , Output the noise removal circuit of the difference between the first and second electrical signals. 8. A kind of image system * which is characterized by including: an optical system that receives an optical image from a subject, guides the optical image to a certain position, and the optical image that is guided to the above-mentioned certain position is in pixel units Image processing device and device of a detector for photoelectric conversion into an electrical signal corresponding to the light quantity of the optical image: and a signal processing unit that processes the output of the image processing device into a certain form and outputs the output of the image processing device The dynamic range is above 70 dB. The paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) -192---------- ^ ------, order ------ ^ (please read the back first Matters needing attention JS --_ write this page) A8 B8 C8 D8 ~, the patent application scope of the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Gas and Economy, such as the patent application scope of 1, 2, 3, 4, 5, 6, The system of item 7 or 8, wherein the output of the detector is an analog signal, and the image processing device further includes an A / D conversion circuit that converts the output of the detector into a digital signal, and controls the detector The timing signal of the operation is supplied to the timing signal generating circuit of the detector. 10. The system as claimed in item 9 of the patent application, wherein the power level of the above-mentioned timing signal is the same as the power level supplied to the above-mentioned detector. 1 1. For the system of patent application items 1, 2, 3, 4, 5, 6, 7 or 8, wherein the output of the above-mentioned detector is a voltage signal, and the above-mentioned image processing device further includes: accepting the above-mentioned detector The output voltage-current conversion circuit: the current-m voltage conversion circuit that receives the output of the voltage-current conversion circuit: an amplifier circuit that amplifies the output of the current-voltage conversion circuit to a gain corresponding to the required sensitivity; and clamp Clamp circuit that locates the output of the amplifier circuit. 1 2. The system as claimed in item 9 of the patent scope, wherein the output of the detector is a voltage signal, and the image processing circuit further includes: a voltage-current conversion circuit that receives the output of the detector; accepts the voltage-current A current-voltage conversion circuit of the output of the conversion circuit; an amplifier circuit that amplifies the output of the current-voltage conversion circuit to a gain corresponding to the required sensitivity; and clamping the output of the amplifier circuit to supply it to the A / D Clamp circuit of the conversion circuit. 1 3. For the system of patent application No. 1, 2, 3, 4, 5, 6, 7 or 8, wherein the signal processing part includes a process circuit that performs a certain process on the output of the image processing device, And the standard of this paper is applicable to the Chinese national standard (〇 邶) 8 4 format (210 \ 297 mm) _193_ --------- g ------, set ------ ^ (Please read the precautions on the back of this page first) β S06G7S _ ^ _ 6. The patent application scope The output of the circuit is converted into a composite video signal encoding circuit. 1 4. The system as claimed in items 1, 2, 3, 4, 5, 6, 7 or 8 of the patent application scope, wherein the above optical system includes: a lens for focusing the above optical image; Aperture adjustment device for the amount of incident light; a focal length adjustment device for adjusting the distance between the lens and the image processing device; and a color filter provided on the pixel "1 5. Such as the patent application No. 1, 2, 3, 4 , 5, 6, 7 or 8, wherein a number of the above image processing devices are provided in accordance with the wavelength of the optical image, the optical system includes: a lens that focuses the optical image: adjustment is made to enter the animal image processing device Aperture adjustment device for the amount of incident light; a focal length adjustment device for adjusting the distance between the lens and many of the image processing devices; and splitting the optical image focused by the lens into many optical images at a wavelength, and supplying the split optical images to many The spectroscopic device of the above image processing device. This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) _ 194---------- approved clothes ----- 1T ------ 0 (please read the back first Note_s,. ^ This page) 'everywhere-everywhere' 6 images, like 6 images 6 'Draw 6 Draw, Draw, 5 narration, narration 5 narration 5 ‘on 5 on’, 4 will, 4 will 4, yes · 4 yes, yes. ’3 Set, set. 3 Set 3, part 3 devices, part 2-2 billion, CTV 2 work brush 2, add 2 to add supervision, stamped, No. 1, No. 1 No. 1 No. 1 billion letter 1 signal The first letter, the first narration, the second essay, the engraving, the enveloping, the enclosing, the upper, the upper, the upper, the upper, the, the, and, Please, please apply for unification, please apply for unification, apply for unification, apply for unification, and apply for unification. Or install or install or install 7 Li 7 Li 7 Li The Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative Printed ABCD The Ministry of Economics Central Standards Agency Employee Consumer Cooperative Printed 6, the system of patent application 7 or 8 items, which also includes: acceptance The interface circuit output from the signal processing section; the signal bus receiving the output of the interface circuit; and the information processing device connected to the signal bus. 20. The system as claimed in item 9 of the patent scope, which also includes: a frame memory that records the output of the above A / D conversion circuit; and a compression device that compresses the signal that is recorded in the frame memory. 2 1 _ The system as claimed in item 20 of the patent scope, which also includes a memory device that records the output of the above-mentioned compression device. 22. A system as claimed in item 20 of the patent scope, which includes sub-contracting: an interface circuit that accepts the output of the above image compression device; and a signal bus that accepts the output of the interface circuit. 2 3_For example, the system of claim 1, 2, 3, 4, 5, 6, 7 or 8 includes a light source that irradiates light on the subject, and the signal processing section includes The output of the processing device prints a printing device corresponding to the image of the subject. The optical image is reflected light reflected by the light emitted from the light source irradiating the subject. 24. The system as claimed in item 23 of the patent scope, which also includes a mobile device that moves the above-mentioned subject relative to the above-mentioned light source · 25. As claimed in the patent application as item 1, 2, 3, 4, 5, 6, 7 Or the system of item 8, which further includes a light source that irradiates light from the subject, the signal processing unit includes a data converter that performs signal conversion to send the output of the image processing device to a telephone line, and the optical image is The light emitted from the light source reflects the reflected light on the subject. The size of this paper is remotely used by the Chinese National Standard (CNS> A4 specification (210X297mm) -195---------- I ------ 、 玎 ----- 1 ^ (please first Read the precautions on the back * 'write this page), the Ministry of Economic Affairs, Central Standard Falcon Bureau Employee Consumer Cooperative Immo A8 II' __D8 々, patent application scope 2 6. For example, the system of patent application item 25, which also includes the use of A mobile device for the relative movement of the above-mentioned subject and the above-mentioned light source. 27. The system as claimed in items 1, 2, 3, 4, 5, 6, 7 or 8 of the patent scope, which also includes: on the above-mentioned subject A light source irradiating light; a moving device that moves the subject relative to the light source: and a position detection device that detects the positional relationship between the subject and the light source, and the signal processing unit processes the output with the output of the position detection device The output of the image processing device, the optical image is the reflected light reflected by the light emitted from the light source shining on the subject. 28. As claimed in the patent application No. 1, 2, 3, 4, 5, 6, 7 or The system of item 8, wherein the above optical system includes A lens moved by the device is located at a certain distance from the lens on the detector side, splits the light 2 of the lens from the lens into the light in a certain direction and supplies it to a pair of separation lenses of the detector • The signal processing part Detects the distance between the focal positions of the light divided by 2 that passes through the separation lens, and generates a signal to drive the mobile device based on the detection result. 29. As claimed in patent application No. 1, 2, 3, 4, 5, 6, 7 Or the system of item 8, which further includes a light source that irradiates light on the above-mentioned subject, the subject is a thin film of a photographed image provided between the light source and the detector * 3 0. — A kind of solid-state imaging device , Which is characterized by including: a photoelectric conversion element; containing an amplified MOS transistor connected to the photoelectric conversion element, amplifying the output of the photoelectric conversion element at the first timing and outputting it, and outputting the output at the second timing and the above The output of the photoelectric conversion element has nothing to do with the miscellaneous paper standard Universal Chinese National Standard (CNS) A4 specification (210X297mm U 196-(Please read the notes on the back first This page)-installed. A8 B8 C8 D8 printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 6. The output circuit of the patent application range; and the output terminal connected to the output circuit, from the first and second timings above The impedance observed by the output circuit at the same time is equal, and a noise removal circuit that generates the difference between the output of the output circuit at the first timing and the second timing is generated. 3 1. The device as claimed in item 30 of the patent scope * It also includes a signal line connecting the output circuit and the noise removal circuit. 3 2. The device as claimed in item 31 of the patent application, wherein the noise removal circuit includes: a clamping capacitor connected at one end to the signal line: connected Between the other end of the clamping capacitor and the clamping potential • A clamping transistor that selectively becomes conductive; a sample holding capacitor connected between the other end of the above clamping capacitor and a certain potential; and connected to the above signal Impedance correction circuit between the line and a certain potential · 3 3. The device as claimed in item 32 of the patent application scope, in which the above-mentioned impedance correction circuit includes: When the clamp transistor becomes non-conducting, it selectively turns on the switching element; and a correction capacitor connected in series with the switch and having a capacitance equal to the series capacitance of the clamp capacitor and the sample holding capacitor. 34. The device of claim 31, wherein the noise removal circuit has an impedance conversion circuit connected to the signal line, and the impedance observed from the output circuit is the input impedance of the impedance conversion circuit. 3 5. The device as claimed in item 34 of the patent application, wherein the resistance and impedance conversion circuit has a gate connected to the signal line, a source connected to an input MOS transistor of a certain potential, and connected to the second MOS The load between the sink of the transistor and the power supply potential. The paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) _ 197 _ --------- ^ ------, order ------ 0 (please read the back first Note 1, this page) (A8 B8 C8 D8 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. Scope of patent application 3 6 · If the device of patent application item 3 1 is included, the above noise removal circuit has The gate is connected to the limiting transistor of the signal line, and the impedance observed from the output circuit is the gate capacitance of the limiting transistor. 37. The device as claimed in item 36 of the patent application, wherein the noise removal circuit Also includes: a limiting capacitor connected between the source of the above-mentioned limiting transistor and a supply terminal of the limiting pulse wave; and a connection between the sink of the above-mentioned limiting transistor and a certain potential to charge the difference Limiting capacitors. 3 8. A solid-state imaging device * characterized by including: a photoelectric conversion element; including an amplified MOS transistor connected to the photoelectric conversion element, which amplifies the photoelectric conversion element at the first timing Output and output it at the second timing An output circuit that outputs noise that has nothing to do with the output of the photoelectric conversion element: a signal line connected to the output circuit; a capacitance of a clamp capacitor connected to the signal line at one end is connected to the other end of the clamp capacitor The capacitance setting of the sample holding capacitor with a certain potential, and the capacitance less than 2 times the difference between the series capacitance of the clamping capacitor and the capacitance of the sample holding capacitor and the capacitance setting of the clamping capacitor An impedance correction circuit that is selectively applied between the signal line and a certain potential; and a noise removal circuit that generates a difference in the output of the output circuit at the first and second timings. 3 9 solid-state imaging devices , Characterized by: photoelectric conversion, element: contains an amplified MOS transistor connected to the photoelectric conversion element, the output of the light pen conversion element is amplified and output at the first timing, and the output at the second timing is the same as the above The output of the photoelectric conversion element has nothing to do with the noise. The paper standard is applicable to the national standard (CNS) A4 specification (210X297 mm _ J98 - --------- g ------, ------ set to 0 (please read the Notes on the back - &, ½ page.) < A8 B8 C8 · D8 ^, patent-applicable output circuit: signal line connected to the output end of the output circuit: input end connected to the source follower circuit of the signal line: one end connected to the source follower circuit Clamp capacitor at the output; sample holding capacitor connected between the other end of the clamp capacitor and the first certain potential; and between the other end of the clamp capacitor and the second fixed potential, selective Clamp the clamp transistor of the above sample holding capacitor. 40. The device as claimed in item 39 of the patent scope, wherein the neutral capacitor and the above sample holding capacitor overlap on the same substrate. 4 1. A solid-state imaging device, which includes: an optical element; including an amplified MOS connected to the photoelectric conversion element, which amplifies the output of the photoelectric conversion element at the first timing and outputs it at the second timing An output circuit independent of the output of the photoelectric conversion element; a signal terminal connected to the output terminal of the output circuit is connected to a clamping capacitor of the signal line; an electric conversion crystal connected to the clamping plane of the clamp, outputs, The miscellaneous line of the container; please read the precautions of the first container for the container I. Order the sample holding capacitor between the other end and the first certain potential: and connect the other end of the above clamping capacitor and the second-constant potential During a certain period of time, the clamping transistor of the above sample holding capacitor is clamped. 4 2. A solid-state imaging device, which is characterized in that it outputs the voltage of complex and incident light at the first timing, at the second timing The pixel of the output voltage matching the above noise; contains the first section that has the output to accept the imaginary, the second section that stores the charge, and the second section accepts the charge According to the potential control of the first section of the first section, the three-terminal element of the third section of the quantitative charge, the difference between the output of the above pixels at the first and second timings (CNS) A4 specification (2 丨 0X297 mm) _ 199-Line printed by the Ministry of Economic Affairs Central Standards Bureau employee consumer cooperatives printed by the Ministry of Economics Central Standards Bureau employee consumer cooperatives A8 B8 C8 · D8 Six, apply for patent scope information removal circuit. 43. The device as claimed in item 42 of the patent scope, wherein the above-mentioned 3 terminal element uses the above-mentioned section 1 as the gate, and the above-mentioned section 2 as the source • The above-mentioned section 3 serves as the MOSFET Crystal. 4 4. A kind of solid-state imaging device, the characteristics of which include: outputting voltages matching noise and incident light at the first timing, and outputting voltages matching the noise at the second timing; and output matching at the above The noise removal circuit for the difference between the charge amount of the output voltage of the pixel at the first timing and the amount of charge matched to the output voltage of the pixel at the second timing. 4 5 ·-A solid-state imaging device, the characteristics of which include: outputting the first electrical signal in conjunction with noise and incident light at the first timing * outputting the second electrical signal in conjunction with the above noise at the second timing ; And a noise removal circuit that inputs the first and second electrical signals with the same input impedance and outputs the difference between the first and second electrical signals. 4 6. A kind of solid-state imaging device, the characteristics of which include: many horizontal selection lines: many vertical signal lines crossing the above horizontal selection lines: set at the crossing positions of the above horizontal selection lines and the above vertical signal lines, matching the above horizontal The potential of the selection line is selectively activated, and the first electrical signal in accordance with noise and incident light is supplied to the corresponding vertical signal line at the first timing in the activation period, and the second timing in the activation period When the second electrical signal matching the above noise is supplied to the corresponding vertical signals, many pixels of the signal line; and are provided at each end of the vertical signal lines, and input the first and second electrical signals with the same impedance The signal outputs many noise removing circuits of the difference between the first and second electrical signals. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) _ goo _ --------- ^ ------, order ------ 0 (please read the back first Note 1:% this page) 1. ABCD Ministry of Economic Affairs t Central Standards Bureau Employee Consumer Cooperative Printed 々, patent application scope 4 7-a solid-state camera device, which is characterized by including: many level selection lines: the level selection above A number of vertical signal lines crossing the line; set at the intersections of the horizontal selection line and the vertical signal line, in accordance with the potential of the horizontal selection line to become selectively activated, the first time sequence within the activation period will match The first electrical signal of the signal and incident light is supplied to the corresponding vertical signal line, and the second electrical signal in conjunction with the noise is supplied to many pixels of the corresponding vertical signal line at the second timing within the activation period ; And Section 3, which has a section 1 connected to each end of the above-mentioned many vertical signal lines, a section 2 that stores charge, and a section 3 that receives a certain charge according to the potential control of the section 1 above from section 2 3 terminal components, produced in Many noise removal circuits for the difference between the output of the pixels at the first and second timings. 4 8. A kind of solid-state imaging device, its special emblem includes: many horizontal selection lines: many vertical signal lines crossing the above horizontal selection lines: set at the crossing positions of the above horizontal selection lines and the above vertical signal lines * The potential of the horizontal selection line becomes activated selectively. At the first timing in the above activation period, the first power with noise and incident light shall be output to the corresponding vertical signal line, and the second in the above activation period. At the time of timing, the second voltage corresponding to the noise will be output to many pixels of the corresponding vertical signal line: and provided at each end of the vertical signal lines, and the charge amount matching the first voltage and the second Many noise removal circuits for the amount of charge and the difference of voltage. 4 9. A solid-state imaging device, the special withdrawal of which includes many horizontal selection lines: a number of vertical signal lines crossing the above horizontal selection lines; set at the size of this paper, applicable to the National Standards (CNS) A4 (210X297) Mm) -201-^-(please read the notes on the back first, and write this page). Ordered by the Central Standard Falcon Bureau of the Ministry of Economic Affairs, the consumer cooperation du printed A8? 88. D8 6. The scope of patent application The above horizontal selection line Each intersection position with the vertical signal line is selectively activated in accordance with the potential of the horizontal selection line, and at the first timing in the activation period, the first electrical signal with noise and incident light is output to the corresponding The vertical signal line, at the second timing within the activation period, will output the second electrical signal in accordance with the noise to many pixels corresponding to the vertical signal: and have many connected to each end of the vertical signal lines Clamping capacitors, many sample holding capacitors connected between the other ends of many clamping capacitors and the first certain potential, and connected to the above many clamping electric The other end of each of the devices and 2 - between the constant potential, with a timed sequence corresponding to the above samples of the clamp capacitor maintaining many noise many crystals of clamp transistor is removed. 50. The device as claimed in items 46, 47, 48 * or 49 of the patent application group, which further includes: a first shift transistor that sequentially activates the above-mentioned many horizontal selection lines selectively; an output terminal; one end is connected to the above The output terminals of many noise removal circuits, the other end of which is commonly connected to the many conversion elements of the output terminals: and sequentially outputs the second shift transistors that control signals that make the many conversion elements selectively conductive. 51. Such as The device of claim 46, 47, 48 or 49, which also includes: output terminal: one end is connected to each output end of the above many noise removal circuits, and the other end is commonly connected to many conversion elements of the above output end; input The address terminal of the address signal; and decoding the above address and signal, and selectively activating the many horizontal selection lines according to the result, and outputting the address of the control signal that selectively turns the many conversion elements on decoder. This paper uses the Chinese National Standard (CNS) A4 specification (210X297 mm) _ 202---------- 1 ------, order ------ 0 (please read first Notes on the back * '·-. Write this page) "A8 B8 C8 D8 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs VI. Patent application scope 5 2 · For example, the device applying for patent scope item 50, which includes : A timing generator for generating timing signals for driving the first and second shift registers; and a digital-to-digital (A / D) conversion circuit in which the input terminal is combined with the output terminal. 5 3. The device as claimed in item 51 of the patent scope, which further includes an A / D conversion circuit whose input terminal is connected to the above-mentioned output terminal. 54. The device according to item 53 of the patent application scope, which further includes an analog amplifying circuit that amplifies the signal of the output terminal and supplies it to the input end of the A / D conversion circuit. 5 5. The device as claimed in item 52 of the patent scope, which further includes an analog amplifying circuit that amplifies the signal of the output terminal and supplies it to the input terminal of the A / D conversion circuit. 5 6 ·-A solid-state imaging device, the characteristics of which include: a number of vertical signal lines; respectively corresponding to the setting of a number of vertical signal lines, the first electrical signal with noise and incident light is supplied to the corresponding above at the first timing The vertical signal, at the second timing, supplies the second electrical signal matching the noise to the many pixels of the corresponding vertical signal line; and is provided at each end of the many vertical signals and inputs the first signal with the same impedance And the second electrical signal, outputting a lot of noise removal circuits for the difference between the first and second electrical signals. 5 7 · A solid-state imaging device, which is characterized by including: many vertical and signal lines; respectively corresponding to the setting of many vertical signal lines, and supplying the first electrical signal with noise and incident light to the corresponding at the first timing The above vertical signal line will be used in conjunction with the second electrical signal of the above noise at the second timing. The paper standard uses the Chinese National Standard (CNS) A4 specification (210X297mm) _ 2〇3 _ ^ — (please read the back first Notes 1 .: ¾¾ This page) Booking-A8 B8 C8 D8 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. The range of patent applications for many pixels of the above vertical signal lines: The first section of each end of the vertical signal line * the second section of the stored charge, the third section of the 3 terminal element that receives a fixed amount of charge according to one of the potential control of the above section 1 from the second section, generated in the above section Many noise removal circuits for the difference between the output of the above pixels at the 1st and 2nd timings. 58. A kind of solid-state imaging device, the characteristics of which include: many vertical signal lines; respectively corresponding to the setting of many vertical signal lines, and supplying the first voltage corresponding to noise and incident light to the corresponding vertical above at the first timing The signal line * supplies the second voltage corresponding to the noise to one end of the corresponding vertical signal line at the second timing, resulting in a lot of difference between the charge amount matching the first voltage and the charge amount matching the second voltage Noise removal circuit. 5 9. A kind of solid-state imaging device, which is characterized by including: many vertical signal lines; respectively corresponding to the setting of many vertical signal lines, and supplying the first electrical signal with noise and incident light to the corresponding above at the first timing Vertical signal, at the second timing, the second electrical signal matching the noise is supplied to many pixels of the corresponding vertical signal line; and many clamping capacitors connected to each end of the many vertical signal lines are connected at Many sample holding capacitors between each other end of many clamping capacitors and the first certain potential, and the other samples connected between each other end of the above many clamping capacitors and the second certain potential, which will correspond to the above samples at a certain timing Many clamp transistors that hold capacitors and clamps. 60. A kind of solid-state imaging device, the characteristics of which include: a number of horizontal selection lines; vertical signal lines crossing the horizontal selection line: set at the above water-based paper scale, applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm ) _ 204-^-(please read the precautions I on the back first, 舄 this page) Stranding A8 B8 C8 β _ D8 ^, please read the precautions written before applying for the patent scope Each intersection of the line and the vertical signal line is selectively activated in accordance with the potential of the horizontal selection line, and at the first timing within the activation period, the first electrical signal with noise and incident light is supplied to the vertical The signal line, at the second timing in the activation period, will supply the second electrical signal in conjunction with the noise to many pixels of the vertical signal line; and is provided at one end of the vertical signal line * with the same input impedance The first and second electrical signals described above generate a noise removal circuit that generates the difference between the first and second electrical signals. 6 A solid-state imaging device characterized by including: many levels Line selection line printed by Beigong Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs: vertical signal line crossing the horizontal selection line: set at the intersection of the horizontal selection line and the vertical signal line, matching the potential of the horizontal selection line Selectively becomes activated, and the first electrical signal with noise and incident light is supplied to the vertical signal line at the first timing in the activation period, and the noise at the second timing in the activation period The second electrical signal is supplied to many pixels of the above vertical signal line: and includes a first section connected to one end of the vertical signal line, a second section storing charge, and receiving from the second section according to the first section above The three-terminal element of the third section of a certain amount of charge is controlled by the potential of the section, which generates the difference in the output of the pixels at the first and second timings. 6 2. A kind of solid-state imaging device, the characteristics of which include: a number of horizontal selection lines; vertical signal lines crossing the horizontal selection line; set at the intersection of the horizontal selection line and the vertical signal line, matching the horizontal The potential of the selection line is selectively activated, and at the first timing in the activation period, the first voltage of noise and incident light will be supplied to the above vertical paper size. The Chinese National Standard (CNS) A4 specification (210X297 %) _ 205-A8 B8 C8 D8 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. The patent-appropriate signal line will supply the second voltage of the above noise to the above-mentioned vertical at the second timing within the above activation period Many pixels of the signal line; and provided at one end of the vertical signal line, a noise removal circuit that generates a difference between the charge amount matching the first voltage and the charge amount matching the second voltage. 6 3. A solid-state imaging device, which is characterized by including: a number of horizontal selection lines; vertical signal lines crossing the above horizontal selection lines: set at the crossing positions of the above horizontal selection lines and the above vertical signal lines, in cooperation with the above horizontal selection The potential of the line is selectively activated, and the first electrical signal in accordance with noise and incident light is supplied to the vertical signal line at the first timing in the activation period, and is coordinated at the second timing in the activation period The second electrical signal of the noise is supplied to many pixels of the vertical signal line; and a clamping capacitor connected to one end of the vertical signal line is connected between the other end of the clamping capacitor and the first certain potential The sample holding capacitor, and the noise removal circuit of the clamping transistor that is connected between the other end of the above clamping capacitor and the second fixed potential at a certain timing to clamp the above sample holding capacitor A semiconductor mortar circuit, the characteristics of which include: a semiconductor substrate; the patent application scope formed on the semiconductor substrate is in the range of 46 to 63 One of said solid state imaging device; and is formed on the solid-state imaging device, a light shielding film having a plurality of openings corresponding to said plurality of picture element. 65. The circuit as claimed in item 64 of the patent scope, which also includes a color filter selectively formed on the opening. 66. For example, the circuit of the patent application group 64, which also includes the paper standard applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm> _ 206---------- ^ --- ---, 玎 ------ ^ (please read the notes on the back ®-.% 'First page) A8 B8 C8 .D8々, patent scope A microlens formed on the above opening. 6 7. A method of outputting the difference signal, which includes the steps of: applying the first voltage to the gate of the MOS transistor; The step of resetting the charge in the capacitor of the source of the crystal; the step of applying a first pulse wave to the other end of the capacitor to discharge a certain charge from the source of the MOS transistor through the sink; The step of applying the second voltage to the gate of the crystal; and applying a second pulse wave with an amplitude equal to the amplitude of the first pulse wave to the other end of the capacitor, which will be equivalent to the difference between the first voltage and the second voltage Steps for the charge to be sent from the source electrode of the above MOS transistor to the sink electrode * 68.—The difference output method The method includes the steps of applying a first voltage to one end of the first capacitor and applying a clamping charge to the other end of the first capacitor: and applying a second voltage to one end of the first capacitor to apply the first voltage The step of charging the difference between the second voltage and one end directly connected to the second capacitor at the other end of the first capacitor. 6 9. The method as claimed in item 68 of the patent application, wherein one end of the first capacitor is connected to The output terminal of the impedance conversion circuit, the above-mentioned first and second voltages are the output of the impedance conversion circuit. 70. The method of claim 67, 68 or 69, wherein one of the first and second voltages is The sum of the output voltage corresponding to the incident light incident on the pixels of the solid-state imaging element and the fixed pattern noise voltage generated from the above pixels, the other is the above fixed pattern noise. ----- ---- ^ ------ iT ------ ^-™ (Please read the precautions on the back V w to write this page first) This paper uses the Chinese National Falcon (CNS> A4 specifications) 2 丨 0X297mm) -207-
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