TW306037B - - Google Patents
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- TW306037B TW306037B TW085112080A TW85112080A TW306037B TW 306037 B TW306037 B TW 306037B TW 085112080 A TW085112080 A TW 085112080A TW 85112080 A TW85112080 A TW 85112080A TW 306037 B TW306037 B TW 306037B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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Description
Α7 Β7 306037 五、發明説明（i ) 發明背景 1 ·發明領域 本發明係關於一種半導體裝置，且更特別而言，係關 於一種具有電容之半導體裝置，該電容含有由具有鈣鈦礦 結晶結構之金屬氧化物製成之介電膜，和關於半導體裝置 之製造方法· 請 先 閲 讀 背 之 注 意 2 相關技藝 半導體記 展已快速的進 之說明 憶裝置當成記憶 行中•典型的半 D R A Μ (動態隨機存取讀寫 裝置以用於資訊處理器之發 導體記憶裝置之例爲 記憶），其使用由一電晶體 項 填 寫 本 頁 經濟部中央標準局員工消费合作社印装 電容構成之一記憶胞 藉由增加 類之半導體裝 億裝置之效能 憶裝置之例中 避免由於記億 在習知技 或一氧化矽膜 單位面稹之電 符合，因此必 之材料· 有蜜於上 ，鋇鈦鐵礦或 整合， 置之例 之改善 ，需要 資訊之 藝中， 使用當 容之電 窬使用 亦即藉由 中，可達 。但是， 使記憶胞 損毀而引 含有氧化 成一電容 容值以和 具有比氧 使記憶胞 成例如D 在例如D 小型化， 起可靠度 矽膜和氮 介電膜》 未來在記 化矽或氮 小型化，在 R A Μ之半 R A Μ之半 並保持電容 之降低· 化矽膜之一 但是，爲了 憶胞之增加 化矽更髙介 其它種 導體記 導體記 值，以 置層膜 增加每 縮小化 電常數 述之構造，現今研究使用一具有如緦鈦鐵礦 Ρ Ζ Τ之鈣鈦礦結晶構造之鐵電材料*其介 本紙張尺度逍用中國國家標準（CNS ) Α4規格（210X297公釐） 4 經濟部中央標隼局貝工消费合作社印製 A7 _B7_ 五、發明説明（2 ) 電常數高於氫化矽50至1000倍。 但是*由具有例如鈣鈦礦結晶構造之嫌電材料所形成 之一電容介電膜會伴隨之問題爲：當膜厚度較薄時，介電 常數亦會降低。膜之介電常數之降低可能是因爲在膜中之 結晶結構之無序，缺陷或應變而造成的》 可能會因爲各種理由而引起一電場（門電場）產生在 —電容介電膜中。但是當使用上述之嫌電材料時，如果產 生在電容介電膜中之內電場較高時，會造成介電膜之介電 常數降低之問題· 亦需考慮的是，內電場不只會由在電容介電膜中之固 定電荷或陷波電荷所引起，且亦會由在膜中之結晶構造之 無序，缺陷，或應變而引起。 如果電容介電膜之介電常數以此方式降低時，會引起 之問題爲：由於在電容中累稹電荷之損失而會使半導體記 憶裝置之可靠度顯著的破壞。 再者，如果在此種鐵電膜中之氧之原子比例下降至落 在其化學計量比例之外時，極易產生漏電流。因此，當進 —步使介電膜變薄以增加電容時，當成介電膜之膜之功能 會顯著的破壞，因此會破壤所得半導體記憶裝置之可靠度 〇 此外，由於此種鐵電膜之禁止帶通常相當窄，當施加 電壓時，可輕易的產生大漏電流•爲了避免此種現象•如 果進一步使介電膜變薄以增加電容時，當成介電膜之膜之 功能會顯著的破壞，因此會破壞所得半導《記憶裝置之可 本紙張尺度適用中國國家標準（CNS)A4规格（ 210X297公釐）_ 5 _ ---：----^—^-- (請先閱讀背面之注意事項再填寫本頁) 訂Α7 Β7 306037 5. Description of the invention (i) Background of the invention 1 · Field of the invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a capacitor, the capacitor contains a crystal structure having a perovskite Dielectric film made of metal oxide, and about the manufacturing method of the semiconductor device · Please read the back notes first. 2 Related Skills The semiconductor exhibition has been quickly introduced. The memory device is regarded as a memory line. • Typical semi-DRA Μ (dynamic The random access read-write device uses the example of a memory conductor device used as an information processor for memory), which uses a transistor to fill in this page. This is a memory cell composed of printed capacitors printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. In the example of increasing the efficiency of a semiconductor-equipped device with 100 million yuan, it is avoided that the energy of the billion yuan is in accordance with the conventional technology or the unit surface of the silicon monoxide film, so the necessary materials are honey, barium ilmenite or Integration, the improvement of the example of placement, in the art that requires informationHowever, damage to the memory cell leads to oxidation to a capacitance value and to have specific oxygen to make the memory cell into, for example, D. Miniaturization of, for example, D, reliability and silicon film and nitrogen dielectric film. In the half of RA Μ, half of RA Μ and keep the reduction of capacitance. One of the silicon film. However, in order to increase the memory cell, the silicon is more sensitive to other types of conductors. The value of the conductor is recorded. For the structure described by the electric constant, a ferroelectric material with a perovskite crystalline structure such as 缌 il 鐌 鳌 P Ｍ Ｍ Ｍ Ｍ Ｍ ＭＯＭ ＭＡＭ ＭＡＭ 4. 4 A7 _B7_ printed by the Beigong Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) The electrical constant is 50 to 1000 times higher than that of hydride silicon. However, the problem associated with a capacitive dielectric film formed of a suspected dielectric material having, for example, a perovskite crystal structure is that when the film thickness is thin, the dielectric constant also decreases. The decrease in the dielectric constant of the film may be due to the disorder, defects or strain of the crystalline structure in the film. It may cause an electric field (gate electric field) in the capacitor dielectric film for various reasons. However, when using the above-mentioned susceptible materials, if the internal electric field generated in the capacitor dielectric film is high, it will cause the problem of lowering the dielectric constant of the dielectric film. It should also be considered that the internal electric field is not only caused by The fixed charge or trapped charge in the capacitor dielectric film is also caused by disorder, defects, or strain of the crystalline structure in the film. If the dielectric constant of the capacitor dielectric film is lowered in this way, the problem may be that the reliability of the semiconductor memory device may be significantly damaged due to the accumulated charge loss in the capacitor. Furthermore, if the atomic ratio of oxygen in such a ferroelectric film falls below its stoichiometric ratio, leakage current is likely to occur. Therefore, when the dielectric film is further thinned to increase the capacitance, the function of the film as the dielectric film will be significantly damaged, so the reliability of the resulting semiconductor memory device will be broken. In addition, due to this ferroelectric film The forbidden band is usually quite narrow, and a large leakage current can be easily generated when a voltage is applied. • To avoid this phenomenon. If the dielectric film is further thinned to increase the capacitance, the function of the film as a dielectric film will be significant Destruction, therefore it will destroy the semi-conducting "Paper Standard of Memory Device Applicable to China National Standard (CNS) A4 Specification (210X297mm) _ 5 _ ---: ---- ^-^-(please read first Note on the back then fill out this page)
T 經濟部中央標準局負工消費合作社印製 A7 ___________B7____ 五、發明説明（3 ) 靠度。 如上所述，現今研究進一步使D RAM之記憶胞小型 化，以使用具有鈣鈦礦結晶結構之鐵電材料當成用於電容 介電膜之材料· 但是，由於以具有鈣鈦礦結晶構造之鐵電材料所形成 之一電容介電膜會因爲膜之厚度變薄而展現在介電常數上 之降低，在電容上之累稹電荷亦會降低，因此會顯著的破 壤半導體記憶裝置之可靠度。 再者，在此種鐵電膜中，因爲在膜中氧的數量傾向於 落在介電材料之化學計量比例之外，且由於介電膜在禁止 帶中相當窄，因此極易產生漏電流•因此，當介電膜進一 步變薄時，當成介電材料之膜之功能會受到顯著的破壞， 因此，會破壞所得半導體記憶裝置之可靠度。 發明概要 因此，本發明之一目的乃在提供一種半導體裝置，其 具有一電容，該電容包含一電容介電膜，其不只可抑制介 電常數之下降，且即使介電膜極薄時，亦可抑制漏電流之 產生。 本發明之另一目的乃在提供一種製造如上述半導體裝 置之方法。 亦即，依照本發明，於此提供一種半導體裝置，包含 :一半導體基底：和一電容形成在半導體基底上：其中該 電容包括一下電極，形成在下電極上之一介電膜，和形成 本紙張尺度適用中國國家揉準（CNS ) A4况格（210X297公釐) ~ ' (請先閱讀背面之注意事項令填寫本頁) 裝· 訂 旅 A7 B7 經濟部中央橾準局貝工消費合作社印装 五、發明説明（4 ) 在介電膜上之一上電極；該介電膜之厚度爲1 〇 〇 nm或 更小，且主要由具有一 A B 03型鈣鈦礦結晶結構之金靥 氧化物構成（其中A爲選自含有S r ，B a，和C a所組 成之群之至少一金屬離子，和B爲Ti離子），並含有選 自由F e ，Μη和C 〇所構成之群之至少一元索。 依照本發明，於此進一步提供一種動態隨機存取記億 裝置，包含：一半導體基底，一 MO S電晶髋形成在該半 導體基底上；和一電容形成在半導體基底上；該記憶裝置 之一記憶胞由MO S電晶體和該電容所構成；其中該電容 包括一下電極，形成在下電極上之一介電膜，和形成在介 電膜上之一上電極；該介電膜之厚度爲1 0 0 nm或更小 ，且主要由具有一A B 03型鈣鈦礦結晶結構之金屬氧化 物構成（其中A爲選自含有Sr，Ba，和Ca所組成之 群之至少一金屬離子，和B爲Ti離子），並含有選自由 F e ，Μη和C 〇所構成之群之至少一元素。 依照本發明，於此進一步提供一種半導體裝置之製造 方法，包含之步驟爲：形成一下電極在一半導體基底上； 形成一介電膜在該下電極上，該介電膜之厚度爲1 0 0 nm或更小，且主要由具有一 ΑΒ03型鈣鈦礦結晶結構 之金靥氧化物構成（其中Α爲選自含有S r ，B a ，和 C a所組成之群之至少一金屬離子，和B爲Ti離子）： 塗覆含有選自由Fe，Μη，和Co所構成之群之至少一 元素之溶液在該介電膜之一表面上：對塗覆以選自由F e ，Μη和C 〇所構成之群之至少一元索之介電膜做熱處理 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐) Ζ (請先閲讀背面之注|事項再填寫本頁) .裝- -訂 旅 五、 發明説明 :5 ) 藉以 擴 散 該 至少 一 元 素 至 該 介 電 膜 > 和 形 成 — 上 電 極 在 該 介電 膜 上 贅 藉以 形 成 含 有 下 電 極 介 電 膜 » 和 該 上 電 極 之 -*電 容 0 依 照 本 發 明， 於 此 提 供 一 種 半 導 體 裝 置 之 製 造 方 法 9 包 含之 步 驟 爲 :形 成 — 下 電 極 在 -- 半 導 體 基 底 上 以 C V D 法 或 濺 鏟法 形 成 一 介 電 膜 在 該 下 電 極 上 » 該 介 電 膜 之 厚度 爲 1 0 On m 或 更 小 I 且 主 要 由 具 有 一 A B 0 3型 鈣 鈦磺 結 晶 結 構之 金 靥 氧 化 物 構 成 ( 其 中 A 爲 選 白 含有 S r » B a t 和C a 所 組 成 之 群 之 至 少 — 金 靥 離 子 和 B 爲 T i 離 子 ) ，並 含 有 選 白 由 F e Μ η 和 C 0 所 構 成 之 群 之至 少 — 元 素； 和 形 成 一 上 電 極 在 該 介 電 膜 上 藉 以 形 成 含有 下 電 極 ，介 電 膜 和 該 上 電 極 之 一 電 容 9 本 發 明 之 其它 巨 的 和 優 點 將於 下 述 之 說 明 中 說 明 其 中 一部 份 可 由 說明 中 得知 而 其 它 部 份 可 由 實 施 本 發 明 而 得 知。 本 發 明 之目 的 和 優 點 可 由 特 別 在 串 請 專 利 範 圔 中 指 出 之設 施 及 其 結合 而 實 現 .〇 圄 式簡 單說 明 下 述 之 圖 式， 其 設 置 在 說 明 窨 中 且 構 成 說 明 睿 之 一 部 份 ，揭 示 了 本 發明 之 現 有 較 佳 實 施 例 » 其 結 合 上 述 之 —► 段 說 明和 下 述 較 佳實 施 例 之 詳 細 說 明 » 共 同 用 以 解 說 本 發 明 之 原理 〇 圖 1 爲 介於鈣鈦 礦 介 電 膜 之 膜 厚 度 和 鈣 鈦 礦 介 電 膜 之 介 電常 數 間 之 關係 圔 • 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X29•/公漦） 經濟部中央標準局員工消费合作社印製 ^〇6〇37 A7 B7 五、發明説明（6 ) 圓2爲電容之C-V特性圖，其中顯示本發明之效果 t 圖3爲以SIMS量測在（Ba ，Sr) Ti03中 之F e之輪廓圓； 圖4 A至4 D分別顯示依照本發明之第一實施例之 DRAM胞之製造步驟之橫截面圖； 圖5 A至5 D分別顯示依照本發明之第二實施例之 DRAM胞之製造步驟之橫截面圖： 圖6 A至6 D分別顯示依照本發明之第三實施例之 DRAM胞之製造步驟之橫截面圄；和 圖7 A至7 E分別顯示依照本發明之第四實施例之 DRAM胞之製造步驟之橫截面圖： 較佳實施例之詳細說明 依照本發明之半導體裝置之特撤在於一電容，其包含 一介電膜之厚度爲1 0 0 nm或更小，且主要由具有T Printed by the National Bureau of Standards, Ministry of Economic Affairs, Negative Work Consumer Cooperative A7 ___________B7____ 5. Description of invention (3) Reliability. As mentioned above, current research has further miniaturized the memory cells of D RAM to use ferroelectric materials with a perovskite crystal structure as materials for capacitor dielectric films. However, due to the iron with a perovskite crystal structure A capacitor dielectric film formed by electrical materials will show a decrease in dielectric constant due to the thinner film thickness, and the accumulated charge on the capacitor will also be reduced, thus significantly deteriorating the reliability of semiconductor memory devices . Furthermore, in this type of ferroelectric film, because the amount of oxygen in the film tends to fall outside the stoichiometric ratio of the dielectric material, and because the dielectric film is quite narrow in the forbidden band, it is very easy to produce leakage current • Therefore, when the dielectric film is further thinned, the function of the film as a dielectric material will be significantly damaged, and therefore, the reliability of the resulting semiconductor memory device will be damaged. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device having a capacitor including a capacitor dielectric film, which not only suppresses the decrease in dielectric constant, but even when the dielectric film is extremely thin It can suppress the leakage current. Another object of the present invention is to provide a method of manufacturing the semiconductor device as described above. That is, according to the present invention, there is provided a semiconductor device including: a semiconductor substrate: and a capacitor formed on the semiconductor substrate: wherein the capacitor includes a lower electrode, a dielectric film formed on the lower electrode, and forming the paper Standards apply to China National Standard (CNS) A4 (210X297mm) ~ '(Please read the precautions on the back to fill out this page) Pack · Book Travel A7 B7 Printed by the Central Bureau of Economics, Ministry of Economic Affairs, Beigong Consumer Cooperative 5. Description of the invention (4) One of the upper electrodes on the dielectric film; the thickness of the dielectric film is 100 nm or less, and it is mainly composed of gold-titanium oxide with an AB 03 type perovskite crystal structure Composition (where A is at least one metal ion selected from the group consisting of S r, Ba, and Ca, and B is Ti ion), and contains a group selected from the group consisting of F e, Mn, and C 〇 At least one yuan. According to the present invention, there is further provided a dynamic random access billion memory device, comprising: a semiconductor substrate, a MOS transistor hip is formed on the semiconductor substrate; and a capacitor is formed on the semiconductor substrate; one of the memory devices The memory cell is composed of a MOS transistor and the capacitor; wherein the capacitor includes a lower electrode, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film; the thickness of the dielectric film is 1 0 nm or less, and mainly composed of a metal oxide having an AB 03 type perovskite crystal structure (where A is at least one metal ion selected from the group consisting of Sr, Ba, and Ca, and B Is Ti ion), and contains at least one element selected from the group consisting of Fe, Mn, and Co. According to the present invention, there is further provided a method of manufacturing a semiconductor device, comprising the steps of: forming a lower electrode on a semiconductor substrate; forming a dielectric film on the lower electrode, the thickness of the dielectric film is 100 nm or less, and is mainly composed of gold tantalum oxide with an AB03-type perovskite crystal structure (where A is at least one metal ion selected from the group consisting of S r, Ba, and Ca, and B is Ti ion): coating a solution containing at least one element selected from the group consisting of Fe, Mn, and Co on one surface of the dielectric film: coating is selected from Fe, Mn, and C 〇 The dielectric film of at least one yuan of the formed group is heat-treated. The paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm) ZO (please read the note on the back | matters and fill out this page). Book 5: Description of the invention: 5) By diffusing the at least one element into the dielectric film > and forming-the upper electrode is formed on the dielectric film to form a dielectric film containing the lower electrode »and the power up极 之-* capacitance 0 According to the present invention, a method for manufacturing a semiconductor device 9 is provided here. The steps include: forming-forming a lower electrode on a semiconductor substrate by CVD method or sputtering method to form a dielectric film under the On the electrode »The thickness of the dielectric film is 10 On m or less I, and it is mainly composed of gold tantalum oxide with an AB 0 3 type perovskite crystalline structure (where A is selected white and contains S r» B at And at least the group consisting of Ca—golden ions and B are Ti ions), and contains at least the element of the group consisting of Fe e M η and C 0; and forming an upper electrode in the medium The electric film is formed to include a lower electrode, a dielectric film, and one of the capacitors of the upper electrode. 9 Other advantages and advantages of the present invention will be described in the following description. One part can be known from the description and the other part can be Implementation of the invention And learned. The purpose and advantages of the present invention can be realized by the facilities and their combinations specifically indicated in the patent application. The formula briefly describes the following diagram, which is set in the description and forms part of the description. The present preferred embodiment of the present invention is disclosed »It combines the above-mentioned paragraph description and the following detailed description of the preferred embodiment» Commonly used to explain the principle of the present invention. FIG. 1 is a perovskite dielectric film The relationship between the thickness of the film and the dielectric constant of the perovskite dielectric film. • This paper scale is applicable to the Chinese National Standard (CNS) A4 (210X29 • / Guanluan). Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy ^ 〇6〇37 A7 B7 V. Description of the invention (6) Circle 2 is the CV characteristic diagram of the capacitor, which shows the effect of the present invention. FIG. 3 is the contour circle of F e measured in (Ba, Sr) Ti03 by SIMS. ; Figures 4 A to 4 D show the first Examples of cross-sectional views of the manufacturing steps of the DRAM cell; FIGS. 5 A to 5 D show cross-sectional views of the manufacturing steps of the DRAM cell according to the second embodiment of the present invention: FIGS. 6 A to 6 D show the steps of the present invention respectively 7A to 7E show the cross-sectional views of the manufacturing steps of the DRAM cell according to the fourth embodiment of the present invention: details of the preferred embodiments The special feature of the semiconductor device according to the present invention lies in a capacitor, which includes a dielectric film with a thickness of 100 nm or less, and is mainly composed of
一 A B 03型鈣鈦礦結晶結構之金屬氧化物構成（其中A 爲選自含有Sr ，Ba ，和C a所組成之群之至少一金靥 離子，和B爲Ti離子），並含有選自由Fe，Μη和 C 〇所構成之群之至少一元素。 關於在介電膜中選自由Fe ，Μη，和Co所構成之 群之元索之澳度方面*最好在0. Olwt%至小於10 wt%之範圍內，更特別而言，最好在〇.lwt%更好 在1. Owt%至5wt%之範園內•如果在介電膜中之 本紙張尺度遑用中國囷家橾率（CNS ) A4規格（210 X297公釐> ~ U-------裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 _ .*_ 五、發明説明（7 ) 元素濃度小於0. Olwt%，則難以改善介電常數•另 —方面，如果在介電膜中之元素之濃度爲1 〇w t %或更 多時，介電膜之絕緣特性會受到破壞。 介電膜之膜厚度之較佳範圍爲5 0 nm或更小。 本發明人發現如果公電膜主要使用具有一 A B 03型 鈣鈦礦結晶結構之金雇氧化物構成（其中A爲選自含有 Sr，Ba，和Ca所組成之群之至少一金屬離子，和B 爲Ti離子），並含有選自由Fe，Μη和Co所構成之 群之至少一元素，當成電容介電膜，則可獲得一電容，該 電容即使在進一步變薄時，亦可折前介電常數之降低和漏 鼋流之產生。以下說明本發明之機構· 已知具有鈣鈦礦結晶構造（以下稱爲鈣鈦硪介電膜） 之介電膜可允許構成鈣鈦礦結晶結構之結晶晶格之金靥離 子由內電場顯著的位移，如此導致廣泛的原子偏極化之產 生，如此可被展出髙介電常數。 經濟部中央標準局負工消費合作社印裝 但是，鈣鈦礦介電膜通常會伴隨如上述之問題，亦即 ，雖然鈣鈦礦介電膜以塊的形式或在膜厚度較大下，鈣鈦 礦介電膜可呈現高的介電常數，膜厚度愈薄時，介電常數 愈低。 圚1爲介於習知型式之每個鈣鈦礦介電膜之膜厚度和 介電常數和符合本發明之鈣鈦礦介電膜之膜厚度和介電常 數間之關係。習知之鈣鈦礦介電膜由以B a 〇. 5，S r 〇. 5 ，T i 〇3表示之複合物所形成，而本發明之鈣鈦礦介電 膜由以 B 3 〇. a * S i 〇.5’ T i 〇.9〇’ F β ο.οι * 〇3 表 本紙張尺度適用中國國家標準（CNSM4規格Ϊ2Ι0Χ297公釐）_ _ A7 B7 經濟部中央標準局貝工消費合作社印製 五、 發明説明 ：8 ) 示 之 複 合 物 所 形 成 〇 由 ΠΒΠ 圖 1 可 知 9 習 知 之 鈣 鈦 礦 介 電 膜 在 介 電 膜 變 成 較 薄 ( 特 別 是 在 介 電 膜相 當 薄 之 區 域 ) 時 t 其 介 電 常 數 顯 著 的 降 低 〇 此 意 即 9 在 習 知 之 鈣鈦 礦 介 電 膜 中 » 即 使膜 厚 度 降 低 時 9 由 鈣 飲 磺 介 電 膜 之 變 薄 難 以 期 望 改 善 介 電 膜 之 電 容 « 相 反 的 9 在本 發 明 之 鈣 鈦 礦 介 電 膜 之 例 中 » 即 使 膜 厚 度 顯 著 的 降 低 > 介 電 常 數 之 降 低 亦 非 常 緩 和 » 且 因 此 * 由 鈣 欽 礦 介 電 膜 之 變 薄 可 顯 著 的 預 期 介 電 膜 之 電 容 改 善 之 顯 著 優 點 〇 鈣 鈦 礦 介 膜 通 常 以 下 述 方 式 構 成 即 以 T i 表 示 之 三 價 金 屬 電 子 位 在 晶 格 之 中 央 ( B 位 置 ) 兩 價 金 屬 電 子 位 在 晶 格 之 頂 處 ( A 位 置 ) 和 負 兩 價 氧 離 子 位 在 晶 格 之 面 中 央 〇 如 果 如 離 子 損 失 之 任 何結 晶 缺 陷 發 生 在鈣 鈦 礦 結 晶 結 構 時 電 荷 之 平 衡 會 局 部 的 破 壞 且 因 此 電 場 受 引 起 以 產 生 在 此 不 平 衡 部 份 處 如 此 會 阻 擋 鈣 鈦 礦 介 電 膜 之 內 在 高 介 電 常 數 之 發 展 〇 在 此 例 中 最 重 要 之 問 題 爲 可 能 由 氧 離 子 之 損 非 而 引 起 之缺 陷 因 爲 此 缺 陷 被 視 爲 變 成 -* 受 子 側 和 構 成 鈣 鈦 礦 結 晶 結 構 之 金 靥 之 價 數 百 不 同 之 金 屬 離 子 之 添 加 可 有 效 的 用 以 消 除 前 述 電 荷 之 不 平 衡 〇 由 於 金 屬 離 子 之 添 加 9 可 能 會 由 電 荷 偏 移 而 引 起 在 介 電 膜 中 之 電 場 之 產 生 可 受 到 有 效 的 抑 制 » 如 此 可 提 供 -- 電 容 介 電 膜 » 即 使 介 電 膜 極 薄 時 9 亦 可 阻 止 介 電 常 數 之 降 低 * 且 亦 可 保持 請 先 閔 背 面 之 注 意 項 Ϊ 寫 本 頁 裝 訂 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局貞工消費合作社印製 A7 _B7_________ 五、發明説明<：9 ) 髙電荷累稹電容* 如上所述，在鈣鈦礦介電膜中之高介電常數之發展可 由金屬離子之大量位移（其會由內電場所產生）而作用。 但是，金靥離子之位移量不需和電場之大小成比例。亦即 ，當電場之大小超過一確定限制時，即使電場進一步增加 ，金靥離子之位移置亦不會增加》結果，在應用之電壓變 大時，介電常數之值會迅速的降低。 由這些現象可知，如果在電容介電膜之內部中有一電 場，整體而言，即使外界並無施加任何電壓，介電膜之介 電常數會實質的降低*產生此種內電場之起因主要歸因於 例如氧原子之損失（或一空位氫）或陷波電荷之晶格缺陷 Ο 如果在介電膜中有載子電荷，載子電荷作用在外部電 場上，如此可引起經由一空間電荷而產生一內部電場。在 介電膜中之載子電荷預期由氧損失或晶格缺陷所產生。 這些內部電場之產生原因主要爲介於電容電極和電容 介電膜間之介面之應變。此種應變可輕易的由發生在形成 電容電極處之破壤而產生*且此種破壊被視爲當m容介電 膜變薄時，用以使介電常數顯著的降低之原因之一· 如果在介電膜中存在有例如空位氧之晶格缺陷時，在 許多例中，電荷之中性會崩潰•但是，如果形成金屬離子 之元素以適當的量添加至介電膜中時（該元素之價電子數 目和構成鈣鈦礦介電膜之金屬不同），可有效的保持電荷 之中性，且因此*可有效的避免內電場之產生*且同時可 本紙張尺度遑用中國國家揉準（CNS ) A4規格（210Χ297公釐） ΓΙ (請先閲讀背面之注意事項-¾填寫本頁) -裝. 線 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（l〇 ) 有效的抑制介電常數之降低* 關於形成金屬離子元素（其可有效的補償氧損失）方 面，其特別可選自離子半徑接近位在B例之例如T i之四 價離子，且其價數目爲+ 3價或+ 4價之金靥元素•此種 金靥元素之特例如F e，Μη和C 〇 ·在這些金靥元素中 ，最好使用F e和Μη »A metal oxide of AB 03 type perovskite crystal structure (where A is at least one gold ions selected from the group consisting of Sr, Ba, and Ca, and B is Ti ions), and contains At least one element of the group formed by Fe, Mn and C 〇. With respect to the Australian degree of the elemental cable selected from the group consisting of Fe, Mn, and Co in the dielectric film * it is preferably in the range of 0.01 wt% to less than 10 wt%, more specifically, it is best 〇.lwt% is better within the range of 1. Owt% to 5wt% • If the original paper standard in the dielectric film is not used in China, the Chinese family rate (CNS) A4 specification (210 X297 mm > ~ U ------- install-- (please read the precautions on the back before filling in this page) Order_. * _ V. Description of the invention (7) If the element concentration is less than 0. Olwt%, it is difficult to improve the dielectric constant • On the other hand, if the concentration of the element in the dielectric film is 10 wt% or more, the insulating properties of the dielectric film will be destroyed. The preferred range of the film thickness of the dielectric film is 50 nm or more The inventor found that if the public electrical film is mainly composed of a gold oxide with an AB 03 type perovskite crystal structure (where A is at least one metal ion selected from the group consisting of Sr, Ba, and Ca, And B are Ti ions) and contain at least one element selected from the group consisting of Fe, Mn, and Co. As a capacitor dielectric film, a capacitor can be obtained. Even when it is further thinned, it can reduce the dielectric constant before the break and the leakage flow. The mechanism of the present invention is described below. It is known to have a perovskite crystal structure (hereinafter referred to as a perovskite dielectric film) The dielectric film allows the gold ions of the crystal lattice of the perovskite crystal structure to be significantly displaced by the internal electric field, thus causing the generation of a wide range of atomic polarization, which can be exhibited as a high dielectric constant. Printed by the Standards Bureau ’s Consumer Cooperatives. However, the perovskite dielectric film is usually accompanied by the above-mentioned problems, that is, although the perovskite dielectric film is in the form of a block or the film thickness is large, the perovskite dielectric film The electrical film can exhibit a high dielectric constant, and the thinner the film thickness, the lower the dielectric constant. Fig. 1 is the film thickness and dielectric constant of each perovskite dielectric film between conventional types and in accordance with the present invention The relationship between the film thickness and the dielectric constant of the perovskite dielectric film. The conventional perovskite dielectric film is formed by a compound represented by Ba 0.5, S r 0.5, Ti 〇3 , And the perovskite dielectric film of the present invention consists of B 3 〇. A * S i 〇.5 'T i 〇.9〇 'F β ο.οι * 〇3 The paper size of the table is applicable to the Chinese national standard (CNSM4 specification Ϊ2Ι0Χ297 mm) _ _ A7 B7 Printed by Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economy V. Description of invention: 8 ) Is formed by the composite shown. From FIG. 1, it can be seen that the dielectric constant of the conventional perovskite dielectric film becomes significantly thinner when the dielectric film becomes thinner (especially in areas where the dielectric film is quite thin). 〇This means 9 in the conventional perovskite dielectric film »Even if the film thickness is reduced 9 thinning of the calcium sulfonate dielectric film is difficult to expect to improve the capacitance of the dielectric film« Converse 9 in the present invention perovskite In the example of mineral dielectric film »Even if the film thickness is significantly reduced > the decrease in dielectric constant is very moderate» and therefore * the improvement of the capacitance of the dielectric film can be expected significantly by the thinning of the calcium ore dielectric film Advantages Calcium Titanium The mineral dielectric film is usually constructed in such a way that the trivalent metal electron position represented by T i is at the center of the lattice (position B), the bivalent metal electron position is at the top of the lattice (position A), and the negative divalent oxygen ion position In the center of the face of the crystal lattice. If any crystal defects such as ion loss occur in the perovskite crystal structure, the balance of charge will be locally destroyed and therefore the electric field is caused to generate at this unbalanced part. This will block the perovskite. The development of a high dielectric constant within the dielectric film. The most important problem in this case is the defect that may be caused by the damage of oxygen ions because this defect is considered to become-* the acceptor side and constitute the perovskite crystal The price of the structure of gold is different. The addition of hundreds of different metal ions can be used to effectively eliminate the aforementioned charge imbalance. Due to the addition of metal ions, 9 The electric field generated in the dielectric film due to charge shift can be effectively suppressed »This can provide-Capacitive dielectric film» Even when the dielectric film is very thin 9 can prevent the dielectric constant from decreasing * and You can also keep the notes on the back of the Min. Ϊ Write this page. The paper size applies to the Chinese National Standard (CNS) A4 (210X297 mm). Printed by the Ministry of Economic Affairs Central Standards Bureau Zhengong Consumer Cooperative A7 _B7_________ V. Description of the invention <: 9) High charge accumulation capacitance * As mentioned above, the development of high dielectric constants in perovskite dielectric films can be effected by a large displacement of metal ions (which can be generated by internal electrical fields). However, the displacement of gold halide ions does not need to be proportional to the magnitude of the electric field. That is, when the magnitude of the electric field exceeds a certain limit, even if the electric field further increases, the displacement of the gold tantalum ions will not increase. As a result, when the applied voltage becomes larger, the value of the dielectric constant will rapidly decrease. From these phenomena, if there is an electric field in the capacitor dielectric film, overall, even if no voltage is applied from the outside, the dielectric constant of the dielectric film will be substantially reduced * The cause of this internal electric field is mainly attributed to Lattice defects due to, for example, the loss of oxygen atoms (or a vacant hydrogen) or trapped charges. If there are carrier charges in the dielectric film, the carrier charges act on the external electric field, which can cause An internal electric field is generated. Carrier charges in the dielectric film are expected to be generated by oxygen loss or lattice defects. The internal electric field is mainly caused by the strain of the interface between the capacitor electrode and the capacitor dielectric film. This strain can easily be caused by the breakage that occurs at the electrode where the capacitor is formed * and this breakage is considered to be one of the reasons for the significant decrease in the dielectric constant when the m-capacitance dielectric film becomes thinner If there are lattice defects, such as vacant oxygen, in the dielectric film, in many cases, the neutrality of the charge will collapse • However, if the element forming the metal ion is added to the dielectric film in an appropriate amount (this The number of valence electrons of the element is different from the metal that constitutes the perovskite dielectric film), which can effectively maintain the neutrality of the charge, and therefore * can effectively avoid the generation of internal electric fields * and can also be used in China on the paper scale. Standard (CNS) A4 specification (210Χ297mm) ΓΙ (please read the precautions on the back-fill in this page)-installed. A7 B7 printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of invention (l〇 ) Effectively suppress the decrease of dielectric constant * With regard to the formation of metal ion elements (which can effectively compensate for the oxygen loss), it can be particularly selected from the tetravalent ions whose ion radius is close to that of B example, such as T i, and their value The number is + 3 price + Gold dimple of tetravalent element such Laid • Elemental e.g. gold dimple F e, Μη and C-square dimple elements in these metals, preferably used F e and Μη »
Ti4+之離子半徑爲0. 605埃。另一方面，在 F e ，Μη和C 〇之例中，如果以一 6 —座標離子量測， 則半徑爲：在F e 3 +之例中，0. 645埃（髙旋轉狀態 )或0. 55埃（低旋轉狀態）：在Fe4 +之例中， 0. 586埃：在Mn3 +之例中，0. 645埃（高旋轉 狀態）或0.5 8埃（低旋轉狀態）；在（：〇3 +之例中， 0. 6 1埃（高旋轉狀態）或0· 545埃（低旋轉狀態 );和在C04 +之例中，〇. 535埃。因此，這些金屬 離子之半徑接近T i 4 +之離子半徑·如果金饜離子之離子 半徑接近上述之T i 4 +時，這些金羼離子可綠易的取代下 T i位置。 如果這些元素變成在T i例上之三價離子時*其會提 供相當於一 1空位之電荷至該位置，因此* 一氧原子之損 失可由這些元素之兩原子所補償•如果電荷沒有偏移*如 同在氧原子損失之例中，則可保持位置上之四價離子，因 此*可保持電荷之平衡· 圖2爲本發明之一例之C — V特性圖，其中F e加入 (Ba ，Sr) Ti03薄膜中，和習知技藝之一例之C 本紙張尺度適用中國國家標準（CNS)八4規格（210X297公釐）_ 13 _ 裝 訂 7"線 :. ( ( (請先閲讀背面之注意事項-I填寫本頁) 經濟部中央標準局貝工消費合作社印製 A7 _B7_ 五、發明説明（11 ) 一 V特性圚，其中Fe並未加入（Ba ，Sr) Ti03 薄膜中。由圖2明顯可知，如果Fe加至一（Ba ，Sr )T i 03薄膜中時，膜之介電常數可顯著的改善。 如上所述，具有和構成鈣鈦礦結晶結構之金屬之價數 目不同之離子之添加可有效的保持晶格之電荷中性•再者 ，依照發明人之研究發現添加雕子之平均濃度最好爲 0. Olwt%或更多，更好爲〇.lwt%，以充份的 捕償例如在介電膜中氧原子損失之結晶缺陷* 由於本發明之添加物採用了 + 3價或+ 4價之價數目 ，亦可允許任何過餘的添加物採用四價在B位置上，就保 持電荷之平衡而言，此種作法相當有效*再者，任何過餘 的添加物會在晶粒邊界上沉澱，藉以促成多晶矽構造之穩 定性。 當形成一鈣鈦礦介電膜時，由膜形成而導致之本微型 應變和由介於介電膜和下層膜間之熱膨脹仔數之差異所導 致之熱應變會留在介電膜中，因此會產生由於這些應力而 引起在晶格中之應變，和降低介電膜之介電常數。 但是，如上所述例如F e離子之三價離子可有效的縮 小在晶格中之應變•並增強介電常數· 但是，如果添加物過度的添加，則會導致反效果·因 此，本發明人認爲所添加之離子之平均濃度爲1 Ow t % 或更小，且最好爲5wt %或更小。由於大部份的結晶缺 陷（例如氧損失）易於產生在介於介氰膜和電極間之介面 上，因此必需添加例如F e之添加物以使在接近介電膜和 本纸張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） ! I I I I I I 裝—.I I I I 訂—— ^線 -- f ( (請先閲讀背面之注意事項再填寫本頁) 306037 A7 B7 經濟部中央標準局員工消費合作社印製 五、 發明説明< 12 ) 電 極 間 之 介 面 附 近 之 添 加 物 之 濃 度 變 高。 另 一 方 面 9 由 於 如 氧 原 子 之 損失 等問題 之 原 因 可 由三 價 電 子 所 補 償 » 因 此 可 解 決 漏 電 流 之 問題· 圖 3 爲 以 S I Μ S ( 二 次 離 子 質 置頻譜 質 ) 所 置 測在 ( B a » S r ) Τ i 0 3膜中 ，F 3之輪廓圖 ，該 (B a 9 S r ) T i 0 3膜之厚度爲7 0 nm並設置在- -Ρ t膜 上 由 圖 3 明 顯 的 可 知 f 和 其 它 區 域 比較， F e 之 厚 度集 中 在 接 近 ( B a S Γ ) T i 0 3膜之表面區域 •由於如 氧 原 子 之 損 失 之 缺 陷 相 當 集 中 在 介 於 介電膜 和 電 極 間 之介 面 上 » 如 圖 3 所 示 之 輪 廓 即 爲 所 需 要 的· 如 上 所 述 依 照 本發 明 藉 由 添 加一金 屬 元 素 以 提供 三 價 或 四 價 金 屬 離 子 至 鈣 鈦 礦 型 金 靥 氧化膜 以 使 三 價或 四 價 金 靥 離 子 由 在 B 側 上 之 四 價 金 屬 離子所 取 代 如 可抑 制 介 電 常 數 之 降 低 和 漏 電 流 之 產 生 〇 因此， 依 照 本 發 明， 可 提 供 一 種 半 導 體 裝 置 即 使 電 容 介 電膜極 薄 時 亦 可保 持 高 可 η 度 〇 以 下 參 考 下 列 各 種 範 例 進 步 說 明本發 明 〇 ( 範 例 1 ) 圖 4 A 至 4 D 分 別 表 示 依 照 本 發 明之第 — 實 施 例 用以 製 造 — D R A Μ 胞 之 步 驟 之 截 面 圖 9 由此製 造 步 驟 所 獲得 之 D R A Μ 胞 乃 構 造 成 使 電 容 設 置 高 於任何 的 Μ 0 S 電晶 體 ( 一 開 關 電 晶 體 ) 鲁 — 字 線 和 位 元線， 和 含 有 小 置 F e 之 ( Β a 9 S r ) T 0 3膜使用當成- -電容介電膜 本紙張尺度逋用中國國家標準（CNS)A4規格（210X297公釐）_ 15 五、發明説明（l3 ) A7 B7 經濟部中央標準局貝工消費合作社印製 如圖4A所示，具有一主表面（（100)結晶面） 和一1 OQcm之特殊電阻之P型單晶矽基底1 〇 1之預 定表面部份受蝕刻，藉以形成一凹槽，在凹槽中後續的充 填元素隔離絕緣膜1 0 2以形成一元素隔離區域•此外， 元素隔離匾域亦可藉由使用L 0 C 0 S法形成· 而後，以熱氧化形成厚度爲1 0 nm之氧化矽膜，而 後況稹矽化鎢膜在其上•這些膜藉由光石印和一反應離子 蝕刻而定圖樣以形成一閘絕緣膜1 0 3和一閘電極1 0 4 。而後，執行離子植入並使用此閘電極1 0 4當成掩模， 藉以以自我對準方式形成由η-型擴散區域1 0 5和 1 0 6所構成之一源/汲極區域，如此可形成η通道 MOSFET當成一開關電晶體。 而後，如圖4Β所示，以CVD法沉稹l〇〇nm厚 之氧化矽膜1 0 7在MO S F E T之整個上表面上，並藉 由光石印和反應離子蝕刻而使接觸孔1 0 8形成在氧化矽 膜1 0 7中。 而後，氧化鈦膜1 0 9選擇性的形成在位在接觸孔 1 0 8之底部之η-型擴散區域1 〇 5上，和可使用當成 位元線1 0 0之氧化鎢膜沉稹在裝置之全部上表面上。而 後，藉由使用光石印和反應離子蝕刻，定圖樣矽化鎢膜， 藉以形成位元線1 0 〇 · 而後，在CVD氧化膜1 1 1沉積在所得裝置之整個 表面後，如圓4 C所示，CVD氧化膜1 1 1之表面平坦 請. 先 閲 讀 背 i 事 項一 填 本衣 頁 訂 線 本紙張尺度遑用中國國家梯準（CNS > Α4规格（210X 297公釐） -16 - A7 B7 經濟部中央揉準局貝工消费合作社印裝 五、 發明説明 ：14 ) 1 I 化 。而 後 以 光 石 印 形 成 —接觸 孔 1 12， 和 使 用當 成一 1 1 1 引 出電 極 1 1 3 之 第 — η +型多晶矽膜沉積在所得裝置之 整 個上 表 面 上 〇 而 後 9 只 有設置 在 接 觸孔1 1 2 中之 第一 請 1 η +型多晶矽膜之- -部份藉由使用例如蝕回之平坦方法而 it 閲 1 1 讀 1 留 下， 藉 以 形 成 引 出 電 極 113 0 背 面 I 而 後 9 當 成 下 叠 層 用 於下電 容 電 極1 1 6 之 T i 膜 之 注 意 1 事 1 1 14 和 T i N 膜 1 1 5 和使用 當 成 下電容 電 極 11 6之 項/ ' 1 填 1 Ρ t膜 連 績 的 沉 稹在 裝 置 之整個 表面 上❶ 寫 本 裝 I 而 後 * 藉 由 光 石 印 以 對膜1 1 4 ，11 5 和 11 6定 頁 1 1 圖 樣以 獲得 下 電 容 電 極 1 16。 1 1 而 後 厚 度 爲 2 0 η m且含 有 約 1 w t % 之 F e 之（ 1 1 Β a , S r ) T i 0 3藉由濺鍍法在5 0 0至7 0 0 °C之 訂 1 溫 度下 形 成 — 電 容 介 電 膜 117 在 裝 置之整 個 表 面上 •如 1 I 此 所獲 得 之 髦 容 介 電 膜 1 1 7爲 A Β 0 3型鈣鈦確結構， 1 I 其 中B a 和 S r 離 子 設 置 在A側 且 T i離 子 設 置在 晶格 1 ，線 之 B側 上 9 1 藉 由 預 先 安裝 F e 在 濺鍍靶 上 或使用 一 多 源濺 鍍方 1 1 法 ，其 中 含 有 相 當 高 濃 度 之含F e 之 耙或F e 靶 和未 含 1 1 F e之 靶 共 同 使 用 9 即 可 執行在 ( Β a S r ) T i 〇 3 I 膜 中F e 之 添 加 0 I 最 後 > 如 圖 4 D 所 示 ，8 0 η m 厚之T i N 膜8 0沉 I 稹 在所 得 裝 置 之 整 個 表 面 上，而 後 藉 由光石 印 定 圖樣 以形 1 Ί 成 一上 電 容 電 極 ( 一 板 電 極）1 1 8 ，藉以 完 成 D R AM 1 1 胞 之基 本 結 構 « 在 實 際 之 裝置中 包 括形成 A 接線 之步 1 1 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） A7 ____B7 五、發明説明（is ) 驟之額外步驟會依照一般用以完成DR AM之步驟執行，. 因此，於此省略這些步驟之說明。 在此例中’ （Ba ，Sr) Ti〇3使用當成電容介 電膜，且F e使用當成一金屬添加物。但是，在本發明中 亦可使用其它的材料· 其它的材料如S rT i 03，BaTi 03,或 C a T i 03等可使用當成電容介電膜以取代（b a ， Sr) TiO 3膜。再者，亦可使用其它的材料如Μη， C 〇或F e ，Μη和C 〇之組合以取代F e * 經濟部中央揉準局員工消費合作社印製 雖然在此例中，P t使用當成下電容電極，且T i N 使用當成上電容電極，亦可使用其它的導電材料以用於電 容電容。例如’亦可使用如Rd，I r，Rh，Ru和 Au之貴金屬，以及如i τ〇，Ru02，B aRu03, SrRU〇3，（Ba，Sr) Ru03 和摻雜 Nb 之 S r T i 03之氧化物導體當成下電容電極e另一方面， 除了上述之導電材料外，亦可使用例如W，Μ 〇或T a之 高溶點金靥，和如WN X，Mo N X或T a N X之化合物 導體當成上電容電極· (範例2 ) 圖5 A至5 D分別表示依照本發明之第二實施例用以 製造一DRAM胞之步驟之截面圖·由此製造步驟所獲得 之D R A Μ胞乃構造成使電容之位準設置高於任何的 MOS電晶體（一開關電晶體），一字線和一位元線，和 本紙張尺度適用中國國家標率（CNS )以規格（210χ297公釐） -18 - 經濟部中央標準局負工消費合作社印褽 A7 _B7_ 五、發明説明（：l6 ) 含有小置Μη以取代Fe之（Ba ，Sr) Ti03膜使. 用當成一電容介電膜。 此實施例之特徴在於：在鈣鈦碛結晶結構之電容介電 膜形成之後，非常少量之Μη黏著在介電膜之表面上，且 所得的介電膜受到退火以擴散黏著Μ η進入介電膜中。在 此例中之退火亦作用以改善介電膜之晶性，因此，在單一 步驟中可同時執行金靥之擴散和晶性之改善，藉此可簡化 整體之處理。 如圖5Α所示，具有一主表面（（1〇〇)結晶面） 和一1 0Ω cm之特殊電阻之Ρ型單晶矽基底2 0 1之預 定表面部份受蝕刻，藉以形成一凹槽，在凹槽中後嫌的充 填元素隔離絕緣膜2 0 2以形成一元素隔離區域。此外， 元素隔離區域亦可藉由使用L Ο C Ο S法形成。 而後，以熱氧化形成厚度爲2 0 nm之氧化矽膜，而 後況積矽化鎢膜在其上。這些膜藉由光石印和一反應離子 蝕刻而定圖樣以形成一閘絕緣膜2 0 3和一閘電極2 0 4 。而後，執行離子植入並使用此閘電極2 0 4當成掩模， 藉以以自我對準方式形成由η-型擴散區域2 0 5和 2 0 6所構成之一源/汲極區域，如此可形成η通道 MOSFET當成一開關電晶體· 而後，如圖5Β所示，以CVD法沉積1 〇〇nm厚 之氧化矽膜2 0 7在M O S F E T之整個上表面上，並藉 由光石印和反應離子蝕刻而使接觸孔2 0 8形成在氧化矽 膜2 0 7中· 本紙張尺度逋用中國國家橾率（CNS ) A4規格（210X297公釐> ~ -iy · I 裝 訂 "7"線 -· · ί 為 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局貝工消费合作社印衷 A7 __B7_ 五、發明説明（π ) 而後，矽化鈦膜109選擇性的形成在位在接觸孔 2 0 8之底部之η-型擴散區域2 0 5上，和之氧化鎢膜 沉積在裝置之全部上表面上*而後，藉由使用光石印和反 應離子蝕刻，定圚樣矽化鎢膜，藉以形成位元線2 1 0。 而後，在CVD氧化膜2 1 1沉稹在所得裝置之整個 表面後，如圖5 C所示，CVD氣化膜2 1 1之表面平坦 化。而後，以光石印形成一接觸孔2 1 2，和第一 η+型 多晶矽膜沉稹在所得裝置之整個上表面上•而後，只有設 置在接觸孔中之第一η +型多晶矽膜之一部份藉由使用例 如蝕回之平坦方法而留下，藉以形成引出電極2 1 3 » 而後，當成下叠層用於下電容電·極2 1 6之T i膜 2 14和TiN膜215和使用當成下電容電極2 1 6之 P t膜連績的沉積在裝置之整個表面上· 而後，藉由光石印以對膜2 1 4，2 1 5和2 1 6定 圖樣以獏得下電容電極2 1 6 · 而後，如圖5D所示，20nm厚之（Ba，Sr) Ti Ο 3膜21 7以濺鍍法在500至700 °C下，形成 在裝置之整個表面上。而後，含有0. lwt%Mn之溶 液200塗覆在（Ba，Sr) Ti03217之表面上 ，並使之乾燥。而後所得之裝置在7 0 0 °C下退火，以將 塗覆Μη擴散至（Ba ，Sr) Ti03膜217中，並 同時改善（Ba ，Sr) 丁103膜217之晶性· 最後，8 0 nm厚之T i N膜8 0沉稹在所得裝置之 整個表面上，而後藉由光石印定圖樣以形成一上電容電極 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐）~ -20 - ^ — — I 裝 訂 N線 • ( ( (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 • A7 — —__B7 五、發明説明（l8 ) 板電極）2 1 8，藉以完成DRAM胞之基本結構。. 在實際之裝置中，包括形成A 接線之步驟之額外步驟會 依照一般用以完成DRAM之步驟執行，因此，於此省略 這些步驟之說明。 在此例中’ （Ba，Sr)Ti〇3使用當成電容介 電膜，且Μη使用當成一金靥添加物•但是，在本發明中 亦可使用其它的材料· 其它的材料如SrTi 03，BaTi03，或 C a T i 03等可使用當成電容介電膜以取代（b a ， Sr) Ti03膜•再者，亦可使用其它的材料如Fe， C 〇或F e ’ Μη和C 〇之組合以取代Μη。 雖然在上述之說明中，含Μ η之溶液塗覆在電容介電 膜之表面，以擴散Μη進入電容介電膜中，但是，含Μη 之溶液亦可塗覆在下電容電極之表面上，以將Μη黏著於 此，而後一電容介電膜重叠在承載有Μ η之下電容電極上 ，以使黏著Μη可擴散進入電容介電膜中· 雖然在此例中，P t使用當成下電容電極，且T i Ν 使用當成上電容電極，亦可使用其它的導電材料以用於電 容電容*例如，亦可使用如Rd，I r ，Rh，Ru和 Au之貴金屬，以及如I TO，Ru02，BaRu03, S r R u 0 a 1 (Ba，Sr) Ru03 和摻雜 Nb 之 S r T i 〇3之氧化物導體當成下電容電極•另一方面， 除了上述之導電材料外，亦可使用例如W，Mo或T a之 高熔點金靥，和如WNx ’MoNx或TaNx之化合物 本紙張尺度遙用中國國家標率（CNS ) A4规格（210X297公釐> _ 21 _ 裝 訂 N線 (請先閲讀背面之注意事項"填寫本頁) A7 B7 306037 五、發明説明（l9 ) 導體當成上電容電極· (範例3 ) 請 先 閲 讀 背 之 注 意 事 ^ y-填 . |裝 頁 圖6 A至6 D分別表示依照本發明之第三實施例用以 製造一DRAM胞之步驟之截面圖。由此製造步驟所獲得 之D R AM胞爲一電晶體/一電容型，其適於增加整合密 度，且構造成使電容設置高於任何的MO S電晶體（一開 關電晶體）· 訂 如圖6 A所示，具有一主表面（（1〇〇)結晶面） 和一1 〇 Ω cm之特殊電阻之P型單晶矽基底3 0 1之預 定表面部份受蝕刻，藉以形成一凹槽，在凹槽中後績的充 填元素隔離絕緣膜3 0 2以形成一元素隔離匾域•此外* 元素隔離區域亦可藉由使用L 0 C 0 S法形成。 線 經濟部中央標準局貝工消费合作社印裝 而後，以熱氧化形成厚度0 nm之氧化矽膜，而 後況積矽化鎢膜在其上以使用當成閘電極3 0 4。這些膜 藉由光石印和一反應離子蝕刻而定圖樣以形成一閘絕緣膜 3 0 3和一閘電極3 0 4。而後，執行離子植入並使用此 閘電極3 0 4當成掩模，藉以以自我對準方式形成由n-型擴散區域3 0 5和3 0 6所構成之一源/汲極區域，如 此可形成η通道MO S F E T當成一開關電晶體· 而後，如圖6Β所示，以CVD法沉積1〇〇nm厚 之氧化矽膜3 0 7在MO S F E T之整個上表面上，並藉 由光石印和反應離子蝕刻而使接觸孔3 0 8形成在氧化矽 膜3 0 7中· 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐）_ _ A7 B7 經濟部中央橾準局貞工消費合作社印製 五、 發明説明 2〇 ) 1 | 而 後 ， 矽 化 鈦 膜 3 0 9 選 擇 性 的 形 成 在 位 在 接 觸 孔 1 1 3 0 8 之 底 部 之 η 一型擴散區域： 3 0 5上 •和可使用當成 ••1 1 位 元 線 3 1 0 之 矽 化 鎢 膜 沉 積 在 裝 置 之 全 部 上 表 面 上 。而 請 1 -1 後 9 藉 由 使 用 光 石 印 和 反 akg 办思 離 子 蝕 刻 » 定 圖 樣 氧 化 鎢 膜， 先 閱 1 1 讀 1 1 藉 以 形 成 位 元 線 3 1 0 0 背 I 之 1 而 後 在 C V D 氧 化 膜 3 1 1 沉 積 在 所 得 裝 置 之 整個 注 1 1 表 面 後 如 圖 6 C 所 示 y C V D 氧 化 膜 3 1 1 之 表 面 平坦 項 再 填 1 化 0 而 後 以 光 石 印 形 成 —· 接 觸 孔 3 1 2 和 第 — η +型 寫 本 ύ 多 晶 矽 膜 沉 稹 在 所 得 裝 置 之 整 個 上 表 面 上 0 而 後 只 有設 頁 1 1 置 在 接觸 孔 3 1 2 中 之 第 一 η +型多晶矽膜之- -部份藉由 1 1 使 用 例 如 蝕 回 之 平 坦 方 法 而 留 下 藉 以 形 成 引 出 電 極 1 | 3 1 3 〇 訂 | 而 後 當 成 下 叠 靥 用 於 下 電 容 電 極 3 1 6 之 T i 膜 1 I 3 1 4 和 丁 i N 膜 3 1 5 和 使 用 當 成 下 電 容 電 極 3 1 6之 1 1 | P t 膜 連 績 的 沉 積 在裝 置 之 整 個 表 面 上 〇 I π 而 後 藉 由 光 石 印 以 對膜 3 1 4 3 1 5 和 3 1 6定 線 1 圖 樣 以 獲 得 下 電 容 電 極 3 1 6 Q 1 1 而 後 9 厚 度 爲 2 0 η m 之 ( Β a S Γ ) T i 0 3膜 1 1 2 0 以 C V D 法 形 成 當 成 一 電 容 介 電 膜 3 1 7 在 裝 置 之整 1 I 個 表 面 上 0 在 此 狀 況 中 用 於 ( Β a S Γ ) T i 0 3膜 I 之 C V D 原 料和 用 於 F e 之 C V D 原 料 同 時 供 afg 應 以 允 許 1 | 0 • 1 至 1 W t % 之 F e 在 膜 形 成 之 步 揉 時 導 入 ( B a 、 1 ) S Γ ) T i 0 3膜中《 1 1 而 後 » 所 得 的 電 容 介 電 膜 3 1 7 可 依 需 要 的 退 火 。在 1 1 本紙張尺度遑用中國國家標率（〇^)八4規格（2〖〇父297公釐）-23 經濟部中央標準局貝工消费合作社印装 A 7 ___B7_'_ 五、發明説明（21 ) 此例中，（Ba、Sr) Ti03在700ec之溫度下退 火，以使Fe在（Ba、Sr) Ti03膜中穩定，並同 時改善膜之晶性。 最後’如圓6 D所示，使用當成上電容電極（一板電 極）318之80nm厚之WNx膜80沉稹在所得裝置 之整個表面上’而後藉由光石印定圓樣以形成一上電容電 極（一板電極）3 1 8，藉以完成DRAM胞之基本結構 。在實際之裝置中，包括形成A 接線之步駭之額外步驟 會依照一般用以完成DRAM之步驟執行，因此，於此省 略這些步驟之說明。 在此例中，（Ba，Sr) TiO 3使用當成電容介 電膜，且F e使用當成一金屬添加物*但是，在本發明中 亦可使用其它的材料· 其它的材料如S r T i 03，B a T i 03，或The ion radius of Ti4 + is 0.605 angstroms. On the other hand, in the case of F e, Mn, and C 〇, if a 6-coordinate ion is measured, the radius is: In the case of F e 3 +, 0.645 angstrom (high rotation state) or 0 . 55 Angstroms (low rotation state): in the case of Fe4 +, 0.586 angstroms: in the case of Mn3 +, 0.545 angstroms (high rotation state) or 0.5 8 angstroms (low rotation state); in (: In the case of 〇3 +, 0.61 Angstrom (high rotation state) or 0.545 Angstrom (low rotation state); and in the case of C04 +, 0.535 Angstrom. Therefore, the radius of these metal ions is close to T The ion radius of i 4 + · If the ion radius of gold ions is close to the above T i 4 +, these gold ions can easily replace the T i position. If these elements become trivalent ions in the case of T i When * it will provide a charge equivalent to a 1 vacancy to this position, so * the loss of an oxygen atom can be compensated by two atoms of these elements • If the charge is not offset * as in the case of the loss of oxygen atoms, it can be maintained The tetravalent ion in the position, so * can maintain the balance of charge. Figure 2 is a C-V characteristic diagram of an example of the present invention, where F e plus Into (Ba, Sr) Ti03 film, and one of the examples of conventional skills C This paper scale is applicable to China National Standard (CNS) 84 specifications (210X297 mm) _ 13 _ binding 7 " line :. (((please first Read the notes on the back-I fill out this page) A7 _B7_ printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (11) A V characteristic, in which Fe is not added to the (Ba, Sr) Ti03 film. It is clear from Figure 2 that if Fe is added to a (Ba, Sr) Ti 03 film, the dielectric constant of the film can be significantly improved. As mentioned above, the number of valences of metals with and constituting the perovskite crystal structure The addition of different ions can effectively maintain the charge neutrality of the lattice. Furthermore, according to the research of the inventors, it is found that the average concentration of the added carving is preferably 0.01 wt% or more, more preferably 0.1 wt%, To fully compensate for the crystal defects such as the loss of oxygen atoms in the dielectric film * Since the additive of the present invention uses a valence of +3 or +4, it is also possible to allow any excess of the additive to use quaternary At the B position, in terms of maintaining the charge balance, this approach is quite * Furthermore, any excess additives will precipitate on the grain boundaries, thereby contributing to the stability of the polysilicon structure. When a perovskite dielectric film is formed, the micro-strain caused by the film formation and the intermediate The thermal strain caused by the difference in the thermal expansion between the electrical film and the underlying film will remain in the dielectric film, and therefore will cause strain in the lattice due to these stresses and reduce the dielectric constant of the dielectric film. However, as described above, trivalent ions such as Fe ion can effectively reduce the strain in the crystal lattice and enhance the dielectric constant. However, excessive addition of additives may cause adverse effects. Therefore, the inventors It is considered that the average concentration of added ions is 1 wt% or less, and preferably 5 wt% or less. Since most of the crystal defects (such as oxygen loss) are likely to occur on the interface between the dielectric film and the electrode, it is necessary to add additives such as Fe to make it suitable for China near the dielectric film and the paper. National Standard (CNS) A4 specification (210X297mm)! IIIIII Pack—.IIII Order— ^ Line--f ((Please read the notes on the back before filling this page) 306037 A7 B7 Employee of Central Bureau of Standards, Ministry of Economic Affairs Printed by a consumer cooperative. 5. Description of the invention < 12) The concentration of additives near the interface between the electrodes becomes higher. On the other hand 9 due to problems such as the loss of oxygen atoms can be compensated by trivalent electrons »so it can solve the problem of leakage current. Figure 3 is measured by SI Μ S (secondary ion mass spectrometry) ( B a »S r) T i 0 3 film, F 3 profile, the thickness of the (B a 9 S r) T i 0 3 film is 70 nm and is set on the--P t film from Figure 3 Obviously, comparing f with other regions, the thickness of F e is concentrated near the surface area of the (B a S Γ) T i 0 3 film. Due to defects such as the loss of oxygen atoms, the defects are quite concentrated between the dielectric film and the electrode. The interface »The outline shown in FIG. 3 is what is needed. According to the present invention, as described above, by adding a metal element to provide trivalent or tetravalent metal ions to the perovskite-type gold oxide film to make three The valence or tetravalent gold ions are replaced by tetravalent metal ions on the B side. For example, the reduction of the dielectric constant can be suppressed Generation of leakage current. Therefore, according to the present invention, it is possible to provide a semiconductor device that can maintain high η degrees even when the capacitor dielectric film is extremely thin. The following describes the present invention by referring to the following various examples. (Example 1) FIG. 4 A to 4 D represents a cross-sectional view of the steps for manufacturing the DRA M cell according to the first embodiment of the present invention. 9 The DRA M cell obtained by this manufacturing step is constructed so that the capacitance setting is higher than any M 0 S transistor (One switch transistor) Lu—word line and bit line, and (Β a 9 S r) T 0 3 film with small set F e is used as--capacitor dielectric film. The paper standard adopts Chinese national standard ( CNS) A4 specification (210X297 mm) _ 15 V. Description of the invention (l3) A7 B7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs as shown in FIG. 4A, with a main surface ((100) crystal surface) and a 1 OQcm special resistance P-type single crystal silicon substrate 1 〇1 pre The surface part is etched to form a groove, and the element isolation insulating film 102 is subsequently filled in the groove to form an element isolation region. In addition, the element isolation plaque field can also be used by the L 0 C 0 S method Formation · Then, thermal oxidation is used to form a silicon oxide film with a thickness of 10 nm, and then a tungsten silicide film on it. These films are patterned by photolithography and a reactive ion etching to form a gate insulating film 10 3 and a gate electrode 1 0 4. Then, ion implantation is performed and the gate electrode 104 is used as a mask to form a source / drain region composed of n-type diffusion regions 105 and 106 in a self-aligned manner. The n-channel MOSFET is formed as a switching transistor. Then, as shown in FIG. 4B, a 100 nm thick silicon oxide film 107 is deposited on the entire upper surface of the MO SFET by CVD, and the contact holes 108 are made by photolithography and reactive ion etching It is formed in the silicon oxide film 107. Then, a titanium oxide film 109 is selectively formed on the n-type diffusion region 1 〇5 at the bottom of the contact hole 108, and the tungsten oxide film can be used as a bit line 100 All the upper surface of the device. Then, by using photolithography and reactive ion etching, the patterned tungsten silicide film is patterned to form bit lines 10 0. Then, after the CVD oxide film 11 1 is deposited on the entire surface of the resulting device, as shown by the circle 4 C The surface of the CVD oxide film 1 1 1 is flat. Please read the back i matters first. Fill in the clothing page. Bookmark the paper size. Use the Chinese National Standard (CNS > Α4 specification (210X 297 mm) -16-A7 B7 Printed and printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs 5. Description of the invention: 14) 1 I. Then, a photolithographic contact hole 1 12 is formed, and the first η + type polysilicon film used as a 1 1 1 extraction electrode 1 1 3 is deposited on the entire upper surface of the resulting device. Then only 9 is provided in the contact hole 1 1 The first of the 2 please 1 η + -type polysilicon film-part by using a flat method such as etchback and it read 1 1 read 1 left, thereby forming the extraction electrode 113 0 back side I and then 9 as the lower stack Note on the T i film used for the lower capacitor electrode 1 1 6 1 thing 1 1 14 and the T i N film 1 1 5 and the item used as the lower capacitor electrode 11 6 / '1 fill 1 Pt film continuous performance Shen Zhen ❶ Write I on the entire surface of the device and then * print the 1 1 pattern of the film 1 1 4, 11 5 and 11 6 by light stone printing to obtain the lower capacitor electrode 16. 1 1 Then (1 1 Β a, S r) with a thickness of 2 0 η m and containing about 1 wt% of Fe (T 1 0 3) by sputtering method at 500 0 to 7 0 0 ° C 1 Formed at temperature — Capacitive dielectric film 117 is on the entire surface of the device • As 1 I The obtained fashionable dielectric film 1 1 7 is a structure of A Β 0 3 type perovskite, 1 I where B a and S r The ions are placed on the A side and the Ti ions are placed on the lattice 1, the B side of the line 9 1 by pre-installing F e on the sputtering target or using a multi-source sputtering method 1 1, which contains a very high concentration The rake with F e or the target with F e and the target without 1 1 F e can be used together with 9 to perform the addition of F e in the (Β a S r) T i 〇3 I film. 0 I Last> As shown in the figure As shown in 4 D, a 80 N η m thick Ti N film 80 Shen I 稹 is formed on the entire surface of the resulting device, and then a pattern is formed by light stone patterning to form an upper capacitor electrode (a plate electrode) 1 1 8 to complete DR AM 1 1 The basic structure of the cell «In the actual installation, including the step of forming the A connection 1 1 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 ____B7 V. The invention description (is) Extra step The steps will be performed in accordance with the steps generally used to complete DR AM. Therefore, the description of these steps is omitted here. In this example, '(Ba, Sr) Ti〇3 is used as a capacitor dielectric film, and Fe is used as a metal additive. However, other materials can also be used in the present invention. Other materials such as SrTi 03, BaTi 03, or CaTi03 can be used as capacitor dielectric films instead of (ba, Sr) TiO3 films. In addition, other materials such as Mn, C 〇, or Fe, a combination of Mn and C 〇 can be used instead of F e * Printed by the Employee Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economy Although in this example, P t is used as The lower capacitor electrode, and T i N is used as the upper capacitor electrode, and other conductive materials can also be used for the capacitor. For example, 'noble metals such as Rd, Ir, Rh, Ru and Au, as well as Sr T i 03 such as i τ〇, Ru02, BaRu03, SrRU〇3, (Ba, Sr) Ru03 and Nb-doped The oxide conductor is used as the lower capacitor electrode. On the other hand, in addition to the above conductive materials, high melting point gold tantalum such as W, Mo or Ta, and such as WN X, Mo NX or Ta NX can also be used The compound conductor is regarded as the upper capacitor electrode. (Example 2) FIGS. 5A to 5D respectively show cross-sectional views of the steps for manufacturing a DRAM cell according to the second embodiment of the present invention. The DRA M cell obtained by this manufacturing step is It is constructed so that the level of the capacitor is set higher than any MOS transistor (a switching transistor), a word line and a bit line, and the paper scale is applicable to China National Standard Rate (CNS) to specifications (210 × 297 mm) -18-The Ministry of Economic Affairs Central Bureau of Standards Consumer Cooperative Printed A7 _B7_ V. Description of the invention (: l6) The (Ba, Sr) Ti03 film containing small Mn to replace Fe is used as a capacitor dielectric film. The special feature of this embodiment is that after the formation of the capacitor dielectric film of the perovskite crystal structure, a very small amount of Mn is adhered to the surface of the dielectric film, and the resulting dielectric film is annealed to diffusely adhere Mn to the dielectric In the membrane. The annealing in this example also serves to improve the crystallinity of the dielectric film. Therefore, the diffusion of gold and the crystallinity can be simultaneously improved in a single step, thereby simplifying the overall processing. As shown in FIG. 5A, a predetermined surface portion of a P-type single crystal silicon substrate 210 having a main surface ((100〇) crystal surface) and a special resistance of 10 Ω cm is etched to form a groove In the groove, the element isolation insulating film 202 is filled behind to form an element isolation region. In addition, the element isolation region can also be formed by using the L Ο C Ο S method. Then, a silicon oxide film with a thickness of 20 nm is formed by thermal oxidation, and then a tungsten silicide film is deposited thereon. These films are patterned by photolithography and a reactive ion etching to form a gate insulating film 203 and a gate electrode 204. Then, ion implantation is performed and the gate electrode 204 is used as a mask to form a source / drain region composed of n-type diffusion regions 250 and 206 in a self-aligned manner. The η-channel MOSFET is formed as a switching transistor. Then, as shown in FIG. 5B, a 100-nm-thick silicon oxide film 207 is deposited on the entire upper surface of the MOSFET by CVD, using photolithography and reactive ions. Etching to form the contact hole 2 0 8 in the silicon oxide film 2 0 7 · This paper standard uses the Chinese National Standard (CNS) A4 specification (210X297mm> ~ -iy · I binding " 7 " line- · Ί is (please read the precautions on the back and then fill out this page) A7 __B7_ of the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs. V. Description of Invention (π) Then, the titanium silicide film 109 is selectively formed in place On the η-type diffusion region 205 at the bottom of the contact hole 308, a tungsten oxide film is deposited on the entire upper surface of the device *, and then, by using photolithography and reactive ion etching, a sample of tungsten silicide is fixed Film to form a bit line 2 1 0. Then, the CVD oxide film 2 1 1 After Shen Zhen over the entire surface of the resulting device, as shown in FIG. 5C, the surface of the CVD vaporized film 2 1 1 is planarized. Then, a contact hole 2 1 2 is formed by photolithography, and the first η + type polysilicon The film sinks on the entire upper surface of the resulting device. Then, only a part of the first η + type polysilicon film provided in the contact hole is left by using a flat method such as etching back, thereby forming the lead-out electrode 2 1 3 »Then, the Ti film 21 and TiN film 215 used as the lower stack for the lower capacitor electrode 2 1 6 and the P t film used as the lower capacitor electrode 2 16 were successively deposited on the entire device On the surface, then, by photolithography to pattern the film 2 1 4, 2 1 5 and 2 1 6 to tap the lower capacitor electrode 2 16. Then, as shown in FIG. 5D, 20nm thick (Ba, Sr ) Ti Ο 3 film 21 7 is formed on the entire surface of the device by sputtering at 500 to 700 ° C. Then, a solution 200 containing 0.1 wt% Mn is coated on the surface of (Ba, Sr) Ti03217 And let it dry. The resulting device was then annealed at 700 ° C to diffuse the coated Mn into the (Ba, Sr) Ti03 film 217 and improve ( Ba, Sr) Ding 103 film 217 crystallinity · Finally, a 80 nm thick TiN film 80 Shen Zhen on the entire surface of the resulting device, and then patterned by light stone to form an upper capacitor electrode paper Standards apply to China National Standard (CNS) A4 (210X297mm) ~ -20-^ — — I Binding N Line • ((Please read the precautions on the back before filling this page) Ministry of Economic Affairs Central Standards Bureau Bei Gong Printed by the consumer cooperative • A7 — —__ B7 V. Description of the invention (l8) Board electrode) 2 1 8 to complete the basic structure of the DRAM cell. In an actual device, the additional steps including the step of forming the A connection will be performed in accordance with the steps generally used to complete the DRAM. Therefore, the description of these steps is omitted here. In this example, '(Ba, Sr) Ti〇3 is used as a capacitor dielectric film, and Mn is used as a gold additive. However, other materials can also be used in the present invention. Other materials such as SrTi 03, BaTi03, or CaTi03, etc. can be used as capacitor dielectric films instead of (ba, Sr) Ti03 films. Furthermore, other materials such as Fe, C 〇 or Fe e Mn and C 〇 can also be used To replace Mn. Although in the above description, the solution containing Mn is coated on the surface of the capacitor dielectric film to diffuse Mn into the capacitor dielectric film, but the solution containing Mn may also be coated on the surface of the lower capacitor electrode to Adhere Mn to this, and then a capacitor dielectric film overlaps on the capacitor electrode carrying Mn, so that the adhered Mn can diffuse into the capacitor dielectric film. Although in this example, P t is used as the lower capacitor electrode , And T i Ν can be used as the upper capacitor electrode, and other conductive materials can also be used for the capacitor * For example, precious metals such as Rd, Ir, Rh, Ru and Au, and I TO, Ru02, BaRu03, S r R u 0 a 1 (Ba, Sr) Ru03 and Nb-doped S r T i 〇3 oxide conductors are used as lower capacitor electrodes. On the other hand, in addition to the above conductive materials, for example W, Mo or Ta high melting point gold compounds, and compounds such as WNx 'MoNx or TaNx This paper scale is remotely used in China National Standard Rate (CNS) A4 specification (210X297mm> _ 21 _ binding N line (please first Read the notes on the back " fill in this page) A7 B7 306037 5. Description (l9) The conductor is regarded as the upper capacitor electrode. (Example 3) Please read the notes on the back ^ y-filling. | Pages 6 A to 6 D show the third embodiment of the invention for manufacturing a A cross-sectional view of the steps of the DRAM cell. The DR AM cell obtained by this manufacturing step is a transistor / a capacitor type, which is suitable for increasing the integration density and is configured to make the capacitor setting higher than any MOS transistor (a Switching transistor) · Order as shown in Figure 6 A, with a main surface ((100〇) crystal surface) and a special resistance of 10 Ω cm P-type single crystal silicon substrate 3 0 1 predetermined surface portion After being etched, a groove is formed, and the element isolation insulating film 30 2 is filled in the groove to form an element isolation plaque field. In addition, the element isolation region can also be formed by using the L 0 C 0 S method. Printed and printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, and then thermally oxidized to form a silicon oxide film with a thickness of 0 nm, and then a tungsten silicide film was deposited on it for use as a gate electrode 304. These films were printed by photolithography Etching with a reactive ion pattern to form a gate insulation 3 0 3 and a gate electrode 3 0 4. Then, ion implantation is performed and this gate electrode 3 0 4 is used as a mask to form the n-type diffusion regions 3 0 5 and 3 0 6 in a self-aligned manner. Constitute a source / drain region, so that the n-channel MO SFET can be formed as a switching transistor. Then, as shown in FIG. 6B, a 100 nm thick silicon oxide film 307 is deposited by CVD on the MO SFET On the entire upper surface, contact holes 3 0 8 are formed in the silicon oxide film 3 0 7 by photolithography and reactive ion etching. This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) _ _ A7 B7 Printed by the Central Ministry of Economic Affairs, Jungong Consumer Service Co., Ltd. V. Description of invention 2) 1 | Then, a titanium silicide film 3 0 9 is selectively formed at the bottom of the contact hole 1 1 3 0 8 Type 1 diffusion area: 3 0 5 • and usable as • • 1 1 bit line 3 1 0 tungsten silicide film is deposited on the entire upper surface of the device. And please 1 -1 after 9 by using photolithography and anti-akg to do the ion etching »patterned tungsten oxide film, first read 1 1 read 1 1 to form bit line 3 1 0 0 back I 1 and then oxidized in CVD The film 3 1 1 is deposited on the entire surface of the resulting device. Note 1 1 as shown in FIG. 6 C. The surface flatness of the CVD oxide film 3 1 1 is filled with 1 0 and then formed with a photolithography—contact hole 3 1 2 and The first — η + type writing book ύ polysilicon film is deposited on the entire upper surface of the resulting device 0 and then only the page 1 1 is set in the first η + type polysilicon film placed in the contact hole 3 1 2-part by 1 1 Use a flat method such as etch-back to leave the lead electrode formed 1 | 3 1 3 〇 order | and then used as the lower stack for the lower capacitor electrode 3 1 6 T i Membrane 1 I 3 1 4 and DIN i N membrane 3 1 5 and used as the lower capacitor electrode 3 1 6 1 1 | P t film was deposited on the entire surface of the device 〇I π and then printed by light stone Membrane 3 1 4 3 1 5 and 3 1 6 alignment 1 pattern to obtain lower capacitor electrode 3 1 6 Q 1 1 and then 9 thickness (2 a η m) T i 0 3 membrane 1 1 2 0 CVD method is used as a capacitor dielectric film 3 1 7 on the entire surface of the device 1 I 0 CVD raw materials used for (Β a S Γ) T i 0 3 film I in this situation and used for F e The CVD raw materials are supplied to afg at the same time. The F e of 1 | 0 • 1 to 1 W t% should be introduced during the film formation step (B a, 1) S Γ) T i 0 3 film "1 1 then» The capacitor dielectric film 3 1 7 can be annealed as required. Use Chinese national standard rate (〇 ^) 84 specifications (2 〖〇 father 297 mm) -23 printed on paper size A 7 ___ B7 _'_ V. Description of invention (21) In this example, (Ba, Sr) Ti03 is annealed at a temperature of 700 ec to stabilize Fe in the (Ba, Sr) Ti03 film and improve the crystallinity of the film. Finally, as shown in circle 6D, use the 80nm thick WNx film 80 as the upper capacitor electrode (a plate electrode) 318 to sink on the entire surface of the resulting device ', and then print a circular sample by light stone to form an upper capacitor Electrodes (one plate electrode) 3 1 8 to complete the basic structure of the DRAM cell. In an actual device, the additional steps including the step of forming the A connection will be performed according to the steps generally used to complete the DRAM. Therefore, the description of these steps is omitted here. In this example, (Ba, Sr) TiO 3 is used as a capacitor dielectric film, and F e is used as a metal additive * However, other materials can also be used in the present invention. Other materials such as S r T i 03, B a T i 03, or
CaTi03等可使用當成電容介電膜以取代（Ba，CaTi03 can be used as a capacitor dielectric film instead of (Ba,
Sr) TiO 3膜•再者，亦可使用其它的材料如Μη，Sr) TiO 3 film • Furthermore, other materials such as Mn can also be used,
Co或Fe，Μη和Co之組合以取代Fe · 雖然在此例中，R u 02使用當成下電容電極，且 WN X使用當成上電容電極，亦可使用其它的導電材料以 用於電容電容。例如，亦可使用如Rd，I r ，Rh ,Co or Fe, a combination of Mn and Co to replace Fe. Although in this example, Ru 02 is used as the lower capacitor electrode, and WN X is used as the upper capacitor electrode, and other conductive materials can also be used for the capacitor. For example, you can also use Rd, Ir, Rh,
Ru和Au之貴金屬，以及如I TO，BaRu〇3,Precious metals of Ru and Au, as well as I TO, BaRu〇3,
SrRu03，（Ba，Sr)RuO 3和接雜 N b 之 S r T i 03之氧化物導體當成下電容電極•另一方面， 除了上述之導電材料外，亦可使用例如W，Μ 〇或T a之 本紙張尺度適用中國國家橾準（CNS)A4規格（ 210X297公釐）_ 24 _ — I:---：---^-!餐II (請先閲讀背面之注意事項再填寫本頁) ，vsThe oxide conductor of SrRu03, (Ba, Sr) RuO 3 and S r T i 03 doped with N b is used as the lower capacitor electrode. On the other hand, in addition to the above conductive materials, for example, W, M 0 or T The paper size of a is applicable to China National Standard (CNS) A4 (210X297mm) _ 24 _ — I: ---: --- ^-! Meal II (Please read the notes on the back before filling this page ), Vs
T 線 經濟部中央樣準局貝工消费合作社印製 A7 __B7_五、發明説明（22 ) 髙熔點金屬，和如T i N，MoNx或TaNx之化合物 導體當成上電容電極。 (範例4 ) 圓7 A至7 E分別表示依照本發明之第四實施例用以 製造一DRAM胞之步驟之截面圓·此例敘述製造一電晶 體/一電容型D RAM胞之方法，其中一電晶體和一電容 分別形成在一分離半導體基底上，而後它們互相重叠且結 請 先 閲 讀 背 it 之 注 意 事 再 填 本衣 頁 合在一起。 此例之特徵在 以濺鍍法形成，且 成介電膜之步驟時 而言，添加以非常 使用當成電容介電 而後，承載電 於使用當成《容介 可提供三價或四價 以濺鍍法導入鈣鈦 少童F e之（B a 膜· 晶體之半導體基底 基底置合在一起以形成一DRAM胞 首先，如圖7A所示，具有一主 晶面）和一 1 0Ω 4 0 1之預定表面 中後續的充填元素 域•此外，元素隔 電膜之鈣鈦礦介電膜 金羼離子之金屬在形 礦介電膜中。更特別 ，S r ) T i 0 3膜 和承載電容之半導體 〇 表面（（1 0 0 )結 P型單晶矽基底 c m之特殊電阻之 部份受蝕刻，藉以 隔離絕緣膜4 0 2 離區域亦可藉由使用L 0 C 0 S法形成 形成一凹槽，在凹槽 以形成一元素隔離區 而後·以熱氧化形成厚度爲1 0 nm之氧化矽膜，而 後況積矽化鎢膜在其上•這些膜藉由光石印和一反應離子 本紙張尺度遑用中國國家梂準（CNS ) A4规格（210X297公釐} 訂 線 -25 - A7 B7 306037 五、發明説明（23 ) 蝕刻而定圖樣以形成一閘絕緣膜4 0 3和一閘電極4 0 4 •而後，執行離子植入並使用此閛電極4 0 4當成掩模’ 藉以以自我對準方式形成由η-型擴散區域4 0 5和 4 0 6所構成之一源/汲極區域，如此可形成η通道 Μ 0 S F Ε Τ當成一開關電晶體。 而後，如圖7Β所示，以CVD法沉稹1OOnm厚 之氧化矽膜4 0 7在MO S F Ε T之整個上表面上，並藉 由光石印和反應離子蝕刻而使接觸孔4 0 8形成在氧化砂 膜407中，以和η-型擴散區域40 5相通* 而後，矽化鈦膜4 0 9選擇性的形成在位在接觸孔 4 08之底部之η-型擴散區域4 0 5上，和之矽化鎢膜 沉積在裝置之全部上表面上。而後*藉由使用光石印和反 應雔子蝕刻，定圓樣矽化鎢膜，藉以形成位元線4 0 0。 而後，在CVD氧化膜4 1 1沉稹在所得裝置之整個 表面上· 而後，在接觸孔4 1 2以光石印形成後，如圄7 C所 示，以L P CVD法沉積η +型多晶矽膜在所得裝置之整 個上表面上。而後，只有設置在接觸孔4 1 2之η+型多 晶矽膜之一部份藉由使用例如蝕回之平坦方法而留下，藉 以形成引出電極4 1 3。 而後，矽化鈦膜4 1 4和T i Ν膜4 1 5連縯的沉積 在裝置之整個表面上，而後以光石印定圖樣。而後，以 CVD法，使用TEO S和03當成原料氣體，而使氧化 矽膜4 1 6形成在基底之整個表面上，而後，以CMP法 本紙張尺度適用中國國家標準（cns >八4规格（2丨〇><297公釐） - -26 - (請先閲讀背面之注意事項声4寫本頁) .装· *5* 經濟部中央橾準局負工消费合作社印製 經濟部中央標準局員工消費合作社印裝 A7 _B7 五、發明説明（24 / 拋光此氧化矽膜4 1 6，直到T i N膜4 1 5之表面曝露 出，藉此可使基底之表面平坦· 由於這些步驟之結果，可得承載MO S電晶體之第一 半導體基底作用當成一開關電晶體。 而後，如圚7 D所示，厚度爲5 0 nm之 Ti S i xNy418，厚度爲 2〇nm 之 Ti 膜 419 ，和使用當成下電容電極4 2 0之5 0 nm厚p t膜連績 的形成在分離矽基底4 1 7之整個表面上β 而後，20nm厚且含有約lwt%之Fe之（Ba ，S r ) T i 03以濺鍍法形成電容介《膜4 2 1在基底 4 1 7之整個表面上。在此例中，採用多源濺鍍法，其使 用兩不同靶用以形成m容介m膜4 2 1 ，亦即，用於（ Ba，Sr) Ti03之靶和用於Fe之靶* 而後，5 0 nm厚之P t膜形成在電容介電膜4 2 1 之整個表面上，並藉由光石印和反應離子蝕刻而定圖樣（ 其是習知的）以形成上電容電極4 2 2 · „ 而後，以CVD法使用TEO S和03當成原料氣雔 而在整個基底之表面上形成氧化矽膜4 2 3，並以CMP 法抛光氧化矽膜4 2 3，直到上電容電極4 2 2之表面曝 露，藉以使基底之表面平坦化。 由於這些步驟，可獲得承載電容之第二半導體基底。 而後，第一半導體基底和第二半導體基底叠層在一起 ，以使形成在第一半導體基底上之T i N膜4 1 5可重叠 在形成在第二半導體基底上之上電極4 2 2上，以獲得一 本紙張尺;!Ϊ適用中國國家梂準（CNS ) A4说格（2丨OX297公釐） (請先閲讀背面之注意事項男填寫本頁) -裝· 訂 -27 - 經濟部中夬標準局員工消費合作社印製 A7 _B7__ 五、發明説明（25 ) 叠層，而後該叠層在9 0 OeC下受到熱處理，藉以黏著兩 半導體基底。 最後，構成第二半導體基底之矽基底4 1 7受蝕刻以 完成D RAM胞之基本結構，在實際之製造中，包括形成 A义接線之步驟之額外步驟會依照一般用以完成D RAM 之步驟執行，因此，於此省略這些步驟之說明。 在此例中，（B a ，Sr) TiO 3使用當成電容介 電膜，且F e使用當成一金靥添加物•但是，在本發明中 亦可使用其它的材料。 其它的材料如SrTi03，BaTi03，或 C a T i 03等可使用當成電容介電膜以取代（B a， Sr) TiO 3膜•再者，亦可使用其它的材料如Μη， Co或Fe，Μη和Co之組合以取代Fe * F e之導入電容介電膜中可與電容介電膜之形成同時 執行，如實施例1和2所示，或是可在電容介電膜形成之 後將F e擴散進入電容介電膜而執行。再者，亦可採用任 何適當的方法以將F e導入電容介電膜。 雖然在此例中，P t使用當成下電容電極，且τ i N 使用當成上電容電極，亦可使用其它的導電材料以用於電 容電容•例如，亦可使用如Rd，I r ，Rh , Ru和 Au之貴金屬，以及如I TO，Ru02，BaRu〇3, S r R u 0 a * (Ba，Sr) Ru03 和摻雜 Nb 之 S r T i 〇3之氧化物導髏當成下電容電極•另—方面， 除了上述之導電材料外，亦可使用例如W，Mo或T a之 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）~ ~ ~ II ; 7 裝 訂 Γ線 (請先閱讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（26 ) 高溶點金屬，和如WN X，Mo N X或T a N X之化合物 導體當成上電容電極。 本發明並不限於上述之例。例如，雖然在上例中，使 用CVD法或濺鍍法以形成電容介電膜，但是亦可使用溶 膠處理以取代這些方法。亦即，如果使用溶膠處理時，例 如F e之前述金屬元素之預定量乃加入溶膠中，而後所得 的溶膠受加熱處理，以使溶膠結晶。 如上所述，依照本發明，由於一絕緣膜，其主要由具 有A B 03型鈣鈦磧結晶結構之金靥氧化的所構成，其中 預定離子位在A側，和B側且含有預定金靥元素，乃使用 於一電容介電膜，如此可抑制介電常數之下降和漏電流之 •產生，即使電容介電膜極薄。 對於熟悉此項技藝之人士而言，其可迅速的了解本發 明之優點和修飾例。因此，本發明之廣義觀點並不限於上 述特殊之細節，表示裝置，和實施例之說明•各種對於本 發明之修飾乃未能脫離由下述申請專利範圍和其等效例所 界定之一般發明概念之精神和範疇。 (請先閲讀背面之注意事項-¾填寫本頁) -裝. -線 經濟部中央橾準局貝工消費合作社印装 本紙張尺度逋用中國國家橾率（CNS > A4规格（2丨0X297公釐）_ 29 -T line Printed by Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 __B7_ V. Description of invention (22) High melting point metals, and compound conductors such as TiN, MoNx or TaNx are used as upper capacitor electrodes. (Example 4) Circles 7 A to 7 E respectively represent the cross-sectional circles of the steps for manufacturing a DRAM cell according to the fourth embodiment of the present invention. This example describes a method of manufacturing a transistor / capacitive D RAM cell, in which A transistor and a capacitor are formed on a separate semiconductor substrate, and then they overlap each other and please read the notes on the back of it before filling in this page. The characteristics of this example are formed by the sputtering method and the step of forming a dielectric film, which is added to be used very much as a capacitor dielectric, and then the carrying power is used as a "capacitor can provide trivalent or tetravalent to sputtering Introduce the perovskite children's Fe (B a film · crystal semiconductor substrates together to form a DRAM cell. First, as shown in FIG. 7A, with a main crystal plane) and a 1 0Ω 4 0 1 Subsequent filling of the element domain in the predetermined surface. In addition, the metal of the perovskite dielectric film of the element barrier film and the metal of the gold ion are in the ore-shaped dielectric film. More particularly, S r) T i 0 3 film and the capacitance-carrying semiconductor surface ((1 0 0) junction P-type single-crystal silicon substrate cm special resistance part is etched, thereby isolating the insulating film 4 0 2 from the region It can also be formed by using the L 0 C 0 S method to form a groove, forming an element isolation region in the groove, and then forming a silicon oxide film with a thickness of 10 nm by thermal oxidation, and then depositing a tungsten silicide film on it Top • These films are made by photolithography and a reactive ion paper standard using the Chinese National Standard (CNS) A4 specification (210X297mm). Stranding-25-A7 B7 306037 5. Description of the invention (23) Etching To form a gate insulating film 4 0 3 and a gate electrode 4 0 4 • Then, perform ion implantation and use this hae electrode 4 0 4 as a mask 'to form a n-type diffusion region 4 0 in a self-aligned manner 5 and 406 constitute a source / drain region, so that n channel Μ0 SF Ε Τ can be formed as a switching transistor. Then, as shown in FIG. 7B, a 100 nm thick silicon oxide film is deposited by CVD 4 0 7 on the entire upper surface of MO SF Ε T, and by photolithography and reactive ion etching The contact hole 408 is formed in the oxide sand film 407 to communicate with the η-type diffusion region 405 *, and then the titanium silicide film 409 is selectively formed at the bottom of the contact hole 4 08 in the η-type On the diffusion area 405, a tungsten silicide film is deposited on the entire upper surface of the device. Then, by etching using photolithography and reactive metallurgy, a tungsten silicide film is formed in a circular shape to form a bit line 400. Then, the CVD oxide film 4 1 1 is deposited on the entire surface of the resulting device. Then, after the contact holes 4 1 2 are formed by photolithography, as shown in FIG. 7 C, the n + type polycrystalline silicon film is deposited by LP CVD On the entire upper surface of the resulting device. Then, only a part of the n + type polysilicon film provided in the contact hole 4 1 2 is left by using a flat method such as etching back, thereby forming the lead-out electrode 4 1 3. Then, the titanium silicide film 4 1 4 and the Ti N film 4 15 were successively deposited on the entire surface of the device, and then the pattern was printed with light stone. Then, using CVD method, TEO S and 03 were used as the raw material gas, and The silicon oxide film 4 1 6 is formed on the entire surface of the substrate, and then, the paper is prepared by CMP The standard is applicable to the Chinese national standard (cns > 8 specifications (2 丨 〇 > < 297mm)--26- (please read the notes on the back of the page to write this page). Install * 5 * Printed by the Central Bureau of Standards and Labor Consumer Cooperatives of the Ministry of Economy Central Standards Bureau Employee Consumer Cooperatives A7 _B7 5. Description of the invention (24 / Polish this silicon oxide film 4 1 6 until the surface of the T i N film 4 1 5 is exposed In this way, the surface of the substrate can be made flat. As a result of these steps, the first semiconductor substrate carrying the MOS transistor can be used as a switching transistor. Then, as shown in Fig. 7D, Ti S i xNy418 with a thickness of 50 nm, Ti film 419 with a thickness of 20 nm, and a pt film with a thickness of 50 nm and a thickness of 420 as the lower capacitor electrode 4 20 After separating β on the entire surface of the silicon substrate 4 1 7 and then, 20 nm thick (Fe, Ba, S r) T i 03 containing about lwt% of Fe forms a capacitor dielectric film 4 2 1 on the substrate 4 1 7 by sputtering On the entire surface. In this example, a multi-source sputtering method is used, which uses two different targets to form the m-capacity m film 4 2 1, that is, the target for (Ba, Sr) Ti03 and the target for Fe * and then , A 50 nm thick P t film is formed on the entire surface of the capacitor dielectric film 4 2 1, and a pattern (which is known) is formed by photolithography and reactive ion etching to form the upper capacitor electrode 4 2 2 · „Then, use TEO S and 03 as raw materials to form a silicon oxide film 4 2 3 on the entire surface of the substrate by CVD, and polish the silicon oxide film 4 2 3 by CMP until the upper capacitor electrode 4 2 2 The surface of the substrate is exposed, thereby flattening the surface of the substrate. Due to these steps, a second semiconductor substrate carrying capacitance can be obtained. Then, the first semiconductor substrate and the second semiconductor substrate are stacked together so as to be formed on the first semiconductor substrate The upper T i N film 4 1 5 can be superimposed on the electrode 4 2 2 formed on the second semiconductor substrate to obtain a paper ruler; Ϊ applies to China National Standards (CNS) A4 said grid (2 丨OX297mm) (please read the precautions on the back first and fill in this page) A7 _B7__ printed by Employee Consumer Cooperative of the Ministry of Standards and Technology Bureau 5. Description of the invention (25) The laminate was then heat-treated at 90 OeC to adhere the two semiconductor substrates. Finally, the silicon substrate constituting the second semiconductor substrate 4 1 7 is etched to complete the basic structure of the D RAM cell. In actual manufacturing, the additional steps including the step of forming the A-wire will be performed in accordance with the steps generally used to complete the D RAM. Therefore, these steps are omitted here Explanation. In this example, (B a, Sr) TiO 3 is used as a capacitor dielectric film, and F e is used as a gold additive. However, other materials can also be used in the present invention. Other materials such as SrTi03, BaTi03, or C a T i 03 can be used as a capacitor dielectric film instead of (B a, Sr) TiO 3 film. Furthermore, other materials such as Mn, Co or Fe, Mn and Co can also be used Combination to replace the introduction of Fe * Fe into the capacitor dielectric film can be performed simultaneously with the formation of the capacitor dielectric film, as shown in Examples 1 and 2, or Fe can be diffused into the capacitor after the capacitor dielectric film is formed Dielectric film. And, Any suitable method can also be used to introduce Fe into the capacitor dielectric film. Although in this example, P t is used as the lower capacitor electrode and τ i N is used as the upper capacitor electrode, other conductive materials can also be used For capacitors • For example, precious metals such as Rd, Ir, Rh, Ru and Au, as well as I TO, Ru02, BaRu〇3, Sr Ruu 0 a * (Ba, Sr) Ru03 and doping can also be used The oxide guide of S r T i 〇3 of Nb is used as the lower capacitor electrode. In addition, in addition to the above conductive materials, the paper standards such as W, Mo or Ta can also be used. The Chinese National Standard (CNS) A4 specification (210X297mm) ~ ~ ~ II; 7 binding Γ line (please read the notes on the back before filling this page) A7 B7 5. Invention description (26) High melting point metals, such as WN X, Mo NX Or the compound conductor of T a NX is regarded as the upper capacitor electrode. The present invention is not limited to the above examples. For example, although in the above example, a CVD method or a sputtering method is used to form the capacitor dielectric film, a solvent treatment may be used instead of these methods. That is, if sol treatment is used, a predetermined amount of the aforementioned metal element such as Fe is added to the sol, and then the resulting sol is subjected to heat treatment to crystallize the sol. As described above, according to the present invention, due to an insulating film, it is mainly composed of gold oxide with an AB 03 type perovskite crystal structure oxidized, where the predetermined ion site is on the A side, and the B side contains the predetermined gold Is used for a capacitor dielectric film, which can suppress the decrease of the dielectric constant and the generation of leakage current, even if the capacitor dielectric film is extremely thin. For those familiar with this skill, they can quickly understand the advantages and modifications of the present invention. Therefore, the broad view of the present invention is not limited to the above specific details, the description of the device, and the embodiments. Various modifications to the present invention have not deviated from the general invention defined by the following patent application scope and equivalent examples The spirit and category of the concept. (Please read the precautions on the back first-fill in this page)-Installation.-Printed copies of the paper standard of the Central Bureau of Industry and Economics of the Ministry of Economic Affairs, Beigong Consumer Cooperatives (CNS> A4 specifications (2 丨 0X297 Mm) _ 29-
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| JP23162795A JP3274326B2 (en) | 1995-09-08 | 1995-09-08 | Semiconductor device and manufacturing method thereof |
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| TW306037B true TW306037B (en) | 1997-05-21 |
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| KR (1) | KR100253866B1 (en) |
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| TW (1) | TW306037B (en) |
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| SG74643A1 (en) * | 1997-07-24 | 2000-08-22 | Matsushita Electronics Corp | Semiconductor device and method for fabricating the same |
| JP3424900B2 (en) * | 1997-10-24 | 2003-07-07 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
| KR20000014388A (en) * | 1998-08-20 | 2000-03-15 | 윤종용 | Ferroelectric memory capacitor and forming method thereof |
| DE19854418C2 (en) * | 1998-11-25 | 2002-04-25 | Infineon Technologies Ag | Semiconductor component with at least one capacitor and method for its production |
| JP2002319636A (en) * | 2001-02-19 | 2002-10-31 | Nec Corp | Semiconductor memory and manufacturing method therefor |
| JP2002367989A (en) * | 2001-06-12 | 2002-12-20 | Tokyo Inst Of Technol | Oxide dielectric thin film and manufacturing method therefor |
| KR100433491B1 (en) * | 2002-06-25 | 2004-05-31 | 동부전자 주식회사 | Method of manufacturing semiconductor device |
| JP5726501B2 (en) * | 2010-12-10 | 2015-06-03 | 一般財団法人ファインセラミックスセンター | Polishing material, polishing composition and polishing method |
| JP5703170B2 (en) * | 2011-08-16 | 2015-04-15 | 株式会社アルバック | Method for producing ferroelectric film |
| US11476261B2 (en) * | 2019-02-27 | 2022-10-18 | Kepler Computing Inc. | High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor |
| US11744081B1 (en) | 2021-05-07 | 2023-08-29 | Kepler Computing Inc. | Ferroelectric device film stacks with texturing layer which is part of a bottom electrode, and method of forming such |
| US11527277B1 (en) | 2021-06-04 | 2022-12-13 | Kepler Computing Inc. | High-density low voltage ferroelectric memory bit-cell |
| US11765908B1 (en) | 2023-02-10 | 2023-09-19 | Kepler Computing Inc. | Memory device fabrication through wafer bonding |
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| US5434102A (en) * | 1991-02-25 | 1995-07-18 | Symetrix Corporation | Process for fabricating layered superlattice materials and making electronic devices including same |
| JP2715736B2 (en) * | 1991-06-28 | 1998-02-18 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| EP0568064B1 (en) * | 1992-05-01 | 1999-07-14 | Texas Instruments Incorporated | Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer |
| EP0571948B1 (en) * | 1992-05-29 | 2000-02-09 | Texas Instruments Incorporated | Donor doped perovskites for thin film dielectrics |
| US5471364A (en) * | 1993-03-31 | 1995-11-28 | Texas Instruments Incorporated | Electrode interface for high-dielectric-constant materials |
| JP2550852B2 (en) * | 1993-04-12 | 1996-11-06 | 日本電気株式会社 | Method of manufacturing thin film capacitor |
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| JPH0982907A (en) | 1997-03-28 |
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