305965 Λ 6 η 6 經濟部屮央#準^工消设合作杜印奴 五、發明説明（1) 發明之範嚙 本發明係關於電腦系統方面。具體言之，本S明锋關於 具有匯流排架構之電腦糸统。 發明之背景 很多電腦系铳均經設計具有匯流排架構。此種電腦系统 一般具有連接至匯流排之處理姐件。其他系统姐件一般亦 連接至匯流排。此種其他姐件包括之顯f姐件例如為vq a 及視頻le憶器，输出入（i / ο)姐件，系統記憶器及健存装 置，其他經由匯流排可接達之處理姐件之裝置。一種此種 電腦系統為IBM個人電腦 （PC)，且係由妞約Armonk IB Μ公司所製造。 為能對電腦糸統之使用者顯示資訊，此電腦糸躲I能產 生霞麗ϋ.及將影像產左黎眼示裝置上。產生可顯示影像 之一典型裝置為於視頻記憶器中產生影像之位元映像η位 元映像為一位元記憶元件之陣列，此記憶元件陣列與典型 視頻幂上之像素陣列相對應。調處位元映像以產生視頻影 像之方法為本行技術中热知之技術。 在先前具有處理姐件及與匯流排相連接之顯示狙件之電 腦系统中，一般係由理姐件負擔大部分產生供顯示姐件 顯示之(位元映t。除去產生位元映像外，處理姐件箱將位 元映像經由較慢之匯流排於sm件與m搏記億器之間往 返轉移。因此|在決定電腦系统中一項特定應用性能時· 匯流排速度為一重要因素。其他彰響此等電腦糸統性能之 (請先閲讀背而之注意亊項再堝寫本7; 本紙張尺度边用中a國家標毕(CNS)«F4規怙（210x297公龙） 81. 7. 20.000¾ (II) 305965 五、發明説明（2) · 因素包括⑴處理姐件速度，⑵資料匯流排寬度，⑶於顯示 |姐件（V G A )與視頻記憶器之間往返轉移資枓之時間。 在先前技術方法中，已有數種可用以改變匯流排導向之 電腦系统中視頻圖形應用之性能。此等方法包括⑴產生t 解除處理姐件之視頻記憶器之任務負擔及產生與 轉移位元映像*⑵使用二-重腺-出入埠視頻動跋《機存取_記 億LDR.AK)而非單一输出入埠DRAM實施視頻記憶，⑶使用萆 一输出入埠K實施液頻記® *但於視頻姐件内部使用視頻 資料緩衝器及更複雜之仲裁順序，Μ對處理姐件提供更頻 繁之視頻記憶存取。於後文中將對於每一種此種先前技術 加以說明。 就第一種使用特別視頻硬體之方法言，太多數Β形乳處 m屑敗tt羯。根據此種系统，處理姐件僅將一命令字 寫入圖形副處理器，副處理器再調處視頻記憶並按照處理 姐件指示產生視頻影像。然而此種系统實施時化費很高， 因為需要額外姐件（例如圖形副處理器及支援硬體）。此 方法之另一缺點為需寫入大i软體驅動程式，以便現有軟 體可於装備有此棰副處理器之機器上執行。再者，使用副 處理器可使電腦系统不能與現有姐件配合。 n.. ~M m .重舅出人埠dr am之先前技術方法亦為一種 經濟部屮央標準局C3C工消价合作杜印^ 化費較高之選擇。根據此種糸统，顯示姐件連接至視頻記 憶器之一输出入埠，而處理姐件連接至第二記憶输出人増 。接達視頻記憶器之處理姐件之數目因此需增加。除去較 高成本外，此方法尚有另外缺點，即需要額外之理輯>乂重 4 81. 7. 20.000張⑻ (請先閲請背而之.注意事項#填窍本7、 本紙法尺度边用中a a家榀準(CHS)甲4規岱（210x297公*) 305965 Λ 6 Π 6 經濟部屮央標準而貝工消许合作社印31 五、發明説明（5) H定1边竄抖之格式。 $ Ξ捶改菩視頻圖形應用之性能之方法為-於顥H件冉- 部使甩t播;要.料进JR-戴及—更滋農之j中裁順序.以使視頻記................ 谭—番更H接名處厘姐件。在此種方式下，故可使用化費 較為少之單一出入埠DRAMK為視頻記憶器使用。此方法之 總體性能仍受特定電腦系铳之匯流排定時頻寬之限制。因 此’此方法無法達到性能之顯著增加。 因此有需要一較佳装置，Μ供於處理姐件，顯示姐件， 視頻記憶器之間之.通信，以縮短視頻記憶器及输出入存取 時間，因此減少或消除匯流排韓爭。 發明之簡述 本發明提供一種装置及方法，用μ笔證季腦糸m連 m形匯流排。此棰高迪画形歷流排*在無_嫌額外姐件或軟 ... ·" —· ·. SS驅動程式情況下，可增強匯流排専向之電腦系铳中之視 頻圖形應用。 較佳具體實例之霉腦系統龟1二_攘玄凰篇件 (LEJWHJ，此姐件利用一資料匯流排連接至一置一晶片输出 入單位G E N I 0 ，一I —晶片鲺形介.面&迎)^六。一系统記憧 器連接至GENCPU及一視頻記憶器連接至GEHVGA。GEHCPU亦 經由一高速匯流排（ΡΊ-bus)連接至GENVGA。 可經由高速Pi-bus將GENCPU與GEHVGA，連接，绅此辑頻…. 圖形指令可直接GEffCPU連接至GENVGA，因此消除與較慢標 準系铳_流排線路相關之延遲。藉利用Pi-bus，GENCPU能 (請先閲讀背而之注意事項#碼寫本_ 裝< 線- 本紙張尺度Λ用中S國家樣準（CNS)T<1規怙（210x297公;《：) 81. 7. 20.000^(11) Λ 6 η 6 經濟部屮央櫺準局貝工消ftv合作杜印¾ 五、發明説明U ) 與GEN VGA通信·而無需將指令置於較為癱擠之系统匯流排 上。 ...r^' 收一位址•將此位址解碼，使用其暫存器*決定目標位址 是否與GENVGA相對應。如果目標位址與GEHVGA空間相對應 办如果Pi-bus被敢動，GEHCPU即啟動-Pi-bus擇期_。 GENCPU指示周期情況指示（是否此周期為一输出入或記憶 周期及是否其為一讀或寫周期）及將指令置於將GEHCPU與 GENVGA相連接之高速Pi-bus上。GENCPU亦產生一開始信號 ，PSTART#以指示Pi-bus周期之開始。 GENVGA監督來自GENCPU之信號，當接收到來自GENCPU之 信號時，即將输入之指令解碼及賁施所收到之指令。 GENCPU送出一 PCMDI»命令K指示Pi-bus周期正在進行。當 GENVGA完成其Pi-bus周期之部分後，GENVGA發出一 PRDY# 信號送回GENCPU。GENCPU藉使PCMD#信號停止而完成其 Pi-bus周期。 圖式之藺述 圖1為具體實施本發明之微處理器糸統之一功能方塊圖 ，所顯示之Pi-bus係與控制，位址及資料埭分開。 圖2為與本發明有闞之信號之定時圖。 較佳具體實例之詳述 本發明提供一種實施高塽圖形匯流排之装置與复拷以供 腦系统之用。於下述說明中，說明很多具賭细節，俾便對 (請先閲請背而之注意事項再填寫本， 裝- 訂· 線· 本紙法尺度边用中a S家標準（CNS) T4規格（2]0χ2ί}7公徒） 81. 7. 20,000^ (j|) 305965 五、發明説明（5 ) 本發明有透徹瞭解。然而對於在此種技術中已有一般热練 人士言，此等具體细節無箱加以使用以實施本發明。在其 他實例中，热知之结構•電路’匯流排議定則未詳细示出 ，如此方不會使本發明特點變為棋糊不清。 現參看圖1 ，本發明之電腦系統之一較佳具體實例於 圖中示出。於此較佳具體實例中’電腦系统10包括一 3 8 6 T M S L ^處理器’其係由Intel公司製造*此公司亦為 本發明之受譆人。此種需腦系統輿IBMtm PC AT傾人電腦相 容。氣統1〇每括玉一主要次糸铳姐件’定名為沿以CP』….20 ，GENI0 30， GpNVGA 40。 GENCPU 20 與 GENI0 30之姐 合，但此姐合無本文中所掲示之改良之處，可自Intel公 司獲得，其產品名稱為386TMSL微處理器Superset 。 GENCPU 20為一擴充之，處理组件；，包括一處理$_，一記 -- __.------- 憶控制器•一快取記憶控制器•歴流排控鄉遍輯*線路緩 衝器。一系铳記憶80連接至GENCPU 20 。系统記憶80主要 包括動態随機存取記憶（DRAM)装置。 GENI0 30為一單一晶片输出入單位，其包括平行埠，二 重串列埠，即時時鐘單位，二重可程式化中斷控制器，二 •重可程式化定時器，二重直接記憶存取控制器及一記憶映 像器。GENI0 30亦包括供GENCPU 20使用之可程式化暫存 、器，Μ命令GENI0 30實施不同功能。 經濟部中央榀準局只工消奸合作杜印5i (請先閲請背而之注意事項再Aa寫本，： ，GEHVGA 40為一單一晶片顯示姐件，其包括一圖形介面 ί及一視頻記憶控制器。視頻記憶控制器連接至GEHVGA 40 。視頻記憶50實質上包括DRAM装置。GENVGA 40亦包括供 本紙張尺度边用中困Η家楳iMCNS)甲Ί規格（210X297公龙) 81. 7. 20.000张（II) 經濟部屮央櫺準而3工消价合作社印奴 Λ fi ___Β 6 _ 五、發明説明（6 ) GENCPU 20使用之可程式化暫存器，Μ命令GENVGA 40實 施各種不同功能。 GENCPU 20 ，GENI0 30，GENVGA 40 係經由系统匯流排 11彼此通信及與其他系统组件通信（例如擴充槽*鍵盤控 制器，磁碟控制器等）。於此較佳具體實例中，系统匯流 排11為AT相容歴流排。此種匯流排為此種技藝中所熟知。 於本發明中，GENCPU - 20音餿由高速匯流排6 0而運ΊΤ至 GENVGA。此高速匯流排60 (亦稱作Pi-bus)係設於 GENCPU 20與GENVGA 40之間·用以改菩視頻記憶及1〇存 .· - ·-. 取時間，因此消除匯流排11上之「匯流排瓶頸」。此匯流 排可使視頻資料以高速移入及移出視頻記憶。因此於IBM PC上執行之視頻圚形應用程式應用於本發明時，將會有改 良之性能。在利用Pi-bus議定時無需特別软體。園1顯示 GEHCPU 20 與 GEHVGA 40 之間之 Pi-bus介面。Pi-bus議定 將於後文中說明。 f在大多數現有系统中，處理姐件係經由例如AT Bus之糸 统匯流排11而與顯示姐件通信。然而根據本發明之新穎架 構，GEHVG A共用PC系铳匯流排11之資料及位址線，除去接 收正常条铳匯流排11之控制信號外，尚接受Pi-Bus 60之 If信號^Pi-Bus 60上提供之個別信號括下述：一啟始 信號（W P S T A R T #表示）一命令信號（以p C M D #表示）， 一記憶或I/O存取型信號（KPMI0#表示），一讀取或寫 入存取型信號（以PWR#表示），一備妥信號（MPRDY#表 (請先閲讀背而之注意事項#蜞寫本Ty 本紙張尺度边用中《«家《MMCNS) Ή規格（210x297公：¢)305965 Λ 6 η 6 Ministry of Economic Affairs # 揮 阳 # 讓 ^ 工 消 設計 cooperating Du Yinnu V. Description of the invention (1) The scope of the invention This invention relates to the computer system. Specifically, this Mingfeng is about a computer system with a bus architecture. Background of the Invention Many computer systems are designed with a bus architecture. Such computer systems generally have processing components connected to the bus. Other system components are generally connected to the bus. Such other sister items include obvious sister items such as vq a and video memory, input / output (i / ο) sister items, system memory and health storage devices, and other processing sister items that can be accessed through the bus之 装置。 The device. One such computer system is an IBM personal computer (PC), and is manufactured by Niyo Armonk IB Μ Company. In order to display information to the users of the computer system, this computer system can generate Xia Li. It can also produce images on the left eye display device. A typical device for generating a displayable image is a bitmap that generates an image in a video memory. The n-bitmap is an array of one-bit memory elements, which corresponds to the pixel array on a typical video power. The method of adjusting the bit image to generate a video image is a well-known technology in the industry. In the previous computer system with processing sisters and display snippets connected to the bus, it is generally the responsibility of the sisters to generate most of them for displaying the sisters (bit map t. In addition to generating bit maps, processing The sister box transfers the bitmap between the SM and M-Block through a slower bus. So | when determining the performance of a particular application in a computer system, the bus speed is an important factor. Other Recognize the performance of these computer systems (please read the back-to-back items first and then write the book 7; this paper uses the national standard (CNS) «F4 regulation (210x297 male dragon) 81. 7. 20.000¾ (II) 305965 V. Description of the invention (2) · Factors include (1) the processing speed of the sister device, (2) the width of the data bus, and (3) the time to transfer the information between the display device (VGA) and the video memory. In the prior art methods, there have been several methods that can be used to change the performance of video graphics applications in bus-oriented computer systems. These methods include: (1) generating t the task of processing the video memory of the sister file and generating and transferring bitmaps * ⑵Use Two-fold gland-in and out port video animation "Machine Access_Jiyi LDR.AK) instead of a single I / O port DRAM to implement video memory, (3) use Iji I / O port K to implement Liquid Frequency Recorder * * but at the video sister The video data buffer and more complex arbitration sequence are used internally in the file, and M provides more frequent video memory access to the processing of the sister file. Each of these prior technologies will be described in the following. The first uses special video hardware According to this system, too many B-shaped breasts are damaged by crumbs. According to this type of system, the processing of sister files only writes a command word to the graphics sub-processor, and the sub-processor then adjusts the video memory and follows the instructions for processing sister files. Generate video images. However, the time-consuming cost of implementing such a system is high because of the need for additional components (such as graphics sub-processors and supporting hardware). Another disadvantage of this method is the need to write large i software drivers for the existing The software can be executed on a machine equipped with this secondary processor. Furthermore, the use of the secondary processor can prevent the computer system from cooperating with the existing sister device. N .. ~ M m. Prior art of dr. Method is also a According to this system, the C3C industrial price bureau of the Ministry of Economic Affairs and the C3C has a higher cost. According to this system, the display device is connected to one of the video memory output ports, and the processing device is connected to the second memory. The number of output is increased. Therefore, the number of processing pieces connected to the video memory needs to be increased. In addition to the higher cost, this method has another disadvantage, that is, additional editing is required > weight 4 81. 7. 20.000 sheets ⑻ (Please read it first and back to it. Note #Fill in this book 7. Use the standard method on this paper to use it (CHS) A 4 standard (210x297 g *)) 305965 Λ 6 Π 6 Ministry of Economic Affairs Printed by Beigongxu Cooperative Society 31 V. Description of invention (5) H sets the format of one-sided shaking. The method of changing the performance of the video graphics application for $ Ξ 擶 is-Yu Hao H Ping Ran-Department of Broadcasting; To feed into JR-Dai and-more Zinong's j cut order. In order to make the video record ... .............. Tan-Fan Geng took over the name of her sister. In this way, a single access port DRAMK with a relatively low usage fee can be used for video memory. The overall performance of this method is still limited by the timing bandwidth of the bus of certain computer systems. Therefore, this method cannot achieve a significant increase in performance. Therefore, there is a need for a better device. M is used for processing communication between sister devices, displaying sister devices, and video memory to shorten the video memory and input / output access time, thereby reducing or eliminating bus contention. Brief description of the invention The present invention provides a device and method for proving the encephalitis m and m-shaped busbars with a μ-pen. This Gaudi drawing style calendar * without the extra sibling or soft ... · " — · ·. SS driver, it can enhance the video graphics application in the computer system of the bus . The preferred specific example of the mildew brain system turtle 1 2 _ 攘 Xuanhuang articles (LEJWHJ, this sister piece is connected to a chip-by-chip input / output unit GENI 0 by a data bus, an I-chip chip-shaped interface. Interface & Welcome) ^ Six. A system memory is connected to GENCPU and a video memory is connected to GEHVGA. The GEHCPU is also connected to GENVGA via a high-speed bus (ΡΊ-bus). The GENCPU can be connected to GEHVGA via high-speed Pi-bus, and the frequency can be edited .... The graphics commands can be directly connected to the GEFFCPU to GENVGA, thus eliminating the delays associated with the slower standard system _streaming line. By using Pi-bus, the GENCPU can (please read the back-to-back precautions # Code Writer _ Install & Line-The paper size Λ uses the Chinese National Standard (CNS) T &1; 1 regulation (210x297 public; ": ) 81. 7. 20.000 ^ (11) Λ 6 η 6 The Ministry of Economic Affairs, the Central Bureau of Economic Development, Beigongxiao ftv cooperation Du Yin ¾ V. Description of invention U) Communicate with GEN VGA without having to put the instruction in a more cramped On the system bus. ... r ^ 'Receive an address • Decode this address and use its scratchpad * to determine whether the target address corresponds to GENVGA. If the target address corresponds to the GEHVGA space, if the Pi-bus is dared to move, the GEHCPU will start -Pi-bus selection. GENCPU indicates the cycle status indication (whether this cycle is an input / output or memory cycle and whether it is a read or write cycle) and places the instruction on the high-speed Pi-bus connecting GEHCPU and GENVGA. The GENCPU also generates a start signal, PSTART #, to indicate the start of the Pi-bus cycle. GENVGA supervises the signal from GENCPU. When receiving the signal from GENCPU, it decodes the input command and the command received by Benshi. The GENCPU sends a PCMDI »command K to indicate that the Pi-bus cycle is in progress. When GENVGA completes part of its Pi-bus cycle, GENVGA sends a PRDY # signal back to GENCPU. The GENCPU completes its Pi-bus cycle by stopping the PCMD # signal. Figure 1 is a functional block diagram of a microprocessor system embodying the present invention. The Pi-bus shown is separated from control, address and data. Fig. 2 is a timing diagram of a signal having a singularity with the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a device for implementing high-speed graphics bus and copying for the brain system. In the following description, many details of gambling are explained, so that it is correct (please read the backing notes first and then fill out this book, install-order · thread · this paper method standard side use S standard (CNS) T4 Specifications (2) 0χ2ί} 7 priests) 81. 7. 20,000 ^ (j |) 305965 V. Description of the invention (5) The present invention has a thorough understanding. However, for those who have been generally practicing in this technology, this Other specific details are used without a box to implement the present invention. In other examples, the structure of the well-known circuit circuit agreement is not shown in detail, so that the features of the present invention will not become obscure. See now Figure 1, a preferred embodiment of the computer system of the present invention is shown in the figure. In this preferred embodiment, the 'computer system 10 includes a 3 8 6 TMSL ^ processor' which is manufactured by Intel Corporation * This company It is also the recipient of this invention. This brain-required system is compatible with IBMtm PC AT. It is compatible with the IBMtm PC AT. The gas system 10 is the primary and secondary sibling piece of each piece of jade. It ’s named after CP ”.. 20, GENI0 30, GpNVGA 40. GENCPU 20 cooperates with GENI0 30 ’s sister, but this sister has no change as shown in this article The product name is 386TMSL Microprocessor Superset. The GENCPU 20 is an expansion, processing component; including a processing $ _, a note-__.------- Recall Controller • A cache memory controller • Streaming control device * line buffer. A series of memory 80 is connected to GENCPU 20. System memory 80 mainly includes dynamic random access memory (DRAM) devices. GENI0 30 It is a single chip I / O unit, including parallel port, double serial port, real-time clock unit, double programmable interrupt controller, double programmable timer, double direct memory access controller and A memory mapper. GENI0 30 also includes a programmable temporary memory for GENCPU 20. M commands GENI0 30 to implement different functions. The Central Bureau of Economic Affairs of the Ministry of Economic Affairs only works to eliminate crime and cooperate with Duin 5i (please read the details first Note the following Aa write :, GEHVGA 40 is a single chip display device, which includes a graphics interface and a video memory controller. The video memory controller is connected to GEHVGA 40. Video memory 50 essentially includes a DRAM device .GENVGA 4 0 also includes for the paper-scale use of the middle-aged 漳 楳 iMCNS) A Ί specifications (210X297 male dragon) 81. 7. 20.000 sheets (II) The Ministry of Economic Affairs is accurate and the 3 industry consumer price cooperatives Indian slave Λ fi ___ Β 6 _ V. Description of invention (6) The programmable register used by GENCPU 20, M commands GENVGA 40 to implement various functions. GENCPU 20, GENI0 30, GENVGA 40 communicate with each other and other system components via the system bus 11 (such as expansion slot * keyboard controller, disk controller, etc.). In this preferred embodiment, the system bus 11 is an AT compatible bus. Such busbars are well known in this art. In the present invention, the GENCPU-20 tone is transferred from the high-speed bus 60 to GENVGA. This high-speed bus 60 (also called Pi-bus) is located between GENCPU 20 and GENVGA 40. It is used to change the video memory and storage of 10.----. Take time, so eliminate the bus 11 "Bus Bottleneck". This bus allows video data to be moved into and out of the video memory at high speed. Therefore, the video-shaped application running on the IBM PC will have improved performance when applied to the present invention. No special software is required when using the Pi-bus protocol. Park 1 shows the Pi-bus interface between GEHCPU 20 and GEHVGA 40. The Pi-bus agreement will be explained later. f In most existing systems, the processing sisterware communicates with the display sisterware via the system bus 11 such as AT Bus. However, according to the novel structure of the present invention, GEHVG A shares the data and address lines of the PC-series busbar 11, and in addition to receiving the control signal of the normal busbar bus 11, it also accepts the If signal of Pi-Bus 60 ^ Pi-Bus The individual signals provided on 60 include the following: a start signal (represented by WPSTART #), a command signal (represented by p CMD #), a memory or I / O access type signal (represented by KPMI0 #), a read or Write access signal (indicated by PWR #), a ready signal (MPRDY # table (please read the backing notes first # 蜞 写 本 Ty This paper size is used in the "« Home "MMCNS) Ή specification (210x297 Public: ¢)
81. 7. 20.000张（W81. 7. 20.000 sheets (W
五、發明説明（7) (請先閲讀背而之注意事項#堝寫本7 示）。此等Pi-Bus信號係用以控制資料自GENCPU 20與 GENVGA 40之間來往之控制’而無需使用系铳匯流排線路 。此等Pi-Bus信號之順序將於下節中說明並於圖2中之定 時圖中例示。 GENCPU包括二暫存器，以GAACR 21及GABCR 2.2表不’此 二暫存器係用以啟動Pi_Bus 60 。暫存器GAACR 2JJB Η峰 存視頻記憶之m梦址。暫存f GABCR...._?1里儲存視踔緊 憶之終止位址。暫存器21及22共同界定視頻記憶中位址空 —-------------------------------—......... ^_.·—·· 間。此二暫存器GAACR 21及GABCR 22亦包括一位元Μ啟用 Pi-Bus。此位元必須設定以啟用Pi-Bus，俾使Pi-Bus周期 能送至視頻記億範圍。因此當_令由GENCPU 20取得並且 執行時，與每一指令相關之位址，可與由暫存器GAACR 21及GABCR 22界定之位址空間相比較。如果一指令包括由 此二暫存器界定而且位於視頻記憶範圍内之一位址’及如 果Pi-Bus位元被啟用，則Pi-Bus被啟用以直接至視頻記憶 中存取，因而使GENCPU 20直接發出位址信號至GENVGA 40 。由GENCPU 20直接達視頻記憶，可由PI-BusM高於 經沭部屮央樑準局β工消"合作社印31 系统匯流排11所提供之速度完成。一旦Pi-Bus 60被啟用 • GENCPU 20及GENVGA 40即產生信號供所有接逹 GENVGA 40中之視頻記憶或_出人暫存器之用。Pi-Bus信 號之定序說明如下。 GENCPU 20自系铳記憶80之取得及執行指令之正常流程 中取得一输入/输出或記憶存取指令。每一输入/输出或 記憶存取指令包括一作業碼部分及位址部分。作業碼 9 - 本紙張尺度边用中88家楳準（CNS)T4规格（2]0Χ297公货） 81. 7 . 20.000¾ (II) 經济部屮央榀準^A工消"合作杜印奴 Λ 6 _ _Π6_ 五、發明説明（8) ' (opcode)對一特定位址之資料實施特定之操作。視頻記憶 中之資料可以此種方式調處。 於取得一输入/输出或記憶存取指令之後，GENCPU 20 將此指令解碼*俾決定指令之目標位址。此目標位址告知 GENCPU作業碼將予實施之位址。GENCPU然後使用GENCPU 20暫存器GAACR 21及GABCR 22比較目檷位址。如果此目標 位址相應於暫存器GAACR 21及GABCR 22中所程式規晝之 GENVGA空間40，及如果Pi-Bus 60被啟用，則GENCPU 20 啟始一 Pi-Bus周期。如果位址並非位於由GENCPU 20之暫 存器GAACR 21及GABCR 22所界定之GENVGA範圍中，則指令 v即置於系统匯流排11之上。 為能啟始一 Pi-Bus 60周期，GENCPU 20產生圖2中所 示之有如PSTART #102之啟始信號。此PSTART信號然後由 GENCPU置於高速Pi-bus 60之上。因此，GENCPU 20能送 控制信號直接至GENVGA 40 ，而無需使用系统匯流排11。 GEHVGA 40使用PSTAIU之下降邊緣Μ鎖住位址及狀態信號 0 了旦G Ε N C P U放始一 Ρ I - bus周期，GENCPU 20產生相應於 GENVGA 40之一 VGACS指令及將此指令之位址置於 Pi-bus 60之上。GENCPU 20亦指示其置於高速Pi-bus 60上之指令周期之狀況。GENCPU 20指示指令之周期是否 為一I/O或記憶周期（ΡΜ/Ι0#)或是否為一讀出或寫入周期 (PW/Rtt)。此等事件之定序經顯示於圖2中101處。 GENVGA 40就GENCPU 20所送出之信號監督高速 (請先閲誚背而之注意事項#蜞窍本7- - 10 - 本紙张尺度边用中a國家楛準（CNS)T4規格（2丨0X297公釐） 81. 7 . 20.000ik(H) 經濟部中央櫺準局CX工消作合作社印览 Λ 6 _ η 6 _ 五、發明説明（9) · Pi-bus 60 。當GEHVGA 40接收指示Pi-bus周期啟始之 P S T A R T #信號時，G Ε Μ V G A 4 0選擇高速P I - b u s 6 0 °於選 擇Pi-bus 60時，GENVGA 40接收來自高速Pi-bus 60之 控制信號及來自系铳匯流排11且對應於GENVGA空間40之位 址信號及資料。GENVGA 40經由高速Pi-bus 60接收來自 GENCPU 20之指令之後，即檢査此指令，俾便決定自 G E N C P U 2 0經高速P I - b u s 6 0發出之指令周期是否為一 I/O或記憶周期及是否為一讀出或寫入周期。 GENCPU 20經高速Pi-bus 60發出PSTART#信號至 GENVGA 40之後*即停止PSTART#信號及將一 PCMD#信號 置於高速Pi-bus 60之上。此PCMDU信號指示一 Pi-bus 周期正在進行。圖2於 103處例示PCHD#之定時。此外， 如果由GENCPU 20置於高速Pi-bus 60上之指令周期係為 寫入周期，則GENCPU 20於此時迫使對應於寫入周期之資 料置於資料匯流排之上。GEH VGA 40然後接收對懕於寫入 周期之資料。圖5於105及106處例示何時讀出及寫入資料 置於高速Pi-bus 60之上。 當GEHVGA 40業已收到由GENCPU 20所送出之全邡對應 於GENVGA空間40之指令及藉載人記憶或I/O暫存器而完成 此周期時· Pi-bus周期即完成。GENVGA 40此時將PRDYII 信號置於高達Pi-bus 60上，指示GEHVGA 40樂已完成其 PI-bus周期部分，此即GENVGA 40業已收到全部包括於比 周期中來自G E N C P U 2 0之指令及現在通知G E H C P U 2 0高速 Pi-bus 60不再忙碌。PRDYI♦信號之定時顯示於圖2之 (請先閲讀背而之法意事项孙填窍本_ 裝- - 11 - 本紙张尺度边用中a 8家棕準（CNS) T4規格（210x297公釐) 81. 7. 20.000^ <'·) 305965 Λ 6 η 6 五、發明説明（10) 1 0 4 處。 GENCPU 20接收到來自GEHVGA 40之PRDYtt信號後， GENCPU 20即停止PCMD#信號，因而終止Pi-bus周期。於 高速Pi-bus 60上無PCMD#信號即表示於高速Pi-bus 60上 無周期進行。因此GENCPU可依裔啟始一新的Pi-bus周期。 由於使用PI-bus60 ，可發現有数種優點。Pi-bus周期 之最小周期時間，較之使用摞準系统匯流排之現有系铳有 遠為較快之最小周期時間。同樣，PI-bus周期之零等待ί狀 態時間較系統匯流排周期之等待狀態時間為短。 PI-bus周期之另一優點為在無需軟體驅動程式實龜请^ TU圖I性能直顧著增_。所有相容软體均可在無需修 改情況下於具有Pi-bus之糸統上實施。最後PI-bus周期議 定不僅限於視頻圖形應用。任何快速邊控制器均可使用 Pi-bus型協定用為增進系统性能之手段。 可認知者，上述之發明，在不背離本文所掲示之精神或 主要特點之情況下’可以其他特定形式實施。因此可瞭解 者，本發明不受前述例示性细節所限制，而係由所附申請 專利範圔所界定。 經濟部屮央檁準，^工消奸合作杜印5i 2 11 本紙張尺度逍用中國Η家楳準（CNS)甲4規怙（210x297公龙） 81. 7. 20.〇〇〇iMH)5. Description of the invention (7) (please read the notes on the back ## Script 7). These Pi-Bus signals are used to control the flow of data from GENCPU 20 to GENVGA 40 without using a system bus line. The sequence of these Pi-Bus signals will be explained in the next section and exemplified in the timing diagram in Figure 2. The GENCPU includes two registers, represented by GAACR 21 and GABCR 2.2. These two registers are used to enable Pi_Bus 60. Scratchpad GAACR 2JJB Η 峰 Stores the dream location of the video memory. Temporarily store f GABCR ...._? 1 to store the end address of the recollection. The temporary memory 21 and 22 jointly define the address space in the video memory ----------------------------------------------... ...... ^ _. · — ·· between. The two registers GAACR 21 and GABCR 22 also include one bit M-enabled Pi-Bus. This bit must be set to enable Pi-Bus, so that the Pi-Bus cycle can be sent to the video billion range. Therefore, when the _command is acquired and executed by the GENCPU 20, the address associated with each instruction can be compared with the address space defined by the registers GAACR 21 and GABCR 22. If a command includes an address defined by these two registers and located within the range of video memory, and if the Pi-Bus bit is enabled, then Pi-Bus is enabled for direct access to the video memory, thus enabling GENCPU 20 directly sends the address signal to GENVGA 40. The video memory can be directly accessed by the GENCPU 20, which can be completed at a speed higher than that provided by the PI-BusM at the speed provided by the busbar 11 of the system 31 of the Yangshuo Department of Economics and Trade Bureau. Once Pi-Bus 60 is enabled • GENCPU 20 and GENVGA 40 will generate signals for all the video memories or _entry registers in GENVGA 40. The sequence of Pi-Bus signal is explained as follows. The GENCPU 20 obtains an input / output or memory access command from the normal flow of acquiring and executing commands of the memory 80. Each input / output or memory access command includes an operation code part and an address part. Operation code 9-This paper uses 88 Chinese standard (CNS) T4 specifications (2] 0Χ297 public goods) 81.7. 20.000¾ (II) Bi Yang, the Ministry of Economic Affairs ^ A 工 消 " Cooperative Du Yin Slave Λ 6 _ _Π6_ V. Description of the invention (8) '(opcode) Implement specific operations on data at a specific address. The data in the video memory can be adjusted in this way. After obtaining an input / output or memory access command, the GENCPU 20 decodes the command to determine the target address of the command. This target address informs the address where the GENCPU operation code will be implemented. GENCPU then uses the GENCPU 20 registers GAACR 21 and GABCR 22 to compare the destination addresses. If the target address corresponds to the GENVGA space 40 programmed in registers GAACR 21 and GABCR 22, and if Pi-Bus 60 is enabled, GENCPU 20 starts a Pi-Bus cycle. If the address is not within the range of GENVGA defined by the registers GAACR 21 and GABCR 22 of the GENCPU 20, the command v is placed on the system bus 11. In order to start a Pi-Bus 60 cycle, the GENCPU 20 generates a start signal like PSTART # 102 shown in FIG. 2. This PSTART signal is then placed on the high-speed Pi-bus 60 by the GENCPU. Therefore, the GENCPU 20 can send the control signal directly to the GENVGA 40 without using the system bus 11. GEHVGA 40 uses the falling edge of PSTAIU to lock the address and status signal. Once G ΕΝCPU starts a PI-bus cycle, GENCPU 20 generates a VGACS command corresponding to GENVGA 40 and places the address of this command in Above Pi-bus 60. The GENCPU 20 also indicates the status of the instruction cycle placed on the high-speed Pi-bus 60. The GENCPU 20 indicates whether the cycle of the instruction is an I / O or memory cycle (PM / Ι0 #) or whether it is a read or write cycle (PW / Rtt). The sequence of these events is shown at 101 in FIG. 2. GENVGA 40 supervises the high speed of the signal sent by GENCPU 20 (please read the notes before you # 蜞 妙 本 7--10-this paper is used in the national standard (CNS) T4 specification (2 丨 0X297 ) 81.7. 20.000ik (H) Printed by the CX Workers ’Cooperative of the Central Bureau of Economic Development of the Ministry of Economics Λ 6 _ η 6 _ 5. Description of the invention (9) · Pi-bus 60. When GEHVGA 40 receives the instruction Pi- When the PSTART # signal at the beginning of the bus cycle, G Ε ΜΜVGA 4 0 selects high-speed PI-bus 6 0 ° When Pi-bus 60 is selected, GENVGA 40 receives the control signal from the high-speed Pi-bus 60 and from the system bus 11 and corresponds to the address signal and data of the GENVGA space 40. After the GENVGA 40 receives the command from the GENCPU 20 via the high-speed Pi-bus 60, it checks the command and decides to send it from the GENCPU 2 0 via the high-speed PI-bus 6 0 Whether the instruction cycle is an I / O or memory cycle and whether it is a read or write cycle. After the GENCPU 20 sends the PSTART # signal to the GENVGA 40 via the high-speed Pi-bus 60 *, the PSTART # signal is stopped and a PCMD # The signal is placed above the high-speed Pi-bus 60. This PCMDU signal indicates a positive Pi-bus cycle 2. Figure 2 illustrates the timing of PCHD # at 103. In addition, if the command cycle placed on the high-speed Pi-bus 60 by the GENCPU 20 is a write cycle, then the GENCPU 20 forces the data corresponding to the write cycle at this time Placed on the data bus. GEH VGA 40 then receives the data on the write cycle. Figure 5 at 105 and 106 illustrates when reading and writing data is placed on the high-speed Pi-bus 60. When GEHVGA 40 I have received the instructions from the GENCPU 20 corresponding to the GENVGA space 40 and completed this cycle by manned memory or I / O register. The Pi-bus cycle is completed. GENVGA 40 will now send the PRDYII signal Placed on Gundam Pi-bus 60, indicating that GEHVGA 40 has completed its PI-bus cycle part, that is, GENVGA 40 has received all the commands from GENCPU 2 0 included in the cycle and now informs GEHCPU 2 0 high-speed Pi- The bus 60 is no longer busy. The timing of the PRDYI signal is shown in Figure 2 (please read the countermeasures beforehand. Sun fills this book _ 装--11-This paper scale is used in a 8 home standard (CNS) T4 specification (210x297 mm) 81. 7. 20.000 ^ < '·) 305965 Λ 6 η 6 5. Description of the invention (10) 1 0 4 places. After the GENCPU 20 receives the PRDYtt signal from the GEHVGA 40, the GENCPU 20 stops the PCMD # signal, thus terminating the Pi-bus cycle. No PCMD # signal on the high-speed Pi-bus 60 means that there is no cycle on the high-speed Pi-bus 60. Therefore, the GENCPU can initiate a new Pi-bus cycle based on its descendants. Due to the use of PI-bus60, several advantages can be found. The minimum cycle time of the Pi-bus cycle is much faster than the existing system that uses the stacking system busbar. Similarly, the zero-wait time in the PI-bus cycle is shorter than the wait time in the system bus cycle. Another advantage of the PI-bus cycle is that without the need for software drivers, the performance of the TU diagram I is directly increased. All compatible software can be implemented on the system with Pi-bus without modification. The final PI-bus cycle agreement is not limited to video graphics applications. Any fast side controller can use Pi-bus protocol as a means to improve system performance. It is recognizable that the above-mentioned invention can be implemented in other specific forms without departing from the spirit or main features shown in this article. Therefore, it can be understood that the present invention is not limited by the foregoing exemplary details, but is defined by the appended patent application. The Ministry of Economic Affairs, the central purlin, ^ work elimination cooperation Du Yin 5i 2 11 This paper standard is easy to use Chinese 掳 楳 准 (CNS) A 4 regulations (210x297 male dragon) 81. 7. 20.〇〇iMH)