TW298668B - - Google Patents

Download PDF

Info

Publication number
TW298668B
TW298668B TW84100210A TW84100210A TW298668B TW 298668 B TW298668 B TW 298668B TW 84100210 A TW84100210 A TW 84100210A TW 84100210 A TW84100210 A TW 84100210A TW 298668 B TW298668 B TW 298668B
Authority
TW
Taiwan
Prior art keywords
substrate
semiconductor
item
leads
patent application
Prior art date
Application number
TW84100210A
Other languages
Chinese (zh)
Original Assignee
Yamaha Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaha Corp filed Critical Yamaha Corp
Application granted granted Critical
Publication of TW298668B publication Critical patent/TW298668B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明(1 ) 發明背景 a )發明領域 本發明係關於半導體裝置和半導體裝置之製法,該半 導體裝置適合使用於半導體積體電路。 b)習知技藝之說明 一種由稹體電路所形成之半導體晶片通常在容器之包 中和一配線板模製,而後安裝在一印刷電路板上。已知的 包封方法稱爲轉換模製法,其以例如環氧基之樹脂在一包 封中射出摸製半導體晶片。依照此方法,如圖8 A所示, 晶片2首先安裝在引線框1之中央部份之層1 a上,而後 ,在藉由鍵合金屬配線以連接墊P,P,____和內引線3a ,3 a____後,晶片2和引線框1以樹脂4射出模製。而 後,如圖8B所示,引線框1之外引線3b,3b____彎 成鳥翼形。而用以在模製和連接每對相鄰之外引線3 b, 3 b____時阻擋樹脂之堰桿乃切除。 圖9顯示另一半導體裝置S (例如,PC-QFP :三菱電 機之印刷電路四平坦包),其使用疊層框6以代圖8之引 線框。曼層框6具有之結構爲用以安裝晶片2之印刷電路 板7和內引線3 a,3 a連接。在此半導髋裝置S中介於 引線端間之節距可降低,因此,和圖8 A和8 B之半導體 裝置S比較下,其可增加引線端之數目。 圖1 〇爲使用金靥基底電路板之無引線晶片載髖(L CC)之另一半導體裝es (例如Mitsui-Toatsu化學公 司之MQP—LCC)。在圖中所示之半導體裝置S中, 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項#-填寫本頁) 訂 經濟部中央標準局貝工消費合作杜印製 A7 B7 _五、發明説明(2 ) 金屬基底電路板5具有一薄金屬膜10用以在金屬基底8 上配線。晶片2直接的黏著在金屬基底8之暴露表面上, 金屬基底8之兩端彎成丁字型。薄聚醯亞胺膜9形成在金 屬基底8上。薄金屬膜10之配線圖樣進一步形成在金靥 基底8上,並構成內和外引線。晶片2之墊P,P藉由配 線鍵合而與內引線連接。晶片2,配線W和形成內引線之 薄金靥膜1 0之部份以樹脂11包覆。此半導體裝置s不僅 可藉由縮小介於引線端間之節距而增加終端之數目,且亦 可因爲晶片2安裝在金靥基底8上而獲得良好的熱輻射。 在如圖8 A和8 B所示之半導體裝置S中,引線框由 蝕刻或沖壓而製成。由於引線部份之製造技術,介於內引 線間之節距之縮小乃受到限制。此時,介於內引線間之最 小節距爲0.21mm。爲了製造一較小的包封,引線框之厚度 必需較薄。小於上述値之節距在組件處理時運送相當困難 。再者,在轉換模製方法中,無可避免的使用堰桿以避免 在模製時樹脂之溢流。當介於外引線間之節距變成0.3mm 或更小時,堰桿之切割在技術上相當困難。 如圖9所示之半導體裝置S由於使用印刷電路板7取 代引線框1而具有較差之熱輻射性。晶片2因此會儲存熱 。因此,必需另外提供熱擴散器以供輻射用。再者,如圖 8 A和8 B所示之半導體裝置S之情形中,該裝置亦需要 堰桿,因此裝置之尺寸變大。再者,在引線框之製造處理 時,內引線和印刷電路板的連接會增加裝置之製造成本。 再者,在圖1 0所示之半導體裝置S中,金靥基底8 (請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家梯準(CNS > A4規格(210X297公釐) A7 298668 _B7____ 五、發明説明(3 ) (請先閲讀背面之注意事項再填寫本頁) 具有LCC結構,該LCC結構並未與每一引線分離,而 薄金靥膜10之圖樣置放在一平面上。因此,可輕易的形 成橋,而在批次方式中焊接之軟熔相當困難。由於L C C 結構,在包封後之檢視相當困難。再者,由於金靥基底8 具有高熱導性,在包封處理時,熱並不必然集中在外引線 安裝至印刷電路板之位置,因此,會輕易發生包封缺點。 如圖8 A和8 B所示,具有鳥翼形之分離外引線由本體凸 出並吸收在包封處理時所產生之熱應力。相反的,由於具 有如圖10所示之結構之金靥基底8並未與分離成引線, 因此,熱應力之吸收相當困難。因此,會產生印刷電路板 一丨丨"" _· - · _ 丨丨丨-------»- 之彎曲和扭曲〇 發明概要 本發明之目的乃在提供一種半導體裝置和半導體裝置 之製法,其可同時降低裝置之尺寸和介於引線間之節距。 經濟部中央標準局員工消費合作社印製 依照本發明之觀點,於此提供一種半導體裝置,包含 :一基底,其承載構成多數引線之薄金靥層:一半導體晶 片安裝在該基底上;一絕緣樹脂構件密封該半導體晶片和 多數引線之內部份;和多數的箝夾引線,其包括具有箝夾 平面物件和自我支撑功能之多數箝夾部份,具有導電性, 且和引線接觸並與其電連接。 依照本發明之另一觀點,於此提供一種用以製造半導 體裝置之方法,包含之步驟爲: 膜片鍵合半導體晶片在表面上具有多數絕緣引線之基 底上; 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) 經濟部中央標準局貝工消費合作社印裝 A7 B7_ 五、發明説明(4 ) 應用絕緣樹脂以覆蓋該半導體晶片和引線之部份:和 將箝夾板組件接附且電連接至基底之引線,箝夾板組 件具有多數之外引線和箝夾平面構件之功能至基底以電連 接外引線和引線。 (1)當內引線由鍵結半導體晶片之基底上之薄金靥 膜所形成時,引線間的節距可降低。 (2 )當包封後應用外引線時,用以避免樹脂溢流之 堰桿變成不必要。且藉由選擇基底之材料以獲得高的熱傳 導率,熱擴散器亦不需要。因此,半導體裝置之尺寸可降 低0 (3 )當包封後外引線受到接合,事先形成鳥翼狀之 外引線可連接。因此,可簡化半導體裝置之製造方法。而 當外引線事先提供測試墊時,測試可相當容易的進行。 附圖簡述 圖1A至1D爲依照本發明之實施例之半導體裝置之 結構之截面圖; 圖2爲依照圖1 A至1 D之寅施例之半導體裝置之製 法之流程圖; 圖3爲在半導體裝置中使用之金肩基底電路板MB之 平面圖; 圖4 A和4 B爲在半導體裝置中使用之箝夾引線1 3 之側面圖和平面圖,圖4 C爲箝夾引線耦合至電路板之圖 9 圖5A和5B爲半導體裝®之箝夾引線14之側面圖 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標隼局員工消費合作社印製 A7 B7 五、發明説明(5 ) 和平面圖: 圖6A和6B爲半導體裝®之箝夾引線14之側面圖 和平面圖: 圖7爲依照本發明之另一實施例之半導髋裝置之側視 圖: 圖8 A和8 B爲習知半導體裝置之圖,其中圖8 A爲 在形成外引線3 b之處理前,外引線之狀態,而圖8 B爲 形成處理後之狀態概略圖: 圖9爲習知半導體裝置之另一型態之截面圖;和 圖10爲習知半導體裝置之另一型態之截面圖。 較佳實施例之說明 以下,本發明之實施例將參考附圖說明。圖1 A爲依 照本發明之實施例之半導體裝置之結構之截面圖。在圇中 ,以皆是金雇板之觀點而言,金靥基底8相似圖1〇中之 金屬基底8,且其爲平面形狀。聚醯亞胺膜9施加在金靥 基底8上以覆蓋金靥基底8之週邊之兩表面和側表面。形 成引線之電路配線圖樣之Cu-Ni-AU薄金屬膜選擇性的鍍在 聚身亞胺膜9上。引線之內部份構成內引線 在D I Ρ (雙列直插式外設)之情形中,其中內引線 形成在金屬基底8之相反側,內引線構件可以如圖所示之 形狀黏著在金靥基底8上,該內引線構件爲帶形狀,其以 薄金屬膜^之配線圖樣形成在聚醯亞胺膜上。 因此,金屬基底8和薄金屬膜1 0構成電路板。電路 板5可爲單層或多層板。如圖所示之金觴基底8之下表面 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(6 ) 之中央部份乃暴露,且晶片2安裝在暴露金靥基底上。鍵 合埜P形成在晶片2之表面上,亦即,圖中之下表面。電 路板之厚度約爲0.15〜1.5mm 。電路板之面稹約爲7mm2 〜4 0 mm2。電路板經由蝕刻或沖壓成型以形成。 在晶片2上之墊P,P藉由配線鍵合而與內引線部份 1 2連接。晶片2,配線W,和內引線部份1 2以樹脂11 (例如環氧樹脂)包覆。再者,以鳥翼形構成外引線之箝 夾引線14接合至未包覆樹脂之薄金靥膜圖樣10之外部 份。箝夾引線1 4由當成彈簧使用之金靥(如鐵合金,銅 合金等)所形成,具有彈性,並構成具有自我支撑功能之 嵌夾。箝夾引線14由多數條形板構件所組成,每一該條 形板構件相關於相連之薄金屬膜圖樣1 0。箝夾引線1 4 以蝕刻或沖壓成型而形成。箝夾引線1 4之厚爲0.15mm 或更小。 電路板5準備成引線框之形狀。如圖3所示,金屬基 底配線板MB具有鑿出空間(間隙部份SP之金靥板形狀 ,且每個金屬基底8,8 .....由懸垂銷1 5,1 5----經由 空間部份S P,S P____支撑至金屬基底配線板MB。因 此,藉由形成金靥基底8,8____以引線框之形狀,習知 膜片鍵合和配線鍵合之處理可直接的應用。雖然圖3中未 顯示,如圖1 A所示之聚醯亞胺膜9和薄金靥膜1 〇形成 在每一金靥基底8,8____上。 以下,如圖1 A所示之半導體裝置之製.造方法將參考 圖2說明。在步驟S 1中,晶片2膜片鍵合在金屬基底8 本紙張尺度適用中國國家標隼(CNS〉A4規格(21〇Χ29>7公釐) (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局貝工消費合作社印製 298668 A7 B7 五、發明説明(7 ) 之中央部份。而後,在步驟S 2中,在晶片2上之每個墊 P,P——和薄金屬膜1 0之相關內引線部份12以配線鍵 合連接。在步踝S3中,晶片2,配線W,和內引線部份 1 2以樹脂1 1包覆模製。其次,在步驟S4中,切斷在 金靥基底之四個角落之懸垂銷1 5,1 5......以使金屬 基底分離。 而後,在步驟S 5中,箝夾引線1 4接合在金靥基底 。在圖4A和4B中,顯示箝夾引線組件14之側視圖和 平面圖。如圖4 A所示,每個箝夾引線組件14之一端爲U 形以形成箝夾部份C L,且在箭頭A所示之方向具有彈性 。藉由箝夾部份C L箝夾電路板5之端部份,箝夾引線14 受到固定,箝夾引線和薄金屬膜10電性的連接。箝夾引線 1 4之一端由繫桿1 6所連接,而另一端由基桿1 7所連 接。箝夾引線組件在相關位置最好具有凸出和凹陷,以互 相嵌合,以作位置之對準。凸出可形成在電路板5之角落 上,藉由引導箝夾引線組件1 4之側表面,以確保箝夾引 線14和板5之對準,如圖4C所示。 而後,箝夾引線組件1 4之引線端L,L____彎曲成 圖1所示之鳥翼形狀。在步驟S 6中,箝夾引線1 4之端 部份受到焊接軟熔。而後,在步驟S 7中,切除箝夾引線 組件1 4之繫桿1 6和基桿1 7。並在步驟S 8中進行各 種測試以檢視電路功能,特性等。而後,此具有良好品質 之半導體裝置可銷售至市場中。或是在步騄S 7中,只除 去繫桿1 6,而基桿1 7可在交付後由客戶自行除去。 本紙浪尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) (請先閲讀背面之注意事項再填寫本頁) 訂 -10 - _B7_ 五、發明説明(8 ) 電路板之形狀並不受限於圖1 A所示。在圖1 B和 1 D中,顯示其他型態之電路板之例。 在圖1 B中,聚醯亞胺膜9 a和9 b形成在金屬基底 8之主頂和底表面上,且薄金靥膜1 0只形成在聚醯亞胺 膜9 b之一上。由於聚醯亞胺膜9 a和9 b只形成在金靥 基底8之主表面上,它們可以利用印刷的方法形成。雖然 金屬基底8之側表面暴露,藉由使聚醯亞胺膜9 a和9 b 過懸垂,則亦可避免箝夾引線之短路情形。雖然薄金靥膜 10只形成在金屬基底8之一表面,如果其可在低電阻下 與箝夾引線連接,亦不會發生任何問題。於此,薄金靥膜 亦可形成在另一聚醯亞胺膜9 a上當成一虛擬物。藉此, 在接合箝夾引線時聚醯亞胺膜9 a可以受到保護。 在圖1C中,電路板5由絕緣基底19和形成在絕緣 基底19上之薄金屬膜圖樣11所構成。此電路板具有和 印刷電路板相同的結構,且可利用相似的製造方法製造。 經濟部中央標準局負工消費合作社印製 圖1D爲圖1B之印刷電路板5形成多層之結構。聚 醯亞胺膜9 a和9 c形成在金靥基底8上。第一配線層 1 0 b形成在聚醯亞胺膜9 c上。聚醯亞胺膜9 b進一步 形成在第一配線層1 0 b上,接著形成引線之薄金靥膜 1 〇 a。以接合引線銷之觀點而言,多層電路板乃和圖 1 B之電路板相似。而圖1 C所示之電路板可以修飾成類 似具有多配線層。對於熟悉此項技藝之人士而言,明顯的 是,三層或更多層之電路板可以利用和雙餍電路配線相同 之方式形成。 本紙張尺度適用中國國家標準(CNS > A4規格(210X297公釐) 11 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(9 ) 箱夾引線組件14之另一實施例如圖5 A和5 B所示 。如圖5 B所示,引線L之每一端部份上具有測試墊1 8 ,1 8....。如圖5A所示,端部份藉由聚醯亞胺層1 9 而黏著至基桿1 7。在引線接合至電路板5之後,藉由切 除繫桿1 6,每個引線L.乃電絕離,因此可操作和測試半 導體裝置。在測試後,切除測試埜1 8。因此,藉由使用 預先提供測試墊1 8,1 8....之箝夾引線,半導體裝置 之測試變的相當容易。 箝夾引線組件14之另一實施例如圖6A和6B所示 。引線之外引線部份1 3膂曲成如圖6A所示之鳥翼形狀 。如圖6B所示,引線1 4具有測試墊1 8,1 8____, 位在每個引線L之端部份上。具有測試墊之端部份以聚醯 亞胺層1 9黏著至基桿1 7。由於完成形成處理之引線會 輕易變形,其應用上相當困難。但是,由於引線在後續中 接合,在本賁施例中不會具有上述之問題。 如圖7所示,聚醯亞胺膜9和薄金靥圇樣10可只形 成在金靥基底之底表面上。外引線2 0可使用熱壓鍵合而 接合至薄金靥膜10之端部份。 於此,在圖1 A至1 D和圖7所顯示之半導體裝置中 ,當使用面下鍵合以將裝置安裝在印刷電路板上時,可利 用晶片.安裝器。 本發明已利用較佳實施例說明如上。但是,本發明並 不受限於實施例中所說明的。對於熟悉此項技藝之人士而 言,明顯的是,各種的變化,取代,結合和改進仍未能悖 本紙張尺度適用中國國家標隼(CNS > Λ4規格(210X297公釐) (請先閲讀背面之注意事項馮填寫本頁) -9 12 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(10 ) 離本發明申請專利範圍之精神和範疇。 (請先閲讀背面之注意事項再填寫本頁) 衣· 訂 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐)Printed by Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of the invention (1) Background of the invention a) Field of the invention The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, which is suitable for use in semiconductor integrated circuits. b) Description of conventional techniques A semiconductor wafer formed from a ballast circuit is usually molded in a container package with a wiring board and then mounted on a printed circuit board. A known encapsulation method is called a conversion molding method, which ejects a molded semiconductor wafer in a encapsulation with a resin such as epoxy. According to this method, as shown in FIG. 8A, the chip 2 is first mounted on the layer 1a of the central part of the lead frame 1, and then, the pads P, P, ____ and the inner leads are connected by bonding metal wiring After 3a, 3a____, the wafer 2 and the lead frame 1 are injection molded with resin 4. Then, as shown in FIG. 8B, the leads 3b, 3b__ outside the lead frame 1 are bent into a bird wing shape. The weir rod used to block the resin when molding and connecting each pair of adjacent outer leads 3 b, 3 b____ is cut off. FIG. 9 shows another semiconductor device S (for example, PC-QFP: Mitsubishi Electric ’s printed circuit quad flat pack), which uses a laminated frame 6 instead of the lead frame of FIG. 8. The man layer frame 6 has a structure for connecting the printed circuit board 7 for mounting the wafer 2 and the inner leads 3 a, 3 a. In this semiconducting hip device S, the pitch between the lead ends can be reduced, and therefore, compared with the semiconductor device S of FIGS. 8A and 8B, it can increase the number of lead ends. Fig. 10 is another semiconductor device (such as MQP-LCC of Mitsui-Toatsu Chemical Co., Ltd.) using a leadless chip carrier (L CC) of a gold-thorium based circuit board. In the semiconductor device S shown in the figure, this paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the notes on the back # -fill in this page). Consumer Cooperation Du Printed A7 B7_V. Description of the invention (2) The metal base circuit board 5 has a thin metal film 10 for wiring on the metal base 8. The wafer 2 is directly adhered to the exposed surface of the metal substrate 8, and both ends of the metal substrate 8 are bent into a T-shape. A thin polyimide film 9 is formed on the metal substrate 8. The wiring pattern of the thin metal film 10 is further formed on the gold-titanium substrate 8, and constitutes inner and outer leads. The pads P, P of the chip 2 are connected to the inner leads by wire bonding. The wafer 2, the wiring W and the portion of the thin gold film 10 forming the inner leads are covered with resin 11. This semiconductor device s not only can increase the number of terminals by reducing the pitch between the lead ends, but also can obtain good heat radiation because the wafer 2 is mounted on the gold-solar substrate 8. In the semiconductor device S shown in FIGS. 8A and 8B, the lead frame is made by etching or stamping. Due to the manufacturing technology of the lead part, the narrowing of the pitch between the inner leads is restricted. At this time, the minimum pitch between the inner leads is 0.21 mm. To make a smaller package, the thickness of the lead frame must be thinner. Pitches smaller than the above values are quite difficult to transport during module handling. Furthermore, in the conversion molding method, weirs are inevitably used to avoid overflow of resin during molding. When the pitch between the outer leads becomes 0.3 mm or less, the cutting of the weir rod is technically quite difficult. The semiconductor device S shown in FIG. 9 has poor heat radiation because the printed circuit board 7 is used instead of the lead frame 1. The chip 2 will therefore store heat. Therefore, it is necessary to additionally provide a heat spreader for radiation. Furthermore, in the case of the semiconductor device S shown in FIGS. 8A and 8B, the device also requires a weir, so the size of the device becomes larger. Furthermore, during the manufacturing process of the lead frame, the connection of the inner lead and the printed circuit board increases the manufacturing cost of the device. In addition, in the semiconductor device S shown in FIG. 10, the gold-based substrate 8 (please read the precautions on the back before filling in this page). The paper size is applicable to China National Standards (CNS & A4 specifications (210X297 ) A7 298668 _B7____ 5. Description of the invention (3) (please read the precautions on the back before filling in this page). It has an LCC structure, which is not separated from each lead, and the pattern of thin gold film 10 is placed On a plane. Therefore, the bridge can be easily formed, and the soldering in the batch mode is very difficult. Due to the LCC structure, the inspection after the encapsulation is very difficult. Furthermore, because the gold-based substrate 8 has a high thermal conductivity In the process of encapsulation, heat is not necessarily concentrated at the location where the outer leads are mounted on the printed circuit board, so encapsulation defects can easily occur. As shown in FIGS. 8 A and 8 B, the separated outer leads with a bird wing shape It protrudes from the body and absorbs the thermal stress generated during the encapsulation process. On the contrary, since the gold-solar substrate 8 having the structure shown in FIG. 10 is not separated into leads, it is quite difficult to absorb the thermal stress. Therefore, it will produce Printed circuit board 1 丨 丨 " " _ ·-· _ 丨 丨 丨 丨 -------------- bending and twisting Summary of the invention The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, It can simultaneously reduce the size of the device and the pitch between the leads. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs According to the view of the present invention, a semiconductor device is provided here, including: a substrate that carries the majority of the leads Thin gold layer: a semiconductor wafer is mounted on the substrate; an insulating resin member seals the semiconductor wafer and the inner part of the majority of leads; and most of the clamp leads, which include the majority with flat objects and self-supporting functions The clamping part has electrical conductivity, and is in contact with and electrically connected to the lead. According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, including the steps of: bonding a semiconductor wafer to a diaphragm On the substrate with most insulated leads on the surface; the paper size is applicable to China National Standard (CNS) Α4 specification (210X 297 mm) in the Ministry of Economic Affairs Standard Bureau Beigong Consumer Cooperative Printed A7 B7_ V. Description of the invention (4) Apply insulating resin to cover the semiconductor chip and the lead: and the lead to attach and electrically connect the clamp plate assembly to the substrate, the clamp plate assembly has Most of the functions of the outer leads and the clamp flat member are connected to the substrate to electrically connect the outer leads and the leads. (1) When the inner leads are formed of a thin gold film on the substrate of the bonded semiconductor wafer, the pitch between the leads can be Reduced. (2) When outer leads are applied after encapsulation, weirs to avoid resin overflow become unnecessary. And by selecting the material of the substrate to obtain high thermal conductivity, a heat spreader is also not required. Therefore, The size of the semiconductor device can be reduced by 0 (3) When the outer leads are bonded after the encapsulation, the outer leads formed in a bird-wing shape can be connected in advance. Therefore, the manufacturing method of the semiconductor device can be simplified. When the outer leads provide test pads in advance, the test can be performed quite easily. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1D are cross-sectional views of the structure of a semiconductor device according to an embodiment of the present invention; FIG. 2 is a flowchart of a method of manufacturing a semiconductor device according to the embodiment of FIGS. 1 A to 1 D; A plan view of a gold-shoulder base circuit board MB used in a semiconductor device; FIGS. 4 A and 4 B are side and plan views of a clamp lead 1 3 used in a semiconductor device, and FIG. 4 C is a coupling of a clamp lead to a circuit board Figure 9 Figures 5A and 5B are side views of the clamp leads 14 of Semiconductor Pack®. The paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back and fill in this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 5. Description of the invention (5) and plan view: Figures 6A and 6B are side and plan views of the clamping leads 14 of Semiconductor Pack®: Figure 7 is another example according to the present invention A side view of a semi-conducting hip device of an embodiment: FIGS. 8 A and 8 B are diagrams of conventional semiconductor devices, where FIG. 8 A is the state of the outer lead before the process of forming the outer lead 3 b, and FIG. 8 B For a schematic view of the state after the formation process: Figure 9 A cross-sectional view of another conventional type of semiconductor device; and FIG. 10 is a cross-sectional view of another conventional type of semiconductor device. Description of preferred embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a cross-sectional view of a structure of a semiconductor device according to an embodiment of the present invention. In Huo, from the viewpoint that they are all gold plates, the gold base 8 is similar to the metal base 8 in FIG. 10, and it has a planar shape. The polyimide film 9 is applied on the gold-thallium substrate 8 so as to cover both peripheral surfaces and side surfaces of the gold-thorium substrate 8. The Cu-Ni-AU thin metal film forming the circuit wiring pattern of the lead is selectively plated on the polyimide film 9. The inner part of the lead constitutes the inner lead in the case of DI Ρ (Dual In-line Peripheral), where the inner lead is formed on the opposite side of the metal substrate 8, and the inner lead member can be adhered to the gold plume as shown in the figure On the substrate 8, the inner lead member has a strip shape, which is formed on the polyimide film in a wiring pattern of a thin metal film. Therefore, the metal substrate 8 and the thin metal film 10 constitute a circuit board. The circuit board 5 may be a single-layer or multi-layer board. As shown in the figure below the surface of the gold base substrate 8 This paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210X 297 mm) (please read the precautions on the back before filling this page). A7 B7 printed by the consumer cooperative. 5. The central part of the invention description (6) is exposed, and the chip 2 is mounted on the exposed gold-tipped substrate. The bonding field P is formed on the surface of the wafer 2, that is, the lower surface in the figure. The thickness of the circuit board is about 0.15 ~ 1.5mm. The surface of the circuit board is about 7mm2 ~ 40 mm2. The circuit board is formed by etching or stamping. The pads P, P on the wafer 2 are connected to the inner lead portion 12 by wire bonding. The chip 2, the wiring W, and the inner lead portion 12 are covered with a resin 11 (for example, epoxy resin). Furthermore, the jaws 14 that constitute the outer leads in the shape of bird wings are bonded to the outside portion of the thin gold-tallow film pattern 10 that is not covered with resin. Clamp lead 14 is formed of gold lute (such as iron alloy, copper alloy, etc.) used as a spring, has elasticity, and constitutes an inlay clamp with self-supporting function. The clamp leads 14 are composed of a plurality of strip-shaped plate members, each of which is associated with a pattern 10 of thin metal films connected thereto. The clamp leads 14 are formed by etching or stamping. The thickness of the clamp wire 14 is 0.15 mm or less. The circuit board 5 is prepared in the shape of a lead frame. As shown in FIG. 3, the metal base wiring board MB has a cut-out space (gold plate shape of the gap portion SP, and each metal base 8, 8 ... is made up of an overhang pin 15 5, 1 5 --- -Supported to the metal base wiring board MB through the space part SP, SP P____. Therefore, by forming the gold tantalum base 8, 8____ in the shape of a lead frame, the conventional membrane bonding and wiring bonding can be directly processed Although not shown in FIG. 3, the polyimide film 9 and the thin gold film 10 as shown in FIG. 1 A are formed on each gold film substrate 8, 8__. Below, as shown in FIG. 1 A The manufacturing method of the semiconductor device shown will be described with reference to Fig. 2. In step S1, the wafer 2 is bonded to the metal substrate 8. This paper standard is applicable to the Chinese National Standard Falcon (CNS> A4 specification (21〇Χ29> 7 Mm) (please read the precautions on the back before filling in this page) Order 298668 A7 B7 printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. The central part of the invention description (7). Then, in step S 2 Each pad P, P on the wafer 2-and the associated inner lead portion 12 of the thin metal film 10 are connected by wire bonding. At the step ankle S In 3, the wafer 2, the wiring W, and the inner lead portion 12 are overmolded with the resin 11. Next, in step S4, the hanging pins 15 and 15 are cut at the four corners of the gold-solar substrate ... To separate the metal substrate. Then, in step S5, the clamp leads 14 are bonded to the gold-solar substrate. In FIGS. 4A and 4B, a side view and a plan view of the clamp lead assembly 14 are shown. As shown in FIG. 4A, one end of each clamp lead assembly 14 is U-shaped to form a clamp portion CL, and is elastic in the direction shown by arrow A. The circuit board 5 is clamped by the clamp portion CL At the end, the clamp leads 14 are fixed, and the clamp leads are electrically connected to the thin metal film 10. One end of the clamp leads 14 is connected by the tie rod 16 and the other end is connected by the base rod 17 The clamp lead assembly preferably has protrusions and depressions at related positions to fit with each other for alignment. The protrusions can be formed on the corners of the circuit board 5 by guiding the clamp lead assembly 14 Side surface to ensure the alignment of the clamp leads 14 and the board 5, as shown in Fig. 4C. Then, the lead ends L, L____ of the clamp lead assembly 14 are bent The shape of the bird wing shown in Fig. 1. In step S6, the end portion of the clamp lead 14 is subjected to solder reflow. Then, in step S7, the tie rod 16 and the clamp lead assembly 14 are cut off Base rod 17. In step S 8, various tests are performed to check the circuit function, characteristics, etc. Then, the semiconductor device with good quality can be sold to the market. Or in step S 7, only the tie rod is removed 1 6, and the base rod 1 7 can be removed by the customer after delivery. This paper wave standard is applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm) (please read the precautions on the back before filling this page). 10-_B7_ 5. Description of the invention (8) The shape of the circuit board is not limited to that shown in FIG. 1A. In Figures 1 B and 1 D, examples of other types of circuit boards are shown. In FIG. 1B, the polyimide films 9a and 9b are formed on the main top and bottom surfaces of the metal substrate 8, and the thin gold film 10 is formed only on one of the polyimide films 9b. Since the polyimide films 9a and 9b are formed only on the main surface of the gold-titanium substrate 8, they can be formed by printing. Although the side surface of the metal substrate 8 is exposed, by causing the polyimide films 9 a and 9 b to overhang, short-circuiting of the clamp leads can also be avoided. Although the thin gold film 10 is only formed on one surface of the metal substrate 8, if it can be connected to the clamp leads under low resistance, no problem will occur. Here, the thin gold film can also be formed on another polyimide film 9a as a virtual object. Thereby, the polyimide film 9a can be protected when the clamp wire is bonded. In FIG. 1C, the circuit board 5 is composed of an insulating substrate 19 and a thin metal film pattern 11 formed on the insulating substrate 19. This circuit board has the same structure as the printed circuit board and can be manufactured using a similar manufacturing method. Printed by the Consumer Labor Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. FIG. 1D is a multilayer structure of the printed circuit board 5 of FIG. 1B. The polyimide films 9 a and 9 c are formed on the gold base 8. The first wiring layer 10b is formed on the polyimide film 9c. The polyimide film 9b is further formed on the first wiring layer 10b, and then a thin gold film 10a of the lead is formed. From the viewpoint of bonding wire pins, the multilayer circuit board is similar to the circuit board of FIG. 1B. The circuit board shown in Figure 1C can be modified to have multiple wiring layers. For those familiar with this technique, it is obvious that a circuit board with three or more layers can be formed in the same way as the double-layer circuit wiring. This paper scale is applicable to the Chinese National Standard (CNS> A4 specification (210X297 mm) 11 A7 B7 printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention description (9) Another embodiment of the box clamp lead assembly 14 is shown in FIG. 5 A and 5 B. As shown in FIG. 5 B, each end portion of the lead L has test pads 18, 18 .... As shown in FIG. 5A, the end portion is made of polyimide The layer 19 is adhered to the base rod 17. After the wire bonding to the circuit board 5, by cutting off the tie rod 16, each lead L. is electrically isolated, so that the semiconductor device can be operated and tested. After the test, The test field 18 is cut off. Therefore, by using the clamp leads provided in advance with the test pads 18, 18 ...., the test of the semiconductor device becomes quite easy. Another embodiment of the clamp lead assembly 14 is shown in FIG. 6A And 6B. The lead part 13 outside the lead is bent into the shape of a bird wing as shown in FIG. 6A. As shown in FIG. 6B, the lead 14 has a test pad 18, 18__, located on each lead L On the end part. The end part with the test pad is adhered to the base rod 17 with a polyimide layer 19. Since the forming process is completed, the lead It will be easily deformed, and its application is quite difficult. However, because the leads are bonded in the follow-up, the above problems will not be the problem in this embodiment. As shown in FIG. 7, the polyimide film 9 and the thin gold oxide-like 10 may be formed only on the bottom surface of the gold-thorium substrate. The outer lead 20 may be bonded to the end portion of the thin gold-thorium film 10 using thermocompression bonding. Here, in FIGS. 1A to 1D and FIG. 7 In the semiconductor device shown, when mounting the device on a printed circuit board using face-to-face bonding, a wafer mounter can be used. The present invention has been described above using preferred embodiments. However, the present invention is not limited to Explained in the examples. For those familiar with this skill, it is obvious that various changes, substitutions, combinations and improvements still fail to comply with the paper standard and apply to the Chinese national standard falcon (CNS > Λ4 specifications (210X297 Mm) (Please read the precautions on the back of Feng to fill this page) -9 12 A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of the invention (10) The spirit and scope of the patent application scope of the invention. ( Please read the notes on the back first Then fill out this page) clothes · Paper scale applicable under this Chinese National Standard (CNS) A4 size (210X 297 mm)

Claims (1)

A8 B8 C8 D8 六、申請專利範圍 第84 1 002 1 0號專利申請案 中文申請專利範圍修正本 民國85年3月修正 1 .—種半導體包裝裝S,包含: 一基底,其承載構成多數引線之薄金饜層: 一半導體晶片安裝在該基底上: 一絕緣樹脂構件密封該半導體晶片和多數引線之內部 份:和 多數的箝夾引線,其包括具有箝夾#平面物件和自我支 择功能之多數箝夾部份,具有導電性,且和引線接觸並與 其電連接。 2. 如申請專利範圍第1項所述之半導體包裝裝置, 其中該半導體晶片上包含多數之鍵結墊,進一步包含多數 之鍵結線以電氣連接該引線和鍵結埜。 3. 如申請專利範圍第1項所述之半導體包裝裝置, 其中該基底爲絕緣基底。 4 .如申請專利範圍第1項所述之半導體包裝裝置, 經濟部中央標準局爲工消费合作社印装 (請先閲讀背面之注意事項再填寫本頁) 其中該基底包含具有一對主表面之金屬基底,而絕緣膜形 成在兩表面上。 5 .如申請專利範圍第4項所述之半導體包裝裝置, 其中該絕緣膜在金靥基底的中央部份具有開口,而半導體 晶片在該開口鍵結在金屬基底上。 6 .如申請專利範園第5項所述之半導體包裝裝置, 其中胲絕緣膜形成一片膜,該膜具有覆盖在金屬基底之週 本紙張尺度逋用中國國家梯準(CNS ) A4规格(210X297公釐) 298668 經濟部中央梂準局貞工消费合作社印製 A8 B8 C8 D8六、申請專利範圍 圍上之該對主表面之部份和延伸在金屬基底之側表面上之 部份。 7. 如申猜專利範園第4項所述之半導體包裝裝置, 進一步包含金屬配線層,其嵌入介於金靥基底和引線間之 絕緣膜中。 8. 如申請專利範圍第4項所述之半導體包裝裝B, 其中該半導體晶片包含積體電路。 9. 如申請專利範園第4項所述之半導體包裝裝置, 其中該箝夾引線在箝夾部份的相反側具有測試墊。 10. 如申請專利範圍第9項所述之半導體包裝裝置 ,進一步包含絕緣連接裝置用以連接該測試墊。 1 1 . 一種用以包裝半導體裝置之方法,包含之步驟 爲: 膜片鍵合半導體晶片在表面上具有多數絕緣引線之基 底上; 應用絕緣樹脂以覆蓋該半導體晶片和引線之部份:和 將箝夾板組件接附且電連接至基底之引線,箝夾板組 件具有多數之外引線和箝夾平面構件之功能。 12. 如申請專利範圍第11項所述之用以包裝半導 嫌裝置之方法,其中該半導體晶片包括多數之鍵結墊, 進一步包含之步驟爲在應用絕緣樹脂之前,配線結合 該鍵結墊和該引線。 13. 如申請專利範園第12項所述之用以包裝半導 粗裝置之方法,其中外引線在外端具有測試墊,該測試墊 . Η 装II (請先聞讀背面之注$項再填寫本頁) 訂 t 本紙張尺度逋用中國國家梂率(CNS ) A4洗格(210X297公釐) A8 B8 C8 D8 六、申請專利範圍 在絕緣狀況下相互的機械的連接, 進一步包含使用該測試墊測試半導體包裝裝置之步驟 〇 14.如申請專利範圔第11項所述之用以包裝半導 體裝置之方法,其中該箝夾引線組件之外引線機械的連接 在兩端上, 進一步包含之步驟爲在接附步驟後,至少部份移去該 箱夾引線組件之連接部份。 (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局貝工消费合作社印製 本紙張尺度逋用中國國家梂準(CNS ) A4規格(210X297公釐)A8 B8 C8 D8 VI. Patent Scope No. 84 1 002 1 0 Patent Application Chinese Application Patent Scope Amendment March 1985 Amendment 1.-A kind of semiconductor packaging S, including: a substrate, which carries the majority of the leads The thin gold coating layer: a semiconductor wafer is mounted on the substrate: an insulating resin member seals the semiconductor wafer and the internal portion of the majority of leads: and the majority of the clamp leads, which includes a flat object with clamp ## and self-selection Most of the clamping parts of the function are conductive, and are in contact with and electrically connected to the leads. 2. The semiconductor packaging device as described in item 1 of the patent scope, wherein the semiconductor wafer includes a plurality of bonding pads, and further includes a plurality of bonding wires to electrically connect the lead wire and the bonding field. 3. The semiconductor packaging device as described in item 1 of the patent application scope, wherein the substrate is an insulating substrate. 4. For the semiconductor packaging device mentioned in item 1 of the patent application scope, the Central Bureau of Standards of the Ministry of Economy prints for the industrial and consumer cooperatives (please read the precautions on the back before filling out this page). The substrate contains a pair of main surfaces A metal substrate, and insulating films are formed on both surfaces. 5. The semiconductor packaging device as described in item 4 of the patent application range, wherein the insulating film has an opening in the central portion of the gold-thorax substrate, and the semiconductor wafer is bonded to the metal substrate at the opening. 6. The semiconductor packaging device as described in item 5 of the patent application park, in which the arboric insulation film forms a film with a paper cover that covers the metal substrate and uses the Chinese National Standard (CNS) A4 specification (210X297 Mm) 298668 A8 B8 C8 D8 printed by the Zhengong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs 6. The part of the pair of main surfaces enclosed by the scope of patent application and the part extending on the side surface of the metal substrate. 7. The semiconductor packaging device as described in item 4 of the Shenchai Patent Fan Garden, further includes a metal wiring layer embedded in the insulating film between the gold-solar substrate and the lead. 8. The semiconductor package B as described in item 4 of the patent application scope, wherein the semiconductor wafer includes an integrated circuit. 9. The semiconductor packaging device as described in item 4 of the patent application park, wherein the jaw lead has a test pad on the side opposite to the jaw portion. 10. The semiconductor packaging device as described in item 9 of the patent application scope further includes an insulating connection device for connecting the test pad. 1 1. A method for packaging a semiconductor device, comprising the steps of: film bonding a semiconductor wafer on a substrate having a large number of insulated leads on the surface; applying an insulating resin to cover the semiconductor wafer and the portions of the leads: and will The jaw plate assembly is attached and electrically connected to the leads of the substrate. The jaw plate assembly has the functions of most external leads and jaw planar members. 12. The method for packaging a semiconductor device as described in item 11 of the patent application scope, wherein the semiconductor chip includes a plurality of bonding pads, and further includes the step of wiring the bonding pads before applying the insulating resin And the lead. 13. The method for packaging a semiconducting thick device as described in item 12 of the patent application park, in which the outer lead has a test pad at the outer end, the test pad. Η 装 II (please read the note $ item on the back first (Fill in this page) Set the size of this paper to use the Chinese National Frame Rate (CNS) A4 wash grid (210X297mm) A8 B8 C8 D8 6. The scope of patent application The mutual mechanical connection under the insulation condition, further including the use of the test Steps for testing semiconductor packaging devices by pads 14. The method for packaging semiconductor devices as described in item 11 of the patent application, in which the leads outside the clamp lead assembly are mechanically connected to both ends, further comprising the steps After the attaching step, the connection part of the box clamp lead assembly is at least partially removed. (Please read the precautions on the back before filling out this page). Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. This paper is based on China National Standards (CNS) A4 (210X297mm)
TW84100210A 1994-01-14 1995-01-11 TW298668B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP279894A JPH07211741A (en) 1994-01-14 1994-01-14 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
TW298668B true TW298668B (en) 1997-02-21

Family

ID=11539402

Family Applications (1)

Application Number Title Priority Date Filing Date
TW84100210A TW298668B (en) 1994-01-14 1995-01-11

Country Status (3)

Country Link
JP (1) JPH07211741A (en)
KR (1) KR0177006B1 (en)
TW (1) TW298668B (en)

Also Published As

Publication number Publication date
KR950034635A (en) 1995-12-28
JPH07211741A (en) 1995-08-11
KR0177006B1 (en) 1999-04-15

Similar Documents

Publication Publication Date Title
TW386272B (en) Wafer level and chip size packaging
JP2819285B2 (en) Stacked bottom lead semiconductor package
TW560019B (en) Enhanced die-down ball grid array and method for making the same
TWI469309B (en) Integrated circuit package system
TW436997B (en) Ball grid array semiconductor package and method for making the same
JP2007221139A (en) Integrated circuit package system having die on base package
JP3724954B2 (en) Electronic device and semiconductor package
JP4070470B2 (en) Multilayer circuit board for semiconductor device, manufacturing method thereof, and semiconductor device
KR100226335B1 (en) Molded plastic packaging of electronic devices
TW569406B (en) Semiconductor device and the manufacturing method thereof
TW409393B (en) Semiconductor device and the manufacture method thereof
KR101202452B1 (en) Semiconductor package and method of manuafacturing thereof
KR20050021905A (en) Package for a semiconductor device
JP2003243565A (en) Packaged semiconductor device and its manufacturing method
TW298668B (en)
TWI406379B (en) Chip scale semiconductor device package and manufacturing method thereof
TWI582905B (en) Chip package structure and manufacturing method thereof
KR960035997A (en) Semiconductor package and manufacturing method
TW426870B (en) Semiconductor device and the manufacturing method thereof
KR100818080B1 (en) Chip stack package
US6198160B1 (en) Surface mounted type semiconductor device with wrap-around external leads
TW533557B (en) Semiconductor device
TW409327B (en) Array metal plug package
KR100533761B1 (en) semi-conduSSor package
TW560021B (en) Wire-bonding type chip package