經濟部中央標準局員工消費合作杜印製 A7 B7 五、發明説明（1 ) 1 本發明係有關於一種積體電路的製造技術，特別是有 關於一種以快速退火處理複晶矽電阻元件阻值的製造方法 〇 電咀在積體電路的應用上，可做為數位電路（例如， 5 靜態隨機存取記億體）之負載元件，亦或類比電路之電阻 器，在積體電路製造技術中，電阻大抵可以兩種方式製成 ，一種是於矽基底（silicon substrate)形成擴散區（diffused r e g i ο η )而為電阻，以離子佈植劑量和佈植能量配合熱擴 散製程調整此擴散區成所需之電阻阻值；另一種是形成薄 10 膜於晶圓表面，以此薄膜為電阻器，通常薄膜的材料是為 複晶矽或非晶矽，利用摻植於複晶矽薄膜的雜質濃度If整 電阻的阻值。然而，以擴散區製成之電阻，因其位於矽基 底内，為避免沿擴散區形成寄生電容，故須增加額外製程 將擴散區接面予以絕緣，此外，其尚具有高溫度偽數 15 (temperature coefficient)和較差的容許度（tolerance) 等缺點，因此，利用複晶矽形成於晶圓表面做為電阻的方 法較為業界所採用。 請參照第1A至1D圖所示，為積體電路之複晶矽電阻元 件的製造方法流程剖面圖，其繪示製程中幾個關鍵的步驟 20 。首先，請參照第1A圖，於一矽基底1 (例如是一 P型矽 底）上，藉由局部氣化法（LOCOS)形成場氧化物100 ,於 場氧化物1 00間定義出主動區1 0 1 ;接著，沈積一複晶矽 層10 (亦或非晶矽）覆蓋於場氣化物100和主動區101上 ,其厚度約介於2000至4000埃之間；此複晶矽層10是做為 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) .裝. 訂 297927 A7 —____B7_ 五、發明説明（2 ) ^ 隨後形成閘極和電阻的材料，但閘極和電胆所需的阻值並 不一定相同，為能掴別調整電阻的阻值，須以兩個佈植程 序來完成•如第1A圖所示，以光學微影技術（lithography) 形成一光阻層102覆蓋場氣化層100上方之複晶矽層10後 5 ，以光阻層102做佈植罩幕，施以離子佈植（譬如是P31 離子）進入未被光阻層102覆蓋之複晶矽層10内，令其片 狙值約介於20 — 80Ω / □之間，此佈植程序之劑量約為 1E16/CIH2 ,而能量約為50KeV;然後，去除光阻層102 ，再施以第二次離子佈植（譬如是以P31的離子）於整個 10 複晶矽層10内，此時，佈植劑量約為3E14- 4E14cm·2及能 量為50KeV ,則位於場氧化層100上方之複晶矽層10,其 K阻值約介於1ΚΩ / 口一 10ΚΩ / 口之間；後缠再經蝕刻 定義圖案，而成閘極12於主動區101上，以及複晶矽電阻 層14於場氣化層100上，即如第1Β圖所示，因閘極12和電 15 阻層14業經不同佈植程序而成，故具有不同的阻值，據此 ，可將電阻層14佈植成預定之阻值，亦可維持閘極12低阻 值的需求。 經濟部中央標準局貝工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 然後，如第1C圖所示，佈植離子進入主動區1 0 1内， 於閘極12兩側下方之矽基底1内形成淡摻植區1 06 ;再沈 20 積一絕緣層104 (如氣化矽、氦化矽或未經摻植之複晶矽 物）覆蓋於整個基底表面；接著，回蝕刻絕緣層104 ,至 形成間隔物16 (spacer)於閛極12和電阻層14之側邊；最後 ，經離子佈植步驟，藉由閘極12和間隔物16之遮蔽，形成 濃佈植區108於主動區101内與淡佈植區106緊鄰相接， 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） 經濟部中央揉準局貝工消費合作社印製 A7 B7 五、發明説明（3) 1 完成如第1D圖所示之結構。 此後，為能將所佈植之離子活化（activation),通常 會將晶圓置入爐管内做退火處理，此退火處理的溫度約為 900t：,持缠約60分鐘，以獲致離子活化的目的。然而， 5 此爐管退火處理會令原本已適度調整之電阻元件阻值産生 漂移變動，而影堪其應用於積體電路時之偏壓值；再者， 後鑛之熱處理亦發生於以旋覆玻璃（S0G)做表面平坦處理 時，因旋覆玻璃之烘烤溫度亦約為9001C 的溫度，故尋求 如何穩定已精確調整之電阻元件阻值，是此業界者急待解 10 決解的問題。 有鑑於此，本發明之主要目的，在於提供一種以快速 退火處理穩定電阻元件阻值的製造方法，可以穩定複晶矽 電阻元件之阻值。 本發明之上述目的，可藉由提供一種以快速退火處理 15 穩定電阻元件阻值的製造方法，包括： 提供一半導體基底，該半導體基底已形成有絕緣層於 表面； 形成電阻元件於該絕緣層上；以及 施以快速退火處理於該等電阻元件。 20 為讓本發明之上述目的、特擻、和優點能更明顯易懂 ，下文特舉一較佳實施例，並配合所附圖式，作詳細說明 如下： 圖式之簡單說明： 第1A至1D圖為複晶矽電阻元件的製程剖面圖； 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） (請先閲讀背面之注意事項再填寫本頁) 、裝· >tr 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（4 ) 1 第2A圖為一快速退火裝置之頂視圖； 第2 B圖為一快速退火裝置内之溫度對時間的特性曲線 9 第3圖為未經快速退火處理逕經爐管退火溫度與K阻 5 值的特性曲線；以及 第4圖為先行經快速退火處理後，爐火退火溫度對K 阻值的特性曲線圖式。 實施例： 根據第1A — 1D圖所示之製程步驟，形成電阻元件14於 10 場氣化物100上，此等電阻元件14業經離子佈植調整其阻 值約為1ΚΩ / □ — 10ΚΩ / □間的範圍；再根據本發明方 法，施以一溫度介於800- 11001C 間持缠約30 - 120秒的 快速退火處理（rapid thermal annealing:RTA),此快速 退火處理裝置的頂視圖即如第2A画所示，標號20為一主鹾 15 殼，標號22為一反應室，24為加熱線圈，26為一門，具有 一把手，經由此門26將己製作電阻元件餐晶圓2δ置入圖示 中的位置，而此快速退火處理裝置内之溫度對時間的曲線 ,即如第2Β圖所示，以AG Associate 010之機台為例，其 反應室22已保持於400Ϊ：的預熱溫度，後經每秒1001C 的 20 昇溫速度，於時間Tt及於預定之退火溫度A ,如是，保持 溫度A至時間T2後，再降溫回預熱溫度，其中時間差T2 — 即為施以退火處理的時間。 經此快速退火處理後，可以令複晶矽電阻元件的阻值 趨於穩定，較不受後缅高溫製程的影堪。 -6 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) •裝. 订 —---*1 經濟部中央橾準局員工消费合作社印製 A 7 __B7___ 五、發明説明（5 ) 1 實驗結果： 將矽晶圓表面施以熱氣化法成氧化矽層於表面，再以 低壓氣柑沈積法（LPCVD)於約5701C溫度下，於氧化矽層 上沈積一厚度約為3000埃之非晶矽層，然後，施以磷離子 5 佈植進入非晶矽層内，佈植能量約為50KeV ,佈植劑置分 別為 3E14cnr2、3.5E14cra-z 及 4E14cn-2 等三種，後缠經 600 一 100013之嫌管退火處理（furnace annealing)而得。如 是，第3圖所示為未經快速退火處理量測得之複晶矽層Η 阻值（sheet resistance)曲線分佈，第4圖所示為根據本 10 發明經1000^及60秒之快速退火處理量測得之複晶矽層的 Μ阻值，E能做一比較。 ， 由第3及4圖相較可知，未經快速退火處理之試Κ, 於爐管退火處理時，尤其是在900它的溫度下，産生阻值 上昇的漂移，此為900¾為摻植雜質活化及偏析（segregation 15 的溫度，此二作用相互抗衝造效的結果，而第4圖根據本 發明以快速退處理先行穩定其阻值後，雖經爐管退火600 -108010間的範圍，尤其是9001C 的溫度下，並無太大之 漂移變化，故可知本發明確能解決電阻漂移的問題。 雖然本發明已以較佳實施例掲露如上，然其並非用以 28 限定本發明，任何熟習此項技藝者，在不脱離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 本紙張尺度適用中國國家橾準（CNS ) Α4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) .裝· 訂Du Printed A7 B7 by the Consumer Cooperation of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (1) 1 The present invention relates to a manufacturing technology of integrated circuits, in particular to a resistance value of polycrystalline silicon resistive elements processed by rapid annealing The manufacturing method of the electric nozzle can be used as a load element of a digital circuit (for example, 5 static random access memory) in the application of integrated circuits, or a resistor of an analog circuit. In the manufacturing technology of integrated circuits The resistance can be made in two ways, one is to form a diffused region (diffused regi ο η) on the silicon substrate and it is the resistance. The diffusion area is adjusted by the ion implantation dose and implantation energy in conjunction with the thermal diffusion process. The required resistance value; the other is to form a thin 10 film on the surface of the wafer, using this film as a resistor, usually the material of the film is polycrystalline silicon or amorphous silicon, using impurities implanted in the polycrystalline silicon film Concentration If the resistance value of the whole resistor. However, the resistor made of the diffusion region is located in the silicon substrate. In order to avoid the formation of parasitic capacitance along the diffusion region, additional processes must be added to insulate the junction of the diffusion region. In addition, it still has a high temperature pseudo-number 15 ( temperature coefficient) and poor tolerance (tolerance) and other shortcomings, therefore, the method of using polycrystalline silicon formed on the wafer surface as a resistor is more commonly used in the industry. Please refer to Figures 1A to 1D for a cross-sectional view of the manufacturing method of a polycrystalline silicon resistor element of an integrated circuit, which shows several key steps in the manufacturing process 20. First, please refer to FIG. 1A, on a silicon substrate 1 (for example, a P-type silicon substrate), a field oxide 100 is formed by LOCOS, and an active region is defined between the field oxide 100 1 0 1; Then, a polycrystalline silicon layer 10 (or amorphous silicon) is deposited on the field vaporization 100 and the active region 101, the thickness of which is between 2000 to 4000 angstroms; the polycrystalline silicon layer 10 It is based on the paper standard applicable to China National Standard (CNS) A4 (210X297mm) (please read the precautions on the back and then fill out this page). Pack. Order 297927 A7 —____ B7_ 5. Description of the invention (2) ^ The materials for the gate and the resistor are subsequently formed, but the required resistance of the gate and the electric bulb is not necessarily the same. In order to adjust the resistance of the resistor separately, two implantation procedures must be completed • As shown in Figure 1A It is shown that a photoresist layer 102 is formed by optical lithography to cover the polycrystalline silicon layer 10 above the field vaporization layer 100, and then the photoresist layer 102 is used as an implantation mask, and ion implantation is applied (such as It is P31 ion) into the polycrystalline silicon layer 10 which is not covered by the photoresist layer 102, so that its sheet value is about 20-80Ω / □ In between, the dose of this implantation procedure is about 1E16 / CIH2, and the energy is about 50KeV; then, the photoresist layer 102 is removed, and then a second ion implantation (such as P31 ion) is applied to the entire 10 times. In the crystalline silicon layer 10, at this time, the implantation dose is about 3E14-4E14cm · 2 and the energy is 50KeV, then the polycrystalline silicon layer 10 above the field oxide layer 100 has a K resistance of about 1KΩ / 10KΩ / Between the mouths; after winding and then etching to define the pattern, the gate 12 is formed on the active area 101, and the polycrystalline silicon resistance layer 14 is on the field vaporization layer 100, as shown in FIG. 1B, due to the gate The 12 and the electrical 15 resistance layers 14 are formed through different implantation procedures, so they have different resistance values. According to this, the resistance layer 14 can be implanted to a predetermined resistance value, and the demand for the low resistance value of the gate electrode 12 can also be maintained. Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). Then, as shown in Figure 1C, implanted ions enter the active zone 101, on both sides of the gate 12 A lightly-doped region 106 is formed in the silicon substrate 1 below; then an insulating layer 104 (such as vaporized silicon, helium silicon or undoped polycrystalline silicon) is deposited on the entire surface of the substrate; then, The insulating layer 104 is etched back to form spacers 16 on the sides of the electrode 12 and the resistance layer 14; finally, after the ion implantation step, the dense implantation is formed by the shielding of the gate electrode 12 and the spacer 16 The area 108 is in close proximity to the light cloth planting area 106 in the active area 101. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). The A7 B7 is printed by the Beigong Consumer Cooperative of the Central Standardization Bureau of the Ministry of Economic Affairs. 3. Description of the invention (3) 1 Complete the structure shown in Figure 1D. Afterwards, in order to activate the implanted ions, the wafer is usually placed in a furnace tube for annealing treatment. The annealing treatment temperature is about 900t :, holding for about 60 minutes, for the purpose of ion activation . However, the furnace tube annealing process will cause the drift of the resistance value of the resistance element that has been moderately adjusted, which will affect the bias value when it is applied to the integrated circuit. When the surface of the glass-clad (S0G) is flattened, the baking temperature of the glass-clad glass is also about 9001C, so it is urgent for the industry to find out how to stabilize the resistance value of the resistive element that has been accurately adjusted. problem. In view of this, the main object of the present invention is to provide a manufacturing method for stabilizing the resistance value of a resistance element by rapid annealing, which can stabilize the resistance value of a polycrystalline silicon resistance element. The above object of the present invention can be achieved by providing a manufacturing method for stabilizing the resistance of a resistive element by rapid annealing, including: providing a semiconductor substrate having an insulating layer formed on the surface; forming a resistive element on the insulating layer Above; and applying rapid annealing treatment to the resistance elements. 20 In order to make the above objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is described below in conjunction with the attached drawings, which are described in detail as follows: Brief description of the drawings: 1A to 1D is a cross-sectional view of the manufacturing process of the polycrystalline silicon resistance element; the paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) (please read the precautions on the back before filling this page), install · > tr Economy A7 B7 printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Education 5. Description of the invention (4) 1 Figure 2A is a top view of a rapid annealing device; Figure 2B is a characteristic curve of temperature versus time in a rapid annealing device 9 Figure 3 is the characteristic curve of the annealing temperature of the furnace tube and the K resistance 5 value without rapid annealing treatment; and Figure 4 is the characteristic curve diagram of the furnace annealing temperature versus K resistance value after the rapid annealing treatment. Embodiment: According to the process steps shown in FIGS. 1A-1D, a resistive element 14 is formed on 10 fields of vaporized material 100. The resistance value of these resistive elements 14 is adjusted by ion implantation to be about 1KΩ / □ -10KΩ / □. According to the method of the present invention, a rapid annealing process (rapid thermal annealing: RTA) with a temperature between 800 and 11001C for about 30 to 120 seconds is applied. The top view of this rapid annealing device is as shown in 2A As shown in the drawing, the reference number 20 is a main falcon 15 shell, the reference number 22 is a reaction chamber, 24 is a heating coil, 26 is a door, and has a handle. And the temperature-time curve in this rapid annealing device, as shown in Figure 2B, taking the machine of AG Associate 010 as an example, the reaction chamber 22 has been maintained at a preheating temperature of 400Ϊ: After heating at a rate of 20 ° C per second at 1001C, at time Tt and at the predetermined annealing temperature A, if the temperature A is maintained for time T2, then the temperature is lowered back to the preheating temperature, where the time difference T2 is the time for the annealing treatment. After this rapid annealing process, the resistance of the polycrystalline silicon resistance element tends to be stable, which is less affected by the post-Burmese high-temperature process. -6-This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back and then fill out this page) • Install. Order —--- * 1 Employee of Central Central Bureau of Economic Affairs Printed by the consumer cooperative A 7 __B7___ V. Description of the invention (5) 1 Experimental results: The silicon wafer surface was applied with thermal gasification to form a silicon oxide layer on the surface, and then low pressure gas citrus deposition (LPCVD) at a temperature of about 5701C An amorphous silicon layer with a thickness of about 3000 angstroms is deposited on the silicon oxide layer, and then implanted with phosphorus ions 5 into the amorphous silicon layer, the implantation energy is about 50KeV, and the implantation agent is 3E14cnr2, Three kinds of 3.5E14cra-z and 4E14cn-2 are obtained after furnace annealing of 600-100013. If so, Figure 3 shows the distribution of the sheet resistance curve of the polycrystalline silicon layer measured without rapid annealing. Figure 4 shows the rapid annealing after 1000 ^ and 60 seconds according to the present invention. According to the measured M resistance of the polycrystalline silicon layer, E can be compared. It can be seen from the comparison of Figures 3 and 4 that the test without rapid annealing treatment, when the furnace tube is annealed, especially at the temperature of 900, the resistance value drifts, which is 900¾ for the implanted impurities The temperature of activation and segregation (segregation 15), the results of these two effects against each other's impact, and Figure 4 according to the present invention firstly stabilizes its resistance value by rapid retreat treatment, although the furnace tube is annealed in the range of 600-108010, Especially at a temperature of 9001C, there is not much drift change, so it can be seen that the present invention can indeed solve the problem of resistance drift. Although the present invention has been exposed as above with the preferred embodiment, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and retouching without departing from the spirit and scope of the present invention, so the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application. This paper Standards apply to China National Standards (CNS) Α4 specifications (210 X 297 mm) (please read the precautions on the back before filling this page).