TW295708B - The polysilicon electromigration sensor - Google Patents

The polysilicon electromigration sensor Download PDF

Info

Publication number
TW295708B
TW295708B TW85106935A TW85106935A TW295708B TW 295708 B TW295708 B TW 295708B TW 85106935 A TW85106935 A TW 85106935A TW 85106935 A TW85106935 A TW 85106935A TW 295708 B TW295708 B TW 295708B
Authority
TW
Taiwan
Prior art keywords
layer
patent application
item
strip
insulating layer
Prior art date
Application number
TW85106935A
Other languages
Chinese (zh)
Inventor
Jyh-Shenq Lin
Shuenn-Yih Lii
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Priority to TW85106935A priority Critical patent/TW295708B/en
Application granted granted Critical
Publication of TW295708B publication Critical patent/TW295708B/en

Links

Abstract

A structure of electromigration sensor is formed on Si wafer substrate fordetecting the adjacent immigration of electron in metal strip. It includes:a polysilicon strip with electric-connection and insulated with substrateelectric by 1st insulated layer, and it is under the metal strip andinsulated with metal strip by 2nd insulated layer.

Description

經濟部中央標準局員工消費合作社印製 A7 __B7 五^説明(τ) ^—— 畳明背景 12)發明領域: 本發明係關於半導體裝置製造的製程,且更特定言之, 係關於一種多晶矽測試結構,其可用於偵測及監控積體電 路互連冶金層之金屬導線特性中之電子移動的開始。該結 構可用於基礎研究,或者它可併用於特殊設計的積體電路 測試晶片中,並用作爲高敏感性的導線監控器。 (2)先前技藝説明: 積體電路晶片的製造涉及積體電路裝置之埋置入已抛光 的矽晶圓中。該製程基本上含有裝置加工,於其中將半導 體裝置和場絕緣區域形成於矽表面之内,以及裝置獨特化 ,於其中晶圓接受二或更多層的互連冶金層,其以絕緣隔 開。第一金屬化層用於界定小的基本電路,例如,含有兩 個互補型金氧半場效電晶體(MOSfleldeffecttransist〇rs,下文簡 稱MOSFETs)的簡單互補型金氧半電晶體。然後提供另外 的金屬導線層以互連這些原始電路成爲較大的單元。施加 最後的金屬化層以連接電路至形成晶片之外部連接點的銲 點。金屬層之間的連接使用經由絕緣層内之孔洞填充的金 屬製成。 電子移動是這些金屬導線的—種失效機構,其自196〇年 代的極早期就已經造成積體電路技術的困擾。相較於它們 目前的大小而言,最早的電路裝置是龐大的。同樣地,用 於互連這些裝置之金屬導線的大小也比它們今日的大小大 很多。要求這些金屬導線載送的電流經常超過i χ i 〇 5安培 -4- 本紙張尺度適用中國國家橾準(CNS ) Α4規格(21 οχ 297公釐〉 n 1 - J.^·—Λ,—ϋ n n-n n 1 n —I— I -ϋ、 * 請先閲讀背面之注意事項再填寫本頁) 裝·A7 __B7 ^ Description (τ) ^ —— 畳 明 background 12 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 12) Field of invention: The present invention relates to the manufacturing process of semiconductor devices, and more specifically, relates to a polysilicon test Structure, which can be used to detect and monitor the onset of electron movement in the characteristics of metal wires of interconnected metallurgical layers of integrated circuits. This structure can be used for basic research, or it can be used in a specially designed integrated circuit test chip and as a highly sensitive wire monitor. (2) Prior art description: The manufacture of integrated circuit chips involves the embedding of integrated circuit devices into polished silicon wafers. The process basically includes device processing, in which semiconductor devices and field insulation regions are formed within the silicon surface, and device uniqueness, in which the wafer receives two or more interconnected metallurgical layers, separated by insulation . The first metallization layer is used to define a small basic circuit, for example, a simple complementary metal oxide semi-transistor containing two complementary metal oxide half field effect transistors (MOSfleldeffecttransistors, hereinafter referred to as MOSFETs). Then additional metal wiring layers are provided to interconnect these original circuits into larger units. A final metallization layer is applied to connect the circuit to the solder joints that form the external connection points of the wafer. The connection between the metal layers is made of metal filled through holes in the insulating layer. Electronic movement is a kind of failure mechanism of these metal wires, which has caused the trouble of integrated circuit technology since the very early years of 1960s. Compared to their current size, the earliest circuit devices were huge. Similarly, the size of the metal wires used to interconnect these devices is much larger than they are today. It is required that the current carried by these metal wires often exceeds i χ i 〇5 ampere-4- This paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (21 οχ 297 mm> n 1-J. ^ · —Λ, — ϋ n nn n 1 n —I— I -ϋ, * Please read the precautions on the back before filling this page)

-1T 經濟部中央樣準局負工消費合作社印製 Α7 Β7 五、發明説明(2 ) /平方厘米。在那個時代的雙極性技術中,達到這種水準 的是射極電流。在很多小時的溫度/濕度試驗之後,由純 銘製成之射極長條的失效開始發生。長條之内的金屬由所 謂之「電子風J中的強電子流沿著該長條而物理性地沖掉 。隨著將金屬沖掉,該長條的斷面變得更薄。這造成那個 區域中電流密度的增加,伴隨著局部的溫度上升,其進_ 步加快該失效。加速之壽命試驗的結果後來由在電場中之 較長時段下的射極長條失效加以證實。這些結果的统計分 析證實’失效確實是鋁冶金層本身上的一個弱點。該現象 稱之爲電子移動(ΕΜ)。對該問題的補救方法很快地出現。 純銘冶金層以含有小量之矽、銅、鈦、或鎢的鋁合金加以 取代。這些合金擁有各種程度的金屬漂移抑制力。幸運地 ’隨著裝置變得更小,操作電壓多少有點降低且電流密度 由於較佳冷卻的輔助而受到抑制。然而,由於電子移動而 引起的長期失效仍然疋主要的關心點。在今日的互補型金 氧半技術中,造成電子移動失效顯露出來的是電源線電流 。晶圓的表面形態也已經變成—個關於金屬導線失效的關 心點。金屬導線的沈積通常藉由自鋁合金靶材濺鍍金屬而 做到。要沈積金屬導線之區域中之表面形態外貌的存在造 成不適當的金屬覆蓋。這些外貌經常難以避免。金屬導線 經常必須橫過下方有氧化物場絕緣區域的範圍,該區域沿 著它們的邊緣具有隆起。橫跨較低層上之其他導線的導線 也遭遇到表面形態上的急降和上升。在這些外貌上之金屬 導線的局部薄化爲電子移動失效提供弱點。 本紙張尺度適用中國國家標準(CNS ) Α4規格(2ΐ〇χ297^ (請先閲讀背面之注意事項再填寫本頁) 裝- 訂 206708 A7 B7 經濟部中央樣準局員工消費合作社印褽 五、發明説明(3 ) 因此,已經設計各種的測試結構以偵測和監控敏感電路 中的電子移動。一種這樣的結構,參見闕西爾(Ch e.sire)和 歐惕斯(Oates)所提之US5,264,377,稱之爲「SWEATS」 (標準晶圓層電子移動加速試驗)。這種結構(見圖丨)具有四 點探針設計(兩個銲點301用於電流施加且兩個銲點3〇2用於 電歷量測)’且含有具多個狹窄區域3丨丨_3 i 7的金屬長條 3〇3。測試藉由通過比正常更大的電流(超過1χ 1〇7安培/ 平方厘米)穿越該長條,同時量測沿著該長條的電壓降而進 行。狹窄的斷面很快地溫度上升,提供熱量以加速試驗而 不傷害到晶圓上的周圍諸結構。該試驗是快速的,且可在 晶圓加工期間進行,作爲單站檢驗。不幸的是,施行的迅 速性和溫度的不確定性只容許它用作爲單站檢驗。因此, 尚缺乏與長期應力測試的關連性。闕西爾和歐惕斯説明一 種類似於SWEATS結構,但不具有寬窄區域的結構。它含 有筆直的金屬長條,再次具有四點探針外貌,但也沿著長 條側邊具有另外的金屬化以偵測短路,以及代表位於試驗 長條下之典型表面形態的橫向導線。這種結構基本上是爲 具有快速旋轉時間的製程監控目的而設計的。它由超過IX 10安培/平方厘米的施加電流驅動,且可爲幾分鐘之内的 製程調整給予適時的資訊。該設計具有的特色爲更平緩的 溫度梯度’吏精確近似於眞實的金屬化層幾何形狀,及與 長時期加速試驗的更佳關連性。 趨向小型化之趨勢所要求之金屬互連系統上的最近進展 已使電子移動失效監控更爲複雜。鋁合金導線附裝有鄰接 -6- —4t m n :ί;.. ---------{裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 J / ? ί 平 你 % 經濟部中央樣準局員工消費合作社印裂 A7 B7 五、發明説明(4 ) 的耐火金屬及雙金屬薄層,其含有.,列出幾種,鈦(Ti)、氮 化飲(TiN)、欽-鎢合金(TiW)。這些材料作爲擴散障壁、 附著性提昇物、抗反射塗覆(anti_refleetiQn eQatings, 下文簡%ARC),且以其他的能力使用,以改良接合,降低 接觸阻抗,且大概而言,改良整個互連系統的完整性。爲 了本纣論之目的,這些層將稱爲障壁層。.障壁層可出現在 銘合金的一個或兩個界面。銘合金仍是主要的電流載體, 但鄰接之障壁層也參與該過程。有關這些複合金屬導線的 測式程序現在必須也包括這些障壁層。當電子移動發生於_ 這樣的結構中時,障壁層保持完整,且夾在他們之間的鋁 合金失效。量測失效導線之電阻係數的標準方法和結構變 知不犯實施,因爲當導線失效時,沒有突然的電阻係數增 加出現。 本發明説明一種電子移動感測器,其鄰接於複合電子移 動測試導線而予以定位,並量測鋁合金中之電子移動所產 生的局部加熱。 發明摘述: 本發明所提供之監控電予移動的方法不直接量測金屬導 線,而是使用置於該導線之下,以一層氧化矽與它隔開的 多晶梦感測器元件。多晶硬感測器對金屬導線中的諸熱量 熱點是高度敏感的。感測器使用稱之爲本質性區域之碎的 一種特性,在該區域中溫度上的小增加造成載子濃度上的 大增加。圖2描述具有lx ι〇15原予/立方厘米按雜劑濃度 之矽之出現於約35 0°C之上的這個溫度區域(取自施敏之「 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公董) (請先閲讀背面之注意事項再填寫本頁) 裝- 訂 經濟部中央標準局員工消费合作社印製 A7 B7 五、發明説明(5 ) 半導體元件物理J,紐約威利(Wiley,New York)於1969 年出版’第36頁關於這點,正遭受電子移動失效之鄰接 金屬導線的局部溫度增加顯示爲感測器之阻抗上的降低。 爲了有效利用本質性特性,必須使用未摻雜(小於1 X i 〇 1 4 原予/平方厘米)的多晶矽作爲感測器。 感測器的製造相容於使用自動對正之多晶矽閘極的現行 互補型金氧半製造製程。感測器可植入於晶圓切口區域中 並在切割.晶粒之前加以測試,或者它可植入於稱爲製造測 試位置(MTS)的晶片中。MTS晶片含有與感測器相容的金 屬導線’且在與產品相同的時間製造。在光罩組件中,幾 個MTS晶片置於產品晶片陣列之内。在此中,在與多.晶梦 閘極相同的步驟中沈積諸感測器。在本製程中,只爲包含 在第一金屬化層的測試金屬導線提供感測器。然而,這些 導線一般是最小的。 附圖簡要説明: 圖1是用於量測電子移動,爲人所知爲SWEATS結構之先 前技藝結構的上視圖。 圖2是矽之電子密度相對絕對溫度之倒數的圖形表示。 圖3是本發明之電子移動結構的上視圖以及探針和測試電 路迴路的輪廓圖表示。 圖4疋使用沈積之金屬接點至本質性多晶珍感測器長條之 結構之橫斷切開的正等轴表示。顯示出兩個感測器用的探 針銲點和一個電子移動試驗長條用的探針銲點。 圖5至11是橫斷面,顯示出多晶矽電子移動感測器之製造和 本紙張尺度適用中國國家梂準(CNS ) A4規格(210X297公釐) ----------ί $------I------^ (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印裂 295708 at ------ B7 五、發明説明(6 ) L位於諸製程步驟之組織内的電子移動試驗金屬長條,該諸步 碌傳統上用於自動對正之多晶矽閘極金氧半場效電晶體的 形成。 輕佳具體實施例説明: 現在參考圖3,其處以輪廓圖形式,沿著它的量測電路迴 路’顯示出一個本發明的典型具體實施例。進行電子移動 測試的金屬長‘ 4 0 0連接於探針銲點4 〇 1和4 0 2之間。以電 源供應器42 0供應電流至該長條。躺置於電子移動金屬長條 400之下方,且藉由一層氧化矽與它絕緣,的感測器14含有 多晶梦長條’其具有大量摻雜的橫向邊緣。複合鋁金屬化 層施加於該邊緣並在長條和量測探針接點4 i 4及4丨5之間形 成電氣連接。量測探針連接至儀器設備4 2 1,其量測多晶矽 感測器的阻抗。爲了更明白該結構,參考圖4 ’其爲具有感 測器和電子移動試驗長條之一部分之橫斷面的正等轴視圖 。在矽晶圓10上的氧化矽層12是互補型金氧半製程中所使 用的場氧化物絕緣。多晶矽感測器長條14含有一個中心本 質性邵分14a和大量掺雜的邊緣部分i4b。 自多晶矽感測器長條1 4隔絕金屬長條4 0 0的氧化矽層j 6 延伸自界定互補型金氧半裝置用之接點的氧化物層16。電 子移動試驗長條400結構含有沈積至長條上的障壁冶金層 18a、銘/矽合金18b和由Ti、Tiw、或Ti]Sf組成的抗反射 塗覆18c。對多晶矽感測器14和探針接點4 14及4 15形成橫 向連接的金屬化層在與電子移動試驗長條400和其探針接點 40 1及402之金屬化層相同的製程步驟中形成(後者未顯示於 -9- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (锖先閲讀背面之注意事項再填寫本頁) 裝.-1T Printed by the Consumer Labor Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention (2) / cm2. In the bipolar technology of that era, it was the emitter current that reached this level. After many hours of temperature / humidity tests, the failure of the emitter strips made of pure Ming began to occur. The metal within the strip is physically washed away along the strip by the so-called "strong electron flow in the electron wind J. As the metal is flushed away, the section of the strip becomes thinner. This results in The increase in current density in that area, accompanied by a local temperature rise, further accelerates the failure. The results of the accelerated life test were later confirmed by the failure of the emitter bar under a longer period of time in the electric field. These results The statistical analysis confirms that 'failure is indeed a weakness in the aluminum metallurgy layer itself. This phenomenon is called electron mobility (EM). The remedy for this problem appears quickly. The pure metallurgical layer contains a small amount of silicon, Aluminum alloys of copper, titanium, or tungsten are substituted. These alloys have various degrees of metal drift suppression. Fortunately, as the device becomes smaller, the operating voltage is somewhat reduced and the current density is assisted by better cooling Suppression. However, the long-term failure caused by the movement of electrons is still the main concern. In today's complementary metal-oxygen technology, what causes the failure of electron movement is revealed. Source line current. The surface shape of the wafer has also become a concern about the failure of metal wires. The deposition of metal wires is usually done by sputtering metal from an aluminum alloy target. The surface in the area where the metal wires are to be deposited The presence of morphological appearances results in improper metal coverage. These appearances are often difficult to avoid. Metal wires must often traverse the area below the oxide field insulation area, which has ridges along their edges. Across the lower layers The wires of other wires also encountered a sharp drop and rise in surface morphology. The local thinning of the metal wires on these appearances provides a weakness for the failure of electronic movement. The paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (2l〇χ297 ^ (Please read the precautions on the back before filling in this page) Binding-Order 206708 A7 B7 Central Sample Bureau of the Ministry of Economic Affairs Employee Consumer Cooperative Printed V. Invention Description (3) Therefore, various test structures have been designed to detect and Monitor electronic movements in sensitive circuits. For such a structure, see Che.sire and Oates The US5,264,377 is called "SWEATS" (standard wafer layer electron movement acceleration test). This structure (see Figure 丨) has a four-point probe design (two solder points 301 for current application and two solder Point 3〇2 is used for electrical calendar measurement) 'and contains a metal strip 3〇3 with multiple narrow areas 3 ~ 丨 _3 i 7. The test is carried out by passing a larger current than normal (over 1 × 10 7 Amps / cm2) across the strip while measuring the voltage drop along the strip. The narrow cross-section quickly rises in temperature, providing heat to accelerate the test without damaging the surrounding structures on the wafer The test is fast and can be performed during wafer processing as a single station inspection. Unfortunately, the rapidity of implementation and the uncertainty of temperature only allow it to be used as a single station inspection. Therefore, there is still a lack of Relevance of stress testing. Quesier and Otis indicate a structure similar to the SWEATS structure, but without a wide and narrow area. It contains straight metal strips, again with the appearance of a four-point probe, but also has additional metallization along the sides of the strip to detect short circuits, as well as lateral wires representing the typical surface morphology under the test strip. This structure is basically designed for process monitoring purposes with fast spin times. It is driven by an applied current in excess of IX 10 amps / cm² and can give timely information for process adjustments within a few minutes. The design features a smoother temperature gradient that accurately approximates the solid metallization layer geometry and better correlation with long-term accelerated testing. Recent advances in metal interconnect systems required by the trend towards miniaturization have made electronic mobile failure monitoring more complicated. The aluminum alloy wire is attached with abutment -6- —4t mn: ί; .. --------- {installed-- (please read the precautions on the back before filling out this page) Order J /? Ί flat You% The Ministry of Economic Affairs, Central Bureau of Prospects and Employee's Consumer Cooperative Printed A7 B7 V. Invention description (4) The refractory metal and bimetallic thin layer, which contains., Lists several types, titanium (Ti), nitrided drink (TiN) ), Qin-tungsten alloy (TiW). These materials serve as diffusion barriers, adhesion lifters, anti-reflective coatings (anti_refleetiQn eQatings, hereinafter referred to as% ARC), and are used with other capabilities to improve bonding, reduce contact resistance, and, roughly speaking, improve the entire interconnect system Integrity. For the purpose of this discussion, these layers will be called barrier layers. The barrier layer can appear at one or two interfaces of Ming Alloy. Ming alloy is still the main current carrier, but the adjacent barrier layer also participates in this process. The test procedure for these composite metal wires must now also include these barrier layers. When electron movement occurs in such a structure, the barrier layer remains intact, and the aluminum alloy sandwiched between them fails. Standard methods and structural changes to measure the resistivity of a failed wire are not implemented, because when the wire fails, no sudden increase in the resistance coefficient occurs. The present invention describes an electronic movement sensor which is positioned adjacent to a composite electron movement test lead and measures local heating caused by electron movement in an aluminum alloy. SUMMARY OF THE INVENTION: The method for monitoring electrical pre-movement provided by the present invention does not directly measure a metal wire, but uses a polycrystalline dream sensor element placed under the wire and separated from it by a layer of silicon oxide. Polycrystalline hard sensors are highly sensitive to thermal hot spots in metal wires. The sensor uses a characteristic called fragmentation of the essential region where a small increase in temperature causes a large increase in carrier concentration. Figure 2 depicts this temperature region where silicon with lx ι〇15 original pre / cubic centimeters by dopant concentration appears above about 350 ° C (taken from Shi Min ’s “This paper scale applies to China National Standard (CNS) A4 Specifications (210X297 company director) (please read the precautions on the back before filling in this page) Binding-Order A7 B7 printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Invention Instructions (5) Semiconductor Element Physics J, Wiley ( Wiley, New York), published in 1969 'page 36. In this regard, the local temperature increase of the adjacent metal wire that is suffering from electronic movement failure is shown as a decrease in the impedance of the sensor. In order to effectively use the essential characteristics, it must be used Undoped (less than 1 X i 〇1 4 original pre / cm2) polysilicon is used as the sensor. The manufacturing of the sensor is compatible with the current complementary metal-oxygen semi-manufacturing process using automatic alignment of the polysilicon gate. The sensor can be implanted in the notch area of the wafer and tested before dicing the die, or it can be implanted in a chip called a manufacturing test location (MTS). The MTS chip contains gold compatible with the sensorIt is a wire and is manufactured at the same time as the product. In the reticle assembly, several MTS wafers are placed in the product wafer array. In this, the sensors are deposited in the same steps as the multi-crystal dream gate In this process, sensors are only provided for the test metal wires contained in the first metallization layer. However, these wires are generally the smallest. Brief description of the drawings: Figure 1 is used to measure the movement of electrons. The top view of the prior art structure known as the SWEATS structure. FIG. 2 is a graphical representation of the reciprocal of the electron density of silicon relative to the absolute temperature. FIG. 3 is a top view of the electronic mobile structure of the present invention and the probe and test circuit loop The outline diagram is shown in Figure 4. The cross-cut positive isometric representation of the structure of the deposited metal contact to the intrinsic polycrystalline sensor strip is shown. It shows the probe solder joints for two sensors and one Solder joints for probes for electronic mobile test strips. Figures 5 to 11 are cross-sections showing the manufacturing of polysilicon electronic mobile sensors and the paper size applicable to China National Standards (CNS) A4 specification (210X297 mm) --------- -ί $ ------ I ------ ^ (Please read the precautions on the back first and then fill out this page) The Ministry of Economic Affairs Central Standards Bureau Negative Work Consumer Cooperative Printing 295708 at ------ B7 Fifth, the description of the invention (6) L is an electronic mobile test metal strip located in the organization of various process steps, which are traditionally used to automatically align the formation of polysilicon gate metal oxide semi-field effect transistors. Description of embodiments: Reference is now made to FIG. 3, which shows an exemplary embodiment of the present invention along the measurement circuit loop in the form of an outline diagram. The metal length for electronic movement test is connected to the probe. Solder joints between 4 〇1 and 402. A power supply 42 0 supplies current to the strip. Lying beneath the electron-moving metal strip 400 and insulated from it by a layer of silicon oxide, the sensor 14 contains polycrystalline dream strips' with heavily doped lateral edges. A composite aluminum metallization layer is applied to the edge and forms an electrical connection between the strip and the measuring probe contacts 4 i 4 and 4 5. The measuring probe is connected to the instrument 4 2 1 and measures the impedance of the polysilicon sensor. For a better understanding of the structure, refer to FIG. 4 'which is an isometric view of a cross-section of a portion of a bar with a sensor and an electronic movement test. The silicon oxide layer 12 on the silicon wafer 10 is a field oxide insulation used in the complementary metal oxide semi-process. The polysilicon sensor strip 14 contains a central intrinsic edge 14a and a heavily doped edge portion i4b. The silicon oxide layer j 6 isolated from the polysilicon sensor strip 14 to isolate the metal strip 400 extends from the oxide layer 16 defining the contact for the complementary metal oxide semiconductor device. The electron movement test strip 400 structure contains a barrier metallurgical layer 18a deposited on the strip, a Ming / Si alloy 18b, and an anti-reflective coating 18c composed of Ti, Tiw, or Ti] Sf. Forming a laterally connected metallization layer on the polysilicon sensor 14 and the probe contacts 4 14 and 4 15 in the same process steps as the metallization layer of the electron movement test strip 400 and its probe contacts 401 and 402 Formed (the latter is not shown in -9- This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (Read the precautions on the back before filling this page).

訂IOrder I

經濟部中央標準局員工消費合作杜印製 五、發明説明(7 ) 圖4中)。 至圖5至圖10 ’敘述藉其而在傳統自動對正多晶矽閘極互 補型金氧半製造製程組成之组織内形成本具體實施例的製 造製程。描緣於這些圖形中的橫斷面與圖4中所表示者相同 現在參考圖5 ’提供由P-型< i 〇〇>排列之單結晶矽晶圓1 Ο 组成的基板。晶圓10含有形成於其表面之内的互補型金氧 半裝置,該表面由幾個氧化矽場絕緣區域12覆蓋β本具體 實施例製造於這樣的一個場氧化物區域12之上。這個區域_ 可位於晶圓切口中,或者位於特殊的製造測試位置(M T s) 中。然後使用600ec和650X:之間的低壓化學氣相沈積,以 矽烷和氫沈積一層本質性多結晶矽(此後稱之爲多晶矽)14 達1500至5000埃之間的厚度。這是用於形成產品裝置之閘 極電極的相同沈積。 下一步驟需要光阻罩幕1>尺1以保護多晶矽感測器的主動部 分免於離子佈植。儘管它施行於某些靜態随機存取記憶體 (Static-Random-Access-Memory,下文簡稱 SRAM)程 序中,但遮蔽某些多晶矽區域免於閘極佈植並不共通於所 有的互補型金氧半製程。因此,這可認爲是電子移動感測 器製造的額外微影步驟。 使用標準的光微影技術,將多晶矽層形成圖樣以界定寬 在1至4微米之間且長達10,000微米的長條。多晶矽長條的 厚度與產品中所使用之多晶矽閘極的厚度一致,厚可在〇又 至1微米之間。圖6敘述這個在位置上的光阻罩幕pRl,其 _ -10- 本紙張尺度逋用中關家標準(CNS)从賴_ (2敝297公羡〉 —------ (请先聞讀背面之注$項再填寫本页) .裝· —訂 經濟部中央標準局員工消費合作社印製 A7 ______B7 五^^7ΓΓ ---— 界定多晶碎長條的中心本質性部分1 4 a。 其次使用坤或嶙施行閘極離子佈植,並以傳統方式剝除 光阻罩幕PR1。施加第二光阻層並形成圖樣以形成罩幕pR2 。這個罩幕界定產品的多晶矽閘極,也界定圖7中之電子移 動感測器的整個多晶矽部分。然後使用具有氣/氬的反應 性離子蚀刻(reactive-ion-etching,下文簡稱rie),將露 出的多晶碎蚀刻掉,留下長條14,其由中心本質性部份1 4 a 和已摻雜的邊緣14b组成,如在圖8中所敘述。這個步驟也 形成產品的多晶矽閘極結構。 互補型金氧半加工以p -通道源極/没極佈植作爲繼續, 而η-通道裝置以光阻保護。然後,接著佈植n_通道裝置, 而以光阻保護p-通道裝置。多晶矽電子移動感測器結構由 這些佈植以光阻加以屏閉。在某些製程中,於源極/汲極 佈植之前’沿著多晶硬閘極提供氧化碎侧壁。多晶梦感測 器也接受這種側壁,但它在感測器的機能性上不會有任何 的衝擊。 現在參考圖9,使用低壓化學氣相沈積法沈積氧化矽層16 。這是將含有矽裝置之接觸開口,且同時提供多晶矽電子 移動感測器和電子移動金屬試驗長條間之絕緣的層。在某 些製程中,它可能含有矽酸磷玻璃(ph〇sphosilicate glass’下文簡稱PSG)或者含有砂·酸鱗领1玻璃 (borophosphosilicate glass,下文簡稱 B P S G)。將光阻 層PR3沈積於氧化矽層16之上並形成圖樣以界定裝置接觸 的存取開口以及暴露出多晶矽電子移動感測器的諸邊緣。 -11 - 本紙張尺度適用中國國家標準(CNS ) A4规格(210X297公着) (請先閣讀背面之注意事項再填寫本頁) 裝. —訂 A7 B7 i、發明説明(9 ) 然後藉由氧化矽層16之使用四氟甲烷(CF〇的反應性離子蚀 刻形成這些開口。 其次以濺鍍沈積金屬化層1 8。首先沈積由鈦層接著氣化 鈦層組成的障壁冶金層《然後沈積鋁/矽/銅合金。最後 將丁 i、TiW、或TiN薄層沈積於鋁合金之上,作爲抗反射塗 覆。這些沈積在多靶材濺鍍系統中實施,如此整個複合金 層化層在單一次抽氣中形成,因此避免不需要的暴露於大 氣。在金屬化層之上施加光阻層PR4並形成圖樣,並以反應 性離子蝕刻將金屬化層1 8蝕刻以形成裝置用的金屬化層, 到多晶矽電子移動感測器的接觸,及電子移動試驗長條4 〇 〇 本身(圖1 1及圖4)。 現在金屬長條可藉由施加探針至探針銲點401、402、 414和415而測試電子移動失效。在銲點401和402之間施 加固定的電壓以爲電子移動試驗長條提供與預先決定之應 力條件一致的電流。然後電路迴路4 2 1使用記錄裝置監控電 流相對時間。 測試方法視電子移動曝光的天性和激烈度而定。晶圓切 口中之電子移動長條的測試可在這點上進行,以決定晶圓 是否要報廢或重新排列。位於製造測試位置上的試驗試片 可予以保留,用於晶圓切割成晶粒後之接續的加速測試。 爲了完成後者,或者在製程中之較後的時點上施行切口測 試,銲點4 0 1、4 0 2、4 1 4和4 1 5的連接必須沿著金屬化體 系延長,穿過通孔,以使它們能用於適當時間的探針探測 -12- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 裝. -訂 經濟部中央橾準局員工消費合作杜印製 A7 B7 五、發明説明(10 ) 前述的具體實施例是用於基本、顯著的電子移動試驗結 構。它與廣泛使用之金氧半場效電晶體系列產品,特別是 互補型金氧半,製造之傳統製程的相容性使它作爲製程監 控器極爲有用...。這種相容性目前只局限於金屬化層的第一 層’儘管這層是電子移動考慮最爲普遍的。這個電子移動 試驗結構能夠在未失效之鄰接障壁金屬層的存在下,偵測 紹合金長條的^子移動失效。當在這些條件之下使用金屬 長條的直接測試時,該失效受到隱匿。製造至製造測試位 置上的試驗裝置可用於產品冶金層的信賴性及參數研究。 圖4至1 1的具體實施例使用p _基板。熟諳此技藝者應可相 當瞭解到,N -基板導電度也可加以使用。更可瞭解到,此 處所稱之基板導電度型態並不必然是稱呼起始晶圓的導電 度’也可以是晶圓内之擴散區域的導電度。 儘管本發明已經參考本文中的較佳具體實施例而特別地 加以顯示並説明’但熟諳此技藝者將瞭解到,在形式及細 節上的各種變化可在不偏離本發明的精神和範疇之下達到 (請先閲讀背面之注意事項再填寫本頁) -IJ, —I n I I--n —Λ · —i— - 經濟部令央標準局員工消費合作社印製 本紙張尺度適用中國國家揉準(CNS ) A4規格(210X297公釐)Du printed by the Ministry of Economic Affairs, Central Bureau of Standards and Staff's Consumer Cooperation V. Description of Invention (7) Figure 4). 5 to 10 'describe the manufacturing process by which this specific embodiment is formed within the organization composed of the conventional automatic alignment polysilicon gate complementary metal oxide semi-manufacturing process. The cross-sections traced in these figures are the same as those shown in FIG. 4. Reference is now made to FIG. 5 'to provide a substrate composed of a single crystal silicon wafer 1 Ο of P-type < i 〇〇 > arrangement. The wafer 10 contains complementary metal oxide semiconductor devices formed within its surface, which is covered by several silicon oxide field insulating regions 12 over β. This embodiment is fabricated on such a field oxide region 12. This area can be located in the wafer notch, or in a special manufacturing test location (MTs). Then using low-pressure chemical vapor deposition between 600ec and 650X :, a layer of intrinsic polycrystalline silicon (hereinafter referred to as polysilicon) 14 with a thickness of between 1500 and 5000 Angstroms is deposited with silane and hydrogen. This is the same deposit used to form the gate electrode of the product device. The next step requires a photoresist mask 1> ruler 1 to protect the active part of the polysilicon sensor from ion implantation. Although it is implemented in certain Static-Random-Access-Memory (hereinafter referred to as SRAM) procedures, it shields certain polysilicon regions from gate implantation and is not common to all complementary gold Oxygen half process. Therefore, this can be considered as an additional lithography step in the manufacture of electronic mobile sensors. Using standard photolithography techniques, the polysilicon layer is patterned to define strips between 1 and 4 microns wide and up to 10,000 microns. The thickness of the polysilicon strip is the same as the thickness of the polysilicon gate used in the product, and the thickness can be between 0 and 1 micron. Figure 6 depicts the position of the photoresist mask pRl, which is _-10- This paper scale uses the Zhongguanjia Standard (CNS) from Lai _ (2297297 public envy) ------- (please Read the note $ item on the back first and then fill out this page). Installed — — Printed by the Ministry of Economy Central Standards Bureau Employee Consumer Cooperative A7 ______B7 5 ^^ 7ΓΓ ---— Defines the central essential part of the polycrystalline broken strip 1 4 a. Secondly, use Kun or Zhuo to implement gate ion implantation and strip the photoresist mask PR1 in the traditional way. Apply a second photoresist layer and form a pattern to form the mask pR2. This mask defines the product's polysilicon gate Electrode, which also defines the entire polysilicon part of the electron movement sensor in Figure 7. Then, using reactive-ion-etching with gas / argon (reactive-ion-etching, rie for short), the exposed polycrystalline fragments are etched away, The strip 14 is left, which is composed of the central essential part 14 a and the doped edge 14 b, as described in Figure 8. This step also forms the polysilicon gate structure of the product. Complementary metal oxide semi-processing Continue with p-channel source / electrode implantation, while the n-channel device is protected with photoresist. Then, the n-channel device is implanted, and the p-channel device is protected by a photoresist. The polysilicon mobile sensor structure is screened by these implants with a photoresist. In some processes, the source / drain Before implanting, the oxidized broken sidewalls are provided along the polycrystalline hard gate. The polycrystalline dream sensor also accepts such sidewalls, but it will not have any impact on the function of the sensor. Now refer to FIG. 9 , Using a low-pressure chemical vapor deposition method to deposit the silicon oxide layer 16. This is the contact opening containing the silicon device, and at the same time provides a polysilicon electronic movement sensor and the insulation layer between the electron movement metal test strip. In some processes It may contain Phosphosilicate Glass (hereinafter referred to as PSG) or borophosphosilicate glass (hereinafter referred to as BPSG). A photoresist layer PR3 is deposited on the silicon oxide layer 16 A pattern is formed to define the access opening of the device contact and expose the edges of the polysilicon mobile sensor. -11-This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 public) (please first Read the precautions on the back of the cabinet and fill out this page) Pack. — Order A7 B7 i. Description of the invention (9) Then these openings are formed by reactive ion etching of silicon oxide layer 16 using tetrafluoromethane (CF〇. Sputter deposit metallization layer 18. First deposit a metallurgical barrier layer consisting of a titanium layer followed by a vaporized titanium layer, then deposit an aluminum / silicon / copper alloy. Finally, deposit a thin layer of Ding, TiW, or TiN on the aluminum alloy As an anti-reflective coating, these deposits are implemented in a multi-target sputtering system, so that the entire composite gold layer is formed in a single extraction, thus avoiding unnecessary exposure to the atmosphere. Apply a photoresist layer PR4 over the metallization layer and form a pattern, and etch the metallization layer 18 with reactive ion etching to form a metallization layer for the device, contact to the polysilicon electron movement sensor, and electron movement The test strip 4000 itself (Figure 11 and Figure 4). Now metal strips can be tested for electronic movement failure by applying probes to probe pads 401, 402, 414, and 415. A fixed voltage is applied between the solder joints 401 and 402 to provide the current for the electron movement test strip in accordance with the predetermined stress conditions. The circuit loop 4 2 1 then uses a recording device to monitor the current relative time. The test method depends on the nature and intensity of the electronic mobile exposure. The test of the electronic moving strip in the wafer cut can be carried out at this point to determine whether the wafer is to be scrapped or rearranged. The test specimens at the manufacturing test location can be retained for accelerated testing after the wafer is cut into die. In order to complete the latter, or perform a notch test at a later point in the manufacturing process, the connection of solder joints 4 0 1, 4 0 2, 4 1 4 and 4 1 5 must be extended along the metallization system, through the through holes, So that they can be used for probe detection at an appropriate time -12- This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling out this page). A7 B7 is printed by the Ministry of Central Administration and Staff of the Ministry of Consumer Affairs. V. Description of the invention (10) The foregoing specific embodiment is used for a basic and remarkable electronic mobile test structure. Its compatibility with the widely used metal oxide semi-field effect transistor series products, especially the complementary metal oxide semi-conductor, the traditional manufacturing process makes it extremely useful as a process monitor ... This compatibility is currently limited to the first layer of the metallization layer 'although this layer is the most prevalent for electronic mobility considerations. This electronic movement test structure can detect the movement failure of the Shao alloy strip in the presence of an unfailed adjacent barrier metal layer. When direct testing of metal strips is used under these conditions, the failure is concealed. The test device from the manufacturing to the manufacturing test position can be used for the reliability and parameter research of the metallurgical layer of the product. The specific embodiments of FIGS. 4 to 11 use p_substrates. Those skilled in the art should be able to understand that N-substrate conductivity can also be used. It can be further understood that the type of substrate conductivity referred to here is not necessarily referred to as the conductivity of the starting wafer ', but may also be the conductivity of the diffusion region within the wafer. Although the present invention has been specifically shown and described with reference to the preferred specific embodiments herein, those skilled in the art will understand that various changes in form and details can be made without departing from the spirit and scope of the present invention Achieved (please read the precautions on the back before filling in this page) -IJ, —I n I I--n —Λ · —i—-The Ministry of Economic Affairs ordered the Central Bureau of Standards to print this paper. The paper standard is suitable for Chinese national Standard (CNS) A4 specification (210X297mm)

Claims (1)

經濟部中央榇準局員工消費合作社印製 A8 B8 C8 D8 申請專利範圍 ι· 一種形成於矽晶圓基板上以偵測鄰接之金屬長條中電子 移動之開始並監控其進行的結構,包含有: 沿著它的侧邊具有電氣連接的本質性多晶欢長條, 以第一絕緣層與該基板電氣絕緣,並位於該金屬長條之 下且以第二絕緣層與該金屬長條絕緣。 2. 根據申請專利範園第丨項之結構,其中該金屬長條在末端 附裝有電氣連接,用於流通電流至金屬長條内之電子移 動造成該長條之局部加熱及最終之失效的程度。 3. 根據申請專利範圍第”頁之結構,其中該金屬長條長達 io,00 0微米,寬在0.1和2.0微米之間,且厚在01和10 微米之間。 4. 根據申請專利範圍第丨項之結構,其中該多晶矽長條比該 金屬長條更寬1至2微米。 5. 根據申請專利範圍第丨項之結構,其中該多晶矽長條的電 阻係數在25°C下,不小於1〇〇歐姆厘米。 6. 根據申請專利範園第之結構,其中第一絕緣層是場氧 化物絕緣層且厚度在3000和5000埃之間。 7. 根據申請專利範圍第丨項之結構,其中該第二絕緣層是氧 化矽且厚度在6000和10, 〇〇〇埃之間。 8·根據申請專利範圍第”頁之結構,其中第二絕緣層是梦酸 磷硼玻璃且厚度在6000和10,000埃之間。 9. 根據申請專利範圍第1項之結構,其中第二絕緣層是梦酸 嶙硼玻璃且厚度在6000和10,000埃之間。 10. 根據申請專利範圍第丨項之結構,其中金屬長條是館-碎- -14- 用中國國家標準(CNS)从胁(2丨οχ297公羡 V- ' C诗先閲讀背面之注意事項再填寫本頁)The A8 B8 C8 D8 is printed by the Employee Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economy. Scope of Patent Application ι · A structure formed on a silicon wafer substrate to detect the start of electronic movement in adjacent metal strips and monitor its progress, including : Essential polycrystalline strips with electrical connections along its sides, electrically insulated from the substrate with a first insulating layer, and under the metal strips and insulated from the metal strips with a second insulating layer . 2. According to the structure of the patent application garden item 丨, the metal strip is attached with an electrical connection at the end, which is used to circulate current to the electrons in the metal strip to cause local heating and final failure of the strip. degree. 3. According to the structure on page "of the patent application scope, in which the metal strip is up to 10,000 micrometers, the width is between 0.1 and 2.0 microns, and the thickness is between 01 and 10 microns. 4. According to the patent application scope The structure of item 丨, wherein the polycrystalline silicon strip is 1 to 2 microns wider than the metal strip. 5. According to the structure of item 丨 of the patent application scope, wherein the resistivity of the polycrystalline silicon strip is at 25 ° C, not Less than 100 ohm cm. 6. According to the structure of the patent application, where the first insulating layer is a field oxide insulating layer and the thickness is between 3000 and 5000 Angstroms. 7. The structure according to item 丨, Where the second insulating layer is silicon oxide and has a thickness between 6000 and 10,000 angstroms. 8. According to the structure of the page of the patent application scope, where the second insulating layer is phosphoric acid boron glass and the thickness is between Between 6000 and 10,000 Angstroms. 9. The structure according to item 1 of the scope of the patent application, in which the second insulating layer is borosilicate glass and has a thickness between 6000 and 10,000 Angstroms. 10. According to the structure of item 丨 in the scope of patent application, where the metal strips are pavilion-broken--14- using Chinese National Standards (CNS) from the threat (2 丨 ο297297 Xian's poems before reading the notes on the back (Fill in this page again) 六、申請專利範圍 'S 經濟部中央標準局員工消費合作社印製 銅合金。 11. 根據申請專利範圍第1項之結構,其中金屬長條含有第〜 鈥層、第二氮化鈦層、第三鋁·矽-銅合金層。 12. 根據申請專利範圍第6項之結構,其中金屬長條含有第〜 鈦層、第二氮化鈦層、 第二招·硬-銅合金層、及選自含有 鈇、鈥-鶴合金、和氮化欽之群體的第四層。 13. —種製造電子移動感測器結構的方法,包含有: 提供半導體基板; 形成第一氧化矽絕緣層於該半導體基板上; 沈積本質性多晶矽層於該第一絕緣層上; 沈積第一光阻層於該多晶矽層上; 將該第一光阻層形成圖樣以形成光阻長條; 佈植摻雜劑原子進入鄰接該光阻長條的多晶梦; 剝除該第一光阻層; 沈積第二光阻層於該多晶矽層上; 將邊第一光阻層形成圖樣以形成較寬的光阻長條,跨 置第一光阻長條的位置,如此,第二光阻長條覆蓋位於 ^亥第一光阻層所界定之本質性邵分之每—侧上之離子佈 植多晶碎的一部分; 蚀刻該多晶梦層,使用具終點偵測能力的異方性蚀刻 技術,因此形成具有本質性中心部分及高度摻雜側邊部 分的多晶梦長條; 剥除該第二光阻層; '沈積第二絕緣層於該半導體基板之上; -15- 本紙張尺度適用中國國家標準(CNS ) A4規格(2!〇χ297公董) --—---f 聚-- .' 5先聞讀背面之注事項再填寫本頁〕 m 5708 A8 B8 C8 D8 六、申請專利範圍 沈積第三光阻層於該第二絕緣層之上; 將該第三光阻層形成圖樣以暴露出位於該高度摻雜侧 邊部分之上的該第二絕緣層; 以上具有終點偵測能力的異方性蝕刻技術蝕刻該第二 絕緣層’以暴露出該多晶矽長條之該高度接雜的侧邊部 分; 剥除該第三光阻層; 沈積金屬化層於該半導體基板的表面之上; 沈積第四光阻層於該金屬化層之上,並將該光阻形成-圖樣以暴露出1)由多晶矽長條之高度摻雜邊緣至探針接 觸焊點的連接及2 )位於多晶矽長條之本質性部分之上的 金屬長條,其具有自該金屬長條之每一端點至探針接觸 點的連接; 蚀刻该第四光阻層所暴露出之區域中的該金屬化層, 使用具有終點债則能力的異方性蚀刻技術;及 剝除該第四光f且層。 14.根據申請專利範圍第1 3項之方法,其中第一絕緣層是場 氧化物絕緣層且厚度在3 000和5000埃之間。 經濟部中央標準局負工消費合作社印製 r!i----{裝—I (請先閲讀背面之注意事項再填寫本頁) 15_根據申請專利範圍第I3項之方法,其中該第二絕緣層是 氧化矽且厚度在6000和10,000埃之間。 16. 根據申請專利範圍第1 3項之方法,其中第二絕緣層是梦 酸磷玻璃且厚度在6000和10,000埃之間。 17. 根據申請專利範圍第1 3項之方法,其中第二絕緣層是碎 酸鱗硼玻璃且厚度在6000和10,000埃之間。 • 16- 本紙乐尺度逋用中國國家橾準(CNS ) Μ規格(210X297公釐)6. Scope of patent application 'S Copper alloy printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 11. The structure according to item 1 of the scope of the patent application, in which the metal strips contain the ~~ layer, the second titanium nitride layer, and the third aluminum · silicon-copper alloy layer. 12. The structure according to item 6 of the patent application scope, in which the metal strip contains the first titanium layer, the second titanium nitride layer, the second stroke-hard-copper alloy layer, and is selected from the group consisting of 鈇, 鈥 -Cr alloy, And the fourth layer of the Ninqin group. 13. A method of manufacturing an electronic motion sensor structure, comprising: providing a semiconductor substrate; forming a first silicon oxide insulating layer on the semiconductor substrate; depositing an intrinsic polysilicon layer on the first insulating layer; depositing a first A photoresist layer on the polysilicon layer; patterning the first photoresist layer to form a photoresist strip; implanting dopant atoms into the polycrystalline dream adjacent to the photoresist strip; stripping the first photoresist Layer; deposit a second photoresist layer on the polysilicon layer; pattern the first photoresist layer to form a wider photoresist strip, spanning the position of the first photoresist strip, so, the second photoresist The strip covers a portion of the polycrystalline fragment that is located on each side of the essential edge defined by the first photoresist layer of the ^ Hai; the polycrystalline dream layer is etched, using the anisotropy with endpoint detection capability Etching technology, thus forming a polycrystalline dream strip with an essential central portion and highly doped side portions; stripping off the second photoresist layer; 'depositing a second insulating layer on the semiconductor substrate; The paper standard applies to the Chinese national standard (CNS) A4 specification (2! 〇χ297 Gongdong) ------ f poly-. '5 Read the notes on the back and then fill in this page] m 5708 A8 B8 C8 D8 VI. Application for patent scope deposit The third photoresist layer is on the second insulating layer; the third photoresist layer is patterned to expose the second insulating layer on the highly doped side portion; Anisotropic etching technique etched the second insulating layer to expose the highly conjunct side portion of the polysilicon strip; stripping the third photoresist layer; depositing a metallization layer on the surface of the semiconductor substrate Depositing a fourth photoresist layer on the metallization layer, and forming the photoresist-pattern to expose 1) the connection from the highly doped edge of the polysilicon strip to the probe contact pad and 2) on the polysilicon A metal strip above the essential part of the strip, which has a connection from each end of the metal strip to the contact point of the probe; etching the metallization layer in the area exposed by the fourth photoresist layer , Using anisotropic etching technology with the ability to end the debt; and In addition to the fourth layer and the light f. 14. The method according to item 13 of the patent application scope, wherein the first insulating layer is a field oxide insulating layer and has a thickness between 3 000 and 5000 angstroms. Printed by the National Bureau of Standards of the Ministry of Economic Affairs, the Consumer Cooperative Society r! I ---- {装 —I (Please read the precautions on the back before filling out this page) 15_ According to the method of patent application scope item I3, of which The second insulating layer is silicon oxide and has a thickness between 6000 and 10,000 Angstroms. 16. The method according to item 13 of the patent application scope, in which the second insulating layer is phosphoric acid phosmonate glass and has a thickness between 6000 and 10,000 Angstroms. 17. The method according to item 13 of the scope of the patent application, in which the second insulating layer is broken acid boron glass and has a thickness between 6000 and 10,000 Angstroms. • 16- This paper music standard uses the Chinese National Standard (CNS) M specifications (210X297mm) 經濟部中央標隼局員工消費合作社印製 18·:據:請專利範圍第13項之方法’其中佈植的摻雜劑原 19. 根據中請專利範圍第13項之方法,其中佈植的摻雜: 子是鱗^ ’、 20. 根據申請專利範圍第13項之方法,其中該多晶矽長條& 比該金屬長條更寬1至2微米。 ’、疋 21. 根據申請專利範圍第13項之方法,其中該多晶矽長條的 电阻係數在2 5 C下’不小於1〇〇歐姆厘米。 ' 22. 根據申請專利範圍第13項之方法,其中蚀刻多晶發的異 方性蝕刻技術是使用氣和氬的反應性離子蚀刻。 ” 23. 根據申請專利範園第13項之方法,其中蝕刻第二絕緣層 的異方性蝕刻技術是使用四氟甲烷的反應性離子蝕刻。 24根據申請專利範圍第13項之方法,其中蝕刻金屬化層的 異方性蝕刻技術是反應性離子蝕刻。 25. 根據中請專利範圍第13項之方法,其中金屬化層是銘 -銅合金。 26. 根據申請專利範圍第1 3項之方法,其中金屬化層含有第 一欽廣、乐一氮化鈥層、及第三銘珍_銅合金層。 27. 根據申請專利範園第1 3項之方法,其中金屬化層含有第 一鈦層、第二氮化鈦層、第三銘_矽_銅合金層、及選自含 有鈦、鈦-鎢合金、和氮化鈦之群體的第四層。 28. —種測試積體電路中所用之金屬導線之電子移動的方法 ,包含有: 形成試驗結構於半導體晶圓基板上,具有本質性多晶 •17· 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁j 'ΊΛ^'''''.'-'''^^^^^^^'*^^·.'4·'"、',.. -裝- -、-ST'Printed by the Ministry of Economic Affairs, Central Standard Falcon Bureau Employee Consumer Cooperative 18 ·: According to: the method of item 13 of the patent application 'The original dopant planted in it 19. According to the method of item 13 of the patent application, the planted Doping: The ions are scales ^ ', 20. According to the method of claim 13 of the patent application scope, wherein the polycrystalline silicon strips & are wider than the metal strips by 1 to 2 microns. ‘疋 21. The method according to item 13 of the patent application scope, wherein the resistivity of the polycrystalline silicon strip at 2 5 C’ is not less than 100 ohm centimeters. '22. The method according to item 13 of the patent application scope, wherein the anisotropic etching technique for etching polycrystalline hair is reactive ion etching using gas and argon. 23. According to the method of Patent Application No. 13 item, wherein the anisotropic etching technique for etching the second insulating layer is reactive ion etching using tetrafluoromethane. 24 According to the method of Item 13 of the patent application range, where etching The anisotropic etching technology of the metallization layer is reactive ion etching. 25. According to the method in item 13 of the patent application, the metallization layer is Ming-copper alloy. 26. According to the method in item 13 of the patent application range , Where the metallization layer contains the first Qinguang, Le-Yu nitride layer, and the third Mingzhen_copper alloy layer. 27. According to the method of item 13 of the patent application, the metallization layer contains the first titanium Layer, the second titanium nitride layer, the third Ming_silicon_copper alloy layer, and the fourth layer selected from the group consisting of titanium, titanium-tungsten alloy, and titanium nitride. The method of electronic movement of the metal wires used includes: forming a test structure on a semiconductor wafer substrate, which is essentially polycrystalline • 17 · The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please Read the notes on the back first Fill in this page again j 'ΊΛ ^' '' '' .'- '' '^^^^^^^' * ^^ · .'4 · '",', ..-装--,- ST ' 六、申請專利範圍 l·% 矽長條,使沿著它每一侧邊的電氣連接接通至探針銲點 ,並以第一絕緣層與該基板電氣隔絕,且位於在每一端 點具有探針銲點的金屬電子移動試驗長條之下並與其絕 緣; 放置該半導體晶圓至電氣測試探針組成的平台上; 連接阻抗亭時間函數之量測的儀器設備至多晶矽長條 的諸探針銲點; 施加電壓於該金屬長條的探針銲點之間以發展出超過i X 105安培/平方厘米的電流;及 記錄多晶矽的阻抗爲時間的函數,超過金屬長條之電 子移動失效足以發生的時段。 訂 29. 根據申請專利範圍第28項之方法,其中金屬長條是銘-珍 _銅合金。 30. 根據申請專利範圍第28項之方法,其中金屬長條含有第 一鈦層、第二氮化鈦層、第三鋁_矽_銅合金層。 3L根據申請專利範圍第28項之方法,其中金屬長條含有第 一鈦層、第二氮化鈦層、第三鋁_矽_銅合金層及選自本 有鈥、鈥-鎢合金,和氮化鈥之群體的第四層。 經濟部中央標隼局負工消費合作社印製 32. 根據申請專利範圍第13項之方法,其中結構是製造於製 造測試位置(MTS)晶片之内,包括在自動對正之多晶矽 閘極金氧半場效電晶體產品晶片罩幕组中。 33. 根據申請專利範圍第13項之方法,其中結構是製造於含 有自動對正之多晶矽閘極金氧半場效電晶體產品晶片之 晶圓的切口區域之内。 -18- 本紙張尺度適用中國國家標準(CNS〉八4規格(21〇><297公釐)6. Patent scope l ·% silicon strip, which connects the electrical connection along each side to the probe solder joint, and is electrically isolated from the substrate by the first insulating layer, and is located at each end Probe solder joints are under and insulated from the metal electron movement test strip; place the semiconductor wafer on a platform composed of electrical test probes; connect the instruments and equipment for measuring the time function of the impedance kiosk to the probes of the polysilicon strip Pin solder joints; applying voltage between the probe solder joints of the metal strip to develop a current in excess of i X 105 amperes per square centimeter; and recording the impedance of the polysilicon as a function of time, electron movement failure over the metal strip Enough time to happen. Order 29. According to the method of claim 28 of the patent application, the metal strip is Ming-Zhen_Copper alloy. 30. The method according to item 28 of the patent application scope, wherein the metal strip contains a first titanium layer, a second titanium nitride layer, and a third aluminum_silicon_copper alloy layer. 3L according to the method of claim 28, wherein the metal strip contains a first titanium layer, a second titanium nitride layer, a third aluminum_silicon_copper alloy layer and is selected from the original 戥, 鈥 -tungsten alloy, and The fourth layer of the group of nitrides. Printed by the Consumer Labor Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 32. According to the method of item 13 of the patent application scope, the structure is manufactured within the manufacturing test position (MTS) wafer, including the automatic alignment of the polysilicon gate metal oxide half field In the wafer cover screen group of effective transistor products. 33. The method according to item 13 of the patent application scope, in which the structure is manufactured in the notch area of the wafer containing the self-aligning polysilicon gate metal oxide half field effect transistor product wafer. -18- This paper scale is applicable to Chinese national standard (CNS> 84 specifications (21〇 < 297mm) A8 B8 C8 D8 穴、申請專利乾圍 34. 根據申請專利範圍第32項之方法,其中位於製^$ 置上的金屬長條在製程元成及晶圓切割成晶粒之後 到長時期可靠性測試。 ’受1 35. 根據申請專利範圍第3 3項之方法,其中金屬長條測試電 子移動失效,以保證繼續加工前之金屬化製造工作的品 質。 (靖先閲;nr背面之注意事項再填寫本頁) -訂 經濟部中央標準局負工消費合作社印製 19 本紙張尺度適用中國國家標準(CNS ) A4规格(210X297公釐)A8 B8 C8 D8 hole, patent application dry circumference 34. According to the method of item 32 of the patent application scope, in which the metal strip on the manufacturing position is reliable after a long process and after the wafer is cut into grains to long-term reliability test. ’Subject 1 35. According to the method of item 33 of the patent application scope, in which the metal strip test electron movement fails to ensure the quality of metallization manufacturing work before continuing processing. (Jing first reading; note on the back of nr and then fill out this page)-Ordered Printed by the National Bureau of Standards, Ministry of Economic Affairs, Negative Consumer Cooperative 19 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm)
TW85106935A 1996-06-10 1996-06-10 The polysilicon electromigration sensor TW295708B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW85106935A TW295708B (en) 1996-06-10 1996-06-10 The polysilicon electromigration sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW85106935A TW295708B (en) 1996-06-10 1996-06-10 The polysilicon electromigration sensor

Publications (1)

Publication Number Publication Date
TW295708B true TW295708B (en) 1997-01-11

Family

ID=51565299

Family Applications (1)

Application Number Title Priority Date Filing Date
TW85106935A TW295708B (en) 1996-06-10 1996-06-10 The polysilicon electromigration sensor

Country Status (1)

Country Link
TW (1) TW295708B (en)

Similar Documents

Publication Publication Date Title
KR100370295B1 (en) Formation of arrays of microelectronic elements
US5712194A (en) Semiconductor device including interlayer dielectric film layers and conductive film layers
KR100187601B1 (en) Semiconductor device and manufacturing method thereof
US4994410A (en) Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process
US6228754B1 (en) Method for forming semiconductor seed layers by inert gas sputter etching
US4926237A (en) Device metallization, device and method
US5627101A (en) Method of fabricating polysilicon electromigration sensor which can detect and monitor electromigration in composite metal lines on integrated circuit structures
US7046029B2 (en) Conductive material for integrated circuit fabrication
EP0310108A2 (en) Interconnection structure of a semiconductor device and method of manufacturing the same
US5043290A (en) Process for forming electrodes for semiconductor devices by focused ion beam technology
US3868723A (en) Integrated circuit structure accommodating via holes
EP0526889B1 (en) Method of depositing a metal or passivation fabric with high adhesion on an insulated semiconductor substrate
US5070391A (en) Semiconductor contact via structure and method
US6261946B1 (en) Method for forming semiconductor seed layers by high bias deposition
US6147361A (en) Polysilicon electromigration sensor which can detect and monitor electromigration in composite metal lines on integrated circuit structures with improved sensitivity
TW295708B (en) The polysilicon electromigration sensor
KR960000360B1 (en) Low contact resistance process
JPH10229086A (en) Semiconductor device and fabrication thereof
US4948749A (en) Process for forming electrodes for semiconductor devices
JP3116534B2 (en) Method for manufacturing flip chip of integrated circuit device
JPS62133713A (en) Formation of electrode and electrode thereof
KR950003221B1 (en) Fabricating method of semiconductor device
US6642518B1 (en) Assembly and method for improved scanning electron microscope analysis of semiconductor devices
US6677608B2 (en) Semiconductor device for detecting gate defects
Cook et al. Performance of vertical power devices with contact-level copper metallization

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees