TW278247B - Fabrication method of full feature EEPROM memory cell - Google Patents

Abstract

A fabrication method of full feature EEPROM memory cell, that Si applicable to implement memory cell of one select gate transistor and one stacked gate transistor on first-type substrate, comprises the steps of: forming gate insulating layer and the first conductive layer ondetermined position of the above substrate as select gate of the above select gate transistor, and confining channel area of the above select gate transistor; forming mask on the above select gate and substrate; forming sidewall spacer on mask of lateral side of the above select gate, and confining channel area of the above stacked gate transistor with the above sidewall spacer; removing mask located between the above select gate and the above sidewall spacer; with the above select gate and sidewall spacer as mask doping the second dopant to the first-type substrate, and forming the second-type doped area on two lateral sides of the above channel area; removing the above sidewall spacer and mask; forming separating insulation on the above select gate surface, and forming tunneling insulation on the above substrate; in sequence forming the second conductive layer, dielectric and the third conductive layer as stack gate of the above stacked gate transistor, and across the above select gate and channel area of stacked gate transistor on its one side; with the above gate as mask doping the second-type dopant to the first-type substrate to form the second-type heavily doped area, then combined with the above second-type lightly doped area to form drain and source electrode of the above select gate transistor and stacked gate transistor.