TW249295B - - Google Patents

Info

Publication number
TW249295B
TW249295B TW083110307A TW83110307A TW249295B TW 249295 B TW249295 B TW 249295B TW 083110307 A TW083110307 A TW 083110307A TW 83110307 A TW83110307 A TW 83110307A TW 249295 B TW249295 B TW 249295B
Authority
TW
Taiwan
Application number
TW083110307A
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of TW249295B publication Critical patent/TW249295B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW083110307A 1993-11-30 1994-11-08 TW249295B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/159,634 US5468340A (en) 1992-10-09 1993-11-30 Highly selective high aspect ratio oxide etch method and products made by the process

Publications (1)

Publication Number Publication Date
TW249295B true TW249295B (zh) 1995-06-11

Family

ID=22573345

Family Applications (1)

Application Number Title Priority Date Filing Date
TW083110307A TW249295B (zh) 1993-11-30 1994-11-08

Country Status (5)

Country Link
US (1) US5468340A (zh)
EP (1) EP0655775A1 (zh)
JP (1) JP3464061B2 (zh)
KR (1) KR100323242B1 (zh)
TW (1) TW249295B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468339A (en) * 1992-10-09 1995-11-21 Advanced Micro Devices, Inc. Plasma etch process
US5935877A (en) * 1995-09-01 1999-08-10 Applied Materials, Inc. Etch process for forming contacts over titanium silicide
US6001699A (en) * 1996-01-23 1999-12-14 Intel Corporation Highly selective etch process for submicron contacts
DE19707886C2 (de) * 1997-02-27 2003-12-18 Micronas Semiconductor Holding Verfahren zum Erzeugen von Kontaktlöchern in einer Halbleiteranordnung
KR19980084172A (ko) * 1997-05-21 1998-12-05 윤종용 고 식각선택비를 이용한 반도체장치의 건식식각방법
TW430900B (en) * 1997-09-08 2001-04-21 Siemens Ag Method for producing structures having a high aspect ratio
US6066566A (en) * 1998-01-28 2000-05-23 International Business Machines Corporation High selectivity collar oxide etch processes
US6057193A (en) * 1998-04-16 2000-05-02 Advanced Micro Devices, Inc. Elimination of poly cap for easy poly1 contact for NAND product
US6080676A (en) * 1998-09-17 2000-06-27 Advanced Micro Devices, Inc. Device and method for etching spacers formed upon an integrated circuit gate conductor
US6281132B1 (en) 1998-10-06 2001-08-28 Advanced Micro Devices, Inc. Device and method for etching nitride spacers formed upon an integrated circuit gate conductor
US6221745B1 (en) * 1998-11-27 2001-04-24 Taiwan Semiconductor Manufacturing Company High selectivity mask oxide etching to suppress silicon pits
US6214742B1 (en) * 1998-12-07 2001-04-10 Advanced Micro Devices, Inc. Post-via tin removal for via resistance improvement
EP1132959A1 (en) 2000-03-03 2001-09-12 STMicroelectronics S.r.l. A method of forming low-resistivity connections in non-volatile memories
JP3539946B2 (ja) * 2002-03-28 2004-07-07 沖電気工業株式会社 Ｓｏｉ構造を有する半導体装置の製造方法
US8246787B2 (en) * 2009-09-03 2012-08-21 Pratt & Whitney Rockedyne, Inc. Solar desalinization plant
US8246786B2 (en) * 2009-09-03 2012-08-21 Pratt & Whitney Rocketdyne, Inc. Solar desalinization plant

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4795722A (en) * 1987-02-05 1989-01-03 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
GB2214709A (en) * 1988-01-20 1989-09-06 Philips Nv A method of enabling connection to a substructure forming part of an electronic device
US5254213A (en) * 1989-10-25 1993-10-19 Matsushita Electric Industrial Co., Ltd. Method of forming contact windows
US5026666A (en) * 1989-12-28 1991-06-25 At&T Bell Laboratories Method of making integrated circuits having a planarized dielectric
US4978420A (en) * 1990-01-03 1990-12-18 Hewlett-Packard Company Single chamber via etch through a dual-layer dielectric
US5021121A (en) * 1990-02-16 1991-06-04 Applied Materials, Inc. Process for RIE etching silicon dioxide
US5213659A (en) * 1990-06-20 1993-05-25 Micron Technology, Inc. Combination usage of noble gases for dry etching semiconductor wafers
US5022958A (en) * 1990-06-27 1991-06-11 At&T Bell Laboratories Method of etching for integrated circuits with planarized dielectric
JP2697952B2 (ja) * 1990-11-15 1998-01-19 シャープ株式会社 半導体装置の製造方法
US5176790A (en) * 1991-09-25 1993-01-05 Applied Materials, Inc. Process for forming a via in an integrated circuit structure by etching through an insulation layer while inhibiting sputtering of underlying metal
US5269879A (en) * 1991-10-16 1993-12-14 Lam Research Corporation Method of etching vias without sputtering of underlying electrically conductive layer
US5284549A (en) * 1992-01-02 1994-02-08 International Business Machines Corporation Selective fluorocarbon-based RIE process utilizing a nitrogen additive
US5468339A (en) * 1992-10-09 1995-11-21 Advanced Micro Devices, Inc. Plasma etch process

Also Published As

Publication number Publication date
KR950015622A (ko) 1995-06-17
JPH07193057A (ja) 1995-07-28
US5468340A (en) 1995-11-21
JP3464061B2 (ja) 2003-11-05
KR100323242B1 (ko) 2002-05-13
EP0655775A1 (en) 1995-05-31

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Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent