TW243544B - - Google Patents

Info

Publication number
TW243544B
TW243544B TW082110602A TW82110602A TW243544B TW 243544 B TW243544 B TW 243544B TW 082110602 A TW082110602 A TW 082110602A TW 82110602 A TW82110602 A TW 82110602A TW 243544 B TW243544 B TW 243544B
Authority
TW
Taiwan
Application number
TW082110602A
Other languages
Chinese (zh)
Original Assignee
At & T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by At & T Corp filed Critical At & T Corp
Application granted granted Critical
Publication of TW243544B publication Critical patent/TW243544B/zh

Links

Classifications

    • H10P50/283
    • H10P95/064
TW082110602A 1992-12-31 1993-12-14 TW243544B (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US99932792A 1992-12-31 1992-12-31

Publications (1)

Publication Number Publication Date
TW243544B true TW243544B (en:Method) 1995-03-21

Family

ID=25546198

Family Applications (1)

Application Number Title Priority Date Filing Date
TW082110602A TW243544B (en:Method) 1992-12-31 1993-12-14

Country Status (3)

Country Link
EP (1) EP0607684A3 (en:Method)
JP (1) JPH06232096A (en:Method)
TW (1) TW243544B (en:Method)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4511430A (en) * 1984-01-30 1985-04-16 International Business Machines Corporation Control of etch rate ratio of SiO2 /photoresist for quartz planarization etch back process
US4545852A (en) * 1984-06-20 1985-10-08 Hewlett-Packard Company Planarization of dielectric films on integrated circuits
US5006485A (en) * 1988-12-09 1991-04-09 U.S. Philips Corporation Method of manufacturing an intergrated circuit including steps for forming interconnections between patterns formed at different levels
JP3092185B2 (ja) * 1990-07-30 2000-09-25 セイコーエプソン株式会社 半導体装置の製造方法
US5378318A (en) * 1992-06-05 1995-01-03 Vlsi Technology, Inc. Planarization

Also Published As

Publication number Publication date
EP0607684A3 (en) 1995-03-15
JPH06232096A (ja) 1994-08-19
EP0607684A2 (en) 1994-07-27

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