TW241349B - - Google Patents
Info
- Publication number
- TW241349B TW241349B TW083102460A TW83102460A TW241349B TW 241349 B TW241349 B TW 241349B TW 083102460 A TW083102460 A TW 083102460A TW 83102460 A TW83102460 A TW 83102460A TW 241349 B TW241349 B TW 241349B
- Authority
- TW
- Taiwan
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/117,278 US5422914A (en) | 1993-09-07 | 1993-09-07 | System and method for synchronizing data communications between two devices operating at different clock frequencies |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW241349B true TW241349B (OSRAM) | 1995-02-21 |
Family
ID=22371974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW083102460A TW241349B (OSRAM) | 1993-09-07 | 1994-03-21 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5422914A (OSRAM) |
| EP (1) | EP0645717A1 (OSRAM) |
| JP (1) | JPH0784668A (OSRAM) |
| KR (1) | KR100304036B1 (OSRAM) |
| TW (1) | TW241349B (OSRAM) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5548620A (en) * | 1994-04-20 | 1996-08-20 | Sun Microsystems, Inc. | Zero latency synchronized method and apparatus for system having at least two clock domains |
| SG47976A1 (en) * | 1994-05-10 | 1998-04-17 | Intel Corp | Method and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a p/q integer ratio relationship |
| US5564027A (en) * | 1995-04-20 | 1996-10-08 | International Business Machines Corporation | Low latency cadence selectable interface for data transfers between busses of differing frequencies |
| US5812875A (en) * | 1995-05-02 | 1998-09-22 | Apple Computer, Inc. | Apparatus using a state device and a latching circuit to generate an acknowledgement signal in close proximity to the request signal for enhancing input/output controller operations |
| US5781765A (en) * | 1995-11-03 | 1998-07-14 | Motorola, Inc. | System for data synchronization between two devices using four time domains |
| US5802132A (en) | 1995-12-29 | 1998-09-01 | Intel Corporation | Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme |
| US5834956A (en) | 1995-12-29 | 1998-11-10 | Intel Corporation | Core clock correction in a 2/N mode clocking scheme |
| US5821784A (en) * | 1995-12-29 | 1998-10-13 | Intel Corporation | Method and apparatus for generating 2/N mode bus clock signals |
| US5862373A (en) * | 1996-09-06 | 1999-01-19 | Intel Corporation | Pad cells for a 2/N mode clocking scheme |
| US5826067A (en) | 1996-09-06 | 1998-10-20 | Intel Corporation | Method and apparatus for preventing logic glitches in a 2/n clocking scheme |
| EP0840237B1 (en) * | 1996-10-29 | 2007-01-03 | Matsushita Electric Industrial Co., Ltd. | Synchronization of data processor with external bus |
| US5794019A (en) * | 1997-01-22 | 1998-08-11 | International Business Machines Corp. | Processor with free running clock with momentary synchronization to subsystem clock during data transfers |
| US5898640A (en) * | 1997-09-26 | 1999-04-27 | Advanced Micro Devices, Inc. | Even bus clock circuit |
| US6269136B1 (en) * | 1998-02-02 | 2001-07-31 | Microunity Systems Engineering, Inc. | Digital differential analyzer data synchronizer |
| FI982040L (fi) * | 1998-09-22 | 2000-03-23 | Nokia Multimedia Network Terminals Oy | Menetelmä ja laite datavirran synkronoimiseksi |
| US6549593B1 (en) | 1999-07-19 | 2003-04-15 | Thomson Licensing S.A. | Interface apparatus for interfacing data to a plurality of different clock domains |
| US6956918B2 (en) * | 2001-06-27 | 2005-10-18 | Intel Corporation | Method for bi-directional data synchronization between different clock frequencies |
| US7134035B2 (en) * | 2003-05-30 | 2006-11-07 | Sun Mircosystems, Inc. | Method for generating a synchronization signal based on the clock ratio between two clock domains for data transfer between the domains |
| US7393450B2 (en) * | 2003-11-26 | 2008-07-01 | Silveri Michael A | System for maintaining pH and sanitizing agent levels of water in a water feature |
| US7219177B2 (en) * | 2004-11-23 | 2007-05-15 | Winbond Electronics Corp. | Method and apparatus for connecting buses with different clock frequencies by masking or lengthening a clock cycle of a request signal in accordance with the different clock frequencies of the buses |
| US7734741B2 (en) | 2004-12-13 | 2010-06-08 | Intel Corporation | Method, system, and apparatus for dynamic reconfiguration of resources |
| US7738484B2 (en) * | 2004-12-13 | 2010-06-15 | Intel Corporation | Method, system, and apparatus for system level initialization |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0042924B1 (en) * | 1980-06-30 | 1984-03-21 | International Business Machines Corporation | Data transfer apparatus |
| US4412342A (en) * | 1981-12-18 | 1983-10-25 | Gte Automatic Electric Labs Inc. | Clock synchronization system |
| US4845437A (en) * | 1985-07-09 | 1989-07-04 | Minolta Camera Kabushiki Kaisha | Synchronous clock frequency conversion circuit |
| EP0375794A1 (en) * | 1988-12-24 | 1990-07-04 | International Business Machines Corporation | Method of synchronizing signals which are generated on different chips having on-chip clocking systems with different speed |
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1993
- 1993-09-07 US US08/117,278 patent/US5422914A/en not_active Expired - Fee Related
-
1994
- 1994-03-21 TW TW083102460A patent/TW241349B/zh active
- 1994-08-17 EP EP94112817A patent/EP0645717A1/en not_active Withdrawn
- 1994-08-24 JP JP6220777A patent/JPH0784668A/ja active Pending
- 1994-09-02 KR KR1019940022059A patent/KR100304036B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0784668A (ja) | 1995-03-31 |
| US5422914A (en) | 1995-06-06 |
| KR100304036B1 (ko) | 2001-11-22 |
| KR950009450A (ko) | 1995-04-24 |
| EP0645717A1 (en) | 1995-03-29 |