TW229293B - Cache memory control system - Google Patents

Cache memory control system

Info

Publication number
TW229293B
TW229293B TW82103437A TW82103437A TW229293B TW 229293 B TW229293 B TW 229293B TW 82103437 A TW82103437 A TW 82103437A TW 82103437 A TW82103437 A TW 82103437A TW 229293 B TW229293 B TW 229293B
Authority
TW
Taiwan
Prior art keywords
cache memory
memory
bits
tag
write
Prior art date
Application number
TW82103437A
Other languages
Chinese (zh)
Inventor
Fa-Jong Shieh
Original Assignee
Acer Sertek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Acer Sertek Inc filed Critical Acer Sertek Inc
Priority to TW82103437A priority Critical patent/TW229293B/en
Application granted granted Critical
Publication of TW229293B publication Critical patent/TW229293B/en

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Abstract

A cache memory control system which can be switching between write-in andwrite-back mode is used in combination with one processing unit, one mainmemory, one cache memory and one tag memory. The cache memory, connectedwith the processing unit and main memory, is mainly used to store partialinformation in main memory to be accessed by processing unit. The tag memoryis mainly used to store the related data for judging the access of cachememory. The tag memory at least has N input ports for receiving N input bitsand at least one enable end for receiving enable signal. The cache memorycontrol system includes one control unit for controlling the data access,when the cache memory control system switches from the write-in mode towrite-back mode, the control unit sets the a bits from N input bits of tagmemory into status bit and (N-a) bits into tag bits, in which the status bitis used to indicate the related status information about the data stored incache memory and the tag bit is used to indicate the related addressinformation of the date stored in cache memory with respect to the mainmemory. When the cache memory control system switches from the write-backmode to write-in mode, the control unit sets the status bits back to tagbits.
TW82103437A 1993-05-03 1993-05-03 Cache memory control system TW229293B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW82103437A TW229293B (en) 1993-05-03 1993-05-03 Cache memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW82103437A TW229293B (en) 1993-05-03 1993-05-03 Cache memory control system

Publications (1)

Publication Number Publication Date
TW229293B true TW229293B (en) 1994-09-01

Family

ID=51348531

Family Applications (1)

Application Number Title Priority Date Filing Date
TW82103437A TW229293B (en) 1993-05-03 1993-05-03 Cache memory control system

Country Status (1)

Country Link
TW (1) TW229293B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103605618A (en) * 2013-11-20 2014-02-26 浪潮电子信息产业股份有限公司 Non-write-back mirror image and direct write switching method for cache mirror image system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103605618A (en) * 2013-11-20 2014-02-26 浪潮电子信息产业股份有限公司 Non-write-back mirror image and direct write switching method for cache mirror image system
CN103605618B (en) * 2013-11-20 2017-02-08 浪潮电子信息产业股份有限公司 Non-write-back mirror image and direct write switching method for cache mirror image system

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