TW202422803A - Electronic packaging structure and manufacturing method thereof - Google Patents

Abstract

An electronic packaging structure including a first circuit structure, a second circuit structure and at least one electronic device is provided. The bottom side of the first circuit structure has at least one cavity. The first circuit structure is disposed on the second circuit structure. The first circuit structure and the second circuit structure are electrically connected to each other. The electronic device is disposed on the second circuit structure. The electronic device is disposed corresponding to the cavity of the first circuit structure.

Description

Electronic packaging structure and manufacturing method thereof

The present invention relates to an electronic packaging structure and a manufacturing method thereof, and in particular to an electronic packaging structure having electronic components embedded between a plurality of circuit structures and a manufacturing method thereof.

With the advancement of technology, the functions of electronic products are becoming more and more abundant, and electronic mobile devices are becoming more and more dependent. In response to the demand for miniaturization and lightweighting of electronic products, the integration of antenna structure and chip packaging structure is conducive to the miniaturization and lightweighting of electronic products. Generally speaking, for the existing chip packaging structure with antenna structure, the chip is usually set on the circuit substrate and the film sealing material is covered on the chip to form a chip packaging structure. The antenna structure is set on the chip packaging structure, and the antenna structure is electrically connected to the circuit substrate through the conductive column or conductive ball that penetrates the film sealing material in the chip packaging structure. However, in the above-mentioned packaging structure, the electronic components may be difficult to be well protected; and/or the above-mentioned packaging structure may not be able to effectively prevent the radio frequency signal from being scattered during the transmission process and has a relatively large volume.

The present invention provides an electronic packaging structure, wherein the electronic components included in the electronic packaging structure may be well protected.

The electronic package structure of the present invention includes a first circuit structure, a second circuit structure and at least one electronic component. The bottom side of the first circuit structure has at least one cavity. The first circuit structure is located on the second circuit structure. The first circuit structure and the second circuit structure are electrically connected to each other. The electronic component is arranged on the second circuit structure. The electronic component corresponds to the cavity of the first circuit structure.

In one embodiment of the present invention, the inner surface of the cavity of the first circuit structure is covered with a conductive material.

In one embodiment of the present invention, the first circuit structure includes at least one coaxial conductive via. The coaxial conductive via includes an inner conductive layer, an outer conductive layer and a dielectric layer. The dielectric layer is located between the inner conductive layer and the outer conductive layer.

In one embodiment of the present invention, the material of the outer conductive layer of the coaxial conductive via includes copper.

In one embodiment of the present invention, the material of the dielectric layer of the coaxial conductive via includes resin.

In an embodiment of the present invention, the first circuit structure further includes an upper conductive layer and a lower conductive layer. Two ends of the outer conductive layer of the coaxial conductive via are respectively connected to a portion of the upper conductive layer and a portion of the lower conductive layer.

In one embodiment of the present invention, the inner conductive layer of the coaxial conductive via is electrically connected to the outermost circuit layers on both sides of the first circuit structure.

In one embodiment of the present invention, at least one of the first circuit structure or the second circuit structure includes an outermost solder resist layer.

In one embodiment of the present invention, the electronic package structure further includes a filling material. The filling material is located between the first circuit structure and the second circuit structure.

In one embodiment of the present invention, the electronic package structure further includes a conductive connector, which is located between the first circuit structure and the second circuit structure to electrically connect the first circuit structure and the second circuit structure.

In one embodiment of the present invention, the electronic package structure further includes a conductive connector, which is located between the electronic element and the second circuit structure to electrically connect the electronic element and the second circuit structure.

The manufacturing method of the electronic packaging structure of the present invention includes the following steps: providing a first circuit structure having at least one cavity on its bottom side; providing a second circuit structure; configuring at least one electronic component on the second circuit structure; and electrically connecting the second circuit structure having the electronic component configured thereon and the first circuit structure to each other, and positioning the first circuit structure on the second circuit structure so that the electronic component configured on the second circuit structure corresponds to the cavity of the first circuit structure.

Based on the above, in the electronic package structure, since the electronic component is located between the first circuit structure and the second circuit structure, and at least part of the electronic component can be located in the cavity of the first circuit structure, the electronic component can be better protected, and the possibility of damage or destruction of the electronic component can be reduced, thereby improving the quality of the electronic package structure.

The following examples are listed and described in detail with the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn according to the original size.

In addition, the terms "including", "having", etc. used in this document are open terms, which means "including but not limited to".

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or portions, these elements, components, regions, and/or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Therefore, the "first element", "component", "region", "layer" or "portion" discussed below may be referred to as a second element, component, region, layer or portion without departing from the teachings of this article.

The directional terms mentioned in this article, such as "upper", "lower", "top", "bottom", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are used for explanation, not for limiting the present invention.

In the accompanying drawings, each diagram depicts the general characteristics of the methods, structures and/or materials used in a particular embodiment. However, these diagrams should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for the sake of clarity, the relative size, thickness and position of various film layers, regions and/or structures may be reduced or exaggerated.

In the following embodiments, the same or similar elements will be denoted by the same or similar reference numerals, and their redundant description will be omitted. In addition, the features in different embodiments can be combined with each other without conflict, and simple equivalent changes and modifications made according to this specification or the scope of the patent application are still within the scope of this patent.

＜ First circuit structure ＞

The first circuit structure 100 (indicated in FIG. 1L) may be formed as shown in FIG. 1A to FIG. 1M. FIG. 1A to FIG. 1L may be partial cross-sectional schematic diagrams of a partial formation method of the first circuit structure 100. FIG. 1M may be a partial bottom schematic diagram of a partial formation method of the first circuit structure 100. FIG. 1M may be a bottom schematic diagram corresponding to FIG. 1K.

1A , a core structure 101 is provided.

In one embodiment, the core structure 101 may include a first core layer 105. The first core layer 105 may include a polymer glass fiber composite substrate, a glass substrate, a ceramic substrate, an insulating silicon substrate, or a polyimide (PI) glass fiber composite substrate, but the present invention is not limited thereto.

In one embodiment, the thickness of the first core layer 105 may be approximately 200 micrometers (µm).

In one embodiment, the core structure 101 may further include a circuit layer located on the surface of the first core layer 105. For example, the core structure may further include a first upper circuit layer 111 and a first lower circuit layer 112. The first upper circuit layer 111 and the first lower circuit layer 112 are located on the upper surface and the lower surface of the first core layer 105, respectively. The circuit design (layout design) of the circuit layer (including but not limited to the first upper circuit layer 111 or the first lower circuit layer 112) can be adjusted according to design requirements and is not limited in the present invention.

In one embodiment, the core structure 101 may include a patterned copper clad laminate (CCL), but the present invention is not limited thereto.

In an embodiment not shown or in a cross section not shown, corresponding circuits in the first upper circuit layer 111 and corresponding circuits in the first lower circuit layer 112 may be electrically connected to each other via a conductive via (not shown) penetrating the first core layer 105 .

1B , corresponding insulating layers are formed on the upper and lower sides of the first core layer 105. For example, the first upper insulating layer 115 and the first lower insulating layer 116 may be located on the upper surface and the lower surface of the first core layer 105, respectively.

The insulating layer (e.g., the first upper insulating layer 115 and/or the first lower insulating layer 116) can be formed by an appropriate method. In one embodiment, the insulating layer can be formed by coating and curing (e.g., light curing, heat curing, or static curing); for example, the insulating layer can include a polyimide coating layer. In one embodiment, the insulating layer can be formed by lamination; for example, the insulating layer can include a polyimide dry film.

In one embodiment, the insulating layer may cover the corresponding circuit layer. For example, the first upper insulating layer 115 may cover the first upper circuit layer 111; and/or the first lower insulating layer 116 may cover the first lower circuit layer 112.

In one embodiment, the first upper insulating layer 115 or the first lower insulating layer 116 may directly contact a portion of the first core layer 105 .

In one embodiment, the thickness of the first upper insulating layer 115 and the first lower insulating layer 116 may be the same or similar. For example, the ratio of the thickness of the first upper insulating layer 115 to the thickness of the first lower insulating layer 116 may be between 90% and 110%. In one embodiment, the thickness of the first upper insulating layer 115 or the thickness of the first lower insulating layer 116 may be approximately 250 microns.

1B , in one embodiment, a conductive layer may be disposed on the insulating layer. For example, the third upper conductive layer 131 c may cover the first upper insulating layer 115 , and/or the third lower conductive layer 132 c may cover the first lower insulating layer 116 .

In one embodiment, the conductive layer on the insulating layer may be formed by sputtering. In one embodiment, the conductive layer on the insulating layer (eg, the third upper conductive layer 131c and/or the third lower conductive layer 132c) may be referred to as a plating seed layer.

In one embodiment, the conductive layer on the insulating layer can be formed by lamination. In one embodiment, the insulating layer and the conductive layer thereon (such as the first upper insulating layer 115 and the third upper conductive layer 131c; and/or the first lower insulating layer 116 and the third lower conductive layer 132c) can be a copper clad laminate (CCL).

In one embodiment, the thickness of the third upper conductive layer 131c and the third lower conductive layer 132c may be the same or similar. For example, the ratio of the thickness of the third upper conductive layer 131c to the thickness of the third lower conductive layer 132c may be between 90% and 110%.

Referring to FIG. 1C , at least one through hole 108 is formed. The through hole 108 may penetrate the first core layer 105 and a portion of the film layer on the surface thereof. For example, the through hole 108 may penetrate a portion of the first upper wiring layer 111. In one embodiment, the through hole 108 may be formed by laser drilling, mechanical drilling, and/or other suitable methods.

It should be noted that only one through hole 108 is exemplarily shown in FIG1C , but the present invention is not limited thereto. In other embodiments not shown or other cross-sections not shown, other through holes identical to or similar to the through hole 108 may be provided.

Referring to FIG. 1D , a conductive layer (which may be referred to as an outer conductive layer) 191 is formed on the inner wall of the through hole 108. In one embodiment, a corresponding electroplated layer may be formed on the third upper conductive layer 131c and/or the third lower conductive layer 132c by electroplating. The aforementioned electroplated layer may further extend to the inner wall of the through hole 108 to form a corresponding conductive layer 191. In one embodiment, the conductive layer 191 on the inner wall may include a copper layer.

In one embodiment, the manner in which the conductive layer 191 covers the inner wall (eg, range and/or thickness) can be adjusted by using appropriate electroplating methods or parameters.

In one embodiment, the conductive layer 191 may completely cover the inner wall of the through hole 108 .

In another embodiment, a conductive layer similar to the conductive layer 191 may partially cover the inner wall of the through hole 108. For example, the current source for electroplating may be applied only to the third lower conductive layer 132c, but not to the third upper conductive layer 131c. In this way, the inner wall of the through hole 108 closer to the third upper conductive layer 131c may not be covered by the conductive layer.

In one embodiment, the conductive layer 191 does not completely fill the through hole 108. In one embodiment, the maximum distance of the inner edge of the conductive layer 191 in a direction perpendicular to the extension direction of the through hole 108 can be about 400 microns to 500 microns. In other words, the inner diameter of the through hole 108 covered with the conductive layer 191 can be about 400 microns to 500 microns.

1E, a first dielectric layer 195 is formed in the through hole 108 covered with the conductive layer 191. The material of the first dielectric layer 195 may include a plugging resin material, a polymer glass-ceramic hybrid material or other appropriate dielectric materials.

In one embodiment, a suitable planarization process (such as a polishing process) may be performed to allow the first dielectric layer 195 to have a relatively flat outer surface, but the present invention is not limited thereto.

Continuing to refer to FIG. 1E , the third upper conductive layer 131c and the electroplated layer thereon may be patterned by a suitable patterning process (e.g., photolithography process) to form a corresponding third upper circuit layer 131; and/or, the third lower conductive layer 132c and the electroplated layer thereon may be patterned by a suitable patterning process (e.g., photolithography process) to form a corresponding third lower circuit layer 132. In other words, the third upper circuit layer 131 or the third lower conductive layer 132c may include a stack of multiple conductive layers.

1F , corresponding insulating layers are formed on the upper and lower sides of the first core layer 105. For example, the third upper insulating layer 135 and the third lower insulating layer 136 may be located on the upper surface and the lower surface of the first core layer 105, respectively.

The insulating layer may be formed by a suitable method. For example, the insulating layer (eg, the third upper insulating layer 135 and/or the third lower insulating layer 136) may include a polyimide coating layer or a polyimide dry film.

In one embodiment, the insulating layer may cover the corresponding circuit layer. For example, the third upper insulating layer 135 may cover the third upper circuit layer 131 , and/or the third lower insulating layer 136 may cover the third lower circuit layer 132 .

In one embodiment, the third upper insulating layer 135 may directly contact a portion of the first upper insulating layer 115 ; and/or, the third lower insulating layer 136 may directly contact a portion of the first lower insulating layer 116 .

In one embodiment, the thickness of the third upper insulating layer 135 and the third lower insulating layer 136 may be the same or similar. For example, the ratio of the thickness of the third upper insulating layer 135 to the thickness of the third lower insulating layer 136 may be between 90% and 110%. In one embodiment, the thickness of the third upper insulating layer 135 and/or the thickness of the third lower insulating layer 136 may be less than the thickness of the first upper insulating layer 115 and/or the thickness of the first lower insulating layer 116. In one embodiment, the thickness of the third upper insulating layer 135 or the thickness of the third lower insulating layer 136 may be approximately 50 microns.

1F , in one embodiment, a conductive layer may be disposed on the insulating layer. For example, the fifth upper conductive layer 151 c may cover the third upper insulating layer 135 ; and/or the fifth lower conductive layer 152 c may cover the third lower insulating layer 136 .

In one embodiment, the conductive layer on the insulating layer may be formed by sputtering. In one embodiment, the conductive layer on the insulating layer (eg, the fifth upper conductive layer 151c and/or the fifth lower conductive layer 152c) may be referred to as a plating seed layer.

In one embodiment, the conductive layer on the insulating layer can be formed by lamination. In one embodiment, the insulating layer and the conductive layer thereon (such as the third upper insulating layer 135 and the fifth upper conductive layer 151c; and/or the third lower insulating layer 136 and the fifth lower conductive layer 152c) can be a copper clad laminate (CCL).

In one embodiment, the thicknesses of the fifth upper conductive layer 151c and the fifth lower conductive layer 152c may be the same or similar. For example, the ratio of the thickness of the fifth upper conductive layer 151c to the thickness of the fifth lower conductive layer 152c may be between 90% and 110%.

Referring to FIG. 1G , at least one through hole 109 is formed. The through hole 109 may penetrate the first dielectric layer 195 and the film layers on the surface thereof (e.g., the third upper insulating layer 135, the fifth upper conductive layer 151c, the third lower insulating layer 136 and/or the fifth lower conductive layer 152c). In one embodiment, the through hole 109 may be formed by laser drilling, mechanical drilling and/or other appropriate methods.

Referring to FIG. 1H , a conductive layer (which may be referred to as an inner conductive layer) 192 is formed on the inner wall of the through hole 109. In one embodiment, a corresponding electroplated layer may be formed on the fifth upper conductive layer 151c and/or the fifth lower conductive layer 152c by electroplating. The aforementioned electroplated layer may further extend to the inner wall of the through hole 109 to form a corresponding conductive layer 192. In one embodiment, the conductive layer 192 on the inner wall may include a copper layer.

In one embodiment, the conductive layer 192 may completely cover the inner wall of the through hole 109.

In one embodiment, the conductive layer 192 does not completely fill the through hole 109. In one embodiment, the maximum distance of the inner edge of the conductive layer 192 in a direction perpendicular to the extension direction of the through hole 109 can be about 50 microns to 150 microns. In other words, the inner diameter of the through hole 109 covered with the conductive layer 192 can be about 50 microns to 150 microns.

In an embodiment not shown, the conductive layer 192 may completely fill the through hole 109. In an embodiment not shown, the conductive layer 192 in the through hole 109 may be a conductive pillar.

1I, in one embodiment, a second dielectric layer 196 is formed in the through hole 109 covered with the conductive layer 192. The material of the second dielectric layer 196 may include a plugging resin material, a polymer glass-ceramic hybrid material or other suitable dielectric materials.

In one embodiment, a suitable planarization process (such as a polishing process) may be performed to allow the second dielectric layer 196 to have a relatively flat outer surface, but the present invention is not limited thereto.

In one embodiment, the outer conductive layer 191 , the first dielectric layer 195 , the inner conductive layer 192 , and the second dielectric layer 196 may constitute a coaxial conductive via 190 .

Please continue to refer to FIG. 1I , the fifth upper conductive layer 151c and the electroplated layer thereon may be patterned by a suitable patterning process (e.g., photolithography process) to form a fifth upper circuit layer 151 accordingly; and/or, the fifth lower conductive layer 152c and the electroplated layer thereon may be patterned by a suitable patterning process (e.g., photolithography process) to form a fifth lower circuit layer 152 accordingly. In other words, the fifth upper circuit layer 151 or the fifth lower circuit layer 152 may include a stack of multiple conductive layers.

1J , a cavity 170 is formed on one side of the first core layer 105. In one embodiment, a portion of the insulating layer (e.g., a portion of the third lower insulating layer 136 and a portion of the first lower insulating layer 116) may be removed by etching, burning, drilling or other appropriate methods to form a corresponding cavity 170.

In one embodiment, the depth of cavity 170 may be approximately 200 microns.

In one embodiment, during the process of forming the cavity 170 , a portion of the third lower insulating layer 136 may be removed, so that a portion of the third lower circuit layer 132 may be exposed.

1K and 1M , in one embodiment, a bottom line layer 172 may be formed on a side of the first core layer 105 corresponding to the cavity 170. The bottom line layer 172 may be formed by sputtering, electroplating, photolithography, and/or other appropriate methods.

In one embodiment, the bottom wiring layer 172 at least completely covers the cavity 170 .

1K , in one embodiment, a corresponding conductive layer may be coated on the fifth upper circuit layer 151. In one embodiment, the conductive layer coated on the fifth upper circuit layer 151 may further cover one side of the second dielectric layer 196.

In terms of structure, the conductive layer coated on the fifth upper wiring layer 151 can directly contact the fifth upper wiring layer 151 to form a multi-layer conductive structure, and there is no insulating material or dielectric material between the multi-layer conductive structure. For simplicity, the fifth upper wiring layer 151 and the conductive layer thereon can still be referred to as the fifth upper wiring layer and use the same label.

1L , in one embodiment, corresponding insulating layers may be formed on the upper and lower sides of the first core layer 105. For example, a fifth upper insulating layer 155 and a fifth lower insulating layer 156 may be located on the upper surface and the lower surface of the first core layer 105, respectively.

In one embodiment, the thickness of the fifth upper insulating layer 155 or the thickness of the fifth lower insulating layer 156 may be approximately 20 micrometers.

In one embodiment, the fifth upper insulating layer 155 and/or the fifth lower insulating layer 156 may be referred to as a solder resist layer. In one embodiment, the solder resist layer of the first circuit structure 100 may be its outermost insulating layer. For example, the fifth upper insulating layer 155 may be the topmost insulating layer in the first circuit structure 100, and/or the fifth lower insulating layer 156 may be the bottommost insulating layer in the first circuit structure 100.

In one embodiment, the bottom wiring layer 172 of the first circuit structure 100 may be the bottommost conductive layer thereof.

After the above-mentioned manufacturing process, the manufacturing of the first circuit structure 100 of an embodiment can be substantially completed.

1L , the first circuit structure 100 has at least one cavity 170 on its bottom side, and the first circuit structure 100 may further include at least one coaxial conductive via 190 .

In one embodiment, the coaxial conductive via 190 may include an outer conductive layer 191, a first dielectric layer 195, and an inner conductive layer 192. The first dielectric layer 195 is located between the outer conductive layer 191 and the inner conductive layer 192. The outer conductive layer 191 at least surrounds a portion of the inner conductive layer 192. The outer conductive layer 191 and the inner conductive layer 192 are electrically separated from each other.

In one embodiment, the coaxial conductive via 190 may further include a second dielectric layer 196. The inner conductive layer 192 may be located between the first dielectric layer 195 and the second dielectric layer 196.

In one embodiment, the first circuit structure 100 may include a first core layer 105, a corresponding circuit layer and/or a corresponding circuit layer insulation layer located on the upper side and/or the lower side of the first core layer 105. The cavity 170 is located on the lower side of the first core layer 105. The coaxial conductive via 190 penetrates the first core layer 105 and a portion of the insulation layer to be electrically connected to the corresponding circuit in the circuit layer.

For example, the first circuit structure 100 may include a fifth upper insulating layer 155, a fifth upper wiring layer 151, a third upper insulating layer 135, a third upper wiring layer 131, a first upper insulating layer 115, a first upper wiring layer 111, a first core layer 105, a first lower wiring layer 112, a first lower insulating layer 116, a third lower wiring layer 132, a third lower insulating layer 136, a fifth lower wiring layer 152, and a fifth lower insulating layer 156. The cavity 170 penetrates a portion of the third lower insulating layer 136 and is recessed in a portion of the first lower insulating layer 116. The coaxial conductive via 190 penetrates the first upper insulating layer 115, the first core layer 105 and the first lower insulating layer 116. The inner conductive layer 192 of the coaxial conductive via 190 is electrically connected to a corresponding line in the fifth upper wiring layer 151 and a corresponding line in the fifth lower wiring layer 152. The outer conductive layer 191 of the coaxial conductive via 190 is electrically connected to a corresponding line in the third upper wiring layer 131 and/or a corresponding line in the first upper wiring layer 111; and the outer conductive layer 191 of the coaxial conductive via 190 is electrically connected to a corresponding line in the third lower wiring layer 132 and/or another corresponding line in the fifth lower wiring layer 152.

In one embodiment, the first circuit structure 100 may further include a bottom wiring layer 172. The bottom wiring layer 172 may include a first wiring portion 172a and a second wiring portion 172b. The first wiring portion 172a and the second wiring portion 172b are electrically separated from each other.

The first circuit portion 172a may be electrically connected to the outer conductive layer 191. For example, the first circuit portion 172a may be embedded in the third lower insulating layer 136 and may be electrically connected to the outer conductive layer 191 through a corresponding circuit in a portion of the third lower circuit layer 132 exposed by the third lower insulating layer 136.

The second circuit portion 172 b may be electrically connected to the inner conductive layer 192 . For example, the second circuit portion 172 b may be electrically connected to the inner conductive layer 192 via a corresponding circuit in the fifth lower circuit layer 152 .

In one embodiment, the first circuit portion 172a at least completely covers the cavity 170. For example, the first circuit portion 172a at least completely covers the sidewall and the bottom of the cavity 170.

In one embodiment, part of the circuit layer may be located between the fifth lower insulating layer 156 and the third lower insulating layer 136. For example, part of the first circuit portion 172a and/or part of the second circuit portion 172b may be located between the fifth lower insulating layer 156 and the third lower insulating layer 136.

In one embodiment, some film layers (such as insulating layers) on both sides of the first core layer 105 can be symmetrically arranged. In this way, the degree and/or possibility of warpage can be reduced during the manufacture and/or subsequent application of the first circuit structure 100, thereby improving the yield and/or quality.

For example, the first upper insulating layer 115 and the first lower insulating layer 116 may be located on both sides of the first core layer 105, and the thickness of the first upper insulating layer 115 and the first lower insulating layer 116 may be the same or similar. For another example, the first upper insulating layer 115 and the first lower insulating layer 116 may contact both sides of the first core layer 105, respectively.

For example, the third upper insulating layer 135 and the third lower insulating layer 136 may be located on both sides of the first core layer 105, and the thickness of the third upper insulating layer 135 and the third lower insulating layer 136 may be the same or similar. For another example, the third upper insulating layer 135 and the third lower insulating layer 136 may contact the first upper insulating layer 115 and the first lower insulating layer 116, respectively.

For example, the fifth upper insulating layer 155 and the fifth lower insulating layer 156 may be located on both sides of the first core layer 105, and the thickness of the fifth upper insulating layer 155 and the fifth lower insulating layer 156 may be the same or similar. For another example, the fifth upper insulating layer 155 and the fifth lower insulating layer 156 may contact the third upper insulating layer 135 and the third lower insulating layer 136, respectively.

＜ Second circuit structure ＞

The second circuit structure 200 may be formed in a manner similar to the first circuit structure 100 .

1N , the second circuit structure 200 may include a second core layer 205, and corresponding circuit layers and/or corresponding circuit layer insulation layers located on the upper side and/or the lower side of the second core layer 205. For example, the second circuit structure 200 may include a sixth upper insulation layer 265, a fourth upper circuit layer 241, a fourth upper insulation layer 245, a second upper circuit layer 221, a second core layer 205, a second lower circuit layer 222, a fourth lower insulation layer 246, a fourth lower circuit layer 242, and a sixth lower insulation layer 266.

In one embodiment, the second core layer 205 may include a polymer glass fiber composite substrate, a glass substrate, a ceramic substrate, an insulating silicon substrate or a polyimide (PI) glass fiber composite substrate, etc., but the present invention is not limited thereto. In one embodiment, the second circuit structure 200 may be referred to as a hard board.

In one embodiment, the second core layer 205 may include a polyimide (PI) substrate, a polyethylene terephthalate (PET) substrate, etc., but the present invention is not limited thereto. In one embodiment, the second circuit structure 200 may be referred to as a flexible board.

In one embodiment, the second circuit structure 200 may be a rigid-flex board.

In one embodiment, the thickness of the second core layer 205 may be approximately 60 microns.

In one embodiment, the material and/or formation method of the fourth upper wiring layer 241, the fourth lower wiring layer 242, the second upper wiring layer 221 and/or the second lower wiring layer 222 may be the same as or similar to the material and/or formation method of the aforementioned wiring layers (e.g., the fifth upper wiring layer 151, the fifth lower wiring layer 152, the third upper wiring layer 131, the third lower wiring layer 132, the first upper wiring layer 111 and/or the first lower wiring layer 112).

In one embodiment, the material and/or formation method of the fourth upper insulating layer 245 and/or the fourth lower insulating layer 246 may be the same or similar to the material and/or formation method of the aforementioned first upper insulating layer 115, first lower insulating layer 116, third upper insulating layer 135 and/or third lower insulating layer 136.

In one embodiment, the thickness of the fourth upper insulating layer 245 or the thickness of the fourth lower insulating layer 246 may be approximately 25 micrometers.

In one embodiment, the material and/or formation method of the sixth upper insulating layer 265 and/or the sixth lower insulating layer 266 may be the same as or similar to the material and/or formation method of the aforementioned fifth upper insulating layer 155 and/or the fifth lower insulating layer 156.

In one embodiment, the thickness of the sixth upper insulating layer 265 or the thickness of the sixth lower insulating layer 266 may be approximately 20 micrometers.

In one embodiment, the sixth upper insulating layer 265 and/or the sixth lower insulating layer 266 may be referred to as a solder resist layer. In one embodiment, the solder resist layer of the second circuit structure 200 may be its outermost insulating layer.

In one embodiment, the sixth upper insulating layer 265 may have a corresponding opening to expose the corresponding circuit in the fourth upper circuit layer 241. In one embodiment, the portion of the fourth upper circuit layer 241 exposed by the opening of the sixth upper insulating layer 265 may be referred to as a connection pad.

In one embodiment, the sixth lower insulating layer 266 may have a corresponding opening to expose the corresponding circuit in the fourth lower circuit layer 242. In one embodiment, the portion of the fourth lower circuit layer 242 exposed by the opening of the sixth lower insulating layer 266 may be referred to as a connection pad.

＜ Integration of the second circuit structure and electronic components ＞

1O , the electronic element 300 may be disposed on the second circuit structure 200 , and the electronic element 300 may be electrically connected to the corresponding circuit in the fourth upper circuit layer 241 .

In one embodiment, the electronic component 300 can be electrically connected to the corresponding circuit in the fourth upper circuit layer 241 through the corresponding conductive connector 402. The conductive connector 402 can include a conductive column (such as a copper column), solder (such as a solder ball), a conductive glue (such as silver paste or solder paste) or other suitable conductive members.

In one embodiment, the electronic element 300 may be electrically connected to the corresponding circuit in the fourth upper circuit layer 241 by flip-chip bonding.

In one embodiment, the electronic component 300 may include a corresponding communication module. For example, the electronic component 300 may be adapted to receive and/or transmit signals via a corresponding antenna. In one embodiment, the electronic component 300 may include a communication chip.

＜ Electronic packaging structure ＞

Referring to FIG. 1P , the corresponding circuits in the second circuit structure 200 integrated with the electronic component 300 and the corresponding circuits in the first circuit structure 100 are electrically connected to each other. Furthermore, the electronic component 300 is arranged corresponding to the cavity 170 of the first circuit structure 100. The electronic component 300 is located between the first circuit structure 100 and the second circuit structure 200. The electronic component 300 is at least partially located in the cavity 170 of the first circuit structure 100.

The corresponding circuits in the second circuit structure 200 and the corresponding circuits in the first circuit structure 100 can be electrically connected via corresponding conductive connectors 401. The conductive connectors 401 can include conductive pillars (such as copper pillars), solder (such as solder balls), conductive glue (such as silver paste or solder paste), or other suitable conductive members.

After the above process, the electronic package structure 901 of an embodiment can be substantially manufactured. It should be noted that the present invention does not limit the manufacturing order of the first circuit structure 100 and the second circuit structure 200.

The electronic package structure 901 includes a first circuit structure 100, a second circuit structure 200, and at least one electronic component 300. The first circuit structure 100 has at least one cavity 170 on the bottom side. The first circuit structure 100 includes at least one coaxial conductive via 190. The first circuit structure 100 is located on the second circuit structure 200. The first circuit structure 100 and the second circuit structure 200 are electrically connected to each other. The electronic component 300 is disposed on the second circuit structure 200. The electronic component 300 corresponds to the cavity 170 of the first circuit structure 100.

In one embodiment, the electronic package structure 901 may further include an insulating filling material 408. The filling material 408 may be located between the first circuit structure 100 and the second circuit structure 200, and/or filled in the cavity 170 of the first circuit structure 100.

In one embodiment, the filling material 408 may include an insulating thermally conductive material. For example, the thermally conductive material may be filled in the cavity 170 of the first circuit structure 100, and the thermally conductive material may be thermally coupled to the electronic component 300 and the first circuit portion 172a located in the cavity 170. In this way, when the electronic component 300 operates, the heat generated can be transferred to the outside more easily or quickly. The thermally conductive material is, for example, a thermal interface material (TIM), but the present invention is not limited thereto.

In one embodiment, the electronic component 300 completely overlaps the first circuit portion 172a in the cavity 170 along a direction parallel to the thickness of the first circuit structure 100. In addition, the first circuit portion 172a can be grounded. The aforementioned grounding can include a floating ground or a physical ground. Therefore, the first circuit portion 172a can be regarded as an electromagnetic interference shielding (EMI Shielding) layer. In this way, when the electronic component 300 is operating, the possibility of the electronic component 300 interfering with other components or being interfered with by other components can be reduced, and the signal quality can be improved.

In one embodiment, at least part of the circuits in the fifth upper circuit layer 151 may be antennas. The electronic component 300 may be electrically connected to the aforementioned antenna through the corresponding circuits in the second circuit structure 200 and the inner conductive layer 192 of the coaxial conductive via 190 of the first circuit structure 100. In one embodiment, the antenna electrically connected to the electronic component 300 may be referred to as a driven antenna. In one embodiment, the part of the fifth upper circuit layer 151 that serves as an antenna may be the topmost conductive layer in the first circuit structure 100.

In one embodiment, at least a portion of a current path between an antenna electrically connected to the electronic component 300 and the electronic component 300 may be surrounded, isolated or shielded by a grounded conductor, thereby reducing signal interference and/or improving signal quality.

In one embodiment, a portion of the circuit layer between the antenna electrically connected to the electronic component 300 and the grounded first circuit portion 172 a (eg, a portion of the first lower circuit layer 112 ) may be referred to as a parasitic antenna, but the present invention is not limited thereto.

Fig. 2 is a partial cross-sectional schematic diagram of an electronic package structure according to the second embodiment of the present invention. Referring to Fig. 2 and Fig. 1P, the electronic package structure 902 and its manufacturing method of this embodiment are similar to the electronic package structure 901 and its manufacturing method of the aforementioned embodiment, and similar components thereof are represented by the same reference numerals and have similar functions, and description thereof is omitted.

The electronic package structure 902 includes a first circuit structure 100', a second circuit structure 200, and at least one electronic component 300. The first circuit structure 100' includes at least one coaxial conductive via 190'.

In one embodiment, the coaxial conductive via 190' may include an outer conductive layer 191', a first dielectric layer 195, and an inner conductive layer 192. The first dielectric layer 195 is located between the outer conductive layer 191' and the inner conductive layer 192. The outer conductive layer 191' surrounds a portion of the inner conductive layer 192. The outer conductive layer 191' and the inner conductive layer 192 are electrically separated from each other.

In one embodiment, in a direction perpendicular to the thickness of the first circuit structure 100', the outer conductive layer 191' is not located between the inner conductive layer 192 and the fifth upper circuit layer 151. In addition, the fifth upper circuit layer 151 is only used as an antenna (e.g., an excited antenna); or, the fifth upper circuit layer 151 is only used as an antenna and a dummy pattern without signal transmission.

In one embodiment, in a direction perpendicular to the thickness of the first circuit structure 100', the outer conductive layer 191' is not located between the inner conductive layer 192 and the third upper circuit layer 131. In addition, the third upper circuit layer 131 is only used as an antenna (e.g., a parasitic antenna); or, the third upper circuit layer 131 is only used as an antenna and a dummy circuit for no signal transmission; or, the third upper circuit layer 131 is only used as a dummy circuit for no signal transmission.

In one embodiment, in a direction perpendicular to the thickness of the first circuit structure 100', the outer conductive layer 191' is not located between the inner conductive layer 192 and the first upper circuit layer 111. In addition, the first upper circuit layer 111 is only used as an antenna (e.g., a parasitic antenna); or, the first upper circuit layer 111 is only used as an antenna and a dummy circuit for no signal transmission; or, the first upper circuit layer 111 is only used as a dummy circuit for no signal transmission.

In one embodiment, in a direction perpendicular to the thickness of the first circuit structure 100', the outer conductive layer 191' is not located between the inner conductive layer 192 and the first lower circuit layer 112. In addition, the first lower circuit layer 112 is only used as an antenna (e.g., a parasitic antenna); or, the first lower circuit layer 112 is only used as an antenna and a dummy circuit for no signal transmission; or, the first lower circuit layer 112 is only used as a dummy circuit for no signal transmission.

In the above embodiments, the conductive layer or circuit layer may be a single layer or a multi-layer structure. If the conductive layer or circuit layer is a multi-layer structure, the multi-layer structure may not have an insulating material or a dielectric material between them. In addition, in terms of structure, if the conductive layer or circuit layer is a multi-layer structure, even if the multi-layer structure is formed by different processes, it can still be (but not limited to) represented by the same terms and/or symbols.

In the above embodiments, the insulating layer or dielectric layer may be a single layer or a multi-layer structure. If the insulating layer or dielectric layer is a multi-layer structure, there may be no conductive material between the multi-layer structure. In addition, in terms of structure, if the insulating layer or dielectric layer is a multi-layer structure, even if the multi-layer structure is formed by different processes, it can still be (but not limited to) represented by the same terms and/or symbols.

In the aforementioned embodiments, corresponding circuits in one circuit layer and corresponding circuits in another circuit layer can be electrically connected to each other through corresponding conductive vias. That is, unless otherwise specified or implied, even if the drawings do not show that corresponding circuits in one circuit layer and corresponding circuits in another circuit layer are electrically connected to each other, the corresponding circuits in the aforementioned circuit layer and corresponding circuits in the aforementioned another circuit layer can still be electrically connected to each other through conductive vias not shown in the drawings or on a cross section not shown.

In summary, in the electronic package structure, since the electronic component is located between the first circuit structure and the second circuit structure, and at least part of the electronic component can be located in the cavity of the first circuit structure, the electronic component can be better protected, and the possibility of damage or destruction of the electronic component can be reduced, thereby improving the quality of the electronic package structure.

On the other hand, the first circuit structure of the electronic package structure may further include a coaxial conductive via. The electronic element may be electrically connected to a corresponding circuit (such as an antenna) through the coaxial conductive via. In this way, the interference of the signal may be improved and/or the quality of the signal may be improved.

901, 902: electronic packaging structure 100, 100': first circuit structure 101: core structure 155: fifth upper insulating layer 151: fifth upper wiring layer 151c: fifth upper conductive layer 135: third upper insulating layer 131: third upper wiring layer 131c: third upper conductive layer 115: first upper insulating layer 111: first upper wiring layer 105: first core layer 112: first lower wiring layer 116: first lower insulating layer 132: third lower wiring layer 132c: third lower conductive layer 136: third lower insulating layer 152: fifth lower circuit layer 152c: fifth lower conductive layer 156: fifth lower insulating layer 108: through hole 109: through hole 190, 190': coaxial conductive via 196: second dielectric layer 192: conductive layer 195: first dielectric layer 191, 191': conductive layer 170: cavity 172: bottom circuit layer 172a: first circuit portion 172b: second circuit portion 300: electronic component 200: second circuit structure 265: sixth upper insulating layer 241: fourth upper circuit layer 245: fourth upper insulating layer 221: Second upper circuit layer 205: Second core layer 222: Second lower circuit layer 246: Fourth lower insulation layer 242: Fourth lower circuit layer 266: Sixth lower insulation layer 401, 402: Conductive connector 408: Filling material

Figures 1A to 1P are partial schematic diagrams of a partial manufacturing method of an electronic packaging structure according to the first embodiment of the present invention. Figure 2 is a partial schematic diagram of an electronic packaging structure according to the second embodiment of the present invention.

901: Electronic packaging structure

100: First circuit structure

155: Fifth upper insulating layer

151: Fifth upper line layer

135: The third upper insulating layer

131: The third upper line layer

115: First upper insulating layer

111: First upper line layer

105: First core layer

112: First lower circuit layer

116: The first lower insulating layer

132: The third lower circuit layer

136: The third lower insulating layer

152: The fifth lower circuit layer

156: The fifth lower insulation layer

190: Coaxial conductive via

196: Second dielectric layer

192: Conductive layer

195: First dielectric layer

191: Conductive layer

170: Cavity

172: Bottom line layer

172a: First line section

172b: Second line section

300: Electronic components

200: Second circuit structure

265: Sixth upper insulating layer

241: Fourth upper line layer

245: The fourth upper insulating layer

221: Second upper line layer

205: Second core layer

222: Second lower circuit layer

246: The fourth lower insulation layer

242: Fourth lower circuit layer

266: The sixth lower insulation layer

401, 402: Conductive connectors

408: Filling material

Claims (12)

An electronic packaging structure includes: a first circuit structure having at least one cavity on its bottom side; a second circuit structure, wherein the first circuit structure is located on the second circuit structure and is electrically connected to each other; and at least one electronic component is disposed on the second circuit structure and corresponds to the at least one cavity of the first circuit structure. An electronic package structure as described in claim 1, wherein the inner surface of the at least one cavity of the first circuit structure is covered with a conductive material. An electronic package structure as described in claim 1, wherein the first circuit structure includes at least one coaxial conductive via, and the at least one coaxial conductive via includes: an inner conductive layer; an outer conductive layer; and a dielectric layer located between the inner conductive layer and the outer conductive layer. An electronic package structure as described in claim 3, wherein the material of the outer conductive layer of the at least one coaxial conductive via includes copper. An electronic package structure as described in claim 3, wherein the material of the dielectric layer of the at least one coaxial conductive via comprises resin. The electronic package structure as described in claim 3, wherein the first circuit structure further comprises: an upper conductive layer; and a lower conductive layer, wherein the two ends of the outer conductive layer of the at least one coaxial conductive via are respectively connected to a portion of the upper conductive layer and a portion of the lower conductive layer. An electronic package structure as described in claim 3, wherein the inner conductive layer of the at least one coaxial conductive via is electrically connected to the outermost circuits on both sides of the first circuit structure. An electronic package structure as described in claim 1, wherein at least one of the first circuit structure or the second circuit structure includes a solder resist layer located at the outermost part. The electronic package structure as described in claim 1 further includes: Filling material located between the first circuit structure and the second circuit structure. The electronic package structure as described in claim 1 further includes: A conductive connector located between the first circuit structure and the second circuit structure to electrically connect the first circuit structure and the second circuit structure to each other. The electronic package structure as described in claim 1 further includes: A conductive connector located between the at least one electronic component and the second circuit structure to electrically connect the at least one electronic component and the second circuit structure to each other. A method for manufacturing an electronic package structure, comprising: providing a first circuit structure having at least one cavity on its bottom side; providing a second circuit structure; configuring at least one electronic component on the second circuit structure; and electrically connecting the second circuit structure having the at least one electronic component configured thereon and the first circuit structure to each other, and positioning the first circuit structure on the second circuit structure so that the at least one electronic component configured on the second circuit structure corresponds to the at least one cavity of the first circuit structure.