TW202310695A - Circuit board and manufacturing method thereof and electronic device - Google Patents
Circuit board and manufacturing method thereof and electronic device Download PDFInfo
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本發明是有關於一種基板結構及其製作方法,且特別是有關於一種電路板及其製作方法與採用此電路板的電子裝置。The present invention relates to a substrate structure and its manufacturing method, and in particular to a circuit board, its manufacturing method and an electronic device using the circuit board.
在現有電路板中,同軸穿孔(coaxial via)的設計在內部導體層與外部導體層之間需要有一層或一層以上的絕緣層來作阻絕,其中形成絕緣層的方式是透過壓合增層的方式來達成。因此在同軸穿孔的兩端會有阻抗不匹配且會出現電磁干擾(electromagnetic interference, EMI)屏蔽缺口,進而影響高頻訊號完整性。此外,在同軸穿孔的設計中,訊號路徑的兩端分別接地路徑的兩端位於不同平面上,且無法減少雜訊干擾。In the existing circuit board, the design of the coaxial via (coaxial via) requires one or more insulating layers between the inner conductor layer and the outer conductor layer for insulation, and the way to form the insulating layer is through lamination. way to achieve. Therefore, there will be impedance mismatch at both ends of the coaxial via and electromagnetic interference (EMI) shielding gaps will appear, thereby affecting the integrity of high-frequency signals. In addition, in the coaxial through-hole design, the two ends of the signal path and the two ends of the ground path are located on different planes, and noise interference cannot be reduced.
本發明提供一種電路板,其具有良好的訊號迴路,可具有較佳的訊號完整性。The invention provides a circuit board with good signal loop and better signal integrity.
本發明還提供一種電路板的製作方法,用以製作上述的電路板。The present invention also provides a method for manufacturing a circuit board, which is used to manufacture the above circuit board.
本發明更提供一種電子裝置,其包括上述的電路板,具有較佳的電磁干擾(EMI)屏蔽及阻抗匹配效果,可提升訊號傳輸可靠度。The present invention further provides an electronic device, which includes the above-mentioned circuit board, which has better electromagnetic interference (EMI) shielding and impedance matching effects, and can improve the reliability of signal transmission.
本發明的電路板,包括一第一基材、一第二基材、一第三基材、多個導電結構以及一導通孔結構。第二基材配置於第一基材與第三基材之間。第三基材具有一開口且包括一第一介電層、一第二介電層及一第三介電層。開口貫穿第一介電層及第二介電層,而第三介電層填滿開口。導通孔結構貫穿第一基材、第二基材、第三基材的第三介電層,且電性連接第一基材與第三基材,而定義出一訊號路徑。第一基材、第二基材以及第三基材透過導電結構電性連接而定義出一接地路徑,其中接地路徑環繞訊號路徑。The circuit board of the present invention includes a first base material, a second base material, a third base material, a plurality of conductive structures and a via hole structure. The second base material is disposed between the first base material and the third base material. The third substrate has an opening and includes a first dielectric layer, a second dielectric layer and a third dielectric layer. The opening penetrates the first dielectric layer and the second dielectric layer, and the third dielectric layer fills the opening. The via hole structure penetrates through the first substrate, the second substrate, and the third dielectric layer of the third substrate, and electrically connects the first substrate and the third substrate to define a signal path. The first substrate, the second substrate and the third substrate are electrically connected through the conductive structure to define a ground path, wherein the ground path surrounds the signal path.
在本發明的一實施例中,上述的導電結構包括多個第一導通孔、多個導電柱以及一導電連接層。第一基材包括一核心層、一第一外部線路層、一第一線路層以及第一導通孔。第一外部線路層與第一線路層分別配置於核心層的相對兩側。第一導通孔貫穿核心層且電性連接第一外部線路層與第一線路層。第二基材包括一基底以及貫穿基底的導電柱。第三基材更包括一第二線路層、一第三線路層、一第二外部線路層、多個第二導通孔以及導電連接層。第二線路層與第三線路層位於第一介電層的相對兩側,而第二介電層覆蓋第三線路層且位於第三線路層與第二外部線路層之間。第二導通孔貫穿第二介電層且電性連接第二外部線路層與第三線路層。導電連接層覆蓋開口的內壁且連接第二線路層、第三線路層及第二外部線路層。導通孔結構包括一貫孔以及一導電材料。貫孔貫穿第一基材的核心層、第二基材的基底、第三基材的第三介電層。導電材料覆蓋貫孔的內壁且電性連接第一外部線路層與第二外部線路層。In an embodiment of the present invention, the above-mentioned conductive structure includes a plurality of first via holes, a plurality of conductive pillars, and a conductive connection layer. The first substrate includes a core layer, a first outer circuit layer, a first circuit layer and first via holes. The first external circuit layer and the first circuit layer are respectively arranged on opposite sides of the core layer. The first via hole penetrates through the core layer and electrically connects the first outer circuit layer and the first circuit layer. The second substrate includes a base and conductive pillars penetrating through the base. The third substrate further includes a second circuit layer, a third circuit layer, a second outer circuit layer, a plurality of second via holes and a conductive connection layer. The second circuit layer and the third circuit layer are located on opposite sides of the first dielectric layer, and the second dielectric layer covers the third circuit layer and is located between the third circuit layer and the second outer circuit layer. The second via hole penetrates through the second dielectric layer and electrically connects the second outer circuit layer and the third circuit layer. The conductive connection layer covers the inner wall of the opening and connects the second circuit layer, the third circuit layer and the second outer circuit layer. The via hole structure includes a through hole and a conductive material. The through hole runs through the core layer of the first substrate, the base of the second substrate, and the third dielectric layer of the third substrate. The conductive material covers the inner wall of the through hole and electrically connects the first outer circuit layer and the second outer circuit layer.
在本發明的一實施例中,上述的第一外部線路層包括一第一訊號線路與一第一接地線路。第二外部線路層包括一第二訊號線路與一第二接地線路。第一訊號線路、導電材料以及第二訊號線路定義出訊號路徑。第一接地線路、第一導通孔、第一線路層、導電柱、第二線路層、導電連接層以及第二接地線路定義出接地路徑。In an embodiment of the present invention, the above-mentioned first external circuit layer includes a first signal circuit and a first ground circuit. The second outer circuit layer includes a second signal circuit and a second ground circuit. The first signal line, the conductive material and the second signal line define a signal path. The first ground circuit, the first via hole, the first circuit layer, the conductive column, the second circuit layer, the conductive connection layer and the second ground circuit define a ground path.
在本發明的一實施例中,上述的電路板還包括一第四介電層,填滿貫孔。第四介電層彼此相對的一第一表面與一第二表面分別切齊於第一外部線路層的一上表面與第二外部線路層的一下表面。In an embodiment of the present invention, the above circuit board further includes a fourth dielectric layer filling the through hole. A first surface and a second surface of the fourth dielectric layer opposite to each other are respectively aligned with an upper surface of the first outer circuit layer and a lower surface of the second outer circuit layer.
在本發明的一實施例中,上述的電路板還包括一罩蓋層,配置於第一外部線路層的上表面、第二外部線路層的下表面以及第四介電層的第一表面與第二表面上。In an embodiment of the present invention, the above-mentioned circuit board further includes a cover layer disposed on the upper surface of the first external circuit layer, the lower surface of the second external circuit layer, and the first surface and the fourth dielectric layer. on the second surface.
本發明的電路板的製作方法,其包括以下步驟。提供一第一基材、一第二基材以及一第三基材。第三基材具有一開口且包括一第一介電層、一第二介電層及一第三介電層。開口貫穿第一介電層及第二介電層,而第三介電層填滿開口。壓合第一基材、第二基材以及第三基材,以使第二基材位於第一基材與第三基材之間。形成多個導電結構,以使而第一基材、第二基材以及第三基材透過導電結構電性連接而定義出一接地路徑。形成一導通孔結構,以貫穿第一基材、第二基材以及第三基材的第三介電層。導通孔結構電性連接第一基材與第三基材而定義出一訊號路徑,且接地路徑環繞訊號路徑。The manufacturing method of the circuit board of the present invention comprises the following steps. A first base material, a second base material and a third base material are provided. The third substrate has an opening and includes a first dielectric layer, a second dielectric layer and a third dielectric layer. The opening penetrates the first dielectric layer and the second dielectric layer, and the third dielectric layer fills the opening. Pressing the first base material, the second base material and the third base material, so that the second base material is located between the first base material and the third base material. A plurality of conductive structures are formed so that the first base material, the second base material and the third base material are electrically connected through the conductive structures to define a grounding path. A via hole structure is formed to penetrate through the third dielectric layer of the first substrate, the second substrate and the third substrate. The via hole structure electrically connects the first substrate and the third substrate to define a signal path, and the ground path surrounds the signal path.
在本發明的一實施例中,上述提供第一基材、第二基材以及第三基材的步驟,包括提供第一基材。第一基材包括一核心層、一第一導電層、一第一線路層。第一導電層與第一線路層分別配置於核心層的相對兩側。提供第二基材。第二基材包括一基底以及貫穿基底的多個導電柱。提供第三基材。第三基材更包括一第二線路層、一第三線路層、一第二導電層以及一導電連接層。第二線路層與第三線路層位於第一介電層的相對兩側。第二介電層覆蓋第三線路層且位於第三線路層與第二導電層之間。導電連接層覆蓋開口的內壁且連接第二線路層、第三線路層及第二導電層。In an embodiment of the present invention, the step of providing the first substrate, the second substrate and the third substrate includes providing the first substrate. The first base material includes a core layer, a first conductive layer, and a first circuit layer. The first conductive layer and the first circuit layer are respectively arranged on opposite sides of the core layer. A second substrate is provided. The second substrate includes a base and a plurality of conductive pillars penetrating the base. A third substrate is provided. The third substrate further includes a second circuit layer, a third circuit layer, a second conductive layer and a conductive connection layer. The second circuit layer and the third circuit layer are located on opposite sides of the first dielectric layer. The second dielectric layer covers the third circuit layer and is located between the third circuit layer and the second conductive layer. The conductive connection layer covers the inner wall of the opening and connects the second circuit layer, the third circuit layer and the second conductive layer.
在本發明的一實施例中,上述於導電結構包括多個第一導通孔、導電柱以及導電連接層。In an embodiment of the present invention, the above-mentioned conductive structure includes a plurality of first via holes, a conductive column, and a conductive connection layer.
在本發明的一實施例中,上述形成導電結構的第一導通孔與導通孔結構的步驟,包括:形成多個第一盲孔、多個第二盲孔以及一貫孔。第一盲孔從第一導電層延伸至第一線路層,而第二盲孔從第二導電層延伸至第三線路層。貫孔貫穿第一基材的核心層、第二基材的基底以及第三基材的第三介電層。形成一導電材料層,以填滿第一盲孔與第二盲孔,且延伸覆蓋第一導電層、第二導電層以及貫孔的內壁。填滿第一盲孔的導電材料層定義出第一導通孔。填滿第二盲孔的導電材料層定義出多個第二導通孔。圖案化導電材料層、第一導電層以及第二導電層,而形成一第一外部線路層、一第二外部線路層以及覆蓋貫孔的內壁且電性連接第一外部線路層與第二外部線路層的一導電材料。第一外部線路層位於第一基材的核心層上。第二外部線路層位於第三基材的第二介電層上。貫孔及導電材料定義出導通孔結構。In an embodiment of the present invention, the step of forming the first via hole and the via hole structure of the conductive structure includes: forming a plurality of first blind holes, a plurality of second blind holes and a through hole. The first blind hole extends from the first conductive layer to the first circuit layer, and the second blind hole extends from the second conductive layer to the third circuit layer. The through hole runs through the core layer of the first substrate, the base of the second substrate and the third dielectric layer of the third substrate. A conductive material layer is formed to fill the first blind hole and the second blind hole and extend to cover the first conductive layer, the second conductive layer and the inner wall of the through hole. The conductive material layer filling the first blind hole defines a first via hole. The conductive material layer filling the second blind holes defines a plurality of second via holes. patterning the conductive material layer, the first conductive layer and the second conductive layer to form a first external circuit layer, a second external circuit layer and the inner wall covering the through hole and electrically connecting the first external circuit layer and the second external circuit layer A conductive material for the outer circuit layer. The first outer circuit layer is located on the core layer of the first base material. The second outer circuit layer is located on the second dielectric layer of the third substrate. The via hole and the conductive material define the via structure.
在本發明的一實施例中,上述的第一外部線路層包括一第一訊號線路與一第一接地線路。第二外部線路層包括一第二訊號線路與一第二接地線路。第一訊號線路、導電材料以及第二訊號線路定義出訊號路徑。第一接地線路、第一導通孔、第一線路層、導電柱、第二線路層、導電連接層以及第二接地線路定義出接地路徑。In an embodiment of the present invention, the above-mentioned first external circuit layer includes a first signal circuit and a first ground circuit. The second outer circuit layer includes a second signal circuit and a second ground circuit. The first signal line, the conductive material and the second signal line define a signal path. The first ground circuit, the first via hole, the first circuit layer, the conductive column, the second circuit layer, the conductive connection layer and the second ground circuit define a ground path.
在本發明的一實施例中,上述的電路板的製作方法,更包括形成導電材料層之後,且圖案化導電材料層、第一導電層以及第二導電層之前,填充一第四介電層於貫孔內。第四介電層填滿貫孔,且第四介電層彼此相對的一第一表面與一第二表面分別切齊於導電材料層的一上表面與一下表面。In one embodiment of the present invention, the above-mentioned circuit board manufacturing method further includes filling a fourth dielectric layer after forming the conductive material layer and before patterning the conductive material layer, the first conductive layer and the second conductive layer in the through hole. The fourth dielectric layer fills the through hole, and a first surface and a second surface of the fourth dielectric layer opposite to each other are respectively aligned with an upper surface and a lower surface of the conductive material layer.
在本發明的一實施例中,上述的電路板的製作方法,更包括填充第四介電層於貫孔內之後,且圖案化導電材料層、第一導電層以及第二導電層之前,形成一金屬層於導電材料層上。金屬層覆蓋導電材料層的上表面與下表面以及第四介電層的第一表面與第二表面。圖案化導電材料層、第一導電層以及第二導電層時,同時圖案化金屬層,而同時形成一罩蓋層。罩蓋層覆蓋第一外部線路層、第二外部線路層以及第四介電層的第一表面與第二表面。In an embodiment of the present invention, the above-mentioned circuit board manufacturing method further includes forming A metal layer is on the conductive material layer. The metal layer covers the upper surface and the lower surface of the conductive material layer and the first surface and the second surface of the fourth dielectric layer. When patterning the conductive material layer, the first conductive layer and the second conductive layer, the metal layer is patterned at the same time, and a cover layer is formed at the same time. The cover layer covers the first surface and the second surface of the first external circuit layer, the second external circuit layer and the fourth dielectric layer.
本發明的電子裝置,其包括一電路板以及一電子元件。電路板包括一第一基材、一第二基材、一第三基材、多個導電結構以及一導通孔結構。第二基材配置於第一基材與第三基材之間。第三基材具有一開口且包括一第一介電層、一第二介電層及一第三介電層。開口貫穿第一介電層及第二介電層,而第三介電層填滿開口。導通孔結構貫穿第一基材、第二基材、第三基材的第三介電層,且電性連接第一基材與第三基材,而定義出一訊號路徑。第一基材、第二基材以及第三基材透過導電結構電性連接而定義出一接地路徑,其中接地路徑環繞訊號路徑。電子元件電性連接電路板。The electronic device of the present invention includes a circuit board and an electronic component. The circuit board includes a first base material, a second base material, a third base material, a plurality of conductive structures and a via hole structure. The second base material is disposed between the first base material and the third base material. The third substrate has an opening and includes a first dielectric layer, a second dielectric layer and a third dielectric layer. The opening penetrates the first dielectric layer and the second dielectric layer, and the third dielectric layer fills the opening. The via hole structure penetrates through the first substrate, the second substrate, and the third dielectric layer of the third substrate, and electrically connects the first substrate and the third substrate to define a signal path. The first substrate, the second substrate and the third substrate are electrically connected through the conductive structure to define a ground path, wherein the ground path surrounds the signal path. The electronic components are electrically connected to the circuit board.
在本發明的一實施例中,上述的電子裝置還包括多個連接件,配置於電路板的第三基材與電子元件之間。電子元件透過連接件與電路板電性連接。In an embodiment of the present invention, the above-mentioned electronic device further includes a plurality of connectors disposed between the third base material of the circuit board and the electronic components. The electronic components are electrically connected with the circuit board through the connector.
基於上述,在本發明的電路板的設計中,導通孔結構貫穿第一基材、第二基材及第三基材的第三介電層,且電性連接第一基材與第三基材而定義出訊號路徑,而第一基材、第二基材以及第三基材透過導電結構電性連接而定義出接地路徑,其中接地路徑環繞訊號路徑。藉此,可形成良好的高頻高速訊號迴路,且後續在積體電路與天線的應用上,亦可解決同一平面訊號干擾的問題,可降低訊號能量損失及減少雜訊干擾,進而可提升訊號傳輸可靠度。Based on the above, in the design of the circuit board of the present invention, the via hole structure penetrates through the third dielectric layer of the first substrate, the second substrate and the third substrate, and electrically connects the first substrate and the third substrate. The signal path is defined by the material, and the first base material, the second base material and the third base material are electrically connected through the conductive structure to define a ground path, wherein the ground path surrounds the signal path. In this way, a good high-frequency and high-speed signal loop can be formed, and the subsequent application of integrated circuits and antennas can also solve the problem of signal interference on the same plane, which can reduce signal energy loss and noise interference, thereby improving the signal transmission reliability.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.
圖1A至圖1E是依照本發明的一實施例的一種電路板的製作方法的剖面示意圖。圖1F是圖1E的電路板的俯視示意圖。關於本實施例的電路板的製作方法,首先,請同時參考圖1A,提供一第一基材110、一第二基材120以及一第三基材130。1A to 1E are schematic cross-sectional views of a manufacturing method of a circuit board according to an embodiment of the present invention. FIG. 1F is a schematic top view of the circuit board of FIG. 1E . Regarding the manufacturing method of the circuit board of this embodiment, firstly, referring to FIG. 1A , a
詳細來說,在本實施例中,第一基材110包括一核心層112、一第一導電層114以及一第一線路層116。第一導電層114與第一線路層116分別配置於核心層112的相對兩側,其中第一導電層114未圖案化,且完全覆蓋核心層112的一側表面,而第一線路層116暴露出核心層112的部分另一側表面。此處,核心層112的材質例如是介電材料,其中核心層112的介電常數(Dielectric Constant,Dk)例如是介於2到3.5之間,而核心層112的介電損耗(Dissipation Factor, Df)例如是小於0.006,而第一導電層114與第一線路層116的材質例如是銅,但不以此為限。In detail, in this embodiment, the
第二基材120包括一基底122以及貫穿基底122的多個導電柱124。提供第二基材120的步驟包括先提供基底122,其中基底122於此時處於一B階段狀態,意即尚未完全固化。接著,可於基底122的相對兩側貼附離型膜,其中離型膜的材質如是聚酯聚合物(PET)。之後,對基底122進行鑽孔程序,而形成通孔,其中鑽孔程序例如是雷射鑽孔或機械鑽孔,但不以此為限。最後,以印刷(printing)或注入(injection)的方式,於通孔內填充導電膠材,而形成導電柱124。之後,移除貼附在基底122相對兩側的離型膜,而使導電柱124的相對兩表面分別突出於基底122的相對兩表面,而完成第二基材120的製作。The
第三基材130包括具有一開口137且包括一第一介電層131、一第二介電層133、一第三介電層135、一第二線路層132、一第三線路層134、一第二導電層136以及一導電連接層138。第三基材130的第二線路層132與第三線路層134位於第一介電層131的相對兩側。第二介電層133覆蓋第三線路層134且位於第三線路層134與第二導電層136之間。開口137貫穿第一介電層131及第二介電層133,而第三介電層135填滿開口137。導電連接層138覆蓋開口137的內壁且連接第二線路層132、第三線路層134及第二導電層136。此處,第一介電層131的介電常數(Dk)例如是介於2.4至4.0之間,而第一介電層131的介電損耗(Df)例如是小於0.02。第二介電層133的介電常數(Dk)例如是介於2.0至3.5之間,而第二介電層133的介電損耗(Df)例如是小於0.008。第三介電層135的介電常數(Dk)例如是介於2.1至5.0之間,而第三介電層135的介電損耗(Df)例如是小於0.025。The
進一步來說,提供第三基材130的步驟包括先提供第一介電層131以及配置於第一介電層131相對兩側的兩導電層,其中兩導電層完全覆蓋第一介電層131的相對兩側。接著,對兩導電層進行圖案化程序,而形成第二線路層132以及第三線路層134。接著,提供第二介電層133及配置於第二介電層133上的第二導電層136,並將第二介電層133壓合於第三線路層134上,而使第二介電層133位於第三線路層134與第二導電層136之間。此時,第二導電層136未圖案化,且完全覆蓋第二介電層133相對遠離第一介電層131的一側。接著,形成開口137以貫穿第二線路層132、第一介電層131、第三線路層134、第二介電層133以及第二導電層136。之後,形成導電連接層138於開口137的內壁,其中導電連接層138電性連接第二線路層132、第三線路層134以及第二導電層136。最後,進行塞孔(plugging)程序,填充第三介電層135於開口137內,其中第三介電層135填滿開口137,而完成第三基材130的製作。Further, the step of providing the
接著,請參考圖1B,壓合第一基材110、第二基材120以及第三基材130,以使第二基材120位於第一基材110與第三基材130之間。此處,由於採用是熱壓合的製程,因此此時的第二基材120的基底122會由原來的B階段狀態轉變成一C階段狀態,意即呈現完全固化狀態,而使第一基材110與第三基材130連接固定在第二基材120上。第二基材120的導電柱124因抵接第一線路層116與第二線路層132而產生變形,且導電柱124電性連接第一基材110的第一線路層116與第三基材130的第二線路層132。Next, referring to FIG. 1B , the
接著,請參考圖1C,形成多個第一盲孔H1、多個第二盲孔H2以及一貫孔T。第一盲孔H1從第一導電層114延伸至第一線路層116,而第二盲孔H2從第二導電層136延伸至第三線路層134。貫孔T貫穿第一基材110的第一導電層114與核心層112、第二基材120的基底122以及第三基材130的第三介電層135。此處,形成第一盲孔H1與第二盲孔H2的方式例如是雷射鑽孔,而形成貫孔T的方式例如是機械鑽孔,但不以此為限。Next, referring to FIG. 1C , a plurality of first blind holes H1 , a plurality of second blind holes H2 and a through hole T are formed. The first blind hole H1 extends from the first
之後,請參考圖1D,形成一導電材料層140,以填滿第一盲孔H1與第二盲孔H2,且延伸覆蓋第一導電層114、第二導電層136以及貫孔T的內壁。此時,填滿第一盲孔H1的導電材料層140定義出導電結構的多個第一導通孔118。填滿第二盲孔H2的導電材料層140定義出導電結構的多個第二導通孔139。此處,形成導電材料層140的方法例如是化學鍍法(Electroless plating)或電鍍法(electrolytic plating process),而導電材料層140例如是銅,但不以此為限。Afterwards, referring to FIG. 1D , a
最後,請同時參考圖1D以及圖1E,透過微影製程,以圖案化導電材料層140、第一導電層114以及第二導電層136,而形成一第一外部線路層C1、一第二外部線路層C2以及覆蓋貫孔T的內壁且電性連接第一外部線路層C1與第二外部線路層C2的一導電材料145。第一外部線路層C1位於第一基材110的核心層112上。第二外部線路層C2位於第三基材130的第二介電層133上。貫孔T及導電材料145定義出導通孔結構150。Finally, please refer to FIG. 1D and FIG. 1E at the same time. Through the lithography process, the
於此,已形成導電結構(即第一導通孔118、導電柱124、導電連接層138),以使而第一基材110、第二基材120以及第三基材130透過導電結構電性連接而定義出一接地路徑L2。已形成導通孔結構150,以貫穿第一基材110、第二基材120以及第三基材130的第三介電層135,其中導通孔結構150電性連接第一基材110與第三基材130而定義出訊號路徑L1,且接地路徑L2環繞訊號路徑L1。更進一步來說,第一外部線路層C1包括一第一訊號線路C11與一第一接地線路C12。第二外部線路層C2包括一第二訊號線路C21與一第二接地線路C22。第一訊號線路C11、導電材料145以及第二訊號線路C21定義出訊號路徑L1。第一接地線路C12、第一導通孔118、第一線路層116、導電柱124、第二線路層132、導電連接層138以及第二接地線路C22定義出接地路徑L2。至此,已完成電路板100a的製作。Here, the conductive structure (namely, the first via
在結構上,請同時參考圖1E以及圖1F,電路板100a包括第一基材110a、第二基材120、第三基材130a、導電結構以及導通孔結構150。第二基材120配置於第一基材110a與第三基材130a之間。第三基材130a具有開口137且包括第一介電層131、第二介電層133及第三介電層135。開口137貫穿第一介電層131及第二介電層133,而第三介電層135填滿開口137。導通孔結構150貫穿第一基材110a、第二基材120、第三基材130a的第三介電層135,且電性連接第一基材110a與第三基材130a,而定義出訊號路徑L1。第一基材110a、第二基材120以及第三基材130a透過導電結構電性連接而定義出接地路徑L2,其中接地路徑L2環繞訊號路徑L1。In terms of structure, please refer to FIG. 1E and FIG. 1F at the same time. The
詳細來說,在本實施例中,導電結構包括第一導通孔118、導電柱124以及導電連接層138。第一基材110a包括核心層112、第一外部線路層C1、第一線路層116以及第一導通孔118。第一外部線路層C1與第一線路層116分別配置於核心層112的相對兩側。第一導通孔118貫穿核心層112且電性連接第一外部線路層C1與第一線路層116。第二基材120包括基底122以及貫穿基底122的導電柱124。第三基材130a更包括第二線路層132、第三線路層134、第二外部線路層C2、第二導通孔139以及導電連接層138。第二線路層132與第三線路層134位於第一介電層131的相對兩側,而第二介電層133覆蓋第三線路層134且位於第三線路層134與第二外部線路層C2之間。第二導通孔139貫穿第二介電層133且電性連接第二外部線路層C2與第三線路層134。導電連接層138覆蓋開口137的內壁且連接第二線路層132、第三線路層134及第二外部線路層C2。導通孔結構150包括貫孔T以及導電材料145。貫孔T貫穿第一基材110a的核心層112、第二基材120的基底122、第三基材130a的第三介電層135。導電材料145覆蓋貫孔T的內壁且電性連接第一外部線路層C1與第二外部線路層C2。In detail, in this embodiment, the conductive structure includes a first via
此處,第一外部線路層C1包括第一訊號線路C11與第一接地線路C12。第二外部線路層C2包括第二訊號線路C21與第二接地線路C22。第一訊號線路C11、導電材料145以及第二訊號線路C21定義出訊號路徑L1。第一接地線路C21、第一導通孔118、第一線路層116、導電柱124、第二線路層132、導電連接層138以及第二接地線路C22定義出接地路徑L2。由於訊號路徑L1被接地路徑L2所環繞且呈封閉性包圍,因此可形成良好的高頻高速迴路。再者,第一導通孔118、導電柱124以及導電連接層138的設置可將屏蔽缺口補起來而形成完整的屏蔽,意即為閉環式屏蔽曲面(closed shielding surface),無電磁屏蔽(EMI)缺口區段,藉此可有效的降低訊號能量損失及減少雜訊干擾,進而可提升訊號傳輸可靠度及高頻訊號完整性。此外,由於第一外部線路層C1的第一訊號線路C11與第一接地線路C12是位於同一平面上,因此可具有較佳的共平面性(co-planar),平坦度較佳,因此後續進行封裝作業時,不會損壞或傷害到元件(如晶片),可具有較高的產品良率與結構可靠度。Here, the first external circuit layer C1 includes a first signal circuit C11 and a first ground circuit C12. The second external circuit layer C2 includes a second signal circuit C21 and a second ground circuit C22. The first signal line C11 , the
簡言之,本實例由第一訊號線路C11、導電材料145以及第二訊號線路C21所定義出的訊號路徑L1被由第一接地線路C12、第一導通孔118、第一線路層116、導電柱124、第二線路層132、導電連接層138以及第二接地線路C22所定義出的接地路徑L2環繞包圍住。意即,可傳輸5G等高頻高速訊號的訊號路徑L1的周圍設置封閉性佳的接地路徑L2,藉此可形成良好的高頻高速迴路,而使得本實施例的電路板100a可具有較佳的訊號完整性。此處,所述的高頻是指頻率大於1GHz;而所述的高速是指資料傳輸的速度大於100Mbps。一般皆知,高頻電路講求的是傳輸訊號的速度與品質,而影響這兩項的主要因素是傳輸材料的電氣特性,即材料介電常數( Dk )與介電損耗( Df )。藉由降低基材的介電常數和介電損耗,可有效地縮短訊號延遲( Signal Propagation Delay Time ),並可提高訊號傳輸速率與減少訊號傳輸損失( Signal Transmission Loss )。In short, in this example, the signal path L1 defined by the first signal line C11, the
再者,本實施例所提供的第二基材120為線路板完成品,而第一基材110與第三基材130則屬於線路板的半成品,且以壓合的方式將第一基材110、第二基材120以及第三基材130整合在一起。因此相較於現有技術中以壓合絕緣層的增層法方式來阻絕同軸穿孔的內部導體層與外部導體層而言,本實施例的電路板100a的製作方法除了可避免產生阻抗不匹配而影響高頻訊號的完整性的問題之外,亦可具有製程簡單且節省成本的優勢。此外,本實施例的第一導通孔118、導電柱124、第二導通孔139沒有位於同一軸線上,因此可改善疊孔的熱應力可靠度不佳的問題。Furthermore, the
在此必須說明的是,下述實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參照前述實施例,下述實施例不再重複贅述。It must be noted here that the following embodiments use the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
圖2A至圖2B是依照本發明的另一實施例的另一種電路板的製作方法的局部步驟的剖面示意圖。請先參考圖1D以及圖2A,本實施例的電路板100b的製作方法與上述的電路板100a的製作方法相似,兩者差異在於:在圖1D形成導電材料層140的步驟之後,填充一第四介電層160於貫孔T內。第四介電層160填滿貫孔T,且第四介電層160彼此相對的一第一表面161與一第二表面163分別切齊於導電材料層140的一上表面141與一下表面143。此處,第四介電層160的介電常數(Dk)例如是介於2.0至4.8之間,而第四介電層160的介電損耗(Df)例如是小於0.021。2A to 2B are schematic cross-sectional views of partial steps of another circuit board manufacturing method according to another embodiment of the present invention. Please refer to FIG. 1D and FIG. 2A first, the manufacturing method of the
之後,請同時參考圖2A與圖2B,透過微影製程,以圖案化導電材料層140、第一導電層114以及第二導電層136,而形成第一外部線路層C1、第二外部線路層C2以及覆蓋貫孔T的內壁且電性連接第一外部線路層C1與第二外部線路層C2的導電材料145。第一外部線路層C1位於第一基材110的核心層112上。第二外部線路層C2位於第三基材130的第二介電層133上。貫孔T及導電材料145定義出導通孔結構150。至此,已完成電路板100b的製作。After that, please refer to FIG. 2A and FIG. 2B at the same time, through the photolithography process, to pattern the
圖3A至圖3B是依照本發明的另一實施例的另一種電路板的製作方法的局部步驟的剖面示意圖。請先參考圖2A以及圖3A,本實施例的電路板100c的製作方法與上述的電路板100b的製作方法相似,兩者差異在於:在圖2A填充第四介電層160於貫孔T內的步驟之後,請參考圖3A,形成一金屬層170於導電材料層140上。金屬層170覆蓋導電材料層140的上表面141與下表面143以及第四介電層160的第一表面161與第二表面163。此處,形成金屬層170的方法例如是化學鍍法(Electroless plating)或電鍍法(electrolytic plating process),而金屬層170例如是銅,但不以此為限。3A to 3B are schematic cross-sectional views of partial steps of another circuit board manufacturing method according to another embodiment of the present invention. Please refer to FIG. 2A and FIG. 3A first. The manufacturing method of the
之後,請同時參考圖3A與圖3B,透過微影製程,以圖案化金屬層170、導電材料層140、第一導電層114以及第二導電層136,而形成第一外部線路層C1、第二外部線路層C2、覆蓋貫孔T的內壁且電性連接第一外部線路層C1與第二外部線路層C2的導電材料145以及一罩蓋層175。第一外部線路層C1位於第一基材110的核心層112上。第二外部線路層C2位於第三基材130的第二介電層133上。貫孔T及導電材料145定義出導通孔結構150。罩蓋層175覆蓋第一外部線路層C1、第二外部線路層C2以及第四介電層160的第一表面161與第二表面163。至此,已完成電路板100c的製作。After that, please refer to FIG. 3A and FIG. 3B at the same time, through the lithography process, the
圖4是依照本發明的一實施例的一種電子裝置的剖面示意圖。請參考圖4,在本實施例中,電子裝置10a包括上述例如是圖1E的電路板100a以及一電子元件200,其中電子元件200電性連接電路板100a,且電子元件200包括多個接墊210。此外,本實施例的電子裝置10a還包括多個連接件300,配置於電路板100a的第三基材130a的第二外部線路層C2與電子元件200之間,其中電子元件200透過連接件300與電路板100a電性連接。此處,連接件300例如是銲球,但不以此為限。在應用上,可在電路板100a相對於電子元件200的另一側上設置天線結構,並使天線結構與電路板100a電性連接。在積體電路與天線的應用上,本實施例的電路板100a可解決同一平面訊號干擾的問題,可降低訊號能量損失及減少雜訊干擾,進而可提升訊號傳輸可靠度。FIG. 4 is a schematic cross-sectional view of an electronic device according to an embodiment of the present invention. Please refer to FIG. 4. In this embodiment, the
圖5是依照本發明的另一實施例的一種電子裝置的剖面示意圖。請參考圖5,在本實施例中,電子裝置10b包括上述例如是圖2B的電路板100b以及一電子元件200,其中電子元件200電性連接電路板100b,且電子元件200包括多個接墊210。此外,本實施例的電子裝置10b還包括多個連接件300,配置於電路板100b的第三基材130a的第二外部線路層C2與電子元件200之間,其中電子元件200透過連接件300與電路板100b電性連接。此處,連接件300例如是銲球,但不以此為限。在應用上,可在電路板100b相對於電子元件200的另一側上設置天線結構,並使天線結構與電路板100b電性連接。在積體電路與天線的應用上,本實施例的電路板100b可解決同一平面訊號干擾的問題,可降低訊號能量損失及減少雜訊干擾,進而可提升訊號傳輸可靠度。FIG. 5 is a schematic cross-sectional view of an electronic device according to another embodiment of the present invention. Please refer to FIG. 5. In this embodiment, the
圖6是依照本發明的另一實施例的一種電子裝置的剖面示意圖。請參考圖6,在本實施例中,電子裝置10c包括上述例如是圖3B的電路板100c以及一電子元件200,其中電子元件200電性連接電路板100c,且電子元件200包括多個接墊210。此外,本實施例的電子裝置10c還包括多個連接件300,配置於電路板100c的罩蓋層165與電子元件200之間,其中電子元件200透過連接件300與電路板100c電性連接。此處,連接件300例如是銲球,但不以此為限。在應用上,可在電路板100c相對於電子元件200的另一側上設置天線結構,並使天線結構與電路板100c電性連接。在積體電路與天線的應用上,本實施例的電路板100c可解決同一平面訊號干擾的問題,可降低訊號能量損失及減少雜訊干擾,進而可提升訊號傳輸可靠度。FIG. 6 is a schematic cross-sectional view of an electronic device according to another embodiment of the present invention. Please refer to FIG. 6. In this embodiment, the
綜上所述,在本發明的電路板的設計中,導通孔結構貫穿第一基材、第二基材及第三基材的第三介電層,且電性連接第一基材與第三基材而定義出訊號路徑,而第一基材、第二基材以及第三基材透過導電結構電性連接而定義出接地路徑,其中接地路徑環繞訊號路徑。藉此,可形成良好的高頻高速訊號迴路,且後續在積體電路與天線的應用上,亦可解決同一平面訊號干擾的問題,可降低訊號能量損失及減少雜訊干擾,進而可提升訊號傳輸可靠度。To sum up, in the design of the circuit board of the present invention, the via structure penetrates through the third dielectric layer of the first substrate, the second substrate and the third substrate, and electrically connects the first substrate and the third substrate. The three substrates define a signal path, and the first substrate, the second substrate, and the third substrate are electrically connected through a conductive structure to define a ground path, wherein the ground path surrounds the signal path. In this way, a good high-frequency and high-speed signal loop can be formed, and the subsequent application of integrated circuits and antennas can also solve the problem of signal interference on the same plane, which can reduce signal energy loss and noise interference, thereby improving the signal transmission reliability.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.
10a、10b、10c:電子裝置
100a、100b、100c:電路板
110、110a:第一基材
112:核心層
114:第一導電層
116:第一線路層
118:第一導通孔
120:第二基材
122:基底
124:導電柱
130、130a:第三基材
131:第一介電層
132:第二線路層
133:第二介電層
134:第三線路層
135:第三介電層
136:第二導電層
137:開口
138:導電連接層
139:第二導通孔
140:導電材料層
141:上表面
143:下表面
145:導電材料
150:導通孔結構
160:第四介電層
161:第一表面
163:第二表面
170:金屬層
175:罩蓋層
200:電子元件
210:接墊
300:連接件
C1:第一外部線路層
C11:第一訊號線路
C12:第一接地線路
C2:第二外部線路層
C21:第二訊號路線
C22:第二接地路線
L1:訊號路徑
L2:接地路徑
H1:第一盲孔
H2:第二盲孔
T:貫孔
10a, 10b, 10c:
圖1A至圖1E是依照本發明的一實施例的一種電路板的製作方法的剖面示意圖。 圖1F是圖1E的電路板的俯視示意圖。 圖2A至圖2B是依照本發明的另一實施例的另一種電路板的製作方法的局部步驟的剖面示意圖。 圖3A至圖3B是依照本發明的另一實施例的另一種電路板的製作方法的局部步驟的剖面示意圖。 圖4是依照本發明的一實施例的一種電子裝置的剖面示意圖。 圖5是依照本發明的另一實施例的一種電子裝置的剖面示意圖。 圖6是依照本發明的另一實施例的一種電子裝置的剖面示意圖。 1A to 1E are schematic cross-sectional views of a manufacturing method of a circuit board according to an embodiment of the present invention. FIG. 1F is a schematic top view of the circuit board of FIG. 1E . 2A to 2B are schematic cross-sectional views of partial steps of another circuit board manufacturing method according to another embodiment of the present invention. 3A to 3B are schematic cross-sectional views of partial steps of another circuit board manufacturing method according to another embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of an electronic device according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of an electronic device according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of an electronic device according to another embodiment of the present invention.
100a:電路板 100a: circuit board
110a:第一基材 110a: first substrate
112:核心層 112: core layer
116:第一線路層 116: The first line layer
118:第一導通孔 118: the first via hole
120:第二基材 120: second substrate
122:基底 122: base
124:導電柱 124: Conductive column
130a:第三基材 130a: third substrate
131:第一介電層 131: the first dielectric layer
132:第二線路層 132: Second line layer
133:第二介電層 133: second dielectric layer
134:第三線路層 134: The third line layer
135:第三介電層 135: The third dielectric layer
137:開口 137: opening
138:導電連接層 138: Conductive connection layer
139:第二導通孔 139: Second via hole
145:導電材料 145: Conductive material
150:導通孔結構 150: Via hole structure
C1:第一外部線路層 C1: the first external line layer
C11:第一訊號線路 C11: The first signal line
C12:第一接地線路 C12: The first ground line
C2:第二外部線路層 C2: second external line layer
C21:第二訊號路線 C21: Second signal route
C22:第二接地路線 C22: Second grounding route
L1:訊號路徑 L1: signal path
L2:接地路徑 L2: Ground path
T:貫孔 T: through hole
Claims (14)
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US202163235105P | 2021-08-19 | 2021-08-19 | |
US63/235,105 | 2021-08-19 | ||
US17/498,757 | 2021-10-12 | ||
US17/498,757 US12057381B2 (en) | 2021-01-21 | 2021-10-12 | Circuit board having laminated build-up layers |
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TW202310695A true TW202310695A (en) | 2023-03-01 |
TWI835074B TWI835074B (en) | 2024-03-11 |
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