TW202418950A - Memory circuit, dynamic random access memory and operation method thereof - Google Patents

Abstract

The present disclosure provides a dynamic random access memory, which includes a storage diode and a control-FET. The storage diode is composed of a gate-floating FET, and two source/drains of the gate-floating FET serve as a cathode and an anode of the storage diode. The control FET is electrically connected to the cathode or the anode of the storage diode.

Description

Memory circuit, dynamic random access memory and operation method thereof

The present invention relates to a storage circuit and an operating method thereof, and in particular to a memory circuit, a dynamic random access memory and an operating method thereof.

With the progress of Moore's Law, various embedded memories have been mass-produced in foundries. In many application fields, semiconductor memories are widely used in various electronic products.

However, due to the increasing cost and difficulty of high aspect ratio stacked capacitor technology using more masks in the back-end of the line (BEOL), the development of one transistor and one capacitor (1T1C) embedded dynamic random access memory (eDRAM) has stopped beyond more advanced processes. Therefore, based on the above reasons, a new dynamic random access memory is needed to adapt to the increasingly miniaturized process.

The present invention provides a memory circuit, a dynamic random access memory and an operation method thereof, which improve the problems of the prior art.

In one embodiment of the present invention, the dynamic random access memory proposed by the present invention includes a storage diode and a control field effect transistor. The storage diode is composed of a field effect transistor with a floating gate, and the two sources/drains of the field effect transistor with a floating gate serve as the cathode and anode of the storage diode respectively. The control field effect transistor is electrically connected to the cathode or anode of the storage diode.

In one embodiment of the present invention, the control field effect transistor includes a first gate, a first source/drain region, a second source/drain region, a first channel region, and a first dielectric layer region. The first source/drain region and the second source/drain region are located at opposite sides of the first gate, the first channel region is located between the first source/drain region and the second source/drain region, and the first dielectric layer region is located between the first gate and the first channel region.

In one embodiment of the present invention, the control field effect transistor and the storage diode share the second source/drain region, and the storage diode includes a second gate, a second source/drain region, a third source/drain region, a second channel region, and a second dielectric layer region. The second source/drain region and the third source/drain region are respectively located on opposite sides of the second gate. The second channel region is located between the second source/drain region and the third source/drain region, and the second dielectric layer region is located between the second gate and the second channel region.

In one embodiment of the present invention, the third source/drain region is electrically connected to the selection line, and the second gate is floating.

In one embodiment of the present invention, the first source/drain region is electrically connected to the bit line, and the first gate is electrically connected to the word line.

In one embodiment of the present invention, the memory circuit proposed by the present invention includes a plurality of memory cells arranged in an array. Each memory cell includes a dynamic random access memory, and the dynamic random access memory includes a control field effect transistor and a storage diode. The gate of the control field effect transistor is electrically connected to the word line, and the storage diode is composed of a field effect transistor with a floating gate. The opposite ends of the storage diode are electrically connected to the selection line and one end of the control field effect transistor respectively, and the other end of the control field effect transistor is electrically connected to the bit line.

In one embodiment of the present invention, each memory cell includes another dynamic random access memory, and the other dynamic random access memory includes another control field effect transistor and another storage diode. The gate of the other control field effect transistor is electrically connected to another word line, and the other storage diode is composed of another field effect transistor with a floating gate. The opposite ends of the other storage diode are electrically connected to another selection line and one end of the other control field effect transistor, respectively, and the other end of the other control field effect transistor is electrically connected to the bit line, and the bit line is located between the above-mentioned selection line and the other selection line.

In one embodiment of the present invention, the present invention provides an operating method for a dynamic random access memory, wherein the dynamic random access memory includes a storage diode and a control field effect transistor connected in series, wherein the storage diode is composed of a field effect transistor with a floating gate, and the operating method includes the following steps: when writing into the dynamic random access memory, a control voltage is applied to a word line, a write voltage is applied to a bit line, and a zero voltage is applied to a selection line, wherein the gate of the control field effect transistor is electrically connected to the word line, the opposite ends of the storage diode are electrically connected to the selection line and one end of the control field effect transistor, respectively, and the other end of the control field effect transistor is electrically connected to the bit line.

In one embodiment of the present invention, a control voltage turns on a control field effect transistor, and a write voltage causes a Zener tunneling mechanism to occur in a storage diode, so that the storage diode stores electricity.

In an embodiment of the present invention, the operating method further includes: when refreshing the dynamic random access memory, applying a control voltage to the word line, applying a write voltage to the bit line, and applying a zero voltage to the select line.

In one embodiment of the present invention, the operating method further includes: when reading the dynamic random access memory, applying a control voltage to the word line, applying a read voltage to the select line, and sensing the read current through the bit line.

In one embodiment of the present invention, the polarity of the read voltage is opposite to the polarity of the write voltage.

In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the existing technology. The dynamic random access memory of the present invention is an embedded dynamic random access memory of one transistor and one diode (1T1D) without capacitors, which can be manufactured entirely by pure wafer foundry field effect transistor technology in the front-end process, and does not require additional masks, materials and capacitor layout in the back-end process, thereby greatly reducing costs and design complexity.

The following will describe the above description in detail with an implementation method and provide a further explanation of the technical solution of the present invention.

In order to make the description of the present invention more detailed and complete, reference may be made to the attached drawings and various embodiments described below, in which the same numbers represent the same or similar elements. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessary limitations on the present invention.

Please refer to FIG. 1. The technical aspect of the present invention is a dynamic random access memory (DRAM) 100, which can be applied to embedded dynamic random access memory (eDRAM) or widely used in related technical links. The dynamic random access memory 100 of the technical aspect can achieve considerable technical progress and has a wide range of industrial utilization value. The specific implementation method of the dynamic random access memory 100 will be described below in conjunction with FIG. 1.

It should be understood that various implementations of the dynamic random access memory 100 are described in conjunction with FIG. 1. In the following description, for ease of explanation, many specific details are further set to provide a comprehensive description of one or more implementations. However, the present technology can be implemented without these specific details. In other examples, in order to effectively describe these implementations, known structures and devices are shown in block diagram form. The term "for example" used here means "as an example, instance or illustration." Any embodiment described herein as "for example" need not be interpreted as better or superior to other embodiments.

FIG. 1 is a block diagram of a dynamic random access memory 100 according to an embodiment of the present invention. As shown in FIG. 1, the dynamic random access memory 100 includes a storage diode 110 and a control field effect transistor 120 connected in series. In terms of architecture, the storage diode 110 is composed of a field effect transistor with a floating gate. Thus, the dynamic random access memory 100 is a capacitor-free one-transistor-one-diode (1T1D) eDRAM, which can be manufactured entirely using pure wafer foundry field effect transistor technology in the front-end process, and does not require additional masks, materials, and capacitor layouts in the BEOL, thereby greatly reducing costs and design complexity.

In terms of application, the eDRAM technology of the present invention shortens the delay between on-chip SRAM/register and on-DIMM DRAM to reduce the memory-wall and balance cost and performance, thereby realizing a wide range of possible applications.

In practice, for example, the gate-floating field effect transistor can be a gate-floating N-type field effect transistor or a gate-floating P-type field effect transistor, and the control field effect transistor 120 can be an N-type control field effect transistor or a P-type control field effect transistor. In order to simplify the following description, the N-type field effect transistor is used as an example. Those with ordinary knowledge in the field should know the difference in properties and electrical properties between the N-type field effect transistor and the P-type control field effect transistor, so it will not be repeated.

In FIG. 1 , the first gate 121 of the control field effect transistor 120 is electrically connected to the word line WL, the opposite ends of the storage diode 110 are electrically connected to the selection line SL and one end of the control field effect transistor 120, respectively, and the other end of the control field effect transistor 120 is electrically connected to the bit line BL.

Furthermore, it should be understood that in the embodiments and the scope of the patent application, the description involving "electrical connection" may generally refer to one element being indirectly electrically coupled to another element through other elements, or one element being directly electrically connected to another element without going through other elements.

Regarding the structure of the storage diode 110, in some embodiments of the present invention, the storage diode 110 is composed of a field effect transistor with a floating gate. The second source/drain region 202 and the third source/drain region 203 of the field effect transistor with a floating gate serve as the anode and cathode of the storage diode 110 respectively. The control field effect transistor 120 is electrically connected to the cathode or anode of the storage diode 110. The second channel region 222 is located between the second source/drain region 202 and the third source/drain region 203. The second dielectric layer region 112 is located between the second gate 111 and the second channel region 222. In practice, for example, the field effect transistor with a floating gate constituting the storage diode 110 may be an N-type field effect transistor with a floating gate, and the second source/drain region 202 serves as the anode of the storage diode 110 , and the third source/drain region 203 serves as the cathode of the storage diode 110 .

Regarding the structure of the control field effect transistor 120, in some embodiments of the present invention, the control field effect transistor 120 and the storage diode 110 share the second source/drain region 202. The first source/drain region 201 of the control field effect transistor 120 is electrically connected to the bit line BL, the second source/drain region 202 of the control field effect transistor 120 is electrically connected to the storage diode 110, the first channel region 221 is located between the first source/drain region 201 and the second source/drain region 202, and the first dielectric layer region 122 is located between the first gate 121 and the first channel region 221. In practice, for example, the control field effect transistor 120 may be an N-type control field effect transistor, the first source/drain region 201 of the N-type control field effect transistor is a drain, and the second source/drain region 202 of the N-type control field effect transistor is a drain.

In order to further explain the overall structure of the dynamic random access memory 100, please refer to Figures 1 and 2 at the same time. Figure 2 is a three-dimensional structure diagram of a dynamic random access memory 100 according to an embodiment of the present invention. As shown in Figure 2, the first source/drain region 201 and the second source/drain region 202 are respectively located on opposite sides of the first gate 121, and the second source/drain region 202 and the third source/drain region 203 are respectively located on opposite sides of the second gate 111. The control field effect transistor 120 and the storage diode 110 share the second source/drain region 202. As shown in FIG. 2 , in practice, for example, the control field effect transistor 120 may be a control fin field effect transistor, and the storage diode 110 may be composed of a fin field effect transistor with a floating gate, but the present invention is not limited thereto.

It should be noted that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the embodiments.

Regarding the structure of the control field effect transistor 120, in some embodiments of the present invention, the control field effect transistor 120 includes a first gate 121, a first source/drain region 201, a second source/drain region 202, a spacer 211 and a first channel region 221 (e.g., a three-dimensional fin channel). In terms of structure, the spacer 211 is located at two opposite sides of the first gate 121, and the first channel region 221 physically connects the first source/drain region 201 and the second source/drain region 202.

Regarding the structure of the storage diode 110, in some embodiments of the present invention, the storage diode 110 includes a second gate 111, a second source/drain region 202, a third source/drain region 203, a spacer 212, and a second channel region 222 (e.g., a three-dimensional fin channel). In terms of structure, the spacer 212 is located at two opposite sides of the second gate 111, and the second channel region 222 physically connects the second source/drain region 202 and the third source/drain region 203.

In some embodiments of the present invention, the third source/drain region 203 is electrically connected to the selection line SL, the second gate 111 is floating, the first source/drain region 201 is electrically connected to the bit line BL, and the first gate 121 is electrically connected to the word line WL.

Regarding the operation method of the DRAM 100, please refer to FIGS. 1 to 3 simultaneously. FIG. 3 is a schematic diagram of the energy level of the operation method of the DRAM 100 according to an embodiment of the present invention.

In the initial stage 301, the DRAM 100 is not selected, and zero voltage is applied to the word line WL, the bit line BL, and the select line SL. At this time, the conduction band _EC , the Fermi energy level _EF , and the valence band _EV are all stable, and the field effect transistor 120 is controlled to be kept in the off state to effectively prevent leakage current.

In the write phase 302, i.e., when writing the DRAM 100, a control voltage is applied to the word line WL, a write voltage is applied to the bit line BL, and a zero voltage is applied to the select line SL. The control voltage turns on the control field effect transistor 120, and the write voltage causes the storage diode 110 to generate a Zener tunneling mechanism, so that the storage diode 110 stores electricity.

In some embodiments of the present invention, the control field effect transistor 120 may be an N-type field effect transistor, the storage diode 110 may be composed of an N-type field effect transistor with a floating gate, the second source/drain region 202 is an N++ doped region (heavily doped region), the second channel region 222 is a P- doped region (lightly doped region), and the third source/drain region 203 is an N++ doped region to facilitate the occurrence of a Zener tunneling mechanism. In the write phase 302, a control voltage (e.g., about +0.8V) turns on the control field effect transistor 120. When the storage diode 110 undergoes Zener tunneling, the electrons ^e- are pulled out by the control voltage (e.g., about +0.8V), thereby generating excess charges (i.e., holes h ⁺ ) stored in the second channel region 222 (e.g., a three-dimensional fin channel).

It should be understood that the terms "about", "approximately" or "substantially" used herein are used to modify any quantity that may vary slightly, but such slight variations do not change its essence. If there is no special explanation in the implementation method, the error range of the value modified by "about", "approximately" or "substantially" is generally allowed within 20%, preferably within 10%, and more preferably within 5%.

In the holding phase 303, the electric quantity (e.g., the electric hole h ⁺ ) is temporarily stored in the second channel region 222 (e.g., the three-dimensional fin channel). In some embodiments of the present invention, the dynamic random access memory 100 can be refreshed periodically, wherein the refresh is the same as the write given voltage, the control voltage is applied to the word line WL, the write voltage is applied to the bit line BL, and zero voltage is applied to the select line SL. It should be understood that the refresh operation means that the information stored in the dynamic random access memory 100 will be lost over time, and it is necessary to periodically rewrite the information into the dynamic random access memory 100 within a predetermined time to maintain the electrical properties of the original stored information to prevent the loss of the information stored in the dynamic random access memory 100.

In the read phase 304, that is, when reading the DRAM 100, a control voltage is applied to the word line WL, a read voltage is applied to the select line SL, and a read current I _read is sensed through the bit line BL.

In some embodiments of the present invention, the control field effect transistor 120 may be an N-type field effect transistor, the storage diode 110 may be composed of an N-type field effect transistor with a floating gate, the second source/drain region 202 is an N++ doped region (heavily doped region), the second channel region 222 is a P-doped region (lightly doped region), and the third source/drain region 203 is an N++ doped region. In other words, the doping concentrations of the second and third source/drain regions 202 and 203 are much greater than the doping concentration of the second channel region 222. In the read phase 304 , the control voltage (eg, about +0.8V) turns on the control field effect transistor 120 , and the read voltage (eg, about −0.2V) attracts holes h ⁺ to form a read current I _read .

In some embodiments of the present invention, the polarity of the read voltage in the read phase 304 is opposite to the polarity of the write voltage in the write phase 302, so as to stably operate the write/read of the dynamic random access memory 100. In practice, for example, the storage diode 110 can be composed of an N-type field effect transistor with a floating gate, the read voltage is about -0.2V, and the write voltage is about +0.8V.

In order to further explain the array formed by the dynamic random access memory 100, please refer to Figures 1 to 4. Figure 4 is a circuit diagram of a memory circuit 400 according to an embodiment of the present invention. As shown in Figure 4, the memory circuit 400 includes a plurality of memory cells 410 arranged in an array, and each memory cell 410 has the same structure. Taking the memory cell 410 in the corner as an example, it can include the dynamic random access memory 100 and the dynamic random access memory 100'. In practice, for example, the DRAM 100 of FIG. 1 is substantially the same as the DRAM 100 of FIG. 4 , and the DRAM 100 and the DRAM 100′ are opposite to each other.

In FIG. 4 , the DRAM 100 includes a control field effect transistor 120 and a storage diode 110. The gate of the control field effect transistor 120 is electrically connected to the word line WL ₀ , and the storage diode 110 is composed of a field effect transistor with a floating gate. The opposite ends of the storage diode 110 are electrically connected to the selection line SL ₃₂ and one end of the control field effect transistor 120 respectively, and the other end of the control field effect transistor 120 is electrically connected to the bit line BL ₃₁ .

Similarly, in FIG. 4 , the DRAM 100 ′ includes a control field effect transistor 120 ′ and a storage diode 110 ′. The gate of the control field effect transistor 120 ′ is electrically connected to the word line WL ₁ , and the storage diode 110 ′ is composed of a field effect transistor with a floating gate. The opposite ends of the storage diode 110 ′ are electrically connected to the selection line SL ₃₁ and one end of the control field effect transistor 120 ′, respectively. The other end of the control field effect transistor 120 ′ is electrically connected to the bit line BL ₃₁ , and the bit line BL ₃₁ is located between the selection line SL ₃₂ and the selection line SL ₃₁ .

In FIG. 4 , the select lines SL ₀ ˜SL ₃₂ are electrically connected to a circuit 401, the word lines WL ₀ ˜WL ₆₃ are electrically connected to a circuit 402, and the bit lines BL ₀ ˜BL ₃₁ are electrically connected to a circuit 403. In some embodiments of the present invention, the circuit 401 may include a select line decoder, a select line driver, and a controller, the circuit 402 may include a word line decoder and a controller, and the circuit 403 may include a bit line decoder, a controller, and a sense amplifier. In practice, for example, the sense amplifier in the circuit 403 may sense and read a current through the bit line BL ₃₁ . In addition, for example, the storage diode 110 may be formed by an N-type field effect transistor with a floating gate, and the selection line driver of the circuit 401 is a negative voltage selection line driver, thereby providing a read voltage (eg, about -0.2V).

In an experimental example, the memory circuit 400 is designed by a standard fin transistor with an ultra-small size of ^0.0242μm2 . The dynamic random access memory 100 achieves a write time shorter than 7ns at a write voltage of 0.8V; the single-core working voltage achieves a read time shorter than 7ns at a read voltage of -0.2V at a clock frequency of about 400MHz. In the retention phase 303, the retention time is 116μs at 25°C and 101μs at 75°C. The write power is about 0.4μW/MHz and the read power is about 36.5nW/MHz.

In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. The dynamic random access memory 110, 100' of the present invention is a storage structure of a transistor and a diode (1T1D) without capacitors, which can be manufactured entirely using pure wafer foundry field effect transistor technology in the front-end process, and does not require additional masks, materials and capacitor layout in the back-end process, thereby greatly reducing costs and design complexity.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the attached symbols are explained as follows: 100, 100': dynamic random access memory 110, 110': storage diode 111: second gate 112: second dielectric layer region 120, 120': control field effect transistor 121: first gate 122: first dielectric layer region 201: first source/drain region 202: second source/drain region 203: third source/drain region 221: first channel region 222: second channel region 301: initial stage 302: write stage 303: hold stage 304: read stage 400: memory circuit 401, 402, 403: circuit 410: memory cell BL, _BL0 to _BL31 : bit line e ^- : electron E _C : conduction band E _F : Fermi level E _V : valence band h ⁺ : hole I _read : read current SL, SL ₀ ~ SL ₃₂ : select line WL, WL ₀ ~ WL ₆₃ : word line

In order to make the above and other purposes, features, advantages and embodiments of the present invention more clearly understandable, the attached drawings are described as follows: FIG. 1 is a circuit diagram of a dynamic random access memory according to an embodiment of the present invention; FIG. 2 is a three-dimensional structure diagram of a dynamic random access memory according to an embodiment of the present invention; FIG. 3 is a power level diagram of an operation method of a dynamic random access memory according to an embodiment of the present invention; and FIG. 4 is a circuit diagram of a memory circuit according to an embodiment of the present invention.

100: Dynamic random access memory

110: Storage diode

111: Second gate

112: Second dielectric layer region

120: Control field effect transistor

121: First Gate

122: first dielectric layer region

201: First source/drain region

202: Second source/drain region

203: Third source/drain region

221: First channel area

222: Second channel area

BL: Bit Line

SL:Selection Line

WL: character line

Claims (12)

A dynamic random access memory comprises: a storage diode, which is composed of a field effect transistor with a floating gate, and the two sources/drains of the field effect transistor with a floating gate serve as a cathode and an anode of the storage diode respectively; and a control field effect transistor, which is electrically connected to the cathode or the anode of the storage diode. A dynamic random access memory as described in claim 1, wherein the control field effect transistor comprises: a first gate; and a first source/drain region and a second source/drain region, respectively located on opposite sides of the first gate; a first channel region, located between the first source/drain region and the second source/drain region; and a first dielectric layer region, located between the first gate and the first channel region. A dynamic random access memory as described in claim 2, wherein the control field effect transistor and the storage diode share the second source/drain region, and the storage diode comprises: a second gate; and a second source/drain region and a third source/drain region, respectively located on opposite sides of the second gate; a second channel region, located between the second source/drain region and the third source/drain region; and a second dielectric layer region, located between the second gate and the second channel region. The dynamic random access memory as described in claim 3, wherein the third source/drain region is electrically connected to a selection line and the second gate is floating. The dynamic random access memory as described in claim 2, wherein the first source/drain region is electrically connected to a bit line, and the first gate is electrically connected to a word line. A memory circuit comprises: A plurality of memory cells arranged in an array, each of the memory cells comprising a dynamic random access memory, the dynamic random access memory comprising: A control field effect transistor, a gate of which is electrically connected to a word line; and A storage diode, which is composed of a field effect transistor with a floating gate, the opposite ends of the storage diode are electrically connected to a selection line and one end of the control field effect transistor, respectively, and the other end of the control field effect transistor is electrically connected to a bit line. A memory circuit as described in claim 6, wherein each of the memory cells includes another dynamic random access memory, the other dynamic random access memory including: another control field effect transistor, one gate of which is electrically connected to another word line; and another storage diode, which is composed of another field effect transistor with a floating gate, the other storage diode has two opposite ends electrically connected to another selection line and one end of the other control field effect transistor, respectively, and the other end of the other control field effect transistor is electrically connected to the bit line. A method for operating a dynamic random access memory, the dynamic random access memory comprising a storage diode and a control field effect transistor connected in series, the storage diode being composed of a field effect transistor with a floating gate, the operation method comprising the following steps: When writing into the dynamic random access memory, a control voltage is applied to a word line, a write voltage is applied to a bit line, and a zero voltage is applied to a selection line, wherein a gate of the control field effect transistor is electrically connected to the word line, two opposite ends of the storage diode are electrically connected to the selection line and one end of the control field effect transistor respectively, and the other end of the control field effect transistor is electrically connected to the bit line. An operating method as described in claim 8, wherein the control voltage turns on the control field effect transistor, and the write voltage causes the storage diode to undergo a Zener tunneling mechanism, causing the storage diode to store electricity. The operating method as described in claim 8 further includes: When refreshing the dynamic random access memory, applying the control voltage to the word line, applying the write voltage to the bit line, and applying the zero voltage to the select line. The operating method as described in claim 8 further includes: When reading the dynamic random access memory, applying the control voltage to the word line, applying a read voltage to the select line, and sensing a read current through the bit line. The operating method of claim 11, wherein the polarity of the read voltage is opposite to the polarity of the write voltage.

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