CN115719600B

CN115719600B - Memory unit, memory method, memory array, memory and preparation method thereof

Info

Publication number: CN115719600B
Application number: CN202211442822.6A
Authority: CN
Inventors: 闫锋; 沈凡翔; 卜晓峰; 马浩文
Original assignee: Nanjing University
Current assignee: Nanjing University
Priority date: 2022-11-16
Filing date: 2022-11-16
Publication date: 2023-08-11
Anticipated expiration: 2042-11-16
Also published as: CN115719600A

Abstract

The present disclosure provides a memory cell, a method of storing, a memory array, a memory and a method of manufacturing the same. The method adopts at least one three-dimensional dynamic random access memory unit, applies proper voltage on a selected grid layer for storing information, enables a charge coupling layer controlled by the grid layer to dynamically and randomly store information, and enables a first doping type material layer and a second doping type material layer to be matched for writing and resetting related information; applying an appropriate voltage to the selected gate layer for reading to change the conduction capability of the signal reading layer controlled by the gate layer, so that the third doping type and the fourth doping type serve as a source and a drain of the signal reading layer respectively, and reading out the voltage or the current related to the information; information stored on the plurality of gate layers is stored in a layer-by-layer manner in the vertical direction or in a region-by-region stacked manner in the horizontal direction. According to the method provided by the disclosure, the separation of the writing path and the reading path can be realized, and the method has the characteristics of high storage density, high speed, low power consumption and the like.

Description

Memory unit, memory method, memory array, memory and preparation method thereof

Technical Field

The invention relates to a three-dimensional dynamic random access memory unit element, in particular to a device and array structure, a working mechanism, an operation method and a preparation method of a three-dimensional dynamic random access memory unit (Dynamic Random Access Memory, DRAM) which has high memory density and low power consumption and can be compatible with three-dimensional integration.

Background

The most commonly adopted memory cell in the computer main memory at present is a dynamic random three-dimensional dynamic random memory cell (DRAM), and the main function principle is to use the charge stored in the capacitor to represent that one binary Bit (Bit) is 1 or 0, so that the working mode brings the characteristics of high reading and writing speed and long erasing and writing service life. However, in reality, the transistor has a leakage current, so that the amount of charges stored in the capacitor is not enough to accurately determine the data, and the data is damaged.

Current DRAMs commonly employ a "1T1C" structure, i.e., a single memory cell is comprised of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and a capacitor in series. The writing process transistor is turned on, and the bit line voltage charges or discharges the capacitor; in the reading process, the transistor is also turned on, and the charge stored in the cell capacitor is transferred to a sampling module of a bit line for reading. In this mode of operation, the accuracy of the read data is greatly affected by the parasitic capacitance of the bit line, resulting in the need to ensure that the capacitance of the DRAM memory cell is at least comparable to the parasitic capacitance to actually read the number of bits it stores. The smallest size currently commercially available is typically 6 feature size areas (6F ² ) Although, before and after 2010, semiconductor companies such as samsung and meiguang have proposed making both transistors and capacitors in DRAM in vertical directions to further reduce the memory cell or the corresponding size of a single bit, for example, patent US7518174B2 and patent USOO8212298B2. This approach allows the DRAM cell size to be reduced to 4 feature size areas (4F ² ) However, the structure is limited by the 1T1C structure, that is, the semiconductor process node is continuously reduced, the capacitance of the storage node cannot maintain a sufficient capacitance value, and the newly added vertical transistor also generates a floating body effect, so that the structure cannot be applied.

In the read aspect, the 3T DRAM can directly read the voltage of the Source terminal of a Source Follow (SF) transistor to determine the stored bit, and the DRAM is read without charge transfer through a bit line, thereby overcoming the disadvantage that a DRAM cell needs a large capacitance. However, the number of transistors is increased from 1 to 3, the periodicity of the original structure is destroyed, and the integration level is not in contrast to that of a 1T1C structure in the process of preparation.

Thus, in planar semiconductor processes, the increase in memory density of DRAMs has been at the end. Even with more advanced process nodes, the storage capacitor is limited in size, and the resulting increase is very limited. The bottleneck of the actual storage density is that all three-dimensional dynamic random access memory unit elements need to be solved, and the current successful comparison case is 3D NAND. The method realizes the connection of the FLASH device in the vertical direction through a three-dimensional process method by using an NAND Flash Memory (Flash Memory) array integrated by an original planar process, and the detailed scheme can be referred to patent US009595.346B2. The 3D NAND fully utilizes the space in the height direction, completes the conversion from a single-layer FLASH array to a ten-layer or hundred-layer array, and improves the storage density of FLASH by times. Due to superposition of layers, the unit FLASH can maintain a relatively large size to a great extent, and the non-ideal effect of the transistor caused by undersize is reduced; advanced nodes of 10nm or below are not needed for the process implementation, and the manufacturing cost is reduced.

In summary, the conversion of semiconductor processes from planarization to stereoscopicity is one of the key means to extend moore's law. The three-dimensional dynamic random access memory unit has the characteristics of simple structure and strong periodicity, and is necessarily an access point for three-dimensional semiconductor in the future. Then an ideal DRAM has a memory cell with an active follower whose memory signal can be read out by controlling the gate voltage of one transistor, thereby avoiding the use of large capacitance, achieving low power consumption, high read-write speed, and multi-bit storage. In addition, the method is compatible with a three-dimensional semiconductor process, designs a device structure, and solves the problem of storage density faced by the traditional planar DRAM.

Disclosure of Invention

The purpose of the invention is that: the structure, the setting method and the process implementation of the novel three-dimensional dynamic random memory unit are provided. Integration of the DRAM cells in the vertical direction is achieved and each memory cell is capable of reading out the voltage related to the information, for example in the form of a source follower, or the current signal in the form of a transconductance amplifier. The mode eliminates the defect of binding large capacitance of the traditional DRAM, and has the characteristics of high integration level, high read-write speed and multi-value storage.

The invention provides an information storage method of a three-dimensional dynamic random access memory, wherein the three-dimensional dynamic random access memory adopted in the method at least comprises a three-dimensional dynamic storage unit. The information writing and erasing of the three-dimensional dynamic storage unit adopts a shift register mode; alternatively, other suitable device structures may be used to remove the information and write it to an appropriate location. And the signal reading is carried out by column and row address selection, a single information storage node is selected, and the signal in the single information storage node is converted into voltage or current for reading. Based on the writing, erasing and reading modes, the three-dimensional dynamic storage unit can refresh all information storage nodes, and the effectiveness of all stored information is ensured. The three-dimensional dynamic random access memory comprises a three-dimensional dynamic random access memory, wherein the three-dimensional dynamic random access memory comprises a stacked structure taking a plurality of grid layers as main bodies, and the grid layers are regulated and controlled by voltage under the working condition of low storage load, so that part of storage nodes can not enter an information storage state, and the low-power consumption operation of the three-dimensional dynamic random access memory is realized.

In another aspect, the present invention provides a three-dimensional dynamic random access memory cell and a three-dimensional dynamic random access memory device including the same. The three-dimensional dynamic random access memory unit comprises: a substrate, and a stacked structure prepared on the substrate. The stacked structure includes a plurality of gate layers, and a channel hole extending through each gate layer in the stacked structure. The plurality of gate layers include a read gate, a write gate, a store and transfer gate, and a reset gate; the channel hole comprises a first insulating medium layer, a charge coupling layer, a second insulating medium layer, a signal reading layer and an insulating core layer. The charge coupling layer comprises a first doping type material layer and a second doping type material layer, and the signal reading layer comprises a third doping type material layer and a fourth doping type material layer. A plurality of the three-dimensional dynamic random access memory cells are disposed on a plane of the semiconductor device, and the plurality of three-dimensional dynamic random access memory cells are disposed to cooperate. The three-dimensional dynamic random access memory cell and memory structure are understood in detail from the claims, embodiments, and accompanying drawings of the present invention.

The invention also discloses a preparation method for the three-dimensional dynamic random access memory unit and the memory, wherein the preparation method comprises the following steps:

forming the second doped type material layer on a substrate;

forming the laminated structure on a substrate;

forming the channel hole penetrating through the laminated structure;

sequentially forming the first insulating medium layer, the charge coupling layer, the second insulating medium layer, the signal reading layer and the insulating core in the channel hole, wherein the charge coupling layer and the signal reading layer are in contact with the substrate;

dividing the stacked layer structure into a plurality of rows of stacked structures, forming the first doping type material layer and the third doping type material layer at the top of the channel hole, and forming a fourth doping type material layer on the substrate at the bottom of the channel hole;

and forming the writing bit line and the reading bit line by metal wire interconnection, and making contact with each layer of gate conductors at two sides of the stacked layer structure to form the bit line, the writing word line, the resetting word line and the isolation word line.

In addition, the invention provides a novel calculation method aiming at the characteristics of the three-dimensional dynamic random access memory unit, the memory device and the storage method, and the calculation method can be particularly used for training the weight of the matrix in the convolutional neural network. The method for storing the three-dimensional dynamic random access memory combines a plurality of three-dimensional dynamic random access memory units to form a three-dimensional dynamic random access memory array. Each information storage node in the three-dimensional dynamic random access memory array stores fixed weight information, a gating signal is applied to the read word line, and the current of the read bit line is used as an output signal to realize basic multiplication and addition operation in computing application. And after the multiplication and addition operation is completed, the three-dimensional dynamic memory reads out and writes new weight information from the writing bit line corresponding to the reading bit line according to feedback, completes the whole shift of all the information storage nodes, and performs the multiplication and addition operation and correction flow of the next period until the weight concerned in the memory array is corrected for one round, thus completing the training process in the memory calculation application.

The beneficial effects of the invention are as follows: the three-dimensional dynamic random access memory unit is equivalent to the integration of a plurality of capacitance-free dynamic random access memories in the height direction in principle, realizes the separation of a writing path and a reading path, and has the characteristics and advantages that:

high storage density: current standard DRAM memory cell size is 6F ² And toward 4F ² Is developed in size. The three-dimensional dynamic random access memory unit is in a stacked structure, and the memory function of each level in the unit is equivalent to that of a single DRAM memory unit. Therefore, the storage capacity of a unit area can reach tens of times of that of the traditional DRAM along with the increase of the number of the three-dimensional dynamic random access memory units. Assume that the three-dimensional dynamic random access memory cell has a size of 36F ² When the number of layers of the multi-layer gate is 64, the multi-layer gate comprises 20 storage nodes, and the single equivalent DRAM size is 1.8F ² The method comprises the steps of carrying out a first treatment on the surface of the When the number of layers of the multi-layer gate is 128, the multi-layer gate comprises 40 storage nodes, and the single equivalent DRAM size is 0.9F ² 。

Support continuous read-only: the single storage node in the three-dimensional dynamic random access memory unit is equivalent to a capacitor-free DRAM, and corresponding storage signals are not destroyed during reading. The inventive device thus supports a continuous read operation without the need for refreshing the memory nodes at the same time as reading like a classical DRAM, which is particularly advantageous for applications in the field of memory.

High speed and low power consumption: after the basic principle of the capacitor-free DRAM is adopted, the capacitance value of the storage node can be reduced by 2-3 orders of magnitude compared with that of a standard DRAM. In the aspect of the reading and writing speed, only a smaller storage capacitor is required to be charged during writing, and the characteristic of high writing speed is achieved; during reading, the signal charge driving transistor charges the read word line, which is an active reading mode and has the characteristic of high reading speed. In addition, the three-dimensional dynamic random access memory unit and the memory also have the characteristic of low power consumption due to the advantages that the original signals are not destroyed after the storage capacitor with low value and the read-out.

Multi-value storage: the storage nodes are not communicated with the read word lines electrically, and a single storage node can store 1-3 bit information according to the needs, and can realize the storage capacity of about 500GB of a single three-dimensional dynamic random access memory by matching with the characteristic of high density.

Is substantially compatible with 3D NAND processes: the preparation flow of the three-dimensional dynamic random access memory unit and the memory is basically compatible with the current general 3D NAND technology, and the preparation of the memory unit and the memory can be realized by completing all layers of process steps on a wafer. Compared with the standard 3D NAND manufacturing process, the three-dimensional dynamic random access memory unit only needs to change part of doping types, and a plurality of layers of thin film structures are added and grown in the channel holes.

Drawings

FIG. 1 is a cross-sectional view of a three-dimensional dynamic random access memory cell taken along the vertical direction of the channel hole diameter;

FIG. 2 is an equivalent circuit diagram of a three-dimensional dynamic random access memory cell;

FIG. 3 is a circuit symbol of a three-dimensional dynamic random access memory cell;

FIG. 4 is a horizontal cut-away view of a three-dimensional DRAM cell at a top point T;

FIG. 5 is a horizontal sectional view of the middle point M of the three-dimensional DRAM cell;

FIG. 6 is a horizontal cut view of a three-dimensional DRAM cell at bottom point B;

FIG. 7 is a vertical cross-sectional view of a three-dimensional dynamic random access memory cell having an insulating core structure along the diameter of a channel hole;

FIG. 8 is a horizontal cross-sectional view of a three-dimensional DRAM cell with an insulating core structure at a middle point M;

FIG. 9 is a vertical cross-sectional view of a three-dimensional dynamic random access memory cell with nonvolatile memory function along the diameter of a channel hole;

FIG. 10 is a view of a horizontal section at a point M in a three-dimensional dynamic random access memory cell with nonvolatile memory function;

FIG. 11 is a vertical cross-sectional view of a three-dimensional dynamic random access memory cell having a metal core structure along the diameter of a trench hole;

FIG. 12 is a horizontal cross-sectional view of a three-dimensional DRAM cell with a metal core structure at a middle point M;

FIG. 13 is a schematic diagram of the operation of a three-dimensional dynamic random access memory cell;

FIG. 14 is a schematic diagram of the band of the charge coupled layer during a write operation of a three-dimensional DRAM cell;

FIG. 15 is a schematic diagram of the band of the charge coupled layer during charge transfer operation of a three-dimensional DRAM cell;

FIG. 16 is a schematic diagram of the band of the charge coupled device during the re-write and read operations of the three-dimensional DRAM cell;

FIG. 17 illustrates the effect of read states '0' and '1' of a three-dimensional DRAM cell on the charge coupled layer and the band of the signal read layer;

FIG. 18 is a diagram showing the information flow of each memory node during refreshing of a three-dimensional dynamic random access memory cell;

FIG. 19 illustrates the usage of the three-dimensional DRAM cell under different storage load conditions;

FIG. 20 is a top view of a three-dimensional dynamic random access memory array;

FIG. 21 is a vertical cross-sectional view of a three-dimensional DRAM array;

FIG. 22 is a schematic diagram of a three-dimensional DRAM array circuit;

FIG. 23 is a schematic diagram of a horizontal stack of three-dimensional DRAM array cells and memory arrays;

FIG. 24 is a schematic diagram of the independent use of a three-dimensional DRAM cell and a memory partition;

FIG. 25 is a schematic diagram of a usage pattern of the three-dimensional dynamic random access memory array under different storage load conditions;

FIG. 26 is a schematic diagram showing electrical connections between memory cells in the same column of a three-dimensional DRAM array;

FIG. 27 is a schematic diagram of a three-dimensional dynamic random access memory array performing a pipelined write operation;

FIG. 28 is a flow chart of the fabrication of a three-dimensional dynamic random access memory cell and memory;

FIG. 29 is a schematic diagram of a process flow of a three-dimensional DRAM cell and memory;

FIG. 30 is a basic schematic diagram of a three-dimensional DRAM array and memory for storage;

FIG. 31 is a schematic diagram of an implementation of a three-dimensional DRAM array and memory processing positive and negative weight matrices.

Detailed Description

The cross-sectional view of the three-dimensional dynamic random access memory cell 110 along the diameter of the channel hole is shown in fig. 1. The memory cell 110 includes a substrate 110-1 and a stacked structure on the substrate, wherein the stacked structure is a multi-layer gate and a channel hole penetrating the multi-layer gate. The insulating medium layers are arranged between the multi-layer grids, and certain thickness and good insulativity are required to ensure that grids of different layers cannot pass through and have coupling effect as low as possible. The multi-layer gate structure is metal or polysilicon and functionally includes a write gate 118, read gates wl0_1-wl0_3, storage and transfer gates wl1_1-wl16_3, and a reset gate 119. The channel hole penetrating through the multi-layer gate is sequentially formed by a first insulating dielectric layer 111, a charge coupling layer 112, a second insulating dielectric layer 113, a signal reading layer 114 and an insulating core layer 115 (wherein the insulating core layer 115 is an optional layer, and can improve the readout performance of the memory cell when the layer exists), the material of the first insulating dielectric layer 111 is silicon oxide (SiO), the charge coupling layer 112 can be all P-type silicon, such as P-type polysilicon, the material of the second insulating dielectric layer 113 is SiO, and the material of the signal reading layer 114 can be all P-type silicon, such as P-type polysilicon. A first doping type material layer 117 and a third doping type material layer 116 are arranged on the top of the three-dimensional dynamic memory cell 110, wherein the first doping type material layer 117 is N ⁺ The third doped type material layer 116 is P ⁺ And is of type polysilicon and is in contact with the signal read layer 114. A second doping type material layer 110_3 and a fourth doping type material layer 110_2 are arranged in the substrate of the three-dimensional dynamic memory cell 110, wherein the second doping type material layer 110_3 is N ⁺ The fourth doping type material layer 110_2 is P ⁺ Polysilicon parallelAnd is in contact with the signal reading layer 114 and the charge coupled layer 112. Also, the first doping type material layer 117 is a writing node, the second doping type material layer 110_3 is a reset node, the third doping type material layer 116 is a reading node, and the fourth doping type material layer 110_2 is set as a voltage reference point. The horizontal cross-section structure 121 of the three-dimensional dynamic random access memory cell 110 at the point T is shown in fig. 4, the first doped type material layer 117 is a ring structure, the third doped type material layer 116 is a solid circle, and the doping types of the two are opposite. The blank portions in the horizontal sectional view 121 at the point T are all insulating materials, and may be set to SiO. The horizontal cross-section structure 122 of the three-dimensional dynamic random access memory cell 110 at the point M is shown in fig. 5, which can more clearly show the structural characteristics of the memory cell, and sequentially includes, from outside to inside, a gate layer, a first insulating dielectric layer 111, a charge coupled layer 112, a second insulating dielectric layer 113, a signal reading layer 114, and an insulating core layer 115. The horizontal cross-section structure 123 of the three-dimensional dynamic random access memory 110 at the point B is shown in fig. 6, wherein the second doping type material layer 110_3 and the fourth doping type material layer 110_2 disposed on the substrate are arranged in a periodic stripe structure, which not only has the characteristic of low manufacturing difficulty, but also facilitates the transmission of voltage when the arrays of the plurality of three-dimensional dynamic random access memory 110 cooperate.

The signal reading layer (114) is doped with P type, the top of the signal reading layer is provided with a P+ type doped region, the bottom of the signal reading layer is contacted with a fourth doped type material layer (110_2), and the fourth doped type material layer (110_2) is contacted with the substrate; the substrate is P-type epitaxial silicon, and a p+ type contact area is arranged on the substrate.

It should be noted that, although the third doped material layer 116 and the first doped material layer 117 are shown at the same end in fig. 1, the third doped material layer 116 and the first doped material layer 117 may be at different ends, which does not affect the normal operation of the third doped material layer 116 and the first doped material layer 117.

In addition, it should be noted that although the fourth doping type material layer 110_2 is shown in fig. 1 to encapsulate the second doping type material layer 110_3, the fourth doping type material layer 110_2 may be just at the bottom of the signal reading layer 114 shown in fig. 1, and may be formed in a juxtaposed configuration with the second doping type material layer 110_3.

As shown in fig. 7 and 8, the three-dimensional dynamic random access memory unit is further provided with an insulating core layer 115 in the signal reading layer 114, and the insulating core layer 115 cooperates with the signal reading layer 114 (may also be referred to as a charge reading layer) and each gate to form a plurality of fully depleted silicon-on-insulator (Full Depletion Silicon on Insulator, FD-SOI) transistors connected in series. The FD-SOI transistors are used for signal readout, have the advantages of high speed, low power consumption and low noise, and play a key role in improving the reading performance of the three-dimensional dynamic random access memory unit and the memory.

The first insulating dielectric layer (111) may include: equivalent SiO ₂ Silicon oxide/silicon nitride/silicon oxide with a thickness of 10-20nm, or silicon oxide with a thickness of 5-12nm, or equivalent SiO ₂ Al with thickness of 1-5nm ₂ O ₃ ，HfO ₂ ，Ta ₂ O ₃ ，ZrO ₂ ，Y ₂ O ₃ Or BaTiO ₃ Is a single layer or a composite layer of (a); and, in addition, the processing unit,

the charge coupled layer (112) may include: equivalent SiO ₂ A silicon nitride layer, a single crystal silicon layer, a polycrystalline silicon layer, an amorphous silicon layer or a germanium silicon layer with a layer thickness of 1-10nm,

the second insulating dielectric layer (113) may include: silicon oxide with thickness of 5-12nm, or equivalent SiO ₂ Al with thickness of 1-5nm ₂ O ₃ ，HfO ₂ ，Ta ₂ O ₃ ，ZrO ₂ ，Y ₂ O ₃ Or BaTiO ₃ A single layer or a composite layer of SiLK, FOx or MSQ with the equivalent oxide layer thickness of 10-30nm, or a low-K material of the single layer or the composite layer,

the third insulating dielectric layer (111_2) (which will be described below with reference to fig. 9 and 10) may include: equivalent SiO ₂ Silicon oxide/silicon nitride/silicon oxide with thickness of 10-20nm, orSilicon oxide with thickness of 5-12nm, or equivalent SiO ₂ Al with thickness of 1-5nm ₂ O ₃ ，HfO ₂ ，Ta ₂ O ₃ ，ZrO ₂ ，Y ₂ O ₃ Or BaTiO ₃ Is a single layer or a composite layer of (a); a kind of electronic device with high-pressure air-conditioning system;

the charge coupled layer, the first doping type material layer, and the second doping type material layer may include: 6-40nm of monocrystalline silicon, 10-200nm of polycrystalline silicon, amorphous silicon, siGe or one of SiC layers;

The signal reading layer (114) may include: 6-20nm of monocrystalline silicon, 5-40nm of polycrystalline silicon, siGe or SiC;

the insulating core layer (115) may include: at least one of silicon oxide, silicon nitride, siLK, FOx, MSQ, or air gap.

As shown in fig. 2, the interface of the fourth doped material layer 110_2 is denoted as a common source line CSL, the interface of the second doped material layer 110_3 is denoted as a common reset source line CRST, and the charge coupling layer 112 and the signal reading layer 114 are respectively used as channels of a charge storage device and a transistor. The Charge of each storage node of the Charge-Coupled layer 112 is written step by step from the write bit line WBL by applying bias voltages to the write gate 118 and each storage and transfer gate WL, and the working principle is similar to that of a Charge-Coupled Device (CCD), and meanwhile, the stored Charge is still controlled to flow out from the common reset node 110_3 at the reset gate 119 by means of the Charge step by step transfer, so as to realize the reset of all storage nodes. The signal reading layer 114 is a common channel in which a plurality of transistors are connected in series, wherein the gate of a single transistor is a charge coupled layer corresponding to the transistor, and the voltage state of the charge coupled layer is determined by the storage and transfer gate WL voltage of the layer and the charge amount stored in the charge coupled layer, so that the gating of each transistor can be realized and the amount of charge in the corresponding charge coupled layer can be determined. The external equivalent circuit model of the three-dimensional dynamic random access memory unit can be further simplified, and only necessary interface parameters are reserved, as shown in fig. 3.

Fig. 13 to 17 are schematic diagrams related to basic operation modes of the three-dimensional dynamic random access memory 110, and the main structure of the memory 110 is centrosymmetric, so that the structure of one side is selected as a principle illustration, as shown in fig. 13. The three consecutive storage and transfer gates WL are grouped, and the gates in the same group are respectively designated as a first phase gate wli_1, a second phase gate wli_2 and a third phase gate wli_3 in order. The first phase gate of the first group is adjacent to the write gate and the third phase gate of the last group is adjacent to the reset gate. The three-dimensional dynamic random access memory unit has the following flow modes of writing, transferring, resetting and reading signal charges:

standby state of three-dimensional dynamic random access memory cell: the voltage reference node 110_2 and the read node 116 are grounded, the gates of the stack are grounded, the write node 117 is grounded, the reset node 110_3 is connected to a 1V saturated reset voltage (V _sat 1V), and can reset carriers of the storage node.

Writing and resetting of the three-dimensional dynamic random access memory unit: an appropriate voltage is applied to a selected gate layer for storing information, the gate layer controlled charge coupled layer (112) is caused to perform dynamic random storage of information, and the first doping type material layer (117) and the second doping type material layer (110_3) are caused to cooperate to perform writing and resetting of the information concerned.

As shown in fig. 14, the writing bit line WBL is the first doping type material layer 117, the writing gate WG is the writing gate 118, the reset gate RG is the reset gate 119, and the reset source line RSL is the second doping type material layer 110_3. The specific operation flow is that the write gate WG is opened and connected with a power supply voltage (V) of 1.8V _CC 1.8V); the first phase gate WL0_1 of the storage and transfer gate is turned on, connected to V _CC 1.8V, the charge-coupled layer 112 corresponding to the gate generates a depletion region, but the signal reading layer 114 is not significantly depleted and remains in an on state; the write nodes 117 are connected to OV/V according to digital 0/1 signals _sat Or connect O-V according to analog signal quantity _sat Realizing multi-value storage by arbitrary voltage valueAnd (5) storing. The write gate 118 is turned off, and the storage and transfer gate voltages are kept unchanged, so that the signal charge amount corresponding to the voltages given by the write nodes is stored in the charge coupled layer 112 of the first phase gate wl0_1 of the first group of storage and transfer gates, and the initial writing is completed.

The charge transfer of the three-dimensional dynamic random access memory cell is shown in fig. 15, in which phase 0, phase 1 and phase 2 correspond to a first phase gate wli_1, a second phase gate wli_2 and a third phase gate wli_3, respectively, and i is a natural number, wli_1 represents a first phase gate of any stage, and wli_2 and wli_3 are the same. The same phase gate of the different groups of storage and transfer gates is connected with the same voltage signal, which is 0V or power supply voltage V _CC Respectively denoted as 0 and 1; after the write operation is completed, the signal charges are stored under a first phase gate wli_1, and the logic state of each phase gate is that the first phase gate wli_1 is set 1, and the second phase gate wli_2 and a third phase gate wli_3 are set 0; then only the second phase gate WLi_2 is changed, and is set to 1, and signal charges are uniformly spread under the first phase gate WLi_1 and the second phase gate WLi_2; then, the first phase gate wli_1 is changed, and set to 0, and the signal charges are all transferred to the second phase gate wli_2. In accordance with the above-described operation, the entire process of signal charge from the first phase gate wli_1 to the second phase gate wli_2, to the third phase gate wli_3, and finally to the next group of first phase gate wli_1 is completed, which is called one charge transfer.

The re-writing and re-transferring of the three-dimensional dynamic random access memory cell is shown in fig. 16, after the charge transfer, the signal charges originally stored in the first group of storage and transfer gates are transferred to the next stage, and the writing and transferring of the three-dimensional dynamic random access memory cell can be completed again according to the writing method and the charge transfer method of the three-dimensional dynamic random access memory cell.

Resetting of the three-dimensional dynamic random access memory unit: the signal charge is transferred to the third phase gate of the last group of storage and transfer gates via the charge transfer process, at which time the third phase gate V _CC 1.8V; the reset grid is then opened to connect V _CC 1.8V; and signal charges flow out of the reset node to realize reset.

As shown in fig. 16 and 17, a suitable voltage is applied to a selected gate layer for reading, so that the conduction capability of a signal reading layer area controlled by the gate layer is changed, the third doped type material layer (116) and the fourth doped type material layer (110_2) are respectively used as a source and a drain of the signal reading layer, and the voltage or the current related to the information is read, and the specific operation principle is that:

since the channel, source (i.e., the third doped type material layer (116)) and drain (i.e., the fourth doped type material layer (110_2)) of the signal reading layer 114 are P-type and are depletion transistors, the voltage applied to the gates of the stacked structure in the non-read mode is low, and the threshold voltage of the signal reading layer 114 cannot be reached, so that the channel is always in a normally-on state. In the read mode, the memory and transfer gates to be read are selected, and a 3V read voltage (V _read 3V). When the signal charge at the position is 0, the output current value is 0 corresponding to the signal reading layer 114 being fully depleted; when the signal charge is 1, the signal reading layer 114 is not depleted, and the normal transistor outputs an on current of about uA level, thereby realizing reading.

In the case of multi-bit storage, the signal charge amount is expressed as modulation of the threshold voltage of the signal reading layer, and the signal charge amount and the threshold variation amount approximately satisfy the following relationship:

wherein c _i1 Is the capacitance per unit area of the first insulating medium layer, Q _sig Is the average charge per unit area, deltaV _th Is the threshold voltage variation of the selected memory cell.

When the signal is read by adopting a current mode, a reference voltage of 0V can be added to the drain terminal, a small bias voltage of 0.5V can be added to the source terminal, a 3V reading voltage can be added to the selected storage and transfer grid, and under the conduction state, the output current and the signal charge can meet the requirements

Wherein I is _out Is the output current of the source, beta is a fixed coefficient, V _G Is the read voltage, V _TO Is the initial threshold voltage, V, of the selected gate corresponding signal reading layer 114 _DS Is the source drain fixed bias of 0.5V.

When signal reading is performed in a voltage mode, a reference voltage of 0V is added to the drain terminal, and the source terminal fixes a rated current source I of 3uA _S And is pulled up to the voltage source V _CC Applying a 5V read voltage to the selected storage and transfer gate, and in the on state, the output voltage and signal charge satisfy

Wherein V is _out The output voltage of the source electrode is the same as the output current expression of the previous formula.

Based on the basic writing, reading and resetting modes of the three-dimensional dynamic random access memory unit, the refreshing flow of the memory nodes in the memory unit 110 is shown in fig. 18, the memory nodes adjacent to the writing grid 118 are marked as a plurality of levels of memory nodes, and the memory nodes adjacent to the resetting grid 119 are marked as tail nodes; and defining the head nodes as buffer nodes, wherein storage nodes except the head nodes are effective storage nodes, and the effective storage nodes adjacent to the buffer nodes are first-stage effective storage nodes. It is assumed that after the writing operation is completed, all the effective storage nodes in the three-dimensional dynamic random access memory cell have stored the corresponding signal charges. Firstly, reading the tail node, and synchronously writing the read signal value into the head node; then, carrying out primary charge transfer on the whole storage node to reset signal charges in an original tail node and transfer a head node signal to a first-stage effective storage node; and repeating the operations of reading, writing and transferring until the data of all the effective storage nodes are rewritten for one time, and finishing the refreshing operation.

The above working state description mainly describes the use method of the three-dimensional dynamic random access memory unit under the working condition of limiting storage load, namely, all storage nodes participate in storing effective information. However, in practical applications, the storage amount required by a part of the scenes cannot reach the extent that the storage unit of the present invention needs full-load work. Under the condition of low storage load, proper voltage is only applied to adjacent partial grid layers or different partitions in the same grid layer to carry out information storage operation, and the grid layers which do not store information are in a low power consumption state without information access by a voltage regulation mode.

At this time, the three-dimensional dynamic memory cell 110 enters a low-memory-density operating state, and is in a low-power-consumption state in which no information access is performed by voltage regulation in other gate layers in which no information is stored. As shown in fig. 19, because the writing node 117 of the three-dimensional dynamic random access memory 110 is located at the top of the memory cell, the memory nodes participating in the memory operation are arranged from top to bottom under the low memory load condition. The remaining gate layer, which does not store information, is kept in agreement with the applied voltage of the reset gate 119 to ensure that signal charges in the last stage of storage nodes involved in operation can be drained through the reset node 110_3 in a desired reset state. With the change of working conditions, the storage pressure is increased, the number of nodes for information storage is increased layer by layer, the low storage load state is transited to the high storage load state, and finally the full storage load state is reached.

Since the three-dimensional dynamic random access memory cell 110 having the insulating core layer 115 has a significant advantage in a read-out speed, the operation method is completely identical to that of the original three-dimensional dynamic random access memory cell, and is even simpler in process implementation. Three-dimensional dynamic random access memory arrays, memories, and methods of making and using the same will be described based on three-dimensional dynamic random access memory cells having an insulating core layer.

Fig. 20 to 22 are block diagrams of an array of a plurality of the three-dimensional dynamic random access memory cells. FIG. 20 is a top view of a three-dimensional dynamic random access memory array in which three-dimensional dynamic random access memory cells are arranged in a rectangular configuration. The write nodes 117 of the memory cells of the same column are connected to form a write bit line WBL of the memory array; the read nodes 116 of the memory cells of the same column are connected to form a read bit line RBL of the memory array. As shown in fig. 20 and 21, the same layer of gates of the memory cells in the same row can generate a connected structure (refer to the 3D NAND method herein) in the preparation process, so as to form corresponding write word lines, reset word lines RWL and storage and transfer word lines WL, and the stacking manner of each layer of gates at the array edge is a pyramid structure, which is the same as the 3D NAND structure, so as to facilitate the access of the electrodes. As shown in fig. 22, the reset nodes 110_3 of all the three-dimensional dynamic random access memory cells of the memory array are connected to form a common reset source line CRST; all voltage reference points 110_2 are connected to form a common source line CSL.

The three-dimensional dynamic random access memory array formed by combining the three-dimensional dynamic random access memory units 110 can also follow the use rules of the memory units 110 in the use process. The grid electrode layers adopt a dynamic random access memory plane array structure to set a plurality of three-dimensional dynamic random access memory units, and each grid electrode layer is enabled to store in a sequential working mode along with the increase of storage load.

As shown in fig. 25, the storage nodes of each layer in the storage array are divided into a storage Block, and when the storage nodes face a designated storage task, the storage blocks are used layer by layer according to the division of the blocks, for example, from top to bottom, so as to meet the application requirement from low storage load to high storage load, and ensure that the memory works with the power consumption of the optimal solution. Similarly, when the memory array or the memory is subjected to reset or refresh operation, the grid electrode below the effective storage node of the last stage participating in the memory is kept synchronous with the corresponding reset grid electrode potential, so that the memory array is reset and refreshed in a low-power consumption mode.

Alternatively, as shown in fig. 23, the plane where each gate layer is located may be partitioned, one of the dynamic random access memory units is disposed in the same partition, and the gate layers in different partitions in the same plane may be made to operate independently with an increase in storage load, so as to store information. The stacking mode of the three-dimensional dynamic memory unit and the memory is not limited to the vertical direction, the grid electrode layer is partitioned in the same horizontal direction, and when information is stored, the information in one partition is integrally pushed to the adjacent other partition.

Alternatively, information stack storage may be performed in a manner other than 3D NAND as shown in fig. 24. The three-dimensional dynamic random access memory unit is arranged on one semiconductor device plane or at the position corresponding to the upper and lower positions in the adjacent semiconductor device planes, and the three-dimensional dynamic random access memory units are arranged to work cooperatively. For example, at the element level, an integral stacked layer is divided into a plurality of parts, and the device is operated so that the capacity of information of each part is not more than 50%, so that when information storage in one part is carried out, the information is pushed from top to bottom or from bottom to top layer by layer only in the part, and the information storage between different parts can be kept from affecting each other. In this way, energy saving of the element group can be achieved. And further extends to the device level or the system level, and accordingly, the energy-saving working modes of the device level and the system level can be realized.

In this way, for example, when designing a customer subsystem, it is possible to set up not less than 50% of the storage redundancy for the customer concerned, enabling this single customer subsystem to operate in a power-efficient manner.

After a write operation is performed on the three-dimensional dynamic random access memory unit, the buffer storage nodes of the same memory unit can be written after the charge signal is transferred to the next stage, so that the write speed of the memory unit is affected. However, after the three-dimensional dynamic random access memory array is formed, the control signal of the time sequence can be optimized, and the non-interval writing of the three-dimensional dynamic random access memory array is realized in a pipeline mode. As shown in fig. 26, for the memory cells of the same column in the memory array, the write bit line WBL is shared by a plurality of memory cells, and their gate voltages are independent of each other. And opening the write-in grid WWL1 of the first three-dimensional dynamic random access memory Cell 1 in the first clock period, closing all write-in grids of other memory cells, and closing the write-in grid WWL1 after the write-in of the buffer memory node of the memory Cell is completed. Then, the write gate WWL2 of the memory Cell2 is turned on, and at the same time, the charge signal written in the memory buffer node in Cell 1 is transferred to the next stage. Similarly, after the writing to the memory buffer node of Cell2 is completed, the write gate WWL2 is turned off, and the signal charge of Cell2 is then transferred downward. As shown in fig. 27, the memory array is periodically written, and each memory cell stops transferring after completing the charge transfer once, and enters a write waiting state. After the writing of all the storage nodes in the storage Block is completed, returning to the position of the Cell 1 again, and performing writing operation on the second-stage storage nodes of the Cell 1. Because the charge transfer requires 6 clock cycles, as long as the number of the memory cells controlled by the same write bit line exceeds 6, the memory cells can enter a write waiting state before the memory Block completes the write operation, thereby realizing the write operation of the memory array and the memory without interval.

In addition, the partial material parameters of the three-dimensional dynamic random access memory unit are adjusted, so that the device can obtain additional functions or improve the original performance.

As shown in fig. 9 and 10, a coupling charge layer 111_1 for storing static information and a third insulating dielectric layer 111_2 are further disposed radially outwards of the first insulating dielectric layer 111, where the material of the first insulating dielectric layer 111 is silicon oxide (SiO), the material of the coupling charge layer 111_1 is silicon nitride (SiN), and the material of the third insulating dielectric layer 111_2 is silicon oxide (SiO). The composite material of SiO/SiN/SiO can tunnel the carriers in the charge coupling layer 112 into SiN corresponding to a designated storage node by FN tunneling, thus completing the nonvolatile storage of the three-dimensional dynamic storage unit.

As shown in fig. 11 and 12, the material of the inner core of the insulating core layer 115 is provided as an insulating layer 120_1 and a metal inner core 120_2, the material of the insulating layer 120_1 is silicon oxide (SiO), and the material of the metal inner core 120_2 is tungsten (W). The columnar metal core 120_2 serves as a back gate of the three-dimensional dynamic random access memory cell, and applies a proper positive high voltage on the premise that the signal reading layer 114 depends on holes as carriers, so that the signal reading layer 114 of the three-dimensional dynamic random access memory cell 110 can be turned off, and a row and column address selecting function is provided. After the memory cells form the memory array, the memory cells can be used as the read gates of the whole memory cells.

It should be noted that, in the description of fig. 1, the doping types of the charge coupled layer 112, the signal reading layer 114, the third doping type material layer 116, the fourth doping type material layer 110_2 are P, and the doping types of the first doping type material layer 117 and the second doping type material layer 110_3 are N, but the doping types of the above layers may be other types according to practical situations.

Specifically, as shown in fig. 1, the doping type of the charge-coupled layer 112 is N or intrinsic, and the first doping type material layer 117 and the second doping type material layer 110_3 are P-type, so that the carriers of the charge-coupled layer 112 are holes, which can reduce the leakage of the storage node; the doping types of the signal reading layer 114, the third doping type material layer 116 and the fourth doping type material layer 110_2 are all N-type, so that the carriers of the signal reading layer 114 are electrons, which can enhance the voltage driving capability of the reading state and improve the signal reading speed and stability. The fourth doping type material layer 110_2 is in contact with the charge coupled layer 112, the fourth doping type material layer 110_2 is in contact with the substrate 110_1, and the voltage transmitted through the fourth doping type material layer 110_2 can provide stable electrical states for the charge coupled layer 112 and the substrate 110_1 at the same time, so that the number of external interfaces of the three-dimensional dynamic memory cell can be effectively reduced, the complexity of connection is reduced, and further reduction of the device size is facilitated.

Fig. 28 and fig. 29 are a schematic flow chart and a schematic flow chart of a preparation process of the three-dimensional dynamic random access memory unit and the memory, and the specific flow chart is as follows:

a) The substrate is subjected to P-type well injection with the concentration of 10 ¹⁸ /cm ³ Forming a fourth doped type material layer on the substrate;

b) Repeatedly growing a SiO/SiN layer until reaching a target layer number, and forming a laminated structure on the substrate, wherein the thickness of the SiO layer is 15nm to 130nm, and the consistency of the thickness of the storage gate and the thickness of the transfer gate are required to be kept good;

c) Etching a channel hole penetrating through the stacked structure to a substrate to form the channel hole penetrating through the stacked structure, and growing a SiO film with the thickness of 7nm along the channel hole to form a first insulating medium layer;

d) Etching SiO at the bottom of a channel hole, and growing a P-type polycrystalline silicon film along the channel hole to form a charge coupling layer; growing a SiO film along the channel hole to form a second insulating medium layer, wherein the thickness of the grown polysilicon is 10nm to 12nm, and the concentration of the polysilicon is as follows

～10 ¹⁷ /cm ³ ；

e) Etching SiO at the bottom of the channel hole, growing a P-type polycrystalline silicon film along the channel hole to form a signal reading layer, wherein the signal reading layer is contacted with the fourth doping type material layer; growing a SiO film along the channel hole, and filling with SiO to form the insulating core layer, wherein the thickness of the grown polysilicon is 6nm to 10nm, the thickness of the SiO is 10nm, and the concentration of the grown polysilicon is 10 ¹⁸ /cm ³ ；

f) Growing a layer of intrinsic polycrystalline silicon on the top;

g) P-type doping is carried out on the top polysilicon material, and the doping concentration is 10 percent ²⁰ /cm ³ Forming a third doped material layer;

h) Etching the multi-layer gate structure to form a multi-row discrete stacked structure, and injecting a mask plate to form the first doping type material layer and the second doping type material layer, wherein the first doping type material layer is arranged at the top of the channel hole, and the second doping type material layer is arranged on the substrate;

i) And washing off all SiN materials, and introducing metal tungsten to form a metal grid electrode.

Forming a writing bit line and a reading bit line by metal wire interconnection, wherein the writing bit line comprises a first doping type material layer of the three-dimensional dynamic random access memory cells in the same column connected with the metal wire and the contact, and the reading bit line comprises a third doping type material layer of the three-dimensional dynamic random access memory cells in the same column connected with the metal wire and the contact;

forming a writing word line, a resetting word line and a storage and transfer word line by making contact with each layer of gate conductors at two sides of the stacked layer structure, wherein the writing word line comprises writing gates in the same row, namely a first layer of gates from top to bottom of the gate layers; the reset word line comprises reset gates in the same row, namely a last layer of gates from top to bottom of the gate layer; the memory and transfer word line includes memory and transfer gates that are in the same row and layer, i.e., the gate layer removes all gates of the first and last layers.

More preferably, before the step of forming the stacked layer structure, an epitaxial layer may be further deposited on the substrate 110_1, and a well implant may be formed in the epitaxial layer, the epitaxial layer being in contact with the charge coupled layer and the signal reading layer.

More preferably, the plurality of gate conductors are formed by metal layers deposited by atomic layer deposition, so that voids are less likely to be formed in the process of gate preparation, and excellent electrical characteristics are achieved.

As shown in FIG. 30, each information storage node in the three-dimensional dynamic random access memory array stores fixed Weight (Weight) information W _ji The information storage nodes of the same layer are divided into an operation block, and a strobe signal X is applied to the read bit line RBL _i The current of the read bit line of the single block is taken as an output signal, and the current value is basically multiplied by an addition operation Y _j ＝∑W _ji X _i . The three-dimensional dynamic memory keeps the first-stage effective information storage node selected by each word line to finishAfter the multiply-add operation, the new weight information W is revised according to the feedback and written into the write bit line WBL corresponding to the read bit line RBL _ji And', completing the whole shift of all the information storage nodes, and performing multiplication and addition operation and correction flow of the next operation block until the weight concerned in the storage array is corrected for one round, thus completing the training process in the storage computing application.

The division of the operation block is positioned at different layers on physical positions, the operation block comprises a plurality of information storage nodes, the information storage nodes are positioned by the layers and the rows where the information storage nodes are positioned, the same layer comprises at least one row of information storage nodes, and the information storage nodes of different layers cannot be positioned in the same row. For example, a first layer of the first row, a third layer of the second row and a third layer of the third row may be selected to form an operation block; however, the first layer of the first row, the third layer of the first row, and the third layer of the third row cannot form an operation block due to the existence of two portions of the same row.

As can be seen from the description above in connection with fig. 20-22 and fig. 30, the three-dimensional dynamic random access memory array includes: the gate layer including a write gate (118), a reset gate (119), and multiple sets of storage and transfer gates; in the three-dimensional dynamic random access memory array, the writing grid electrodes of the same row are connected to form a writing word line; the reset gates in the same row are connected to form a reset word line RWL; the storage and transfer grid electrodes of the same row and the same layer are connected to form a storage and transfer word line WLm_n, wherein m is a natural number and represents the group number of the storage and transfer grid electrodes; n is a positive integer representing the intra-group number of the storage and transfer gates in the same group; the charge coupling layer (112) forms a plurality of groups of periodic potential wells under the control of the externally applied voltages of the gate layers, the potential wells have the function of storing carriers, and a single potential well for storing carriers is defined as an information storage node; each information storage node in the three-dimensional dynamic random access memory array is set to store fixed weight information W during operation _ji The information storage nodes of the same layer are divided into one block so that the gate signal X is applied to the storage and transfer word line WLm_n _i When in use, singlyThe current of the read bit line of each block is taken as an output signal, and the value of the current is Y _j ＝∑W _ji X _i Wherein i and j are positive integers, and the read nodes of the three-dimensional dynamic random access memory units in the same column in the three-dimensional dynamic random access memory array are connected to form the read bit line; and setting the three-dimensional dynamic random storage units in the three-dimensional dynamic random storage array to select storage and transfer word lines corresponding to the first-stage effective information storage nodes, after completing multiplication and addition operation, revising according to feedback, writing new weight information into the writing bit lines corresponding to the reading bit lines, completing integral displacement of all the information storage nodes, and performing multiplication and addition operation and revision flow of the next block until the weight concerned in the storage array is subjected to one-round revision, thus completing training process in storage and calculation application.

In the operation process of multiply-add of convolutional neural network, the problem of positive and negative weights can be related, and the numerical subtraction is generally completed in the form of positive and negative matrixes at present. As shown in fig. 31, pos.w and neg.w in the figure respectively represent a positive weight and a negative weight, and three-dimensional dynamic random access memory units in even columns of the three-dimensional dynamic random access memory array are selected to store the positive weight, the memory units in odd columns store absolute values of the negative weight, and each two adjacent columns of the memory units are a group, so that output currents of the two columns respectively satisfy:

I _CELL0 ＝∑W _ji X _i

I _CELL1 ＝∑|W _ji ’|X _i ’＝∑-W _ji ’X _i ’

I _CELL ＝I _CELL0 –I _CELL1 ＝∑(W _ji X _i +W _ji ’X _i ’)

Wherein W is _ji ' is a negative value.

In addition, the electrical characteristics of the device are generally related to the position of the wafer in the manufacturing process, two adjacent storage units are respectively used for storing positive weights and negative weights, the output signals of the storage array are the current difference between the two, and the adjacent two rows with almost the same positions are used for carrying out subtraction, so that the non-uniformity caused by preparation can be eliminated to a certain extent, and the operation precision is improved.

Claims

1. A method for three-dimensional dynamic random information storage, which is characterized in that:

at least one three-dimensional dynamic random access memory cell is employed, the three-dimensional dynamic random access memory cell comprising a substrate (110_1), and a stacked structure fabricated on the substrate, the stacked structure comprising a plurality of gate layers, and a channel hole extending through each gate layer in the stacked structure, and,

in each grid electrode layer plane, a first insulating medium layer (111), a charge coupling layer (112) for storing dynamic information, a second insulating medium layer (113) and a signal reading layer (114) are sequentially arranged along the radial direction from outside to inside taking the center of the channel hole as an end point; and, a first doping type material layer (117) is provided at one end of the charge coupling layer (112) in an axial direction penetrating the gate layer, a second doping type material layer (110_3) is provided at the other end of the charge coupling layer (112) in the axial direction penetrating the gate layer, and the doping types of the first and second doping type material layers are the same, so that charges can be transferred in the axial direction, and at least one node is provided in each of the first doping type material layer (117) and the second doping type material layer (110_3), and a node of one layer is a writing node, a node of the other layer is a reset node, and,

A third doping type material layer (116) is arranged at one end of the signal reading layer (114) along the axial direction penetrating through the gate layer, a fourth doping type material layer (110_2) is arranged at the other end of the signal reading layer (114) along the axial direction penetrating through the gate layer, the doping type of the fourth doping type material layer (110_2) is the same as that of the third doping type material layer (116), the doping type of the third doping type material layer (116) and the doping type of the fourth doping type material layer (110_2) are opposite to that of the first doping type material layer (117) and the second doping type material layer (110_3), at least one node is respectively arranged at the nodes of the third doping type material layer (116) and the fourth doping type material layer (110_2), the node of one layer is a reading node, and the node of the other opposite layer is a voltage reference node, so that signals can be read out by the signal reading layer; and is also provided with

1) applying an appropriate voltage to a selected gate layer for storing information, causing a charge-coupled layer (112) controlled by the gate layer to perform dynamic random storage of information, and causing the first doping type material layer (117) and the second doping type material layer (110_3) to cooperate, writing and resetting the information concerned,

2) Applying an appropriate voltage to a selected gate layer for readout, causing the turn-on capability of the signal reading layer controlled by the gate layer to change, causing the third doped type material layer (116) and the fourth doped type material layer (110_2) to serve as the source and drain, respectively, of the signal reading layer, reading out a voltage or current associated with the information,

3) And storing the information stored in the plurality of gate layers layer by layer in the vertical direction or in a mode of stacking the information in the horizontal direction region by region.

2. The method of claim 1, wherein:

under the condition of low storage load, proper voltage is only applied to adjacent partial grid layers or different partitions in the same grid layer to carry out information storage operation, and the grid layers which do not store information are in a low power consumption state without information access by a voltage regulation mode.

3. A method according to claim 1 or 2, characterized in that:

a coupling charge layer (111_1) and a third insulating medium layer (111_2) for storing static information are further arranged outside the first insulating medium layer (111) in the radial direction, and the first insulating medium layer (111), the coupling charge layer (111_1) and the third insulating medium layer (111_2) are combined for storing nonvolatile static information.

4. The method of any one of claims 1 or 2, wherein:

the grid electrode layers adopt a dynamic random access memory plane array structure to set a plurality of three-dimensional dynamic random access memory units, and each grid electrode layer is enabled to store in a sequential working mode along with the increase of storage load.

5. The method of any one of claims 1 or 2, wherein:

partitioning the plane where each grid layer is located, setting one three-dimensional dynamic random access memory unit in the same partition, and enabling the grid layers in different partitions in the same plane to work independently along with the increase of storage load so as to store information.

6. A three-dimensional dynamic random access memory cell comprising a substrate (110_1), and a stacked structure fabricated on said substrate, said stacked structure comprising a plurality of gate layers, and a channel hole extending through each gate layer in said stacked structure, characterized in that,

in each grid electrode layer plane, a first insulating medium layer (111), a charge coupling layer (112) for storing dynamic information, a second insulating medium layer (113) and a signal reading layer (114) are sequentially arranged along the radial direction from outside to inside taking the center of the channel hole as an end point; and, a first doping type material layer (117) is provided in one end of the charge coupling layer (112) along an axial direction penetrating the gate layer, a second doping type material layer (110_3) is provided in the other end of the charge coupling layer (112) along the axial direction penetrating the gate layer, and the doping types of the first and second doping type material layers are the same, so that charges can be transferred in the axial direction, and at least one node is provided in each of the first doping type material layer (117) and the second doping type material layer (110_3), and a node of one layer is a writing node, a node of the other layer is a reset node, and the nodes of the other layer are reset nodes for writing and resetting information, and

A third doped material layer (116) is arranged at one end of the signal reading layer (114) along the axial direction penetrating through the gate layer, a fourth doped material layer (110_2) is arranged at the other end of the signal reading layer (114) along the axial direction penetrating through the gate layer, the doping type of the fourth doped material layer (110_2) is the same as that of the third doped material layer (116), the doping type of the fourth doped material layer (110_2) is opposite to that of the first doped material layer (117) and the second doped material layer (110_3), at least one node is respectively arranged at the third doped material layer (116) and the fourth doped material layer (110_2), the node of one layer is a reading node, and the node of the other opposite layer is a voltage reference node, so that signals can be read by means of the signal reading layer.

7. The three-dimensional dynamic random access memory unit according to claim 6, wherein,

the three-dimensional dynamic random access memory unit is further provided with an insulating core layer (115) in the signal reading layer (114).

8. The three-dimensional dynamic random access memory unit according to claim 6 or 7, wherein,

A coupling charge layer (111_1) for storing static information and a third insulating medium layer (111_2) are also arranged radially outwards of the first insulating medium layer (111).

9. The three-dimensional dynamic random access memory unit according to claim 8,

the first insulating medium layer comprises: equivalent SiO ₂ A composite layer of silicon oxide and silicon nitride with a thickness of 10-20nm, or silicon oxide with a thickness of 5-12nm, or equivalent SiO ₂ Al with thickness of 1-5nm ₂ O ₃ ，HfO ₂ ，Ta ₂ O ₃ ，ZrO ₂ ，Y ₂ O ₃ Or BaTiO ₃ Is a single layer or a composite layer of (a);

the coupled charge layer includes: equivalent SiO ₂ A silicon nitride layer, a single crystal silicon layer, a polycrystalline silicon layer, an amorphous silicon layer or a germanium silicon layer with a layer thickness of 1-10nm,

the third insulating medium layer (111_2) includes: equivalent SiO ₂ A composite layer of silicon oxide and silicon nitride with a thickness of 10-20nm, or silicon oxide with a thickness of 5-12nm, or equivalent SiO ₂ Al with thickness of 1-5nm ₂ O ₃ ，HfO ₂ ，Ta ₂ O ₃ ，ZrO ₂ ，Y ₂ O ₃ Or BaTiO ₃ Is a single layer or a composite layer of (a);

the second insulating medium layer comprises: silicon oxide with thickness of 5-12nm, or equivalent SiO ₂ Al with thickness of 1-5nm ₂ O ₃ ，HfO ₂ ，Ta ₂ O ₃ ，ZrO ₂ ，Y ₂ O ₃ Or BaTiO ₃ A SiLK, FOx or MSQ single-layer or composite-layer low-K material having an equivalent oxide layer thickness of 10-30nm, and;

The charge-coupled layer, the first doping type material layer, and the second doping type material layer include: 6-40nm of monocrystalline silicon, 10-200nm of polycrystalline silicon, amorphous silicon, siGe or one of SiC layers;

the signal reading layer includes: 6-20nm of monocrystalline silicon, 5-40nm of polycrystalline silicon, siGe or SiC.

10. The three-dimensional dynamic random access memory unit according to claim 7,

the insulating core layer includes: at least one of silicon oxide, silicon nitride, siLK, FOx, MSQ, or air gap.

11. A three-dimensional dynamic random access memory according to any one of claims 6 to 9, wherein a plurality of the three-dimensional dynamic random access memory cells are provided on one semiconductor device plane or at vertically corresponding positions in adjacent semiconductor device planes, and a plurality of the three-dimensional dynamic random access memory cells are provided to cooperate.

12. The three-dimensional dynamic random access memory of claim 11, wherein the plurality of gate layers of the stacked structure comprises a read gate, a write gate, a store and transfer gate, a reset gate; the writing grid is adjacent to the writing node and is positioned at the top of the stacking structure, and the reset grid is adjacent to the reset node and is positioned at the bottom of the stacking structure; at least three continuous storage and transfer gates are a group, and gates in the same group are sequentially marked as a first phase gate, a second phase gate and an nth phase gate; the storage and transfer gates are sequentially ordered, wherein a first group of storage and transfer gates are adjacent to a first phase gate and a writing gate, and a last group of storage and transfer gates are adjacent to an nth phase gate and a reset gate; and n is a positive integer.

13. The three-dimensional dynamic random access memory of claim 12, wherein the material radially inward of the insulating core layer is provided as an insulating layer and a metallic core, said metallic core being biased as a back gate of said signal reading layer for controlling the opening and closing of said signal reading layer.

14. The three-dimensional dynamic random access memory according to claim 13, wherein the charge-coupled layer (112) is P-doped, and the first doped type material layer (117) and the second doped type material layer (110_3) are both N-doped; the signal reading layer (114) is P-type doped, a p+ type doped region is arranged at the top of the signal reading layer, a p+ type doped region is arranged at the bottom of the signal reading layer, the bottom of the signal reading layer is contacted with the fourth doped type material layer (110_2), and the fourth doped type material layer (110_2) is contacted with the substrate; the substrate is P-type epitaxial silicon, and a p+ type contact area is arranged on the substrate.

15. A method for preparing a three-dimensional dynamic random access memory, the three-dimensional dynamic random access memory comprising a plurality of three-dimensional dynamic random access memory cells arranged in a plane, the three-dimensional dynamic random access memory comprising a substrate and a stacked structure on the substrate, the stacked structure comprising a plurality of gate layers and a channel hole penetrating each gate layer in the stacked structure, and in each gate layer plane, a first insulating dielectric layer (111), a charge coupled layer (112), a second insulating dielectric layer (113) and a signal reading layer (114) are sequentially arranged along a radial direction from outside to inside with the center of the channel hole as an end point; and, in addition, the processing unit,

A first doping type material layer (117) is arranged at one end of the charge coupling layer (112) along the axial direction penetrating through the gate layer, a second doping type material layer (110_3) is arranged at the other end of the charge coupling layer (112) along the axial direction penetrating through the gate layer, and the doping types of the first doping type material layer and the second doping type material layer are the same, so that charges can be transferred in the axial direction; and at least one node is respectively arranged in the first doped material layer (117) and the second doped material layer (110_3), wherein the node of one layer is a writing node, the node of the other layer is a resetting node which is used for writing and resetting information respectively,

a third doping type material layer (116) is arranged at one end of the signal reading layer (114) along the axial direction penetrating through the gate layer, a fourth doping type material layer (110_2) is arranged at the other end of the signal reading layer (114) along the axial direction penetrating through the gate layer, and the doping type of the fourth doping type material layer (110_2) is the same as that of the third doping type material layer (116); the doping types of the third doping type material layer (116) and the fourth doping type material layer (110_2) are opposite to those of the first doping type material layer (117) and the second doping type material layer (110_3), at least one node is respectively arranged on the third doping type material layer (116) and the fourth doping type material layer (110_2), the node of one layer is a reading node, and the node of the other opposite layer is a voltage reference node, so that signals can be read by means of the signal reading layer; the preparation method is characterized by comprising the following steps:

Forming the fourth doped type material layer on the substrate;

forming the stacked structure on the substrate;

forming the channel hole penetrating through the stacked structure;

sequentially forming the first insulating medium layer, the charge coupling layer, the second insulating medium layer, the signal reading layer and the insulating core in the channel hole, wherein the charge coupling layer and the signal reading layer are in contact with the fourth doping type material layer;

dividing the stacked structure into a plurality of rows of stacked structures, forming a first doping type material layer and a third doping type material layer at the top of the channel hole, and forming a second doping type material layer on the substrate;

forming a writing word line, a resetting word line and a storage and transfer word line by making contact with each layer of grid electrode at two sides of the stacking structure, wherein the writing word line comprises writing grid electrodes in the same row, namely a first layer of grid electrode from top to bottom of the grid electrode layer; the reset word line comprises reset gates in the same row, namely a last layer of gates from top to bottom of the gate layer; the memory and transfer word line includes memory and transfer gates that are in the same row and layer, i.e., the gate layer removes all gates of the first and last layers.

16. The method of claim 15, further comprising depositing an epitaxial layer on the substrate, forming a well implant in the epitaxial layer, the epitaxial layer in contact with the charge-coupled layer and the signal read layer, prior to the step of forming the stacked structure.

17. The method of claim 15 or 16, wherein each gate electrode is formed of a metal layer deposited using an atomic layer deposition.

18. A three-dimensional dynamic random access memory array comprising at least two three-dimensional dynamic random access memory cells, the three-dimensional dynamic random access memory cells comprising a substrate, and a stacked structure fabricated on the substrate, the stacked structure comprising a plurality of gate layers, and a channel hole extending through each gate layer in the stacked structure,

it is characterized in that the method comprises the steps of,

in each grid electrode layer plane, a first insulating medium layer (111), a charge coupling layer (112), a second insulating medium layer (113) and a signal reading layer (114) are sequentially arranged along the radial direction from outside to inside taking the center of the channel hole as an end point; and, in addition, the processing unit,

a first doping type material layer (117) is arranged at one end of the charge coupling layer (112) along the axial direction penetrating through the gate layer, a second doping type material layer (110_3) is arranged at the other end of the charge coupling layer (112) along the axial direction penetrating through the gate layer, and the doping types of the first doping type material layer (117) and the second doping type material layer (110_3) are the same, so that charges can be transferred in the axial direction; and at least one node is respectively arranged in the first doped material layer (117) and the second doped material layer (110_3), wherein the node of one layer is a writing node, the node of the other layer is a resetting node which is opposite to the writing node and is respectively used for writing and resetting information, and

A third doping type material layer (116) is arranged at one end of the signal reading layer (114) along the axial direction penetrating through the gate layer, a fourth doping type material layer (110_2) is arranged at the other end of the signal reading layer (114) along the axial direction penetrating through the gate layer, the doping type of the fourth doping type material layer (110_2) is the same as that of the third doping type material layer (116), the doping type of the third doping type material layer (116) and the doping type of the fourth doping type material layer (110_2) are opposite to that of the first doping type material layer (117) and the second doping type material layer (110_3), at least one node is respectively arranged at the nodes of the third doping type material layer (116) and the fourth doping type material layer (110_2), the node of one layer is a reading node, and the node of the other opposite layer is a voltage reference node, so that signals can be read out by means of the signal reading layer;

and further characterized in that the three-dimensional dynamic random access memory array comprises:

the gate layer including a write gate (118), a reset gate (119), and multiple sets of storage and transfer gates;

in the three-dimensional dynamic random access memory array, the writing grid electrodes of the same row are connected to form a writing word line; the reset gates in the same row are connected to form a reset word line RWL; the storage and transfer grid electrodes of the same row and the same layer are connected to form a storage and transfer word line WLm_n, wherein m is a natural number and represents the group number of the storage and transfer grid electrodes; n is a positive integer representing the intra-group number of the storage and transfer gates in the same group;

The charge coupling layer (112) forms a plurality of groups of periodic potential wells under the control of the externally applied voltages of the gate layers, the potential wells have the function of storing carriers, and a single potential well is defined as an information storage node;

each information storage node in the three-dimensional dynamic random access memory array is set to store fixed weight information W during operation _ji The information storage nodes of the same layer are divided into one block so that the gate signal X is applied to the storage and transfer word line WLm_n _i When the current of the read bit line of the single block is taken as an output signal, and the value of the current is Y _j ＝∑W _ji X _i Wherein i and j are positive integers, and the completion and weight information W _ji A related multiply-add operation, wherein the read nodes of the three-dimensional dynamic random access memory cells of the same column in the three-dimensional dynamic random access memory array are connected to form the readA bit line;

and setting the three-dimensional dynamic random storage units in the three-dimensional dynamic random storage array to select storage and transfer word lines corresponding to the first-stage effective information storage nodes, after completing multiplication and addition operation, revising according to feedback, writing new weight information into the writing bit lines corresponding to the reading bit lines, completing integral displacement of all the information storage nodes, and performing multiplication and addition operation and revision flow of the next block until the weight concerned in the storage array is subjected to one-round revision, thus completing training process in storage and calculation application.

19. The three-dimensional dynamic random access memory array of claim 18, wherein the blocks are partitioned in such a way that the blocks are physically located at different layers, the blocks include a plurality of information storage nodes, the information storage nodes are located by the layer and row in which they are located, the same layer includes at least one row of information storage nodes, and the information storage nodes of different layers cannot be located in the same row.

20. The three-dimensional dynamic random access memory array of any one of claims 18 to 19, wherein two adjacent three-dimensional dynamic random access memory cells are respectively used for storing a positive weight and a negative weight, and the output signal of the three-dimensional dynamic random access memory array is the difference between the three-dimensional dynamic random access memory cell readout signal storing the positive weight and the three-dimensional dynamic random access memory cell readout signal storing the negative weight, and is used for realizing the multiplication and addition operation of the positive weight and the non-uniformity correction of the three-dimensional dynamic random access memory array.