TW202416549A - Static random access memory bit cell - Google Patents

Abstract

A static random access memory bit cell includes: a first inverter composed of a first PMOS transistor and a second NMOS transistor. The Schmitt trigger inverter composed of a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor is a second inverter. The first inverter and the second inverter are cross-coupled, a first stable node and a second stable node are formed to store data of each bit cell. And a first NMOS transistor and a sixth NMOS transistor are access devices, for controlling the transfer of data from the first stable node and the second stable node.

Description

static random access memory bit unit

The present invention relates to the field of static memory, and more particularly to a static random access memory bit cell circuit structure.

In a computer device, the memory device is used second only to the central processing unit. If the power consumption of the memory device is reduced, the life cycle of any computer device can be effectively extended. With the rapid development of devices such as smartphones, smart watches, and biomedical instruments, the battery life of portable devices has become a major issue. In digital systems, static random access memory (SRAM) has been widely used as a cache device.

SRAM is widely used because it is very fast at startup and consumes low power when idle. Compared with dynamic random access memory (DRAM) cells, SRAM cells do not need to be constantly refreshed when power is supplied to retain the stored value. As CMOS scale has been applied to the deep submicron level, there are problems such as threshold leakage, short channel effect, and gate dielectric leakage. The power consumption of this scale is mainly due to leakage power. With the existing storage logic chip architecture, a large area of the chip is occupied by SRAM formed by multiple bit cells. Therefore, reducing the power of SRAM bit cells is a difficult problem for the industry, which in turn affects the power consumption of the overall storage logic chip.

There are several known methods to reduce SRAM power consumption. One effective technique to reduce SRAM power consumption is to use only one bit line and use different voltage supplies to obtain lower power consumption. However, the single-ended bit cell design will lead to asymmetric static noise margin (SNM), which may affect the stability of the bit cell during read, write and hold operations. In addition, as the operating voltage (VDD) scales, the standard 6T SRAM bit cell (T refers to the Transistor transistor) will be disturbed by the read current due to the low operating voltage (VDD), thereby reducing the read and write stability of the SRAM. In order to cope with these challenges, various SRAM bit cell variation structures have been proposed, such as 7T, 8T, 9T, 10T and many other bit cell structures.

The object of the present invention is to provide a static random access memory bit cell, the memory bit cell is based on a tilted inverter design, specifically, using a Schmitt trigger inverter in the bit cell to enhance the read, write and retain capabilities.

In order to achieve the above-mentioned object, the present invention provides a static random access memory bit unit, which includes: a first inverter composed of a first PMOS transistor and a second NMOS transistor, and a second inverter based on a Schmitt trigger composed of a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor, wherein after the first inverter and the second inverter are cross-coupled, a first stable node and a second stable node are formed respectively to store data of each bit unit; and a first NMOS transistor and a sixth NMOS transistor are respectively access devices for controlling the transmission of data from the first stable node and the second stable node.

Further, the source of the first PMOS transistor and the second PMOS transistor and the drain of the fifth NMOS transistor are connected to a power source; the gate of the first PMOS transistor, the second NMOS transistor and the drain of the second PMOS transistor are electrically connected; the first PMOS transistor, the second NMOS transistor and the drain of the first NMOS transistor are electrically connected; the gate of the second PMOS transistor, the third NMOS transistor and the fourth NMOS transistor and the drain of the first PMOS transistor are electrically connected; the second PMOS transistor, the fourth NMOS transistor and the drain of the first PMOS transistor are electrically connected The drain of the MOS transistor, the gate of the fifth NMOS transistor and the source of the sixth NMOS transistor are electrically connected; the sources of the fourth NMOS transistor, the fifth NMOS transistor and the drain of the third NMOS transistor are electrically connected; the sources of the second NMOS transistor and the third NMOS transistor are grounded; the gates of the first NMOS transistor and the sixth NMOS transistor are both electrically connected to a word line; the source of the first NMOS transistor is electrically connected to a first bit line; the drain of the sixth NMOS transistor is electrically connected to a second bit line.

Furthermore, the drain of the first PMOS transistor is a first stable node, and the drain of the second PMOS transistor is a second stable node; the first stable node and the second stable node are interlocked nodes.

Furthermore, the Schmitt trigger inverter composed of the second PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor has a positive feedback comparator, and the fifth NMOS transistor maintains the output level of the inverter logic "1".

Furthermore, the transmission curve of the Schmitt trigger inverter composed of the second PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor is sharper, which can improve the noise tolerance of the memory bit unit.

Furthermore, during standby operation, the two access devices, the first NMOS transistor and the sixth NMOS transistor, are disconnected from the memory bit cell when the word line is not activated; if power is available, the memory bit cell will maintain its previous state.

Furthermore, when the state of the memory bit unit is a logical "1" and writing "0" is executed, the first stable node and the second stable node are respectively at a high potential and a low potential; the voltage levels of the second NMOS transistor and the second PMOS transistor are cut off, and the first PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor are in a saturated state, and the word line activates the first NMOS transistor and the sixth NMOS transistor, and the first bit line and the second bit line are driven to a logical "0".

Furthermore, when the state of the memory bit unit is a logical "0" and writing "1" is executed, the first stable node and the second stable node are respectively at a low potential and a high potential; the voltage levels of the first PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor are cut off, and the second PMOS transistor and the second NMOS transistor are in a saturated state, and the word line activates the first NMOS transistor and the sixth NMOS transistor, and the first bit line and the second bit line are driven to a logical "1".

Furthermore, when the state of the memory bit cell is a logical "0", when the memory bit cell needs to perform a read "0" operation, the first stable node and the second stable node are respectively at a low potential and a high potential; the voltage levels of the first PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor are cut off, the second NMOS transistor and the second PMOS transistor are in a saturated state, and the word line activates the first NMOS transistor and the sixth NMOS transistor.

Furthermore, when the state of the memory bit cell is a logical "1", when the memory bit cell needs to perform a read "1" operation, the first stable node and the second stable node are respectively at a high potential and a low potential; the voltage levels of the second NMOS transistor and the second PMOS transistor are cut off, and the first PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor are in a saturated state, and the word line activates the first NMOS transistor and the sixth NMOS transistor.

This invention provides a static random access memory bit cell, an 8T SRAM bit cell based on a Schmitt trigger, which has better read, write and retention capabilities. At the same time, it has the following application features: (1) low energy consumption through voltage selection, (2) fast access through the use of selective power gating technology, and (3) high noise immunity through the use of an inverter configuration based on a Schmitt trigger.

The following will describe in detail various embodiments of the present invention, and will be illustrated with accompanying drawings. In addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and any easy replacement, modification, and equivalent changes of the embodiments are included in the scope of the present invention and are subject to the scope of the patent application. In the description of the specification, many specific details are provided to enable readers to have a more complete understanding of the present invention; however, the present invention may still be implemented on the premise of omitting some or all of the specific details. In addition, well-known steps or components are not described in the details to avoid unnecessary limitations on the present invention. The same or similar components in the drawings will be represented by the same or similar symbols. It should be noted that the drawings are for illustration purposes only and do not represent the actual size or quantity of components. Some details may not be fully drawn for the sake of simplicity.

Please refer to FIG1, which is a schematic diagram of a static random access memory bit cell of the present invention. The present invention provides a static random access memory bit cell, the memory bit cell 100 comprises: a first inverter 110 composed of a first PMOS transistor MP1 and a second NMOS transistor MN2, and a second inverter 120 based on a Schmitt trigger composed of a second PMOS transistor MP2, a third NMOS transistor MN3, a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5. After the first inverter 110 and the second inverter 120 are cross-coupled, a first stable node Q and a second stable node QB are formed respectively to store data of each bit cell. The memory bit cell 100 also includes a first NMOS transistor MN1 and a sixth NMOS transistor MN6 as access devices of the first inverter 110 and the second inverter 120, respectively, for controlling the transfer of data from the first stable node Q and the second stable node QB, and controlling the transfer of data from the memory bit cell 100 to the bit lines (BL and BLB), and the detailed operation will be described later.

In practical application, the circuit composition of the memory bit cell 100 is as follows. The source of the first PMOS transistor MP1 and the second PMOS transistor MP2, and the drain of the fifth NMOS transistor MN5 are connected to the power voltage VDD; the gate of the first PMOS transistor MP1, the second NMOS transistor MN2 and the drain of the second PMOS transistor MP2 are electrically connected; the first PMOS transistor MP1, the second NMOS transistor MN2 and the drain of the first NMOS transistor MN1 are electrically connected; the gate of the second PMOS transistor MP2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 and the drain of the first PMOS transistor MP1 are electrically connected; the second PMOS transistor MP2, the fourth NMOS transistor MN3 and the fourth NMOS transistor MN4 are electrically connected. The drain of the MOS transistor MN4, the gate of the fifth NMOS transistor MN5 and the source of the sixth NMOS transistor MN6 are electrically connected; the sources of the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the drain of the third NMOS transistor MN3 are electrically connected; the sources of the second NMOS transistor MN2 and the third NMOS transistor MN3 are grounded; the gates of the first NMOS transistor MN1 and the sixth NMOS transistor MN6 are both electrically connected to a word line WL; the source of the first NMOS transistor MN1 is electrically connected to a first bit line BL; the drain of the sixth NMOS transistor MN6 is electrically connected to a second bit line BLB.

In practical application, the drain of the first PMOS transistor MP1 is used as the first stable node Q, and the drain of the second PMOS transistor MP2 is used as the second stable node QB; the first stable node Q and the second stable node QB are interlocked nodes. The memory bit unit 100 is composed of two PMOS transistors MP1-MP2 and six NMOS transistors MN1-MN6; the first inverter 110 formed by these MOS transistors is connected to a second inverter 120 based on a Schmitt trigger structure, providing two interlocked nodes, the first stable node Q and the second stable node QB, for data storage.

The memory bit cell 100 circuit design is used to store one bit of data. The memory bit cell 100 includes two stable nodes, namely a first stable node Q and a second stable node QB. The data bit stored in the memory bit cell 100 can be accessed through a word line WL and a complementary first bit line BL and a second bit line BLB.

In practical application, the Schmitt trigger inverter composed of the second PMOS transistor MP2, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 in the memory bit cell 100 can be used to change the inverter transfer function. The Schmitt trigger inverter is used as a comparator with positive feedback. The fifth NMOS transistor MN5 as a feedback transistor maintains the output level of the inverter logic "1". It increases the voltage of the node "X" to the power supply VDD voltage (Vth), which will increase the minimum input voltage required for the Schmitt trigger input to be higher than Vth. FIG2 shows the transfer curve of the Schmitt trigger inverter in this case and the traditional CMOS inverter. The transfer curve of the Schmitt trigger inverter in this case is sharper than that of the traditional CMOS inverter. Therefore, we can use the second inverter 120 based on the Schmitt trigger to improve the noise tolerance of the memory bit unit 100.

In practical applications, the sizes of transistors in the second inverter 120 using a Schmitt trigger are based on the following equations (1), (2) and (3).

The pull-up ratio (PR) and cell ratio (CR) of the first NMOS transistor MN1 and the sixth NMOS transistor MN6 as access transistors are specified as CR=PR=1 to minimize the impact of negative bias temperature instability (NBTI). The upper limit trip point V _SPH of the Schmitt trigger is set to 0.5V, slightly higher than 0.5 V _DD , so as to have better retention characteristics for the logical "1" value.

Please refer to FIG. 3 for a timing diagram of the read and write cycles of the memory bit unit 100. The operation of the static random access memory is divided into three operations: standby operation (Standby), write operation (Write "1" and Write "0") and read operation (Read "1" and Read "0").

In practical application, in the standby operation, the first NMOS transistor MN1 and the sixth NMOS transistor MN6 serve as two access devices. In this operation, when the word line WL is not activated, they are disconnected from the memory bit cell 100; if power is available, the memory bit cell 100 will maintain its previous state. In addition, since the column capacitor is charged to the power supply voltage (VDD) through the first PMOS transistor MP1, the second PMOS transistor MP2 and the fifth NMOS transistor MN5, the memory bit cell 100 consumes less energy.

In practical applications, when the state of the memory bit unit 100 is logically "1" and write "0" is executed. The data state of the memory bit cell 100 was previously recorded as a logical ‘1’, and the voltage levels on the first stable node Q and the second stable node QB were respectively a high potential (VDD) and a low potential (0V); therefore, the voltage levels of the second NMOS transistor MN2 and the second PMOS transistor MP2 were cut off, and the first PMOS transistor MP1, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 were in a saturated state, the first bit line BL and the second bit line BLB were driven to a logical “0”, and the word line WL activated the first NMOS transistor MN1 and the sixth NMOS transistor MN6, completing the write “0” operation.

In practical applications, when the state of the memory bit unit 100 is logically "0" and a write "1" is executed. The data state of the memory bit cell 100 was previously recorded as a logical ‘0’, and the voltage levels on the first stable node Q and the second stable node QB were low (0V) and high (VDD), respectively; therefore, the voltage levels of the first PMOS transistor MP1, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 were cut off, and the second PMOS transistor MP2 and the second NMOS transistor MN2 were in a saturated state, the first bit line BL and the second bit line BLB were driven to a logical “1”, and the word line WL activated the first NMOS transistor MN1 and the sixth NMOS transistor MN6, completing the write “1” operation.

In practical application, when the state of the memory bit cell 100 is logical "0", when the memory bit cell needs to perform a read "0" operation, the first stable node Q and the second stable node QB are low potential (0V) and high potential (VDD) respectively; the voltage levels of the first PMOS transistor MP1, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are cut off, the second NMOS transistor MN2 and the second PMOS transistor MP2 are in a saturated state, and the word line WL activates the first NMOS transistor MN1 and the sixth NMOS transistor MN6. Now there is no current flowing through the transistors because there is almost no voltage difference between the voltages of the second stable node QB and the second bit line BLB. On the other hand, the first NMOS transistor MN1 and the second NMOS transistor MN2 will drive the first bit line BL to discharge from the high potential (VDD) to the ground by generating a non-zero current. Then, the first bit line BL and the second bit line BLB voltages are fed to the input of the sense amplifier, and then the sense amplifier outputs a logical "0" because there is a voltage difference between the first bit line BL and the second bit line BLB voltages.

In practical application, when the state of the memory bit cell 100 is logical "1", when the memory bit cell 100 needs to perform a read "1" operation, the first stable node Q and the second stable node QB are respectively at a high potential (VDD) and a low potential (0V); the voltage levels of the second NMOS transistor MN2 and the second PMOS transistor MP2 are cut off, and the first PMOS transistor MP1, the third NMOS transistor MN2, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are in a saturated state, and the word line WL activates the first NMOS transistor MN1 and the sixth NMOS transistor MN6. Now there is no current flowing through the transistors because there is almost no voltage difference between the voltage of the first stable node Q and the first bit line BL. On the other hand, the sixth NMOS transistor MN6 and the third NMOS transistor MN3 will drive the second bit line BLB to discharge from the high potential (VDD) to the ground by generating a non-zero current. Then, the second bit line BLB and the first bit line BL voltage are fed to the input of the sense amplifier, and then the sense amplifier outputs a logic "1" because there is a voltage difference between the first bit line BL and the second bit line BLB voltage.

Please refer to FIG. 4 again, which is a schematic diagram of the memory bit cell of the present invention having a power voltage selection circuit. In practical applications, the memory bit cell 100 is recommended to have a power voltage selection circuit 200, and the power voltage selection circuit 200 uses three low Vthp PMOS transistors (MP3, MP4 and MP5) in each column of the memory bit cell 100 to reduce standby power when each column of the memory bit cell 100 is not accessed.

1) In standby operation, the power supply voltage VDD-Vthp is selected to make the word line WLB high and the word line WL low. Since no cell is accessed, power is saved by reducing the power supply voltage (VDD) to Vthp.

2) In the write/read operation, the word line WL is high, turning off the PMOS transistor MP5. The word line WLB (low) turns on the PMOS transistor MP3 to provide the normal power supply voltage VDD for the entire memory bit cell 100 columns.

This invention provides a static random access memory bit cell, an 8T SRAM bit cell based on a Schmitt trigger, which has better read, write and retention capabilities. At the same time, it has the following application features: (1) low energy consumption through voltage selection, (2) fast access through the use of selective power gating technology, and (3) high noise immunity through the use of an inverter configuration based on a Schmitt trigger.

The above disclosed embodiments are merely illustrative of the principles, features and effects of the present invention, and are not intended to limit the scope of the present invention. Any person skilled in the art may modify and alter the above embodiments without violating the spirit and scope of the present invention. Any equivalent changes and modifications made using the contents disclosed in the present invention shall still be covered by the scope of the patent application below.

100: memory bit cell 110: first inverter 120: second inverter 200: power voltage selection circuit MP1: first PMOS transistor MP2: second PMOS transistor MN1: first NMOS transistor MN2: second NMOS transistor MN3: third NMOS transistor MN4: fourth NMOS transistor MN5: fifth NMOS transistor MN6: sixth NMOS transistor Q: first stable node QB: second stable node VDD: power voltage WL, WLB: word line BL: first bit line BLB: second bit line MP3, MP4, MP5: PMOS transistors

[Figure 1] is a schematic diagram of the static random access memory bit unit of the present invention. [Figure 2] is a transfer curve of the Schmitt trigger inverter of the present invention and the conventional CMOS inverter. [Figure 3] is a timing diagram of the read and write cycle of the memory bit unit of the present invention. [Figure 4] is a schematic diagram of the memory bit unit of the present invention with a power supply voltage selection circuit.

100: memory bit unit

110: First inverter

120: Second inverter

MP1: First PMOS transistor

MP2: Second PMOS transistor

MN1: First NMOS transistor

MN2: Second NMOS transistor

MN3: The third NMOS transistor

MN4: the fourth NMOS transistor

MN5: Fifth NMOS transistor

MN6: Sixth NMOS transistor

Q: The first stable node

QB: Second stable node

VDD: power supply voltage

WL: character line

BL: First line

BLB: Second bit line

Claims (10)

A static random access memory bit unit, the memory bit unit comprises: a first inverter composed of a first PMOS transistor and a second NMOS transistor, and a second inverter based on a Schmitt trigger composed of a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor, the first inverter and the second inverter are cross-coupled to form a first stable node and a second stable node to store data of each bit unit; and a first NMOS transistor and a sixth NMOS transistor are access devices, respectively, for controlling the transmission of data from the first stable node and the second stable node. A static random access memory bit cell as described in claim 1, wherein the source of the first PMOS transistor and the second PMOS transistor, and the drain of the fifth NMOS transistor are connected to a power source; The gate of the first PMOS transistor, the second NMOS transistor, and the drain of the second PMOS transistor are electrically connected; The drain of the first PMOS transistor, the second NMOS transistor, and the first NMOS transistor are electrically connected; The gate of the second PMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the drain of the first PMOS transistor are electrically connected; The drain of the second PMOS transistor, the fourth NMOS transistor, the gate of the fifth NMOS transistor, and the source of the sixth NMOS transistor are electrically connected; The sources of the fourth NMOS transistor, the fifth NMOS transistor, and the drain of the third NMOS transistor are electrically connected; The sources of the second NMOS transistor and the third NMOS transistor are grounded; The gates of the first NMOS transistor and the sixth NMOS transistor are both electrically connected to a word line; The source of the first NMOS transistor is electrically connected to a first bit line; The drain of the sixth NMOS transistor is electrically connected to a second bit line. A static random access memory bit cell as described in claim 2, wherein the drain of the first PMOS transistor is a first stable node, and the drain of the second PMOS transistor is a second stable node; the first stable node and the second stable node are interlocked nodes. A static random access memory bit cell as described in claim 2, wherein the Schmitt trigger inverter composed of the second PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor has a positive feedback comparator, and the fifth NMOS transistor maintains the output level of the inverter logic "1". As described in claim 4, the transmission curve of the Schmitt trigger inverter composed of the second PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor is sharper, which can improve the noise tolerance of the memory bit cell. A static random access memory bit cell as described in claim 2, wherein during standby operation, the two access devices, the first NMOS transistor and the sixth NMOS transistor, are disconnected from the memory bit cell when the word line is not activated; if power is available, the memory bit cell will maintain its previous state. A static random access memory bit cell as described in claim 2, wherein, when the state of the memory bit cell is a logical "1" and a write "0" is executed, the first stable node and the second stable node are respectively at a high potential and a low potential; the voltage levels of the second NMOS transistor and the second PMOS transistor are cut off, and the first PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor are in a saturated state, and the word line activates the first NMOS transistor and the sixth NMOS transistor, and the first bit line and the second bit line are driven to a logical "0". A static random access memory bit cell as described in claim 2, wherein, when the state of the memory bit cell is a logical "0" and a write "1" is executed, the first stable node and the second stable node are respectively at a low potential and a high potential; the voltage levels of the first PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor are cut off, and the second PMOS transistor and the second NMOS transistor are in a saturated state, and the word line activates the first NMOS transistor and the sixth NMOS transistor, and the first bit line and the second bit line are driven to a logical "1". A static random access memory bit cell as described in claim 2, wherein, when the state of the memory bit cell is a logical "0", when the memory bit cell needs to perform a read "0" operation, the first stable node and the second stable node are respectively at a low potential and a high potential; the voltage levels of the first PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor are cut off, the second NMOS transistor and the second PMOS transistor are in a saturated state, and the word line activates the first NMOS transistor and the sixth NMOS transistor. A static random access memory bit cell as described in claim 2, wherein when the state of the memory bit cell is a logical "1", when the memory bit cell needs to perform a read "1" operation, the first stable node and the second stable node are respectively at a high potential and a low potential; the voltage levels of the second NMOS transistor and the second PMOS transistor are cut off, and the first PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor are in a saturated state, and the word line activates the first NMOS transistor and the sixth NMOS transistor.