TW202416486A - Electronic device and manufacturing method thereof - Google Patents

Abstract

An electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has recesses. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.

Description

Electronic device and method of manufacturing the same

The present disclosure relates to an electronic device and a manufacturing method thereof, and in particular to an electronic device and a manufacturing method thereof that can reduce stress or improve reliability.

Electronic devices or spliced electronic devices have been widely used in different fields such as communication, display, automotive, high-speed computing, power management or aviation. With the rapid development of electronic devices, electronic devices are developing towards thinner and lighter, so the reliability or quality requirements for electronic devices are higher.

According to an embodiment of the present disclosure, an electronic device includes a packaging structure, a circuit structure, a bonding structure, and an external component. The circuit structure is disposed on the packaging structure and is electrically connected to the packaging structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external component. The external component is electrically connected to the circuit structure through the bonding structure. The width of the first bonding pad is smaller than the width of the second bonding pad.

According to an embodiment of the present disclosure, a method for manufacturing an electronic device includes the following steps: providing a substrate; forming a package structure on the substrate; forming a circuit structure so that the circuit structure is electrically connected to the package structure; forming a bonding structure on the circuit structure, wherein the bonding structure includes a first bonding pad and a second bonding pad, and the first bonding pad is disposed between the second bonding pad and the circuit structure; and disposing an external element so that the bonding structure is located between the circuit structure and the external element, and the external element is electrically connected to the circuit structure. The width of the first bonding pad is smaller than the width of the second bonding pad.

In order to make the above features and advantages of the present disclosure more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The present disclosure can be understood by referring to the following detailed description and the accompanying drawings. It should be noted that, in order to make it easier for readers to understand and for the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the figure are only for illustration and are not used to limit the scope of the present disclosure.

In the following description and patent application, the words "including" and "comprising" are open-ended words and should be interpreted as "including but not limited to..."

It should be understood that when an element or film layer is referred to as being "on" or "connected to" another element or film layer, it can be directly on or directly connected to the other element or film layer, or there may be an intervening element or film layer between the two (indirect situation). Conversely, when an element is referred to as being "directly" "on" or "directly connected to" another element or film layer, there may be no intervening element or film layer between the two.

Although the terms "first", "second", "third" ... can be used to describe a variety of components, the components are not limited to these terms. These terms are only used to distinguish a single component from other components in the specification. The same terms may not be used in the patent application, but may be replaced by first, second, third ... according to the order of the components declared in the patent application. Therefore, in the following specification, the first component may be the second component in the patent application.

The directional terms mentioned in the following specification and patent application, such as: up, down, left, right, front or back, etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are used to illustrate and not to limit the present disclosure. It must be understood that the elements specifically described or illustrated can exist in various forms known to those skilled in the art. In this article, when an element is said to "overlap" with another element, it should be understood that the element partially overlaps or completely overlaps with the other element.

In this document, the terms "about", "approximately", "substantially", and "generally" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The quantities given here are approximate quantities, that is, in the absence of specific description of "about", "approximately", "substantially", and "generally", the meanings of "about", "approximately", "substantially", and "generally" can still be implied.

In some embodiments of the present disclosure, terms such as "connected", "interconnected", etc., related to bonding and connection, unless otherwise specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein other structures are disposed between the two structures. Such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed. In addition, the term "coupled" includes any direct and indirect electrical connection means.

In some embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an elliptical thickness gauge, or other suitable methods may be used to measure the area, width, thickness, or height of each component, or the distance or spacing between components. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including the component to be measured, and the area, width, thickness, or height of each component, or the distance or spacing between components may be measured.

The electronic device disclosed herein may include a display device, a light-emitting device, a solar cell, an antenna device, a semiconductor device, a packaging device, a sensing device, a vehicle device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The electronic device may, for example, include a liquid crystal light-emitting diode; the light-emitting diode may, for example, include an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED or a quantum dot light-emitting diode (QD, which may be, for example, QLED or QDLED), fluorescence, phosphor or other suitable materials and the materials may be arranged and combined in any manner, but is not limited thereto. The antenna device may, for example, be a liquid crystal antenna, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the aforementioned, but is not limited thereto. The following will illustrate the present disclosure with reference to an electronic device, but the present disclosure is not limited thereto.

It should be noted that the following embodiments may replace, reorganize, or mix features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features between embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and description to represent the same or like parts.

FIG. 1A to FIG. 1H are partial cross-sectional schematic diagrams of a method for manufacturing an electronic device according to an embodiment of the present disclosure. FIG. 2 is a top view schematic diagram of the electronic device of FIG. 1H , and FIG. 1H is a cross-sectional schematic diagram of the electronic device of FIG. 2 along the section line I-I'. For the sake of clarity and convenience of explanation, FIG. 2 omits some components of the electronic device 100 (for example, the first bonding pad 151 and the external component 160 are omitted, but not limited to this).

According to some embodiments of the present disclosure, a method for manufacturing the electronic device 100 may include the following steps:

First, please refer to FIG. 1A , provide a substrate 110, and form a package structure 120 on the substrate 110. The substrate 110 may include a hard substrate, a soft substrate, or a combination thereof. For example, the material of the substrate 110 may include glass, quartz, sapphire, ceramic, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), other suitable substrate materials, or a combination thereof, but not limited thereto. In addition, in the present embodiment, the direction Z is, for example, the normal direction of the substrate 110 or the normal direction of the electronic device 100, but not limited thereto.

In this embodiment, a release layer 130 may be selectively disposed between the substrate 110 and the package structure 120, but is not limited thereto. The release layer 130 may be removed together with the substrate 110 in a subsequent step. The material of the release layer 130 may include an adhesive material that loses its adhesive properties when heated or irradiated by ultraviolet light, but is not limited thereto. In some embodiments, a release layer may not be disposed between the substrate and the package structure.

In the present embodiment, the packaging structure 120 includes an electronic component 121 and a protective layer 122 surrounding the electronic component 121. Specifically, the electronic component 121 has an upper surface 121a, a lower surface 121b opposite to the upper surface 121a, and a side surface 121c connecting the upper surface 121a and the lower surface 121b. The upper surface 121a may be, for example, an active surface of the electronic component 121, but is not limited thereto. In addition, the electronic component 121 has a height H1. The height H1 is, for example, the height of the electronic component 121 measured along the normal direction of the substrate 110 (i.e., direction Z). In the present embodiment, the height H1 of the electronic component 121 may be, for example, greater than or equal to 200 micrometers (μm) (i.e., H1 ≥ 200 μm), but is not limited thereto. In this embodiment, the electronic element 121 may include a chip (e.g., a known good die (KGD)), a diode, an antenna unit, a sensor, a structure of a semiconductor-related process, or a structure of a semiconductor-related process disposed on a substrate (e.g., polyimide, glass, a silicon substrate, or other suitable substrate materials), but is not limited thereto.

The protective layer 122 surrounds the electronic component 121, that is, the protective layer 122 may contact at least one side surface 121c of the electronic component 121. The protective layer 122 may further contact the lower surface 121b of the electronic component 121. According to some embodiments, the protective layer 122 may contact the side surface 121c of the electronic component 121, but the protective layer 122 does not contact the lower surface 121b of the electronic component 121. The protective layer 122 has an upper surface 122a and a lower surface 122b opposite to each other. The lower surface 122b of the protective layer 122 may contact the release layer 130, but is not limited thereto. The material of the protection layer 122 may include epoxy molding compound (EMC), other suitable protection materials or a combination thereof, but is not limited thereto.

In this embodiment, the package structure 120 further includes a pad 123, a first insulating layer 124, and a second insulating layer 125. The pad 123 is disposed on the upper surface 121a of the electronic element 121, and the pad 123 can be electrically connected to the electronic element 121. The material of the pad 123 may include aluminum, titanium, copper, molybdenum, silver, gold, other suitable conductive materials, or a combination thereof, but is not limited thereto.

The first insulating layer 124 is disposed on the upper surface 121a of the electronic element 121. The first insulating layer 124 has a thickness T1. The thickness T1 is, for example, the maximum thickness of the first insulating layer 124 measured along the normal direction of the substrate 110 (i.e., direction Z). In addition, the first insulating layer 124 has a first opening 124a, and the first opening 124a can expose the pad 123. The bottom of the first opening 124a has a width W1. The first insulating layer 124 may be a single-layer structure or a multi-layer structure, and the material of the first insulating layer 124 may include silicon oxide, silicon nitride, aluminum oxide, polyimide (PI), photosensitive polyimide (Photosensitive PI), other suitable inorganic materials, other suitable organic materials or a combination thereof, but is not limited thereto.

The second insulating layer 125 is disposed on the first insulating layer 124 and in the first opening 124a. The second insulating layer 125 has a thickness T2. The thickness T2 is, for example, the maximum thickness of the second insulating layer 125 measured along the normal direction of the substrate 110 (i.e., direction Z). In the present embodiment, the thickness T1 of the first insulating layer 124 may be, for example, smaller than the thickness T2 of the second insulating layer 125, but is not limited thereto. In the present embodiment, by making the thickness of the insulating layer close to the electronic element 121 thinner, that is, the thickness T1 of the first insulating layer 124 is smaller than the thickness T2 of the second insulating layer 125, the area of the circuit fan-out can be increased, but is not limited thereto. In addition, the second insulating layer 125 has a second opening 125a. The second opening 125a may overlap the first opening 124a in the normal direction of the substrate 110. The second opening 125a may expose a portion of the pad 123. The bottom of the second opening 125a has a width W2. In the present embodiment, the width W1 of the first opening 124a may be, for example, greater than the width W2 of the second opening 125a, but is not limited thereto. Through the above design, the second insulating layer 125 may contact the side surface 124c of the first insulating layer 124 through the first opening 124a, thereby, for example, increasing the interface contact area to improve the connection strength or the reliability of the electronic device. In this embodiment, the protective layer 122 may also be disposed on the side surface of the second insulating layer 125 to surround the second insulating layer 125. The upper surface 122a of the protective layer 122 may be substantially aligned with the surface of the second insulating layer 125 away from the substrate 110, but is not limited thereto. The second insulating layer 125 may be a single-layer structure or a multi-layer structure, and the material of the second insulating layer 125 may include polyimide (PI), photosensitive polyimide (PSPI), ajinomoto build-up layer (ABF), other suitable polymer materials or a combination thereof, but is not limited thereto.

Then, referring to FIG. 1B to FIG. 1D , a circuit structure 140 is formed so that the circuit structure 140 is electrically connected to the package structure 120. The circuit structure 140 includes at least one seed layer 141, at least one conductive layer 142, and at least one third insulating layer 143 ( FIG. 1H schematically shows one seed layer 141, one conductive layer 142, and one third insulating layer 143 as an example). The conductive layer 142 and the third insulating layer 143 can be stacked alternately along the direction Z. According to some embodiments, the circuit structure 140 may include a thin film transistor (TFT), and the thin film transistor may include a gate, a source, a drain, a semiconductor layer, etc., but the present disclosure is not limited thereto. In addition, the circuit structure 140 may have a recess 145. The seed layer, the conductive layer, and the insulating layer referred to in the present disclosure may be a single layer or a multi-layer stack, wherein the seed layer and the conductive layer may include copper, titanium, molybdenum, aluminum, or other suitable materials. According to some embodiments, the circuit structure 140 is, for example, a redistribution structure, which is used to redistribute the circuit or increase the fan-out range of the circuit, and can be applied to semiconductor devices, but is not limited thereto.

Specifically, please refer to FIG. 1B , a seed layer 141 is formed on the protective layer 122, on the second insulating layer 125, and in the second opening 125a, and a mask 200 is disposed on the seed layer 141 to cover the seed layer 141. The material of the seed layer 141 may include titanium, copper, other suitable materials, or a combination thereof, but is not limited thereto. The material of the mask 200 may include photosensitive polyimide, ajinomoto laminate film, other suitable mask materials, or a combination thereof, but is not limited thereto.

Next, referring to FIG. 1C , the mask 200 is patterned to form a plurality of openings 200 a. The openings 200 a may expose at least a portion of the seed layer 141 on the second insulating layer 125 and the seed layer 141 within the second openings 125 a. The openings 200 a may overlap the second openings 125 a in the normal direction (i.e., direction Z) of the substrate 110. In the present embodiment, the method of patterning the mask 200 may include photolithography or laser direct imaging, but is not limited thereto.

Next, please refer to Figure 1D to form a conductive layer 142 in the opening 200a and in the second opening 125a. The conductive layer 142 can be electrically connected to the electronic element 121 through the seed layer 141 and the pad 123. The conductive layer 142 has a thickness T3. The thickness T3 is, for example, the thickness of the conductive layer 142 measured along the normal direction of the substrate 110 (i.e., direction Z). In the present embodiment, the thickness T3 of the conductive layer 142 may be, for example, greater than or equal to 60 microns and less than or equal to 100 microns (i.e., 60μm≤T3≤100μm), but is not limited thereto. The material of the conductive layer 142 may include copper, titanium, chromium, aluminum, gold, nickel, the aforementioned metal alloys, other suitable conductive materials, or the aforementioned combinations, but is not limited thereto. In some embodiments, the conductive layer 142 can be considered as a metal stud that can be used to electrically connect to the electronic device 121 .

Then, please refer to FIG. 1E to FIG. 1G to form a bonding structure 150 on the circuit structure 140, wherein the bonding structure 150 includes a first bonding pad 151 and a second bonding pad 152. Specifically, please refer to FIG. 1E first, remove the patterned mask 200, pattern the seed layer 141 below the mask 200 by a yellow photoetching process, configure the first bonding pad 151 on the conductive layer 142, and remove the substrate 110 and the release layer 130. The first bonding pad 151 may directly contact the conductive layer 142. The first bonding pad 151 may not overlap the side surface 121c of the electronic element 121 in the normal direction of the substrate 110 (i.e., direction Z). The bonding interface between the first bonding pad 151 and the conductive layer 142 will have an intermetallic compound (IMC) (not shown). In the present embodiment, the first bonding pad 151 may be a solder ball, but is not limited thereto. The material of the first bonding pad 151 may include tin silver (SnAg), nickel, gold, conductive glue or other suitable conductive metals, but is not limited thereto. According to some embodiments, the seed layer 141 and the conductive layer 142 may have different etching rates, so that after the seed layer 141 is patterned, the seed layer 141 will shrink to form a groove G; thereby, the third insulating layer 143 formed subsequently can be filled into the groove G to enhance the interface bonding strength. The groove G may be defined as a gap between the conductive layer 142 and the protective layer 122 , and the groove G may be surrounded by the conductive layer 142 , the seed layer 141 and the protective layer 122 .

In the present embodiment, the first bonding pad 151 has a height H2 and a width W3. The height H2 is, for example, the height of the first bonding pad 151 measured along the normal direction of the substrate 110 (i.e., direction Z). The height H2 and the width W3 of the first bonding pad 151 may be, for example, greater than or equal to 60 microns and less than or equal to 100 microns (i.e., 60μm ≤H2≤100μm, 60μm ≤W3≤100μm), but are not limited thereto. In addition, in the present embodiment, in the cross-sectional view (as shown in FIG. 1E ), the height H1 of the electronic element 121 may be, for example, greater than or equal to 3 times the height H2 of the first bonding pad 151, and less than or equal to 10 times the height H2 of the first bonding pad 151 (i.e., 3×H2≤H1≤10×H2), but are not limited thereto.

In this embodiment, the first bonding pad 151 is configured on the conductive layer 142 instead of the general method of forming a metal column on the conductive layer. In this way, the steps of setting up a mask again, patterning the mask again, and removing the patterned mask again, which are generally required when forming the metal column, can be omitted, which has the effect of simplifying the process or saving time.

In this embodiment, the first bonding pad 151 is disposed on the conductive layer 142 instead of the general method of forming a metal column on the conductive layer, thereby reducing the stress generated by the mismatch of the coefficient of thermal expansion (CTE) when the heterogeneous interface is bonded, reducing the risk of cracks at the heterogeneous interface joint, or improving the reliability of the electronic device. The heterogeneous (heterogeneous) referred to in this disclosure generally refers to film layers or components with different materials or functions.

Next, referring to FIG. 1F , a third insulating layer 143 is formed on the conductive layer 142. The third insulating layer 143 may cover the conductive layer 142 and the protective layer 122 and the second insulating layer 125 exposed by the conductive layer 142. The third insulating layer 143 may surround the first bonding pad 151 and the intermetallic compound between the first bonding pad 151 and the conductive layer 142 to increase the bonding strength between the first bonding pad 151 and the conductive layer 142. The third insulating layer 143 has an opening 143a, and the opening 143a may expose the first bonding pad 151. In this embodiment, the opening 143a of the third insulating layer 143 can be regarded as the recess 145 of the circuit structure 140. In some embodiments, when the circuit structure includes multiple insulating layers, the recess of the circuit structure can be regarded as the opening of the outermost insulating layer in the circuit structure (i.e., the insulating layer farthest from the packaging structure in the circuit structure).

In the present embodiment, the third insulating layer 143 has a thickness T4. The thickness T4 is, for example, the maximum thickness of the third insulating layer 143 measured along the stacking direction of the conductive layer 142 and the third insulating layer 143 (i.e., direction Z). In the present embodiment, the thickness T4 of the third insulating layer 143 may be, for example, greater than the thickness T2 of the second insulating layer 125, so that the rigidity (including hardness, Young's modulus, etc.) of the third insulating layer 143 may be greater than that of the second insulating layer 125, so as to have the effect of preventing scratches, chemical corrosion or moisture, but is not limited thereto.

In the present embodiment, the step of forming the third insulating layer 143 on the conductive layer 142 may, for example, include the following steps: first, forming an insulating material (not shown) on the conductive layer 142 so that the insulating material can cover the conductive layer 142 and the first bonding pad 151; then, the insulating material can be polished as needed to flatten the insulating material away from the surface of the electronic element 121; then, a hole is punched at a position of the insulating material corresponding to the first bonding pad 151 to form an opening 143a that can expose the first bonding pad 151. In this embodiment, the third insulating layer 143 may be a single-layer structure or a multi-layer structure, and the material of the third insulating layer 143 may include photosensitive polyimide, Ajinomoto laminate film, other suitable polymer materials or a combination thereof, but is not limited thereto.

Next, referring to FIG. 1G , a second bonding pad 152 is disposed in the recess 145, so that the second bonding pad 152 is disposed on the first bonding pad 151, and the first bonding pad 151 is disposed between the second bonding pad 152 and the conductive layer 142 of the circuit structure 140. The second bonding pad 152 may directly contact the first bonding pad 151. A portion of the second bonding pad 152 may be located in the recess 145, and another portion of the second bonding pad 152 may be located outside the recess 145. The contact surface CS between the second bonding pad 152 and the first bonding pad 151 may be located in the recess 145, and the contact surface CS may be lower than the third insulating layer 143 and away from the surface of the package structure 120 in the normal direction of the substrate 110 (i.e., direction Z), so as to fix the second bonding pad 152 or limit the bonding position of the second bonding pad 152, thereby improving the alignment accuracy. According to some embodiments, the contact surface between the second bonding pad 152 and the first bonding pad 151 may be located outside the recess 145. The second bonding pad 152 may not overlap the side surface 121c of the electronic element 121 in the normal direction of the substrate 110 (i.e., direction Z). In this embodiment, the second bonding pad 152 may be a solder ball, but is not limited thereto. The material of the second bonding pad 152 may include tin-silver, conductive glue or other suitable conductive metals, but is not limited thereto.

In the present embodiment, the second bonding pad 152 has a height H3 and a width W4. The height H3 and the width W4 of the second bonding pad 152 may be, for example, greater than or equal to 200 microns and less than or equal to 300 microns (i.e., 200μm ≤ H3 ≤ 300μm, 200μm ≤ W4 ≤ 300μm), but are not limited thereto. In addition, in the present embodiment, the width W3 of the first bonding pad 151 may be, for example, smaller than the width W4 of the second bonding pad 152, but are not limited thereto.

In this embodiment, although FIG. 1G schematically shows that the first bonding pad 151 is a single structure, and a single first bonding pad 151 can directly connect the second bonding pad 152 and the conductive layer 142, the present disclosure does not limit the number of structures of the first bonding pad 151. In some embodiments, the first bonding pad can also be a structure in which a plurality of sub-bonding pads (not shown) are stacked, wherein the plurality of sub-bonding pads are all surrounded by the third insulating layer 143, the sub-bonding pad closest to the conductive layer 142 among the plurality of sub-bonding pads can directly contact the conductive layer 142, and the sub-bonding pad farthest from the conductive layer 142 among the plurality of sub-bonding pads can directly contact the second bonding pad 152.

Then, referring to FIG. 1H and FIG. 2 , an external component 160 is disposed so that the bonding structure 150 is located between the circuit structure 140 and the external component 160, and the external component 160 is electrically connected to the circuit structure 140 through the bonding structure 150. The external component 160 can be electrically connected to the circuit structure 140 through the second bonding pad 152 and the first bonding pad 151 of the bonding structure 150. The external component 160 may include a printed circuit board, an integrated circuit chip, a capacitor, or a resistor, but is not limited thereto.

2, the protective layer 122 further has a side surface 122c and a side surface 122d connected to each other. The length L1 of the side surface 122c may be, for example, greater than or equal to 6 millimeters (mm) and less than or equal to 6.2 mm (i.e., 6 mm ≤ L1 ≤ 6.2 mm), and the length L2 of the side surface 122d may be, for example, greater than or equal to 6.4 mm and less than or equal to 6.6 mm (i.e., 6.4 mm ≤ L2 ≤ 6.6 mm), but are not limited thereto. The minimum distance D1 between the center of the second bonding pad 152 and the side surface 122c may be, for example, greater than or equal to 200 microns and less than or equal to 300 microns (i.e., 200μm≤D1≤300μm), and the minimum distance D2 between the center of the second bonding pad 152 and the side surface 122d may be, for example, greater than or equal to 200 microns and less than or equal to 300 microns (i.e., 200μm≤D2≤300μm), but is not limited thereto. In addition, among two adjacent second bonding pads 152, the minimum distance D3 between the center of one second bonding pad 152 and the center of the other second bonding pad 152 may be, for example, greater than or equal to 350 microns and less than or equal to 450 microns (i.e., 350μm≤D3≤450μm), but is not limited thereto. At this point, the electronic device 100 of this embodiment has been substantially manufactured.

Based on the above, the electronic device 100 of the present embodiment may include a package structure 120, a circuit structure 140, a bonding structure 150 and an external component 160. The circuit structure 140 is disposed on the package structure 120 and is electrically connected to the package structure 120. The circuit structure 140 has a recess 145. The bonding structure 150 includes a first bonding pad 151 and a second bonding pad 152. The first bonding pad 151 is disposed in the recess 145, and the second bonding pad 152 is disposed on the first bonding pad 151. The bonding structure 150 is disposed between the circuit structure 140 and the external component 160. The external component 160 is electrically connected to the circuit structure 140. The width W3 of the first bonding pad 151 is smaller than the width W4 of the second bonding pad 152.

In addition, in the manufacturing method of the electronic device 100 of the present embodiment, although a chip first manufacturing method is used as an example, the package structure 120 containing the electronic element 121 is first formed, and then the circuit structure 140 is formed on the package structure 120, but the present disclosure does not limit the arrangement order of the electronic element 121 and the circuit structure 140. In some embodiments, the manufacturing method of the electronic device can also be a redistribution layer first (RDL first) manufacturing method, in which the circuit structure is first formed, and then the electronic element is arranged on the circuit structure.

Other embodiments are listed below for illustration. It should be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

3 is a partial cross-sectional schematic diagram of another embodiment of the electronic device of the present disclosure. Please refer to FIG1H and FIG3 simultaneously, the electronic device 100a of this embodiment is similar to the electronic device 100 in FIG1H, but the difference between the two is that: in the electronic device 100a of this embodiment, the circuit structure 140a further includes a dummy metal 144.

Specifically, please refer to FIG. 3 , the alignment metal 144 can be the same film layer as the conductive layer 142. The alignment metal 144 is closer to the side surface 122c or the side surface 122d of the protective layer 122 than the conductive layer 142. The alignment metal 144 is not electrically connected to the conductive layer 142. The alignment metal 144 can be used for alignment purposes. For example, the first bonding pad 151 can be aligned and set on the conductive layer 142 according to the position of the alignment metal 144. In addition, in some embodiments, in the top view of FIG. 3 , the outline of the alignment metal 144 can be any shape as a mark for product traceability, but is not limited thereto.

FIG4 is a partial cross-sectional schematic diagram of another embodiment of the electronic device of the present disclosure. Please refer to FIG1H and FIG4 simultaneously, the electronic device 100b of this embodiment is similar to the electronic device 100 in FIG1H, but the difference between the two is that: in the electronic device 100b of this embodiment, the insulating layer and the first bonding pad can be omitted.

Specifically, referring to FIG. 4 , the conductive layer 142 in the circuit structure 140 b may be exposed, and the second bonding pad 152 in the bonding structure 150 b may be directly disposed on the conductive layer 142 . Thus, the manufacturing process of the electronic device may be simplified or the cost may be saved.

In summary, in the electronic device and the manufacturing method thereof of the disclosed embodiment, by replacing the general metal column with the first bonding pad and being disposed between the second bonding pad and the conductive layer, the steps of re-disposing a mask, re-patterning the mask, and re-removing the patterned mask, which are generally required when forming the metal column, can be omitted, which has the effect of simplifying the process or saving time. By replacing the general metal column with the first bonding pad and being disposed between the second bonding pad and the conductive layer, the stress generated by the mismatch of the thermal expansion coefficient during heterogeneous bonding can be reduced, the risk of cracks at the heterogeneous bonding can be reduced, or the reliability of the electronic device can be improved.

Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Any person having ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the definition of the attached patent application scope.

100, 100a, 100b: electronic device 110: substrate 120: package structure 121: electronic element 121a, 122a: upper surface 121b, 122b: lower surface 121c, 122c, 122d, 124c: side surface 122: protective layer 123: pad 124: first insulating layer 124a: first opening 125: second insulating layer 125a: second opening 130: release layer 140, 140a, 140b: circuit structure 141: seed layer 142: conductive layer 143: third insulating layer 143a: opening 144: alignment metal 145: depression 150, 150b: bonding structure 151: first bonding pad 152: second bonding pad 160: external component 200: mask 200a: opening CS: contact surface D1, D2, D3: minimum distance G: groove H1, H2, H3: height L1, L2: length T1, T2, T3, T4: thickness W1, W2, W3, W4: width Z: direction

Figures 1A to 1H are partial cross-sectional schematic diagrams of a method for manufacturing an electronic device according to an embodiment of the present disclosure. Figure 2 is a top view schematic diagram of the electronic device of Figure 1H. Figure 3 is a partial cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. Figure 4 is a partial cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure.

100: Electronic devices

121: Electronic components

122c, 122d: side surface

122: Protective layer

123:Pad

124: First insulation layer

125: Second insulation layer

140: Circuit structure

141: Seed layer

142: Conductive layer

143: The third insulating layer

150:Joint structure

151: First bonding pad

152: Second bonding pad

160: External components

Z: Direction

Claims (10)

An electronic device, comprising: a package structure; a circuit structure disposed on the package structure and electrically connected to the package structure, wherein the circuit structure has a recess; a bonding structure, comprising a first bonding pad and a second bonding pad, wherein the first bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad; and an external element, wherein the bonding structure is disposed between the circuit structure and the external element, and the external element is electrically connected to the circuit structure through the bonding structure, wherein the width of the first bonding pad is smaller than the width of the second bonding pad. An electronic device as described in claim 1, wherein the packaging structure includes an electronic component and a protective layer surrounding the electronic component, and in a cross-sectional view, the height of the electronic component is greater than or equal to 3 times the height of the first bonding pad and less than or equal to 10 times the height of the first bonding pad. An electronic device as described in claim 2, wherein the packaging structure further includes a first insulating layer and a second insulating layer, wherein the first insulating layer is disposed on the electronic element and has a first opening, the second insulating layer is disposed on the first insulating layer and has a second opening, and the width of the first opening is greater than the width of the second opening. An electronic device as described in claim 3, wherein the second insulating layer contacts the side surface of the first insulating layer through the first opening. An electronic device as described in claim 3, wherein a thickness of the first insulating layer is smaller than a thickness of the second insulating layer. An electronic device as described in claim 3, wherein the circuit structure has a third insulating layer, and the thickness of the third insulating layer is greater than the thickness of the second insulating layer. An electronic device as described in claim 1, wherein the second bonding pad directly contacts the first bonding pad. An electronic device as described in claim 7, wherein the contact surface between the second bonding pad and the first bonding pad is located within the recess. An electronic device as described in claim 1, wherein the packaging structure includes an electronic component, and the first bonding pad and the second bonding pad do not overlap on a side surface of the electronic component in a normal direction of the electronic device. A method for manufacturing an electronic device, comprising: providing a substrate; forming a package structure on the substrate; forming a circuit structure so that the circuit structure is electrically connected to the package structure; forming a bonding structure on the circuit structure, wherein the bonding structure comprises a first bonding pad and a second bonding pad, and the first bonding pad is disposed between the second bonding pad and the circuit structure; and disposing an external element so that the bonding structure is located between the circuit structure and the external element, and the external element is electrically connected to the circuit structure, wherein the width of the first bonding pad is smaller than the width of the second bonding pad.

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