TW202414224A - Memory device and management method thereof - Google Patents

Abstract

A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.

Description

Memory device and management method thereof

The present invention relates to a memory device and a management method thereof, and in particular to a memory device and a management method thereof capable of reducing controller load.

In today's technology, solid-state drives have been widely used in a variety of applications. In order to improve the performance and memory capacity of solid-state drives, multiple memory chips are often set in one memory channel. However, it is not easy to identify the idle or busy status of each memory chip in the memory channel.

In the prior art, the controller can read the idle or busy status of each memory chip by frequently sending status read commands. However, frequently reading the idle or busy status of each memory chip often causes controller overload and reduces the performance of the controller, affecting the overall working performance of the memory device.

The present invention provides a variety of memory devices and management methods thereof, which can effectively alleviate the overload state of the controller.

The memory device of the present invention includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The memory chips are coupled to the controller through an interrupt signal line, wherein the memory chip generates at least one local interrupt signal and performs a logic operation on the local interrupt signal to generate a common interrupt signal. The interrupt signal line is used to transmit the common interrupt signal to the controller.

Another memory device of the present invention includes a controller and at least one memory channel. The controller has at least one command queue, wherein the at least one command queue records a plurality of operation commands and a plurality of operation completion times respectively corresponding to the operation commands. The at least one memory channel is coupled to the at least one command queue, and the at least one memory channel includes at least one memory chip. The controller, based on each executed operation command, transmits a status read command to the corresponding selected memory chip at a time point according to the corresponding operation completion time.

The management method of the memory device of the present invention includes: coupling at least one memory chip to a controller through an interrupt signal line; generating at least one local interrupt signal by the memory chip; performing a logic operation on the local interrupt signal to generate a common interrupt signal; and transmitting the common interrupt signal to the controller through the interrupt signal line.

Another memory device management method of the present invention includes: setting at least one command queue to correspond to at least one memory channel, wherein the at least one memory channel includes at least one memory chip; allowing the at least one command queue to record multiple operation commands and multiple operation completion times; and setting a timer, allowing the timer to count according to each operation completion time, and thereby generate a time point for sending a status read command to the corresponding selected memory chip.

Based on the above, each memory chip of the present invention transmits its idle or busy status through a common interrupt signal. When the common interrupt signal shows that at least one memory chip is idle, the controller inquires about the idle or busy status of each memory chip. In this way, the controller can effectively reduce the overload phenomenon caused by repeatedly inquiring about the idle or busy status of multiple memory chips, thereby improving the working efficiency of the memory device.

Please refer to FIG. 1A, which shows a schematic diagram of a memory device of an embodiment of the present invention. The memory device 100 includes a controller 110 and a memory channel MC formed by a plurality of memory chips 121-12N. The memory chips 121-12N are commonly coupled to an interrupt signal line IRW, and are coupled to the controller 110 through the interrupt signal line IRW. The memory chips 121-12N also share a data bus DBUS to communicate with the controller 110. The controller 110 also transmits chip select signals CS1-CSN to the memory chips 121-12N respectively through a plurality of chip select signal lines.

In this embodiment, the memory chips 121-12N can generate a plurality of regional interrupt signals respectively. The memory chips 121-12N can respectively transmit the regional interrupt signals to the interrupt signal line IRW, and generate a common interrupt signal IR by performing a logic operation on the regional interrupt signals. The memory chips 121-12N can be coupled to the interrupt signal line IRW by wired AND, so the memory chips 121-12N can generate a common interrupt signal IR by performing and operating on the regional interrupt signals, and transmit the common interrupt signal IR to the controller 110.

In this embodiment, the common interrupt signal IR can be used to display the busy and idle states of the memory chips 121-12N. In detail, each regional interrupt signal generated by each memory chip 121-12N is used to indicate the completion status of the operation command of the corresponding memory chip 121-12N. Among them, taking the memory chip 121 as an example, when the memory chip 121 receives an operation command (such as a data access command), the memory chip 121 can enter a busy state to perform a data access operation. At this time, the memory chip 121 can make the generated regional interrupt signal logical 1. Furthermore, when the memory chip 121 is in an idle state where the operation command has been completed, the memory chip 121 can pull down the generated regional interrupt signal to logic 0. Since the common interrupt signal IR is the result of the logical operation of all the regional interrupt signals, the common interrupt signal IR can be correspondingly pulled down to logic 0. In contrast, if the memory chip 121 is in a busy state where the operation command has not been completed, the memory chip 121 can maintain the generated regional interrupt signal to logic 1.

That is, in this embodiment, when the common interrupt signal IR is pulled down to logic 0, the controller 110 can know that at least one of the memory chips 121-12N has completed the operation command to be executed and is in an idle state.

On the other hand, when the controller 110 detects that the common interrupt signal IR is pulled down to logic 0, the controller 110 can perform a status query operation on the memory chips 121-12N. By enabling one of the chip selection signals CS1-CSN, the controller 110 can select one of the memory chips 121-12N as the selected memory chip (for example, the memory chip 121), and transmit a status read command to the memory chip 121 via the data bus DBUS to read the idle or busy state of the memory chip 121.

When the memory chip 121 receives the status read command, if the memory chip 121 is in an idle state having completed the operation command, the idle information can be transmitted to the controller 110 via the data bus DBUS; on the contrary, if the memory chip 121 is in a busy state having not completed the operation command, the busy information can be transmitted to the controller 110 via the data bus DBUS. In addition, if the memory chip 121 is in an idle state having completed the operation command, the local interrupt signal generated by it can be cleared according to the received status read command, and the local interrupt signal generated by it can be set to logic 1.

In this embodiment, the controller 110 may sequentially set each memory chip 121-12N as a selected memory chip, and sequentially send status read commands to the memory chips 121-12N, thereby inquiring the idle or busy status of all the memory chips 121-12N.

In addition, regarding the time point of sending the status read command, the controller 110 can estimate the time required for the selected memory chip to complete the operation command, and send the status read command to the selected memory chip based on the time when the operation command is sent to the selected memory chip. In this way, the controller 110 can reduce the number of inquiries to the idle or busy status of the memory chips 121~12N, saving power consumption.

When the local interrupt signals generated by all memory chips 121-12N are cleared to logic 1, the common interrupt signal IR can be restored to logic 1.

In this embodiment, the number of memory channels MC can be one or more, without fixed restrictions. The memory chips 121-12N included in the memory channel MC can be single-bit (SLC) or multi-bit (MLC) NAND Flash memory chips, NAND Flash memory, random access memory, and any other memory chips known in the art.

Please refer to FIG. 1B , which shows a schematic diagram of a memory device of another embodiment of the present invention. Unlike the memory device 100 of FIG. 1A , the memory channel MC in the memory device 100 of FIG. 1B can be formed by a single memory chip 121. The memory channel MC is coupled to the controller 110 through the interrupt signal line IRW, the data bus DBUS, and the chip selection signal line. The memory chip 121 receives the chip selection signal CS1. The memory chip 121 is coupled to the interrupt signal line IRW, transmits the regional interrupt signal to the interrupt signal line IRW, and generates a common interrupt signal IR by performing a logic operation on the regional interrupt signal and logic 1.

Please refer to FIG. 2A to FIG. 2C below, which illustrate the operation waveforms of the memory device of the embodiment of the present invention. Please refer to FIG. 1 simultaneously. In FIG. 2A, the controller 110 provides an operation command RDCMD, which is a read command, to the selected memory chip via the data bus DBUS. After receiving the operation command RDCMD, the selected memory chip pulls down its internal ready signal RDY to logic 0, and after a time delay tR, after completing the operation command RDCMD, pulls up the internal ready signal RDY to logic 1. Based on the completion of the operation command RDCMD, the selected memory chip can pull down the regional interrupt signal generated by it, and further pull down the common interrupt signal IR to logic 0.

In FIG2B , under the condition that the common interrupt signal IR is logic 0, when the time cycle CT is the operation command transmission cycle CMDIN, the controller 110 transmits the status read command RSTA to the selected memory chip through the data bus DBUS. If the selected memory chip is in an idle state having completed the operation command at this time, the selected memory chip can transmit idle information STA in an idle state to the controller 110 through the data bus DBUS when the time cycle CT is the data output cycle DOUT. In addition, the selected memory chip can respond to the status read command RSTA to clear the generated regional interrupt signal to logic 1, and further make the common interrupt signal transition to logic 1.

In FIG2C , under the condition that the common interrupt signal IR is logic 1, when the time cycle CT is the operation command transmission cycle CMDIN, the controller 110 transmits the status read command RSTA to the selected memory chip through the data bus DBUS. If the selected memory chip is in a busy state of not completing the operation command at this time, the selected memory chip can transmit busy information STB in a busy state to the controller 110 through the data bus DBUS when the time cycle CT is the data output cycle DOUT. At this time, the common interrupt signal can be maintained as logic 1.

Please refer to FIG. 3 below, which is a flow chart showing the recording action of the idle or busy state of the memory chip of the memory device of the embodiment of the present invention. Please refer to FIG. 1 in combination. In step S310, the controller 110 determines whether there is a new operation command to be executed. If the controller 110 determines that there is no new operation command to be executed, this process can be terminated. If the controller 110 determines that there is a new operation command to be executed, step S320 can be executed. In step S320, the controller 110 converts the logical address corresponding to the operation command to obtain the physical address of the memory chip that executes the operation command. Next, in step S330, the controller 110 may determine whether the memory chip corresponding to the operation command is in an idle state. If the memory chip is not in an idle state, this process may be terminated. Conversely, if the memory chip is in an idle state, step S340 may be executed.

In step S340, the controller 110 sends an operation command to the corresponding memory chip. And in step S350, the controller 110 may record that the memory chip is busy and terminate the process.

Please refer to FIG. 4 below, which is a flowchart of the triggering action of the interrupt event of the memory device of the embodiment of the present invention. Please also refer to FIG. 1. In step S410, the controller 110 can determine whether the interrupt signal IR is at a falling edge. If the determination result is yes, step S430 can be executed to trigger the interrupt event. Among them, when the interrupt signal IR has a falling edge for the first time (transitioning from logic 1 to logic 0), the controller 110 can directly execute step S430 to trigger the interrupt event.

After the interrupt event is triggered, the controller 110 may issue a status read command to the memory chips 121-12N.

In addition, if the determination result in step S410 is no, the controller 110 can determine whether the interrupt signal IR remains at logic 0 after the memory chips 121~12N receive the status read command for a predetermined time. If the interrupt signal IR still remains at logic 0, the controller 110 can directly execute step S430 to trigger an interrupt event. If the interrupt signal IR does not remain at logic 0, this process can be terminated.

Please continue to refer to FIG. 5, which is a flowchart of the interrupt event of the embodiment of FIG. 4 of the present invention. After step S430 is executed to trigger the interrupt event, the step flow of FIG. 5 can be entered. Among them, the controller 110 determines whether the interrupt event is triggered in step S510, and if so, enters step S520, otherwise, terminates this process. Then, the controller 110 can select one of the memory chips 121~12N as the selected memory chip, and determine whether the selected memory chip is busy (step S520). If the result of the determination is yes, the controller 110 may send a status read command to the selected memory chip (step S530), and in step S540, update the idle or busy status of the memory chip. By sending the status read command to the selected memory chip, the regional interrupt signal sent by the selected memory chip may be cleared, and the controller 110 may record the idle status of the selected memory chip in a search information.

If the result of the controller 110's determination in step S520 is no, step S560 may be executed.

In this embodiment, the search information can be recorded using a register in the controller 110, or using a built-in or external memory, without any limitation.

In step S550, the controller 110 may execute the operation strategy of the memory chips 121-12N according to the latest status information.

In step S560, the controller 110 may determine whether the selected memory chip is the last memory chip, and if so, may execute step S570. If the determination result is no, the controller 110 may select the next memory chip and re-execute step S520.

In step S570, a preset time may be set, and a timer may be set to check whether the common interrupt signal is still logic 0 at a time point after the preset time.

Please refer to Figure 6 below, which shows a block diagram of a memory device of another embodiment of the present invention. The memory device 600 can be a solid state hard disk and is coupled to the host end 601. The memory device 600 includes a controller 610 and memory channels MC1 and MC2. The memory channel MC1 has memory chips 6211~621N, and the memory chips 6211~621N generate a common interrupt signal IR1 through a common interrupt signal line. The controller 610 performs data transmission operations with the memory chips 6211~621N through the data bus DBUS1, and the controller 610 selects one of the memory chips 6211~621N for operation through the chip selection signal CS11~CS1N. The memory channel MC2 has memory chips 6221-622M, and the memory chips 6221-622M generate a common interrupt signal IR2 through another common interrupt signal line. The controller 610 performs data transmission with the memory chips 6221-622M through the data bus DBUS2, and the controller 610 selects one of the memory chips 6221-622M for operation through the chip selection signals CS21-CS2M. The number of memory chips 6211-621N in the memory channel MC1 and the number of memory chips 6221-622M in the memory channel MC2 may be the same or different.

In this embodiment, the controller 610 includes a plurality of processors 611, interface circuits 612 and 613, a timer 614, a flash translation layer (FTL) 615, and a static memory 616. The processor 611 is coupled to the interface circuit 612, and is coupled to the host end 601 through the interface circuit 612. The processor 611 is also coupled to the interface circuit 613, and is coupled to the memory channels MC1 and MC2 through the interface circuit 613. The processor 611 is used to send a plurality of operation commands to the memory channels MC1 and MC2 according to the requirements of the host end 601, and perform data access operations on the memory chips 6211~622M in the memory channels MC1 and MC2.

The controller 610 may be used to execute the operation flow of the aforementioned embodiments, and thereby record the idle or busy status of the memory chips 6211 - 622M in the memory channels MC1 and MC2.

In addition, the timer 614 is coupled to the processor 611. The timer 614 can count according to a preset time, and at a time point after the preset time, check whether the common interrupt signal is still logic 0.

Incidentally, the processor 611 in the controller 610 may be further coupled to an external dynamic memory 630, and use the dynamic memory 630 to access the temporary data.

Regarding the operation mode of the memory device, please refer to the waveform diagram of the memory chip management method of the memory device shown in FIG7. Please refer to FIG6 simultaneously and take the memory chips 6211 and 6212 in the memory channel MC1 as an example. The memory chips 6211 and 6212 generate the regional interrupt signals LIR1 and LIR2 respectively. The common interrupt signal IR1 is the result of the logical operation of the regional interrupt signals LIR1 and LIR2.

In FIG. 7 , at time points 0 and 1, the controller 610 sequentially sends the operation command CMD0 to the memory chip 6211 and CMD1 to the memory chip 6212 via the data bus DBUS1. At time point 3, the memory chip 6211 has completed the operation command CMD0 and causes the generated local interrupt signal LIR1 to be pulled down to logic 0. At this time, the common interrupt signal IR1 is correspondingly pulled down to logic 0 and generates a falling edge.

Next, at time point 4, the memory chip 6212 has completed the operation command CMD1 and causes the generated local interrupt signal LIR2 to be pulled low to logic 0. At the same time, the controller 610 sends a status read command RSTA0 to the memory chip 6211 via the data bus DBUS1.

Since at time point 4, the memory chip 6211 has completed the operation command CMD0 and is in an idle state, the memory chip 6211 corresponds to the status read command RSTA0 to clear the generated local interrupt signal LIR1 to logic 1 at time point 5. On the other hand, at time point 5, based on the memory chip 6211 being in an idle state, the controller 610 can send the operation command CMD0 to the memory chip 6211 via the data bus DBUS1.

At time point 6, the controller 610 sends a status read command RSTA1 to the memory chip 6212 via the data bus DBUS1. At time point 7, the memory chip 6212 responds to the status read command RSTA1 to clear the generated regional interrupt signal LIR2 to logic 1. The common interrupt signal IR1 also transitions to logic 1 at time point 7. It is worth mentioning that the controller 610 can check whether the common interrupt signal IR1 is logic 1 at time point 9 after a preset time TD (e.g., equal to 2) based on the status read command RSTA1 sent at time point 6.

At time point 7, the controller 610 sends the operation command CMD1 to the memory chip 6212. After time points 8 to 10, at time point 11, based on the memory chip 6211 having completed the operation command CMD1, the local interrupt signal LIR2 and the common interrupt signal IR1 are synchronously changed to logic 0 at time point 11.

Next, at time points 12 and 13, the controller 610 sequentially sends status read commands RSTA0 and RSTA1 to the memory chips 6211 and 6212. At time point 14, since the memory chip 6211 has completed the operation command CMD0 received at time point 5, the memory chip 6211 pulls down the generated local interrupt signal LIR1.

Here, the controller 610 can check whether the common interrupt signal IR1 is logic 1 at a time point 16 after a preset time TD based on the status read command RSTA1 sent at the time point 13. Since the common interrupt signal IR1 is not logic 1 at this time, the controller 610 can send the status read command RSTA0 to the memory chip 6211 at a time point 17 after the time point 16, and clear the local interrupt signal LIR1 generated by the memory chip 6211 to logic 1 at the time point 18, and correspondingly make the common interrupt signal IR1 to logic 1.

Please refer to FIG. 8 below, which shows a block diagram of a memory device of another embodiment of the present invention. The memory device 800 may be a solid state hard disk and is coupled to a host terminal 801. The memory device 800 includes a controller 810 and memory channels MC1 and MC2. The memory channel MC1 has memory chips 8211~821N. The memory channel MC2 has memory chips 8221~822M. The number of memory chips 8211~821N in the memory channel MC1 may be the same as or different from the number of memory chips 8221~822M in the memory channel MC2.

In this embodiment, the controller 810 includes a plurality of processors 811, interface circuits 812, 813, a timer 814, a flash translation layer (FTL) 815, a static memory 816, and command queues 817, 818. Different from the embodiment of FIG. 6, the memory device 800 of this embodiment is provided with command queues 817, 818. The command queues 817, 818 can be implemented by a first in first out (FIFO) circuit. The command queues 817, 818 are coupled between the processor 811 and the interface circuit 812, and correspond to the memory channels MC1 and MC2, respectively.

In this embodiment, the processor 811 writes each operation command and the operation completion time of the operation command into the command queue 817 or 818. Each operation command can be a read, write or erase operation command. The command queue 817 or 818 can send the operation command and the operation completion time to the memory chip 8211~821N or the memory chip 8221~822N through the interface circuit 812. In addition, the interface circuit 812 writes the operation completion time of the operation command into the timer 814. After completing the timing action of the operation completion time, the timer 814 notifies the interface circuit 812 and causes the interface circuit 812 to send a status read command to read the operation status of the memory chip 8211~821N or the memory chip 8221~822N. And after the operation command has been completed, the processor 811 can trigger an interrupt event.

Please refer to FIG. 9 below, which shows the action flow chart of the memory device of the embodiment of FIG. 8 of the present invention. In step S910, the controller can determine whether there is a task in the command queue (whether there is a storage operation command). If there is no task in the command queue, this process can be terminated. If there is a task in the command queue, the controller can execute step S920 to determine whether the memory chip corresponding to the operation command in the command queue is idle. If the corresponding memory chip is idle, step S930 can be executed; if the corresponding memory chip is busy, step S950 can be executed.

In step S930, the controller can read out the operation completion time of the corresponding operation command in the command queue and set it in the timer. In step S940, the controller can transmit the operation command to the corresponding memory chip.

In step S950, the controller determines whether the timer has completed the counting action, and after the timer has completed the counting action, determines whether the data bus is idle. When the data bus is idle, a status read command is transmitted to the corresponding memory chip.

In step S980, the controller checks the status result of the corresponding memory chip through the status read command to see whether it has completed the operation command. When the operation command has not been completed, step S970 is re-executed, and when the operation command has been completed, step S990 is executed. The controller can trigger an interrupt event in step S990.

After the interrupt event is triggered, the controller can determine whether all the operation commands received by the command queue have been completed, and can execute relevant access strategies according to the status information of the memory chip.

Please refer to FIG. 10, which is a flow chart of a memory device management method according to an embodiment of the present invention. In step S1010, at least one memory chip is coupled to a controller through an interrupt signal line. In step S1020, the memory chip generates at least one regional interrupt signal. In step S1030, the memory chip can perform a logic operation on the regional interrupt signal to generate a common interrupt signal through a wired AND method. In step S1040, the common interrupt signal is transmitted to the controller through the interrupt signal line.

The implementation details of the above steps have been described in detail in the aforementioned embodiments, and will not be elaborated here.

Please refer to FIG. 11, which is a flow chart of a memory device management method according to an embodiment of the present invention. In step S1110, at least one command queue is set to correspond to at least one memory channel, wherein the memory channel includes one or more memory chips. In step S1120, at least one command queue is made to record multiple operation commands and multiple operation completion times. In step S1130, a timer is set, and the timer is made to count according to the completion time of each operation, and thereby generate a time point for transmitting a status read command to the corresponding selected memory chip.

The implementation details of the above steps have been described in detail in the aforementioned embodiments, and will not be elaborated here.

In summary, in the embodiment of the present invention, each memory chip can pull down the interrupt signal by pulling down the generated regional interrupt signal. The controller can query the idle or busy state of each memory chip in response to the pulling down of the interrupt signal. In this way, the memory device can query the idle or busy state of each memory chip at an appropriate time point, which can effectively save power consumption and improve the working performance of the memory device.

0~18: Time point 100, 600, 800: Memory device 110, 610, 810: Controller 121~12N, 6211~621N, 6221~622M, 8211~821N, 8221~822M: Memory chip 611, 811: Processor 612, 613, 812, 812: Interface circuit 614, 814: Timer 615, 815: Flash conversion layer 616, 816: Static memory 817, 818: Command queue CMDIN: Operation command transmission cycle CS1~CSN: Chip selection signal CT: Time cycle DBUS, DBUS1, DBUS2: data bus DOUT: data output loop IR: common interrupt signal IRW: interrupt signal line LIR1, LIR2: regional interrupt signal MC, MC1, MC2: memory channel RDCMD, CMD0, CMD1: operation command RDY: ready signal RSTA, RSTA0, RSTA1: status read command S310~S350, S410~S430, S510~S560, S910~S990, S1010~S1040, S1110~S1130: step TD: default time

FIG. 1A is a schematic diagram of a memory device of one embodiment of the present invention. FIG. 1B is a schematic diagram of a memory device of another embodiment of the present invention. FIG. 2A to FIG. 2C are waveform diagrams of the operation of the memory device of the embodiment of the present invention. FIG. 3 is a flow chart of the recording operation of the idle or busy state of the memory chip of the memory device of the embodiment of the present invention. FIG. 4 is a flow chart of the triggering operation of the interrupt event of the memory device of the embodiment of the present invention. FIG. 5 is a flow chart of the operation of the interrupt event of the embodiment of FIG. 4 of the present invention. FIG. 6 is a block diagram of the memory device of another embodiment of the present invention. FIG. 7 is a waveform diagram of the management method of the memory chip of the memory device. FIG8 is a block diagram of a memory device of another embodiment of the present invention. FIG9 is a flow chart of the operation of the memory device of the embodiment of FIG8 of the present invention. FIG10 and FIG11 are flow charts of the management method of the memory device of different embodiments of the present invention, respectively.

100: Memory device

110: Controller

121~12N: memory chip

MC: Memory Channel

IRW: Interrupt signal line

DBUS: Data Bus

CS1~CSN: chip selection signal

IR: common interrupt signal

Claims (20)

A memory device comprises: a controller; and at least one memory channel, comprising: at least one memory chip, which is commonly coupled to the controller through an interrupt signal line, wherein the at least one memory chip generates at least one regional interrupt signal respectively, and the at least one regional interrupt signal performs a logic operation to generate a common interrupt signal, and the interrupt signal line is used to transmit the common interrupt signal to the controller. A memory device as described in claim 1, wherein each of the at least one local interrupt signals is used to indicate a completion status of an operation command of the corresponding at least one memory chip. A memory device as described in claim 2, wherein the logical operation is a logical and operation, when each of the at least one memory chips has completed an operation command and is in an idle state, the corresponding each of the at least one regional interrupt signals is a logical 0, and when each of the at least one memory chips has not completed an operation command and is in a busy state, the corresponding each of the at least one regional interrupt signals is a logical 1. A memory device as described in claim 3, wherein when the at least one memory chip is in the busy state, the common interrupt signal is logic 1. A memory device as described in claim 3, wherein when at least one of the at least one memory chip is in the idle state, the common interrupt signal is logic 0. A memory device as described in claim 1, wherein the controller is further coupled to the at least one memory chip via a data bus, and sends a plurality of chip selection signals to the at least one memory chip via at least one chip selection signal line. A memory device as described in claim 6, wherein when the common interrupt signal changes to a set logic value, the controller sends a status read command to a selected memory chip via the data bus. A memory device as described in claim 7, wherein when the selected memory chip is in an idle state, the selected memory chip responds to the state read command to restore idle information and clear the corresponding interrupt signals of each region. A memory device as described in claim 7, wherein when the selected memory chip is in a busy state, the selected memory chip responds to the state read command to return a busy message and maintains the corresponding interrupt signals of each region unchanged. A memory device as described in claim 1, wherein the controller further records the idle or busy status of each of the at least one memory chips. A memory device comprises: a controller having at least one command queue, wherein the at least one command queue records a plurality of operation commands and a plurality of operation completion times respectively corresponding to the operation commands; and at least one memory chip, forming at least one memory channel corresponding to the at least one command queue, wherein the controller, based on each of the operation commands being executed, transmits a status read command to a corresponding selected memory chip at a time point according to the corresponding completion time of each of the operation commands. The memory device as described in claim 11, wherein the controller further comprises: A timer, which counts according to the completion time of each operation and generates the time point for transmitting the status read command to the corresponding selected memory chip. A method for managing a memory device, comprising: enabling at least one memory chip to be commonly coupled to a controller via an interrupt signal line; enabling the at least one memory chip to generate at least one regional interrupt signal; enabling the at least one regional interrupt signal to perform a logic operation to generate a common interrupt signal; and transmitting the common interrupt signal to the controller via the interrupt signal line. A memory device management method as described in claim 13, wherein each of the at least one regional interrupt signals is used to indicate the completion status of the corresponding operation command of each of the at least one memory chips. A memory device management method as described in claim 13, wherein the logic operation is a logic and operation, when each of the at least one memory chips has completed the operation command and is in an idle state, the corresponding at least one regional interrupt signal is made to be logic 0; and when each of the at least one memory chips has not completed the operation command and is in a busy state, the corresponding at least one regional interrupt signal is made to be logic 1 A memory device management method as described in claim 15, wherein when the at least one memory chip is in the busy state, the common interrupt signal is logical 1, and when at least one of the at least one memory chip is in the idle state, the common interrupt signal is logical 0. The memory device management method as described in claim 13 further includes: When the common interrupt signal changes to a set logic value, a status read command is transmitted to a selected memory chip through a data bus in combination with a corresponding chip selection signal according to an operation completion time. The memory device management method as described in claim 17 further includes: When the selected memory chip is in an idle state, the selected memory chip responds to the state read command to restore an idle information and clear the corresponding at least one region interrupt signal. As described in claim 17, the memory device management method, when the selected memory chip is in a busy state, enables the selected memory chip to respond to the state read command to reply with a busy message and maintain the corresponding at least one regional interrupt signal unchanged. A method for managing a memory device, comprising: Setting at least one command queue to correspond to at least one memory channel, wherein the at least one memory channel includes at least one memory chip; Making the at least one command queue record a plurality of operation commands and a plurality of operation completion times; and Setting a timer, making the timer count according to each of the operation completion times, and thereby generating a time point for transmitting a status read command to a corresponding selected memory chip.

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