TW202410134A - Laminated structure, semiconductor device and method for producing the same - Google Patents

Abstract

An objective of this invention is to provide a laminated structure having excellent crystallinity, a semiconductor device, and a producing method capable of obtaining these in an industrially advantageous manner. This invention provides a method for producing semiconductor devices including Schottky barrier diode (SBD), Junction barrier Schottky diode (JBS), Merged-PiN Schottky barrier diode(MPS), metal semiconductor field effect transistors (MESFETs), high electron mobility transistors (HEMTs), metal oxide semiconductor field effect transistors (MOSFETs), static induction transistor (SIT), Junction Field Effect Transistor (JFET), an insulated gate bipolar transistor (IGBT), light emitting diode (LED) or a combination thereof by laminating a buffer layer containing a crystal film containing Hf and/or Zr on a semiconductor crystal substrate and having cubic structure; and laminating an epitaxial film made of a compound semiconductor directly or via another layer on the buffer layer.

Description

Multilayer structure, semiconductor device and manufacturing method thereof

The present invention relates to a multilayer structure, a semiconductor device and a method for manufacturing the same.

In the past, heteroepitaxial growth processes that grow gallium nitride crystals on sapphire substrates have been studied. However, due to differences in thermal expansion rates and lattice mismatch, it is not easy to form high-quality epitaxial films. There are problems with the complexity and high/precision of the epitaxial film formation steps, and this also leads to increased costs.

In recent years, epitaxial substrates whose thermal expansion coefficient (CTE) has been adjusted to be substantially suitable for the epitaxial layer have been studied (for example, Patent Document 1). However, the manufacturing steps of the above-mentioned substrate for epitaxy are complicated and highly refined, and cannot fundamentally solve the problem. Moreover, after peeling off the substrate for epitaxy, there is a need to perform surface treatment and then polish. Problems such as connecting electrodes must be made. Therefore, measures are expected to make it possible to easily form an epitaxial film of a compound semiconductor such as gallium nitride and to easily manufacture a semiconductor device.

[Prior Art Literature]

[Patent Document]

Patent Document 1: Japanese Patent Application Publication No. 2020-161833

The purpose of the present invention is to provide a multilayer structure with excellent crystallinity, a semiconductor device with excellent semiconductor characteristics, and a method for manufacturing the multilayer structure with excellent crystallinity and a semiconductor device with excellent semiconductor characteristics that are industrially advantageous.

As a result of intensive research in order to achieve the above object, the inventors of the present invention found that in order to laminate a buffer layer on a semiconductor crystal substrate, a compound semiconductor composed of a compound semiconductor must be layered directly on the buffer layer or via another layer. In the case of a crystal film, when a crystal film of Hf and/or Zr nitride or oxynitride having a cubic crystal structure is used as the buffer layer, a good quality conductive crystal film can be easily obtained. The conductive crystal film can be used As a buffer layer, an epitaxial film composed of a high-quality compound semiconductor can be easily formed. Furthermore, it was found that the formed conductive crystal film can also be used in an electrode layer or the like based on the above-mentioned multilayer structure, and the conductive crystal film can be easily used. Awareness of various phenomena such as manufacturing semiconductor devices has led to the realization that the above-mentioned multilayer structure is a multilayer structure that can solve the problems of the past.

Furthermore, after obtaining the above-mentioned knowledge, the inventors of the present invention further repeatedly studied and finally completed the present invention.

That is, the present invention is related to the following invention.

[1] A multilayer structure having an epitaxial film composed of a compound semiconductor deposited on a buffer layer directly or via other layers, wherein the buffer layer comprises a crystalline film containing Hf and/or Zr and having a cubic crystal structure.

[2] The multilayer structure as described in [1] above, wherein the crystalline film is a conductive crystalline film containing a nitride or nitride oxide of Hf and/or Zr.

[3] The laminated structure according to [1] or [2] above, wherein the epitaxial film has a cubic crystal structure.

[4] The laminated structure according to any one of [1] to [3] above, wherein the compound semiconductor is a wide bandgap semiconductor.

[5] The laminated structure according to any one of [1] to [4] above, wherein the compound semiconductor is a nitride semiconductor.

[6] A multilayer structure as described in any one of [1] to [5] above, wherein the buffer layer is stacked on the semiconductor single crystal substrate directly or via other layers.

[7] The laminated structure according to the above [6], wherein the buffer layer is laminated on the semiconductor single crystal substrate by crystal growth.

[8] The laminated structure according to the above [6] or [7], wherein the semiconductor single crystal substrate is a Si substrate.

[9] A semiconductor device comprising a multilayer structure, wherein the multilayer structure is a multilayer structure as described in any one of [1] to [8] above.

[10] The semiconductor device according to the above [9], wherein the semiconductor device is a vertical device.

[11] A semiconductor device as described in [9] or [10] above, wherein the semiconductor device is a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a merged-PiN Schottky barrier diode (MPS), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), an electrostatic induction transistor (SIT), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), a light emitting diode (LED), or a combination thereof.

[12] A method for manufacturing a multilayer structure, comprising laminating a buffer layer on a semiconductor crystal substrate, and laminating an epitaxial film composed of a compound semiconductor on the buffer layer directly or via other layers, wherein the buffer layer comprises a crystalline film, and the crystalline film contains Hf and/or Zr and has a cubic crystal structure.

[13] The method for manufacturing a multilayer structure as described in [12] above, wherein the semiconductor single crystal substrate is a Si substrate and the compound semiconductor is a nitride semiconductor.

[14] A method of manufacturing a semiconductor device using a laminated structure, and the laminated structure system is the laminated structure described in any one of [1] to [8] above.

[15] A system comprising a semiconductor device, wherein the semiconductor device is a semiconductor device as described in any one of [9] to [11] above.

The multilayer structure and semiconductor device of the present invention have excellent crystallinity. According to the manufacturing method of the present invention, the aforementioned multilayer structure and semiconductor device having industrial advantages can be achieved.

1: Epitaxial film (compound semiconductor)

5: Oxide film/buffer layer

9: Crystal substrate

101: n-type semiconductor layer

101a: n ^- type semiconductor layer

101b: n ⁺ type semiconductor layer

102: p-type semiconductor layer

104: Insulation layer

105a: Schottky electrode

105b: Ohmic electrode

106: Protective ring

111a:n ^- type semiconductor layer

111b: n ⁺ type semiconductor layer

114: Semi-insulated body layer

115a: Gate electrode

115b: Source electrode

115c: Drain electrode

118: Buffer layer 118

119: Crystal substrate

121a: N-type semiconductor layer with wider bandwidth

121b: n-type semiconductor layer with narrow energy band

121c: n ⁺ type semiconductor layer

123:Electrons pass through the layer

124: Semi-insulated body layer

125a: Gate electrode

125b: Source electrode

125c: Drain electrode

128:Buffer layer

129:Crystal substrate

131a:n ^- type semiconductor layer

131b: first n ⁺ type semiconductor layer

131c: second n ⁺ type semiconductor layer

132: p-type semiconductor layer

132a: p ⁺ type semiconductor layer

134: Gate insulation film

135a: Gate electrode

135b: Source electrode

135c: Drain electrode

141a: n ^- type semiconductor layer

141b: First n ⁺ type semiconductor layer

141c: Second n ⁺ type semiconductor layer

p-type semiconductor layer

145a: Gate electrode

145b: Source electrode

145c: Drain electrode

151: n-type semiconductor layer

151a:n ^- type semiconductor layer

151b: n ⁺ type semiconductor layer

152: p-type semiconductor layer

154: Gate insulation film

155a: Gate electrode

155b: Emitter electrode

155c: Collector electrode

161: n-type semiconductor layer

162: p-type semiconductor layer

163: Luminescent layer

165a: first electrode

165b: Second electrode

167: Translucent electrode

1101a to 1101b: Metal source

1102a to 1102h: grounding

1103a to 1103b: ICP electrode

1104a to 1104b: Cutoff filter

1105a to 1105b: DC power supply

1106a to 1106b: RF power supply

1107a to 1107b: Lights

1108: Ar source

1109: Reactive gas source

1110: Power supply

1111:Substrate holder

1112:Substrate

1113: Cutoff filter

1114:ICP Ring

1115: Vacuum tank

1116: Rotation axis

FIG1 is a diagram schematically showing an example of a suitable implementation form of the layered structure of the present invention.

FIG. 2 is a schematic diagram for explaining the buffer layer formation step in the manufacturing method of the laminated structure of the present invention.

FIG. 3 is a diagram schematically showing an example of a suitable embodiment of the semiconductor device (SBD) of the present invention.

FIG4 is a diagram schematically showing an example of a suitable implementation form of the semiconductor device (JBS) of the present invention.

FIG5 is a diagram schematically showing an example of a suitable implementation form of the semiconductor device (MESFET) of the present invention.

FIG. 6 is a diagram schematically showing an example of a suitable implementation mode of the semiconductor device (HEMT) of the present invention.

FIG. 7 is a diagram schematically showing an example of a suitable implementation mode of the semiconductor device (MOSFET) of the present invention.

FIG8 is a diagram schematically showing an example of a suitable implementation form of the semiconductor device (SIT) of the present invention.

FIG. 9 is a diagram schematically showing an example of a suitable implementation mode of the semiconductor device (JFET) of the present invention.

FIG. 10 is a diagram schematically showing an example of a suitable embodiment of the semiconductor device (IGBT) of the present invention.

FIG11 is a diagram schematically showing an example of a suitable implementation form of the semiconductor device (LED) of the present invention.

FIG12 is a diagram schematically showing an example of a suitable implementation form of a power supply system.

FIG. 13 is a diagram schematically showing a suitable example of the system device.

FIG14 is a diagram schematically showing a suitable example of a power circuit diagram of a power supply device.

FIG. 15 is a diagram schematically showing a film-forming apparatus suitably used in Examples.

The laminated structure of the present invention is characterized in that an epitaxial film composed of a compound semiconductor is laminated on a buffer layer directly or via another layer, and the buffer layer includes a crystalline film containing Hf and/or Or Zr and has a cubic crystal structure. FIG. 1 shows a suitable example of the above-mentioned laminated structure. In the laminated structure system of FIG. 1, a buffer layer 5 is laminated on a crystal substrate 9, and an epitaxial film 1 composed of a compound semiconductor is laminated on the buffer layer 5. In addition, in this specification, the terms "film" and "layer" may be replaced by each other according to various situations or situations.

A preferred example of the laminated structure of the present invention is as shown in FIG. 2 , in which the buffer layer 5 is formed on the crystal substrate 9 using a known crystal growth method using nitrogen. The aforementioned crystal growth means may be a publicly known means, or may be any one of a vapor phase crystal growth means and a liquid phase crystal growth means. Examples of the crystal growth means include vapor deposition, CVD (chemical vapor deposition), and sputtering. In the present invention, it is preferable that after the buffer layer 5 is formed, an epitaxial film composed of a compound semiconductor is formed on the buffer layer using the crystal growth means. In this way, by forming the epitaxial film, as shown in FIG. 1 In the mode shown, the buffer layer changes along the crystal growth direction to form a valley structure at the interface with the epitaxial film. With this valley structure, the epitaxial film of good quality and excellent in crystallinity can be easily obtained.

The substrate material of the crystal substrate (hereinafter also referred to as "substrate") is not particularly limited as long as it does not hinder the object of the present invention, and it may be a known crystal substrate. It may also be an organic compound or an inorganic compound. In the present invention, the crystal substrate preferably contains an inorganic compound. In the present invention, the aforementioned substrate is preferably a crystal substrate having crystals on part or all of its surface, more preferably all or part of the main surface on the crystal growth side, and most preferably the entire main surface on the crystal growth side. Having a crystalline substrate. The aforementioned crystal is preferably a cubic crystal structure, and more preferably a crystal along the (100) or (200) orientation. Furthermore, the crystal substrate may have an offset angle. Examples of the offset angle include an offset angle of 0.2° to 12.0°. The "offset angle" referred to here refers to the angle formed by the substrate surface and the crystal growth surface. The shape of the substrate is not particularly limited as long as it is a plate-like shape and forms a support for the insulating film. It may be an insulator substrate or a semiconductor substrate. However, in the present invention, the aforementioned substrate is preferably a Si substrate, more preferably a crystalline Si substrate, and most preferably a crystalline Si substrate along the (100) orientation. Examples of the substrate material include, in addition to the Si substrate, one or two or more metals belonging to Group 3 to Group 15 of the periodic table of elements, or oxides of these metals. The shape of the substrate is not particularly limited and may be a substantially circular shape (such as a circle, an ellipse, etc.) or a polygonal shape (such as a triangle, a square, a rectangle, a pentagon, a hexagon, a heptagon, an octagon, or a nonagonal shape). etc.), various shapes can be used appropriately.

Furthermore, in the present invention, the crystal substrate preferably has a flat surface. However, the crystal substrate may preferably have a concave and convex shape on part or all of its surface. The crystal substrate having an uneven shape is not particularly limited as long as the uneven portions composed of concave portions or convex portions are formed on part or all of the surface. The concave and convex portions are not particularly limited as long as they are composed of concave portions or convex portions. It may be a concave-convex part composed of a convex part, or it may be a concave-convex part composed of a concave part, It may also be a concave and convex part composed of a convex part and a concave part. Furthermore, the aforementioned concave and convex parts may also be formed by regular convex parts or concave parts, or may be formed by irregular convex parts or concave parts. In the present invention, the concave and convex portions are preferably formed periodically, and more preferably are patterned periodically and regularly. The shape of the uneven portions is not particularly limited, and examples thereof include striped, dotted, meshed, or random shapes. However, in the present invention, dotted or striped shapes are preferred, and dotted shapes are more preferred. good. Furthermore, when the concave and convex parts are patterned periodically and regularly, the pattern shape of the concave and convex parts is preferably a triangle, a quadrangle (such as a square, a rectangle or a trapezoid, etc.), a polygonal shape such as a pentagon or a hexagon, a circle, an ellipse, etc. shape etc. In addition, when the uneven portions are formed into point shapes, the point-like lattice shape is preferably a lattice shape such as a square lattice, an orthorhombic lattice, a triangular lattice, or a hexagonal lattice, and more preferably a triangular lattice shape. The lattice shape of the lattice. The cross-sectional shape of the concave or convex portions of the concave and convex portions is not particularly limited, but examples thereof include U-shaped, U-shaped, inverted U-shaped, corrugated or triangular, quadrangular (for example, square, rectangular or trapezoidal, etc.), pentagonal or hexagonal. Angular and other polygonal shapes. In addition, the thickness of the crystal substrate is not particularly limited, but is preferably 50 to 2000 μm, more preferably 100 to 1000 μm.

The aforementioned buffer layer is not particularly limited as long as it includes a crystalline film, and the crystalline film contains Hf and/or Zr and has a cubic crystal structure. However, in the present invention, it is preferred that the aforementioned crystalline film is a conductive crystalline film containing a nitride or nitride oxide of Hf and/or Zr. The aforementioned conductive crystalline film is preferably one containing HfN and/or ZrN, and more preferably one containing HfN. Since the aforementioned conductive crystalline film contains HfN, even when the aforementioned epitaxial film is formed by growing more than two layers of crystals, in each case, a transformation can be produced to further improve the crystallinity of the epitaxial film. Furthermore, the aforementioned conductive crystalline film is preferably one having a cubic crystal structure, and more preferably one containing crystals oriented along (100) or (200). The aforementioned buffer layer can be suitably formed on the aforementioned crystal substrate by a known crystal growth method such as sputtering at, for example, 350°C to 700°C using a Hf source and/or a Zr source and nitrogen. Furthermore, the aforementioned buffer layer may also include a mixed crystal (also referred to as a "mixed crystal") film. The aforementioned mixed crystal film is not particularly limited as long as it is a crystalline film composed of mixed crystals, and as for the aforementioned mixed crystal, in addition to nitrides or nitride oxides of, for example, Hf and/or Zr, it may also contain, for example, a mixed crystal of one or more nitrides or nitride oxides selected from Ti, Al, Y and Ce. According to the above-mentioned suitable mixed crystal, not only the stress relief effect of the aforementioned buffer layer can be further optimized, but also the film quality of the aforementioned epitaxial film can be further optimized.

The epitaxial film is not particularly limited as long as it is a crystal growth film composed of a compound semiconductor. The compound semiconductor is not particularly limited either, and may be a known compound semiconductor. Examples of the compound semiconductor include a nitride semiconductor, a carbide semiconductor (for example, SiC, etc.), an oxide semiconductor, InP, and GaAs. In the present invention, the compound semiconductor is preferably a wide bandgap semiconductor, and more preferably a nitride semiconductor. Examples of the nitride semiconductor include III-V semiconductors (aluminum nitride (AlN)), gallium nitride (GaN), indium nitride (InN), etc.), or boron nitride (BN). wait. In the present invention, the epitaxial film preferably has a cubic crystal structure, and is more preferably a crystal growth film composed of a cubic crystal semiconductor. Examples of cubic crystal semiconductors include c-BN, c-AlN, c-GaN, c-InN, c-SiC, GaAs, AlAs, InAs, GaP, AlP, InP, and mixed crystal semiconductors thereof. wait.

The laminated structure obtained in the above manner can be kept as it is according to general methods or further processed as desired to be used in a semiconductor device. In the present invention, the buffer layer in the laminated structure can be suitably used as an electrode or buffer layer for ohmic bonding or electron emission of the semiconductor device, and the laminated structure can be used The epitaxial film is suitably used for the semiconductor layer of the semiconductor device. Furthermore, when the above-described laminated structure is used in a semiconductor device, it can be used in the semiconductor device as it is, and other layers (such as insulator layers, semi-insulator layers, conductor layers, semiconductor layers, buffer layers) can also be formed. or other intermediate layers, etc.) before use. Furthermore, in the semiconductor device, a known peeling means may be used to peel off the crystal substrate.

The semiconductor device is not particularly limited as long as it does not hinder the purpose of the present invention, and may be a known semiconductor device. It may be a vertical device or a horizontal device, but in the present invention, the semiconductor device is preferably a vertical device. As the aforementioned semiconductor device, for example, a diode or a transistor can be cited, and more specifically, a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a high electron mobility transistor (HEMT), a metal semiconductor field effect transistor (MESFET), a metal oxide semiconductor field effect transistor (MOSFET), an electrostatic induction transistor (SIT), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), a light emitting diode (LED), or a combination thereof are suitable examples.

Hereinafter, the drawings will be used to explain how the laminated structure is suitably used in a semiconductor device, and more specifically, how the buffer layer in the laminated structure is suitably used for ohmic bonding or electron emission of the semiconductor device. An electrode or a buffer layer, and the epitaxial film in the multilayer structure can be suitably used as a semiconductor layer of the semiconductor device. However, the present invention is not limited to these examples. In addition, the semiconductor device to be exemplified below may further include other layers (such as insulator layers, semi-insulator layers, conductor layers, semiconductor layers, buffer layers or other intermediate layers, etc.) as long as they do not hinder the object of the present invention. , Furthermore, the crystal substrate, buffer layer, etc. can also be omitted appropriately.

(SBD)

FIG. 3 shows an example of the Schottky barrier diode (SBD) of the present invention. The SBD of FIG. 3 includes an n-type semiconductor layer 101, an n ^- type semiconductor layer 101a, an n ⁺ -type semiconductor layer 101b, an insulator layer 104, a Schottky electrode 105a, and an ohmic electrode 105b.

The material of the electrode such as the Schottky electrode can be a known electrode material. Examples of the aforementioned electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or alloys of these metals, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures of these compounds, etc.

The electrode can be formed by known means such as vacuum evaporation or sputtering. More specifically, when a Schottky electrode is formed, a layer composed of Mo and a layer composed of Al are stacked, and the layer composed of Mo and the layer composed of Al can be formed by patterning using photolithography.

Examples of the material of the insulator layer 104 include GaO, AlGaO, InAlGaO, AlInZnGaO ₄ , AlN, Hf ₂ O ₃ , SiN, SiON, Al ₂ O ₃ , MgO, GdO, SiO ₂ or Si ₃ N ₄ . The insulator layer 104 is provided between the n ^- type semiconductor layer 101a and the Schottky electrode 105a. The insulating layer can be formed by, for example, sputtering, vacuum evaporation, CVD (chemical vapor deposition), or other known means.

When a reverse bias voltage is applied to the SBD in FIG. 3 , a depletion layer (not shown) expands in the n-type semiconductor layer 101 , thereby forming a high withstand voltage SBD. Furthermore, when a forward bias voltage is applied, electrons flow from the ohmic electrode 105b to the Schottky electrode 105a. As a result, SBDs using the above-mentioned semiconductor structure are excellent in high withstand voltage and large current applications, and are therefore The switching speed is also fast, it is also excellent in terms of voltage resistance and reliability, it is also excellent in insulation characteristics, and it has high current controllability.

(JBS)

FIG. 4 shows a junction barrier Schottky diode (JBS) which is one of the suitable embodiments of the present invention. The semiconductor device of FIG. 4 includes an n-type semiconductor layer 101, an n ^- type semiconductor layer 101a, an n ⁺ -type semiconductor layer 101b, a p-type semiconductor layer 102, a Schottky electrode 105a, an ohmic electrode 105b, and a guard ring 106. It includes an n ^- type semiconductor layer 101a, a Schottky electrode 105a disposed on the n ^- type semiconductor layer 101a and capable of forming a Schottky barrier between the n ^- type semiconductor layer 101a, and a Schottky electrode 105a disposed on the n-type semiconductor layer 101a. A Schottky barrier with a greater barrier height than the Schottky barrier height of the Schottky electrode 105a can be formed between the n ^- type semiconductor layer 101a and the n ^- type semiconductor layer 101a. p-type semiconductor layer 102. In addition, the p-type semiconductor layer 102 is buried in the n ^- type semiconductor layer 101a. In the present invention, it is preferable that the p-type semiconductor layers 102 are arranged at certain intervals, and it is more preferable that a p-type semiconductor layer is provided between both ends of the Schottky electrode 105a and the n ^- type semiconductor layer 101a. 102. With the above-mentioned various preferred forms, JBS can be constructed in a manner that is more excellent in terms of thermal stability and adhesion, reduces leakage current, and is more excellent in semiconductor characteristics such as withstand voltage.

(MESFET)

Fig. 5 shows an example of a metal semiconductor field effect transistor (MESFET) of the present invention. The MESFET of Fig. 5 has an n ^- type semiconductor layer 111a, an n ⁺ type semiconductor layer 111b, a buffer layer 118, a crystal substrate 119, a semi-insulating layer 114, a gate electrode 115a, a source electrode 115b and a drain electrode 115c.

The materials of the gate electrode, source electrode and drain electrode can be well-known electrode materials. Examples of the electrode materials include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, Metals such as In, Pd, Nd or Ag or alloys of these metals, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide (IZO), polyaniline, polythiophene or Organic conductive compounds such as polypyrrole or mixtures of these compounds. The gate electrode, source electrode and drain electrode can be formed by known means such as vacuum evaporation or sputtering.

The semi-insulating layer 114 only needs to be composed of a semi-insulating material. Examples of the semi-insulating material include those containing a semi-insulating dopant or those without a doping treatment.

The MESFET in Figure 5 can effectively control the current flowing from the drain electrode to the source electrode because a good depletion layer is formed under the gate electrode.

(HEMT)

FIG6 shows an example of a high electron mobility transistor (HEMT) of the present invention. The HEMT of FIG6 has an n-type semiconductor layer 121a with a wider energy band, an n-type semiconductor layer 121b with a narrower energy band, an n ⁺ -type semiconductor layer 121c, an electron passing layer 123, a semi-insulating layer 124, a gate electrode 125a, a source electrode 125b, a drain electrode 125c, a buffer layer 128, and a crystal substrate 129.

The materials of the gate electrode, the source electrode and the drain electrode can be known electrode materials respectively. Examples of the aforementioned electrode materials include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, and Ti. , Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag and other metals or alloys of these metals, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO ), metal oxide conductive films such as indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures of these compounds. The gate electrode, source electrode and drain electrode can be formed by known means such as vacuum evaporation or sputtering.

In addition, the n-type semiconductor layer under the gate electrode is composed of at least a wider energy band layer 121a and a narrower layer 121b. The semi-insulator layer 124 only needs to be composed of a semi-insulator. Examples of the aforementioned semi-insulator include Examples include those containing semi-insulating dopants or those without doping treatment. For example, when GaN, which is a nitride semiconductor, is used as the semiconductor, i (intentionally undoped)-GaN or the like can be used as the electron passage layer 123 formed on the semi-insulating layer 124 .

Since the HEMT in FIG6 forms a good depletion layer under the gate electrode, the current flowing from the drain electrode to the source electrode can be effectively controlled. Furthermore, in the present invention, a normally-off state can be exhibited by further providing a groove structure.

(MOSFET)

FIG. 7 shows an example when the semiconductor device of the present invention is a MOSFET. 7 shows an n ^- type semiconductor layer 131a, a first n ⁺ type semiconductor layer 131 b, a second n ⁺ type semiconductor layer 131 c, a p type semiconductor layer 132, a p ⁺ type semiconductor layer 132 a, a gate insulating film 134, and a gate electrode. A suitable example of the electrode 135a, the source electrode 135b and the drain electrode 135c is a metal oxide semiconductor field effect transistor (MOSFET). In addition, the p ⁺ -type semiconductor layer 132 a may be a p-type semiconductor layer, or may be the same as the p-type semiconductor layer 132 .

An n ⁺ type semiconductor layer 131 b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 135 c formed of the conductive crystal film, and an n ⁻ type semiconductor layer 131 a having a thickness of, for example, 100 nm to 100 μm is formed on the n ⁺ type semiconductor layer 131 b.

Furthermore, a plurality of trenches are formed in the n ^- type semiconductor layer 131a and the p-type semiconductor layer 132 to a depth reaching the middle of the n ^- type semiconductor layer 131a. The gate electrode 135a is embedded and formed in the trench by a gate insulating film 134 having a thickness of, for example, 10 nm to 1 μm.

When the MOSFET in FIG. 7 is in the on state, when a voltage is applied between the source electrode 135b and the drain electrode 135c, a positive voltage is applied to the gate electrode 135a relative to the source electrode 135b. When the voltage is applied, a channel layer is formed on the side surface of the n ^- type semiconductor layer 131a, and power is injected into the n ^- type semiconductor layer to become turn-on. In the off state, by setting the voltage of the gate electrode to 0V, the channel layer cannot be formed, and the n ^- type semiconductor layer is filled with the depletion layer, thereby becoming turn-off.

The MOSFET of FIG. 7 is provided with an etching mask (etching mask) in predetermined areas of the n ^- type semiconductor layer 131 a, the p type semiconductor layer 132 and the n ⁺ type semiconductor layer 131 c. The aforementioned etching mask is used as a mask, and further by Anisotropic etching is performed using a reactive ion etching method or the like to form a trench with a depth extending from the surface of the n ⁺ -type semiconductor layer 131 c to the middle of the n ⁻ -type semiconductor layer 131 a. Next, a gate insulating film 134 having a thickness of, for example, 50 nm to 1 μm is formed on the side and bottom surfaces of the trenches using known means such as thermal oxidation method, vacuum evaporation method, sputtering method, CVD method, etc., and then using CVD method, vacuum evaporation method, etc. The gate electrode material, such as polysilicon, is formed in the trench by plating or sputtering methods up to the thickness of the n ^- type semiconductor layer.

Next, a power MOSFET can be manufactured by forming a source electrode 135b on the n ⁺ type semiconductor layer 131c using a known method such as vacuum evaporation, sputtering, or CVD. In addition, the electrode material of the source electrode can be a well-known electrode material. As the aforementioned electrode material, for example, metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or alloys of these metals, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures of these compounds, etc. can be cited.

Compared with conventional trench-type MOSFETs, the MOSFET obtained in the above manner has superior voltage resistance. In addition, FIG. 7 shows an example of a trench-type vertical MOSFET. However, the present invention is not limited to this form and can be applied to various types of MOSFETs. For example, the depth of the trench in FIG. 7 may be dug down to the depth of the bottom surface of the n ^- type semiconductor layer 131a to reduce series resistance.

(SIT)

Fig. 8 shows an example in which the semiconductor device of the present invention is a SIT. The SIT of Fig. 8 has an n ^- type semiconductor layer 141a, n ⁺ type semiconductor layers 141b and 141c, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

An n ⁺ type semiconductor layer 141b having a thickness of, for example, 100 nm to 100 μm is formed on a drain electrode 145c formed of a conductive crystal film, and an ^n- type semiconductor layer 141a having a thickness of, for example, 100 nm to 100 μm is formed on the n ⁺ type semiconductor layer 141b. Furthermore, an n ⁺ type semiconductor layer 141c is formed on the n- type semiconductor layer 141a, ^{and a source electrode 145b is formed on the n+ type} semiconductor layer 141c.

Furthermore, a plurality of trenches are formed in the n ^- type semiconductor layer 141a, penetrating the n ⁺ -type semiconductor layer 141c and reaching the depth of the middle of the n ^- type semiconductor layer 141a. A gate electrode 145a is formed on the n ^- type semiconductor layer in the trench.

When the SIT in FIG. 8 is in the on state, when a voltage is applied between the source electrode 145b and the drain electrode 145c, and a positive voltage is applied to the gate electrode 145a with respect to the source electrode 145b, A channel layer will be formed in the n ^- type semiconductor layer 141a, and power will be injected into the n ^- type semiconductor layer to become turn-on. In the off state, by setting the voltage of the gate electrode to 0V, the channel layer cannot be formed, and the n ^- type semiconductor layer is filled with the depletion layer, thereby becoming turn-off. .

The SIT shown in FIG8 can be manufactured by using known means. For example, similarly to the manufacturing steps of the MOSFET described above, an etching mask is provided in predetermined regions of the n ^- type semiconductor layer 141a and the n ⁺ -type semiconductor layer 141c, and the etching mask is used as a mask to perform anisotropic etching by reactive ion etching or the like to form a trench having a depth from the surface of the n ⁺ -type semiconductor layer 141c to the middle of the n ^- type semiconductor layer. Then, a gate electrode material such as polysilicon is formed in the trench to a depth less than the thickness of the n ^- type semiconductor layer by using CVD, vacuum evaporation, sputtering, or the like. Then, by forming a source electrode 145b on the n ⁺ type semiconductor layer 141c and a drain electrode 145c on the n ⁺ type semiconductor layer 141b by using a known method such as vacuum evaporation, sputtering, or CVD, the SIT shown in FIG. 8 can be manufactured.

In addition, the electrode material of the source electrode can be a known electrode material. Examples of the aforementioned electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys of these metals, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures of these compounds, etc.

FIG. 9 shows a suitable example of a junction field effect transistor (JFET) having an n ^- type semiconductor layer 141a, a first n ⁺ type semiconductor layer 141b, a second n ⁺ type semiconductor layer 141c, a p-type semiconductor layer 142, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

FIG10 shows a suitable example of an insulated gate bipolar transistor (IGBT) having an n-type semiconductor layer 151, an n ^- type semiconductor layer 151a, an n ⁺ -type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c.

(LED)

FIG. 11 shows an example when the semiconductor device of the present invention is a light emitting diode (LED). The semiconductor light-emitting element of FIG. 11 has an n-type semiconductor layer 161 on the second electrode 165b, and a light-emitting layer 163 is laminated on the n-type semiconductor layer 161. Then, the p-type semiconductor layer 162 is laminated on the light-emitting layer 163 . The p-type semiconductor layer 162 is provided with a translucent electrode 167 through which light generated by the light-emitting layer 163 can pass, and a first electrode 165a is laminated on the translucent electrode 167 . In addition, the semiconductor light-emitting element of FIG. 11 may be covered with a protective layer except for the electrode portion.

Examples of materials for the translucent electrode include conductive materials containing oxides of indium (In) or titanium (Ti). More specifically, examples thereof include In ₂ O ₃ , ZnO, SnO ₂ , Ga ₂ O ₃ , TiO ₂ , CeO ₂ , mixed crystals of two or more of these oxides, or the latter doped with these oxides. These materials can be provided by known means such as sputtering to form a translucent electrode. Furthermore, thermal annealing (thermal annealing) for the purpose of making the translucent electrode transparent may be performed after forming the translucent electrode.

According to the semiconductor light-emitting element of FIG. 11 , the first electrode 165 a is set as the positive electrode, and the second electrode 165 b is set as the negative electrode. Through these two electrodes, the p-type semiconductor layer 162 , the light-emitting layer 163 and the n-type semiconductor layer 161 are connected. So that the light-emitting layer 163 emits light.

As for the material of the first electrode 165a, there can be cited metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys of these metals, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures of these compounds, etc. The electrode formation method is not particularly limited, and can be formed by a method appropriately selected from among wet methods such as printing, spraying, coating, vacuum evaporation, sputtering, ion plating, and other physical methods, CVD, plasma CVD, and other chemical methods, etc., in consideration of compatibility with the above-mentioned materials.

The semiconductor device of the present invention can be used not only as described above, but also as a semiconductor device such as a power module, an inverter (also called "inverter") or a converter by known means. Moreover, as a semiconductor device, it can be applied to a semiconductor system using, for example, a power supply device. In addition, the aforementioned power supply device can be manufactured by connecting the aforementioned semiconductor device to a wiring pattern, etc. using known means. Figure 12 shows an example of a power supply system. Figure 12 uses a plurality of the aforementioned power supply devices and a control circuit to form a power supply system. The aforementioned power supply system can be combined with an electronic circuit to be used in a system device, as shown in Figure 13. In addition, Figure 14 shows an example of a power supply circuit diagram of a power supply device. Figure 14 shows the power supply circuit of the power supply device composed of a power circuit and a control circuit. After the DC voltage is converted to AC at a high frequency by an inverter (composed of MOSFETA to D), the transformer is used for insulation and transformation, and after rectification by a rectifier MOSFET (A to B'), the DC voltage is smoothed by DCL (smoothing coils L1, L2) and capacitors to output the DC voltage. At this time, the output voltage is compared with the reference voltage by a voltage comparator, and the PWM (pulse width modulation) control circuit is used to control the inverter and the rectifier MOSFET in such a way that the desired output voltage is obtained.

[Implementation example]

(Implementation Example 1)

The crystal growth surface side of the Si substrate (100) is treated with RIE (reactive ion etching), using nitrogen and using an evaporation method to thermally react the metal (Hf, Zr) of the evaporation source with the nitrogen to form a crystal on the Si substrate. A crystalline film composed of nitrides. It can be seen that the results obtained by XPS (X-ray photoelectron spectrometer) The crystal film contains HfN and ZrN each having a cubic crystal structure. Furthermore, the obtained crystal film was investigated by the four-terminal method (four-terminal measurement technology) and found to have good conductivity. Next, a GaN film is formed as a semiconductor film on the crystal film by a sputtering method. From XPS, it was found that the obtained semiconductor film was a c-GaN single crystal film. Furthermore, when the interface is observed using a cross-sectional STEM (Scanning Transmission Electron Microscope) image, it can be seen that the buffer layer deforms in the direction of crystal growth and forms a valley structure with different angles formed by adjacent vertices and bottom points. The semiconductor film exhibits good stress relaxation properties when formed. In addition, when the obtained semiconductor film was observed using an X-ray crystal lattice image, it was found to be a large-area semiconductor film without defects, indicating that the laminated structure of the present invention has good crystallinity.

FIG15 shows an evaporation film forming apparatus used in Example 1. The evaporation film forming apparatus of FIG15 has at least metal sources 1101a to 1101b, grounds 1102a to 1102h, ICP (inductively coupled plasma) electrodes 1103a to 1103b, cut filters 1104a to 1104b, DC power sources 1105a to 1105b, RF power sources 1106a to 1106b, lamps 1107a to 1107b, Ar sources 1108, reactive gas sources 1109, power sources 1110, substrate holders 1111, substrates 1112, cut filters 1113, ICP rings 1114, vacuum chambers 1115, and rotating shafts 1116 in a crucible. In addition, the ICP electrodes 1103a to 1103b of FIG. 15 have a generally concave shape or a parabolic shape that is bent toward the center side of the substrate 1112.

As shown in FIG. 15 , the substrate 1112 is locked on the substrate holder 1111 , and then the power supply 1110 and the rotating mechanism (not shown) are used to rotate the rotating shaft 1116 to rotate the substrate 1112 , and further, the lamp 1107 a is used to rotate the rotating shaft 1116 . 1107b. The substrate 1112 is heated, and the vacuum chamber 1115 is evacuated by a vacuum pump (not shown) to bring it to a vacuum or reduced pressure. Thereafter, Ar gas is introduced into the vacuum chamber 1115 from the Ar source 1108, and DC power supplies 1105a to 1105b and RF power supply are used. 1106a to 1106b, ICP electrodes 1103a to 1103b, cutoff filters 1104a to 1104b and grounds 1102a to 1102h form argon plasma on the substrate 1112, thereby cleaning the surface of the substrate 1112.

Ar gas is introduced into the vacuum chamber 1115 and at the same time, the reactive gas is introduced using the reactive gas source 1109 . At this time, by repeatedly turning on and off the lamps 1107a to 1107b belonging to the lamp heater, a crystal growth film of higher quality can be formed.

[Industrial Applicability]

The laminated structure of the present invention can be used in all fields such as semiconductors (such as chemical semiconductor electronic devices, etc.), electronic parts and electrical equipment parts, optical and electrophotographic related devices, industrial components, etc., but is more suitable for use in semiconductor devices.

1: Epitaxial film (compound semiconductor)

5: Oxide film

9: Crystal substrate

Claims (15)

A multilayer structure is a structure in which an epitaxial film composed of a compound semiconductor is stacked on a buffer layer directly or via other layers, wherein the buffer layer includes a crystalline film, and the crystalline film contains Hf and/or Zr and has a cubic crystal structure. The laminated structure according to claim 1, wherein the crystal film is a conductive crystal film containing a nitride or nitride oxide of Hf and/or Zr. The laminated structure according to claim 1 or 2, wherein the epitaxial film has a cubic crystal structure. The laminated structure according to any one of claims 1 to 3, wherein the compound semiconductor is a wide bandgap semiconductor. A multilayer structure as described in any one of claims 1 to 4, wherein the compound semiconductor is a nitride semiconductor. The laminated structure according to any one of claims 1 to 5, wherein the buffer layer is laminated on the semiconductor single crystal substrate directly or through other layers. The laminated structure according to claim 6, wherein the buffer layer is laminated on the semiconductor single crystal substrate by crystal growth. The multilayer structure as described in claim 6 or 7, wherein the semiconductor single crystal substrate is a Si substrate. A semiconductor device including a laminated structure, wherein the laminated structure system is the laminated structure according to any one of claims 1 to 8. A semiconductor device as described in claim 9, wherein the semiconductor device is a vertical device. The semiconductor device according to claim 9 or 10, wherein the aforementioned semiconductor device is a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), or a combined PiN Schottky diode. Polar body (MPS), metal semiconductor field effect transistor (MESFET), high electron mobility transistor (HEMT), metal oxide semiconductor field effect transistor (MOSFET), electrostatic induction transistor (SIT), junction field effect transistor Crystal (JFET), Insulated Gate Bipolar Transistor (IGBT), Light Emitting Diode (LED) or a combination thereof. A method for manufacturing a multilayer structure, wherein a buffer layer is stacked on a semiconductor crystal substrate, and an epitaxial film composed of a compound semiconductor is stacked on the buffer layer directly or via other layers, wherein the buffer layer includes a crystalline film, and the crystalline film contains Hf and/or Zr and has a cubic crystal structure. The method of manufacturing a laminated structure according to claim 12, wherein the semiconductor single crystal substrate is a Si substrate, and the compound semiconductor is a nitride semiconductor. A method for manufacturing a semiconductor device using a multilayer structure, wherein the multilayer structure is a multilayer structure as described in any one of claims 1 to 8. A system includes a semiconductor device, wherein the semiconductor device is a semiconductor device as described in any one of claims 9 to 11.

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