TW202408138A - Power conversion circuit and controlling method thereof - Google Patents

Abstract

A power conversion circuit and controlling method thereof are provided. A switch element has a gate electrode and a field plane electrode. The gate electrode receives a first controlling signal, and the field plane electrode receives a second controlling signal. A rising edge of a high voltage period of the second controlling signal is earlier than a rising edge of a high voltage period of the first controlling signal, and the high voltage period of the second controlling signal is longer than the high voltage period of the first controlling signal during a heavy load period of the power conversion circuit.

Description

Power conversion circuit and control method thereof

The present invention relates to a power conversion circuit, and in particular to a power conversion circuit and a control method thereof.

In current applications, switching power conversion circuits use, for example, Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or Laterally Diffused Metal Oxide Semiconductor as the Switching elements perform power conversion. These switching elements have field plate (FP) electrodes and are coupled to their gate potential or source potential to reduce parasitic capacitance or parasitic resistance of the switching elements.

Specifically, if the field plate electrode is coupled to the gate potential, although the parasitic capacitance during device operation can be improved, when the switching element is turned off, the falling edge of the voltage on the field plate electrode is consistent with the drop of the voltage on the gate. The instantaneous voltage difference between the source and drain of the semiconductor device and between the field plate electrode and the drain will produce a ringing phenomenon. This ringing phenomenon may cause the device to break down. On the other hand, if the field plate electrode is coupled to the source potential, the parasitic resistance of the device can be improved, but the parasitic capacitance of the device will increase.

On the other hand, if the aforementioned switching element is applied to the lower bridge switch of the half-bridge rectifier, and the field plate electrode is coupled to the gate potential of the lower bridge switch. In this application, the ringing phenomenon caused when the low-side switch is turned off will cause the voltage difference between the gate and source (or drain) of the semiconductor device to be too large and collapse, causing shoot-through of the half-bridge rectifier. (shoot through) phenomenon causes damage to the half-bridge rectifier.

Embodiments of the present invention provide a power conversion circuit and a control method thereof, which can reduce the parasitic capacitance and parasitic resistance of switching elements in the power conversion circuit when they are operating, and at the same time improve the tolerance of the power conversion circuit to the occurrence of shoot-through phenomena. .

The power conversion circuit of the embodiment of the present invention includes a first switching element. The first switching element has a first gate electrode and a first field plate electrode. The first gate receives a first control signal, and the first field plate electrode receives a second control signal. During the reload period of the power conversion circuit, the rising edge of the high-potential period of the second control signal is earlier than the rising edge of the high-potential period of the first control signal, and the high-potential period of the second control signal is higher than that of the first control signal. The potential period is long.

In one embodiment, during the overload period of the power conversion circuit, the falling edge of the high-potential period of the second control signal is later than the falling edge of the high-potential period of the first control signal.

In one embodiment, the power conversion circuit further includes a second switching element connected in series between the input voltage and the first switching element. The second switching element has a second gate for receiving the third control signal. During the reloading period of the power conversion circuit, the second control signal is an inverse signal of the third control signal. There is a dead time between the high potential period of the first control signal and the high potential period of the third control signal.

In one embodiment, the second switching element further has a second field plate electrode. The second field plate electrode is used to receive a fourth control signal different from the third control signal.

In one embodiment, the fourth control signal is a DC voltage signal or a synchronization signal of the third control signal.

In one embodiment, the first switching element, the second switching element and the driving circuit are formed on the same chip.

In one embodiment, the power conversion circuit further includes a sensing circuit and a logic circuit. The sensing circuit senses at least one of the current flowing through the first switching element or the temperature of the first switching element, and generates a sensing signal. The logic circuit is coupled between the sensing circuit and the first field plate electrode, and provides a second control signal according to the sensing signal. When the sensing signal is lower than the preset value in response to the light load period of the power conversion circuit, the logic circuit maintains the second control signal at a fixed operating voltage.

An embodiment of the present invention further provides a control method for a power conversion circuit. The power conversion circuit includes a first switching element and has a first gate electrode to receive a first control signal and a first field plate electrode to receive a second control signal. The control method includes the following steps. Determine the load condition of the power conversion circuit. During the reload period of the power conversion circuit, the rising edge of the high-potential period of the second control signal is earlier than the rising edge of the high-potential period of the first control signal, and the high-potential period of the second control signal is earlier than the rising edge of the first control signal. The high potential period is long.

In another embodiment, during the overload period of the power conversion circuit, the falling edge of the high-potential period of the second control signal is later than the falling edge of the high-potential period of the first control signal.

In another embodiment, the control method further includes when a sensing signal related to one of the current flowing through the first switching element or the temperature of the first switching element is lower than a preset value in response to a light load period of the power conversion circuit. value, the second control signal is maintained at a fixed operating voltage.

Based on the above, the power conversion circuit and its control method according to the embodiment of the present invention can control the first control signal received by the gate electrode and the second control signal received by the field plate electrode, so that when the first switching element is turned on, it can pass through the second control signal. The control signal is used to reduce the parasitic resistance of the power, so that when the first switching element is turned on, the voltage on the field plate electrode can be maintained at a high voltage to avoid ringing and improve the tolerance of the shoot-through phenomenon. In this way, the power conversion circuit and its control method can reduce conduction loss (Conduction Loss), switching loss (Switch Loss) and prevent the first switching element from being shot through.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Some embodiments of the present invention will be described in detail with reference to the accompanying drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementations of the present invention. Rather, these embodiments are only examples within the scope of the patent application of the invention.

FIG. 1 is a circuit diagram of a power conversion device according to an embodiment of the present invention. Please refer to FIG. 1 , the power conversion device 10 includes a power conversion circuit 100 and a controller 200 . The power conversion circuit 100 is coupled to the controller 200 . The power conversion circuit 100 can receive the control signal PWM output by the controller 200, and can control the first switching element 110 and the second switching element 120 in the power conversion circuit 100 at least according to the control signal PWM, so that the first switching element 110 And the second switching element 120 converts the input voltage Vin to generate (and output) the output voltage Vsw at the output terminal N1.

In this embodiment, the power conversion device 10 further includes a strap capacitor (Cboost) C1 and a diode D1. The first terminal of the diode D1 is coupled to (or receives) the power supply voltage VDD. The second terminal of the diode D1 is coupled to the first terminal of the shoe capacitor C1 at the coupling terminal N2. The second terminal of the shoe capacitor C1 is coupled to the output terminal N1 of the power conversion circuit 100 . In this embodiment, the boot strap capacitor C1 and the diode D1 can generate the bootstrap voltage (Boost strap) VBOOST at the coupling terminal N2 according to the power supply voltage VDD, so that the power conversion circuit 100 can receive the bootstrap voltage VBOOST as The driving voltage of the second switching element 120 .

In this embodiment, the power conversion device 10 further includes a filter capacitor C2 and a filter inductor L1. The first terminal of the filter inductor L1 is coupled to the second terminal of the shoe capacitor C1 and the output terminal N1 of the power conversion circuit 100 . The second terminal of the filter inductor L1 is coupled to the first terminal of the filter capacitor C2. The second terminal of the filter capacitor C2 is coupled to the output terminal VOUT of the power conversion device 10 and the controller 200 . In this embodiment, the filter capacitor C2 and the filter inductor L1 can be used as filters to perform a filtering operation on the output signal of the power conversion circuit 100 (ie, the output voltage Vsw on the output terminal N1), so as to convert the filtered output The voltage Vsw is provided to a load device (not shown) coupled to the output terminal VOUT.

FIG. 2 is a circuit diagram of a power conversion circuit according to an embodiment of the present invention. Referring to FIG. 2 , the power conversion circuit 100 includes a first switching element 110 . The first switching element 110 may be, for example, an N-type metal oxide semi-field effect transistor (NMOSFET) having a field plate electrode. When the first switching element 110 is turned on, a channel (Channel) is formed between the source and the drain of the first switching element 110 (ie, between the gate and the field plate electrode) and has a drift layer resistance RD1. The drift layer resistor RD1 may be exemplarily shown on the first field plate electrode of the first switching element 110 .

In some embodiments, the first switching element 110 may be implemented as a p-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOSFET) with a field plate electrode. The signals in some embodiments are inverse to the corresponding signals in this embodiment.

The gate of the first switching element 110 receives the first control signal LS_G to control the first switching element 110 to be turned on or off. In this embodiment, the first field plate electrode of the first switching element 110 receives the second control signal LS_FP to control the charge of the drift layer to reduce the drift layer resistance RD1, thereby further reducing the parasitic resistance and conduction in the power conversion circuit 100. loss. In this embodiment, the source of the first switching element 110 is coupled to the ground terminal voltage GND. The drain of the first switching element 110 is coupled to the output terminal N1.

During the reload period of the power conversion circuit 100, the first control signal LS_G and the second control signal LS_FP are square wave signals, and the high potential period of the second control signal LS_FP occurs earlier than and covers the high potential period of the first control signal LS_G. The high potential period of the first control signal LS_G. That is to say, during the overload period of the power conversion circuit 100 , the rising edge of the high-potential period of the second control signal LS_FP is earlier than the rising edge of the high-potential period of the first control signal LS_G. The high potential period of the second control signal LS_FP is longer than the high potential period of the first control signal LS_G. The falling edge of the high potential period of the second control signal LS_FP is later than the falling edge of the high potential period of the first control signal LS_G. This ensures low parasitic resistance during the turn-on period of the first switching element 110 and better tolerance to the ringing phenomenon of the source-to-sink voltage during the turn-on/turn-off transient periods. At the same time, the first switching element 110 can also have a high drift layer resistance RD1 during the off period to prevent current leakage.

The power conversion circuit 100 may further include a second switching element 120 . The second switching element 120 is coupled to the first switching element 110 . Specifically, the second switching element 120 is connected in series between the input voltage Vin and the first switching element 110 . The source of the second switching element 120 receives (or is coupled to) the input voltage Vin. The drain of the second switching element 120 is coupled to the drain of the first switching element 110 and the output terminal N1. In this embodiment, the first switching element 110 and the second switching element 120 form a half-bridge rectifier structure. The first switching element 110 can be used as a low-side transistor, and the second switching element 120 can be used as a high-side transistor. (High-side) transistor.

In this embodiment, the second switching element 120 may be implemented, for example, as an N-type MOSFET having a field plate electrode. When the second switching element 120 is turned on, a channel (Channel) is formed between the source and the drain of the second switching element 120 (ie, between the gate and the field plate electrode) and has a drift layer resistance RD2. The drift layer resistance RD2 may be exemplarily shown on the field plate electrode of the second switching element 120 .

In some embodiments, the second switching element 120 may be implemented as a p-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOSFET) with a field plate electrode. The signals in some embodiments are inverse to the corresponding signals in this embodiment.

In this embodiment, the second switching element 120 is controlled by the third control signal HS_G. Specifically, the second switching element 120 has a second gate for receiving the third control signal HS_G to control the on or off of the second switching element 120 . In this embodiment, the second switching element 120 has a second field plate electrode for receiving a fourth control signal HS_FP1 that is different from the third control signal HS_G to reduce the drift layer resistance RD2 and further enter the low power conversion circuit 100 parasitic resistance and conduction losses.

In this embodiment, during the reloading period of the power conversion circuit 100, the third control signal HS_G and the second control signal LS_FP are inverse signals of each other. Specifically, the second control signal LS_FP is the inverse signal of the third control signal HS_G, and there is a dead time between the high potential period of the first control signal LS_G and the high potential period of the third control signal HS_G. And staggered from each other.

In this embodiment, the power conversion circuit 100 may generate the third control signal HS_G and the fourth control signal HS_FP1 based on the low-side control signal LS and/or the high-side control signal HS to further generate the output voltage Vsw. In some embodiments, the control circuit may output the fourth control signal HS_FP1 to the second switching element 120 .

In this embodiment, the fourth control signal HS_FP1 can be, for example, a DC voltage signal (which can be, for example, the power supply voltage VDD), so that the second switching element 120 can maintain a low on-resistance during operation. In some embodiments, the fourth control signal HS_FP1 can be, for example, a synchronization signal of the third control signal HS_G (which can be, for example, the boost strap voltage VBOOST), which can keep the second switching element 120 high during the turn-off period. On-resistance.

In the embodiment of FIG. 2, the power conversion circuit 100 further includes a driving circuit DRC. The input terminal of the driving circuit DRC is coupled to (or receives) the driving voltage PWM. A plurality of output terminals of the driving circuit DRC are respectively coupled to the first switching element 110 and the second switching element 120 to output the first control signal LS_G and the third control signal HS_G to the first switching element 110 and the second switching element 120 respectively.

Specifically, the power conversion circuit 100 further includes a level shifter 140 and an inverter 150 . The level shifter 140 and the inverter 150 can be integrated into the driving circuit DRC. The input terminal of the level shifter 140 receives the high-side control signal HS (ie, the driving voltage PWM). The output terminal of the level shifter 140 is coupled to the gate of the second switching element 120 . The level shifter 140 can adjust (for example, increase or decrease) the voltage value (or voltage level) of the high-side control signal HS to generate the third control signal HS_G. The input terminal of the inverter 150 receives the high-side control signal HS (ie, the driving voltage PWM). The output terminal of the inverter 150 is coupled to the gate of the first switching element 110 . The inverter 150 may invert the high-side control signal HS to generate the low-side control signal LS. The driving circuit DRC may receive one of the bootstrap voltage VBOOST or the power supply voltage VDD as the fourth control signal HS_FP1.

In the embodiment of FIG. 2 , the power conversion circuit 100 further includes a logic circuit 130 and a sensing circuit (not shown in FIG. 2 ). The logic circuit 130 and the sensing circuit can be integrated into the driving circuit DRC. The logic circuit 130 is coupled between the sensing circuit and the first field plate electrode of the first switching element 110 . Specifically, multiple input terminals of the logic circuit 130 can respectively receive the high-side control signal HS, the operating voltage VFON, the preset value Vth, and the sensing signal Vsense provided by the sensing circuit. The output terminal of the logic circuit 130 is coupled to the first field plate electrode of the first switching element 110 . The logic circuit 130 may provide the second control signal LS_FP to the first field plate electrode of the first switching element 110 according to at least one of the high-side control signal HS, the operating voltage VFON, the preset value Vth, and the sensing signal Vsense.

In this embodiment, the logic circuit 130 includes a switching circuit 132 and a comparator 133 . In this embodiment, the logic circuit 130 may further include an inverter 131 . The input terminal of the inverter 131 receives a high-side control signal HS. The output terminal of the inverter 131 is coupled to the first field plate electrode of the first switching element 110 . The inverter 131 may invert the high-side control signal HS to generate a second control signal LS_FP, and output an inverted signal of the high-side control signal HS as the second control signal LS_FP.

In this embodiment, the switching circuit 132 has a first input terminal, a second input terminal and an output terminal. The first input terminal of the switching circuit 132 receives the second control signal LS_FP. The second input terminal of the switching circuit 132 receives (or is coupled to) the operating voltage VFON. The third input terminal (or control terminal) of the switching circuit 132 is coupled to the output terminal of the comparator 133 to receive the comparison result VS. The output terminal of the switching circuit 132 is coupled to the first field plate electrode of the first switching element 110 . In this embodiment, the switching circuit 132 is controlled by the comparator 133 between the first input terminal of the switching circuit 132 (ie, the output terminal of the inverter 131) and the second input terminal (ie, the operating voltage VFON). A switching operation is performed to output the inverted signal of the high-side control signal HS output by the inverter 131 or to output the operating voltage VFON. In this embodiment, the switching circuit 132 may be a switch, for example.

In this embodiment, the comparator 133 is coupled to the sensing circuit (not shown in FIG. 2 ) and the switching circuit 132 . Specifically, multiple input terminals of the comparator 133 receive the sensing signal Vsense and the preset value Vth from the sensing circuit. The output terminal of the comparator 133 is coupled to the control terminal of the switching circuit 132 . In this embodiment, the comparator 133 can perform comparison according to the sensing signal Vsense and the preset value Vth to generate a comparison result VS and output it to the switching circuit 132 . That is to say, the comparator 133 can compare the sensing signal Vsense and the preset value Vth, and provide the comparison result VS to the switching circuit 132, so that the switching circuit 132 switches to output the second control signal LS_FP (ie, the high-side control signal HS Inverted signal) or operating voltage VFON.

In this embodiment, the sensing signal Vsense may be, for example, a parameter associated with the load condition of the power conversion circuit. For example, the sensing signal Vsense may be at least one of a current sensing value flowing through the first switching element 110 and a temperature sensing value of the first switching element 110 .

In this embodiment, when the voltage value of the sensing signal Vsense is higher than the preset value Vth, it indicates that the load condition is a heavy load (ie, the power conversion circuit 100 operates during a heavy load period). The switching circuit 132 switches and outputs the inverted signal of the high-side control signal HS as the second control signal LS_FP according to the comparison result VS. Specifically, in this embodiment, when a current flows through the first switching element 100 and the sensing signal Vsense of this current is higher than the preset value Vth, the switching circuit 132 switches the output high-side control according to the comparison result VS. The inverse signal of the signal HS serves as the second control signal LS_FP, so that the second control signal LS_FP switches between a relatively high voltage value and a relatively low voltage value (ie, a square wave signal).

On the other hand, in this embodiment, when the voltage value of the sensing signal Vsense is lower than the preset value Vth, it indicates that the load condition is light load (ie, the power conversion circuit 100 operates during the light load period). Specifically, in this embodiment, when the sensing signal Vsense is lower than the preset value Vth in response to the light load period of the power conversion circuit 100, the switching circuit 132 switches the output operating voltage VFON as the second output voltage VFON according to the comparison result VS. The signal LS_FP is controlled to maintain the second control signal LS_FP at a fixed operating voltage (ie, a high potential state with a fixed relatively high voltage value).

In this embodiment, since the switching circuit 132 can switch between the inverted signal of the high-side control signal HS and the operating voltage VFON according to the comparison result VS, the switching circuit 132 can output a DC voltage signal (ie, the high-side control signal HS an inverted signal) or a square wave signal (ie, the operating voltage VFON), so that the second control signal LS_FP can switch the DC voltage signal or the square wave signal according to the light/heavy load condition of the load.

In other words, the logic circuit 130 can determine the loading status of the output terminal N1 through the sensing signal Vsense and output the corresponding signal as the second control signal LS_FP, which can improve the switching of the power conversion circuit 100 at light load or heavy load respectively. efficiency.

It is worth mentioning that the circuit in Figure 2 can preferably be applied to a driving switch (Driving MOS, DrMOS) or smart power stage (Smart Power Stage, SPS) integrated circuit packaging structure. That is, the first switching element 110, the second switching element 120 and the driving circuit DRC are in the same integrated circuit package.

For example, the first switching element 110, the second switching element 120 and the driving circuit DRC may have a monolithic structure formed in the same wafer. Or a multi-chip packaging structure in which at least two components of the first switching element 110, the second switching element 120 and the driving circuit DRC are in the same chip. In this way, the package pins of the integrated circuit can be compatible with commercially available product specifications.

FIG. 3 is a flow chart of a control method of a power conversion circuit according to an embodiment of the present invention. Referring to FIG. 2 and FIG. 3 , the control circuit may perform the following steps S210 to S220 to execute the control method to control the power conversion circuit 100 . In this embodiment, steps S210 to S220 may be applied to the following exemplary situations.

In step S210, the load condition of the power conversion circuit 100 is determined through the control circuit. In this embodiment, when the sensing signal Vsense is higher than the preset value Vth in response to the overload period of the power conversion circuit 100, the first control signal LS_G and the second control signal LS_FP are configured as square wave signals through the control circuit. That is to say, the first control signal LS_G switches between the first voltage value and the second voltage value. The second control signal LS_FP switches between a first voltage value (or a third voltage value) and a second voltage value (or a fourth voltage value).

In step S220, during the reload period of the power conversion circuit 100, the rising edge of the high potential period of the second control signal LS_FP is earlier than the rising edge of the high potential period of the first control signal LS_G through the control circuit, and the second control signal The high potential period of LS_FP is longer than the high potential period of the first control signal LS_G.

Specifically, in this embodiment, when the first switching element 110 is to be turned on, the rising edge of the second control signal LS_FP occurs before the corresponding rising edge of the first control signal LS_G. When the first switching element 110 is turned on, the second control signal LS_FP and the first control signal LS_G are respectively maintained at relatively high voltage values (eg, the first voltage value and/or the third voltage value). When the first switching element 110 is to be turned off, the falling edge of the second control signal LS_FP occurs after the corresponding falling edge of the first control signal LS_G.

It is worth mentioning here that since the falling edge of the second control signal LS_FP occurs after the falling edge of the first control signal LS_G, the high potential period of the second control signal LS_FP can cover the instant when the first switching element 110 is turned off. state time point (that is, the time point when the falling edge of the first control signal LS_G occurs). In this embodiment, the falling edge of the voltage on the gate electrode of the first switching element 110 (ie, the first control signal LS_G) is consistent with the voltage on the first field plate electrode of the first switching element 110 (ie, the second control signal LS_G). The falling edges of LS_FP) are staggered to avoid the ringing phenomenon caused when the first switching element 110 is turned off. That is to say, through the configuration of the second control signal LS_FP, the uniformity of the electric field distribution of the first switching element 110 can be improved to reduce the voltage difference between the first field plate electrode and the drain electrode. In this way, the first switching element 110 can increase the tolerance to the ringing phenomenon, so as to increase the voltage value of the breakdown voltage (breakdown voltage) when the first switching element 110 is turned off.

FIG. 4A is a circuit block diagram of a sensing circuit according to the embodiment of FIG. 2 of the present invention. The first switching element 110 , the output terminal N1 , the first control signal LS_G and the sensing signal Vsense can refer to the relevant description of the power conversion circuit 100 and be deduced by analogy, so they will not be repeated here. On the other hand, in order to facilitate the description of the present invention, some components and component numbers of the power conversion circuit 100 shown in FIG. 4A are omitted.

Referring to FIG. 4A and FIG. 2 , the input terminal of the sensing circuit 360 of the power conversion circuit 100 is coupled to the source of the first switching element 110 to sense the current flowing through the first switching element 110 (ie, the output terminal N1 current). The output terminal of the sensing circuit 360 is coupled to the comparator 133 in the logic circuit 130 to output the sensing signal Vsense to the comparator 133 based on the aforementioned current. That is to say, the sensing circuit 360 can sense the current flowing through the first switching element 110 and generate the sensing signal Vsense.

FIG. 4B is a circuit block diagram of the sensing circuit according to the embodiment of FIG. 2 of the present invention.

Referring to FIG. 4B and FIG. 2 , the sensing circuit 360 of the power conversion circuit 100 includes a current source 361 and a thermistor Rth. The current source 361 is coupled to the thermistor Rth. The thermistor Rth is disposed adjacent to the first switching element 110 to sense the temperature of the first switching element 110 . The output terminal of the sensing circuit 360 is coupled to the comparator 133 in the logic circuit 130 to output the sensing signal Vsense to the comparator 133 based on the aforementioned temperature. That is to say, the sensing circuit 360 can sense the temperature generated by the current flowing through the first switching element 110 and generate the sensing signal Vsense.

In some embodiments, the sensing circuit 360 may be implemented in both the embodiments shown in FIG. 4A and FIG. 4B. That is to say, the sensing circuit 360 can sense at least one of the current flowing through the first switching element 110 and the temperature of the first switching element 110 and generate the sensing signal Vsense.

FIG. 5 is a schematic diagram of the operation of the power conversion circuit according to the embodiment of FIG. 2 of the present invention. In FIG. 5 , the horizontal axis represents the operation time of the power conversion circuit 100 and the vertical axis represents the voltage value. For details of the operation of the power conversion circuit 100, please refer to FIG. 2 and FIG. 5. In this embodiment, the power conversion circuit 100 can operate by determining the status of the load device coupled to the output terminal N1 according to the sensing signal Vsense.

For example, before time t3 (referred to as the first operation period in the following embodiment), when the loading state of the load device is light load, the current flowing through the switching element is low, causing the temperature of the switching element to be low, and the corresponding inductance The voltage value of the test signal Vsense is lower than the preset value Vth. At this time, the logic circuit 130 outputs a fixed voltage as the second control signal LS_FP1. The fixed voltage can be the operating voltage VFON, the high level voltage of the second control signal LS_FP1, or other voltage values according to circuit design requirements. For example, it can be a voltage value between the output voltage Vsw and the ground voltage GND.

During the first operation period, the fourth control signal HS_FP1 is a DC voltage signal with a relatively high voltage value (for example, the power supply voltage VDD), which can keep the second switching element 120 in the on-resistance state. The third control signal HS_G is a square wave signal and switches between a relatively high voltage value and a relatively low voltage value. In some embodiments, the fourth control signal HS_FP1 may be replaced by the fourth control signal HS_FP2. The fourth control signal HS_FP2 may be, for example, a synchronization signal of the third control signal HS_G (which may be, for example, a boost strap voltage).

During the first operation period, the second control signal LS_FP is a DC voltage signal with a relatively high voltage value. The first control signal LS_G is a square wave signal and switches between a relatively high voltage value and a relatively low voltage value. In this embodiment, there is a dead time between the high potential period of the third control signal HS_G and the high potential period of the first control signal LS_G, for example, from time t1_1 to time t1_2 or from time t1_2 to time t1_4. The high-potential period T_G of the first control signal LS_G and the high-potential period of the third control signal HS_G are staggered from each other without overlapping.

On the other hand, after time t3 (referred to as the second operation period in the following embodiment), when the load pumping state of the load device is overloaded, the voltage value of the sensing signal Vsense is higher than the voltage value of the preset value Vth. At this time, the logic circuit 130 outputs a square wave signal as the second control signal LS_FP.

During the second operation period, the fourth control signal HS_FP1 is a DC voltage signal with a first voltage value. The third control signal HS_G, the second control signal LS_FP and the first control signal LS_G are square wave signals and have a high potential period and a low potential period. In some embodiments, the fourth control signal HS_FP1 may be replaced by the fourth control signal HS_FP2. The fourth control signal HS_FP2 may be, for example, a synchronization signal of the third control signal HS_G (which may be, for example, a boost strap voltage).

During the second operation period, the second control signal LS_FP is an inverse signal of the third control signal HS_G, and there is a dead time between the high potential period of the first control signal LS_G and the high potential period of the third control signal HS_G.

Specifically, during the second operation period, the rising edge of the second control signal LS_FP occurs at time t4_3, and the corresponding rising edge of the first control signal LS_G occurs at time t4_4. That is, the rising edge of the second control signal LS_FP occurs before the corresponding rising edge of the first control signal LS_G. At least part of the high-potential period T_FP of the second control signal LS_FP overlaps with at least part of the high-potential period T_G of the first control signal LS_G.

It should be noted that from time t4_3 to time t4_4, the high potential period T_FP of the second control signal LS_FP covers the rising edge of the first control signal LS_G, so that the second control signal LS_FP does not occur simultaneously with the first control signal LS_G. Switching of voltage values (i.e., transients). In this way, the first switching element 110 can prevent the parasitic capacitance on the first field plate electrode and the parasitic capacitance on the gate from being charged at the same time, causing the overall parasitic capacitance value to increase. Therefore, the first switching element 110 can be shortened when the first switching element 110 is turned on. time between switching and being turned off to reduce switching losses.

During the second operation period, at time t5_1, the first control signal LS_G switches from a relatively high voltage value to a relatively low voltage value to generate a falling edge of the first control signal LS_G. Then, at time t5_2, the second control signal LS_FP switches from a relatively high voltage value to a relatively low voltage value to generate a falling edge of the second control signal LS_FP. That is, the falling edge of the second control signal LS_FP occurs after the corresponding falling edge of the first control signal LS_G. The high voltage period T_FP of the second control signal LS_FP covers the high voltage period T_G of the first control signal LS_G.

It should be noted that from time t5_1 to time t5_2, through the second control signal LS_FP having a relatively high voltage value, the voltage difference between the field plate electrode and the drain electrode of the first switching element 110 can be reduced, and therefore the first switching element 110 can be improved. The electric field distribution of the switching element 110 is uniform to prevent the first switching element 110 from collapsing and being mistakenly turned on or off.

In another embodiment, the field plate electrode of the second switching element 120 may receive a square wave signal synchronized with the third control signal HS_G as the fourth control signal HS_FP2 (for example, it may be a bootstrap voltage signal of the power conversion circuit 100). , ensuring large resistance during HSMOS turn-off.

FIG. 6 is a schematic diagram of the operation of the power conversion circuit according to the embodiment of FIG. 2 of the present invention. In FIG. 6 , the horizontal axis represents the operation time of the power conversion circuit 100 and the vertical axis represents the voltage value. For details of the operation of the power conversion circuit 100, please refer to FIG. 2 and FIG. 6.

Before time t6_1, the second control signal LS_FP and the first control signal LS_G maintain a relatively low voltage value. At this time, the drift layer resistor RD1 has a relatively high resistance value. In this embodiment, the second control signal LS_FP having a relatively low voltage value can ensure that the first switching element 110 has a high impedance value when it is turned off, so as to increase the current resistance when the first switching element 110 is turned off. breaking ability.

At time t6_1, the second control signal LS_FP switches from a relatively low voltage value to a relatively high voltage value to generate a rising edge of the second control signal LS_FP. At this time, the first field plate electrode of the first switching element 110 receives the second control signal LS_FP, causing the drift layer resistance RD1 to decrease from a relatively high resistance value to a relatively low resistance value. In this embodiment, the drift layer resistance RD1 can be reduced by applying the second control signal LS_FP to the first field plate electrode, thereby reducing the parasitic resistance and conduction loss of the first switching element 110 and increasing the energy of the first switching element 110 conduction efficiency.

At time t6_2, the first control signal LS_G switches from a relatively low voltage value to a relatively high voltage value to generate a rising edge of the first control signal LS_G. At this time, the second control signal LS_FP has a relatively high voltage value. Regarding the operation of the power conversion circuit 100 from time t6_1 to time t6_2, reference can be made to the relevant description of the embodiment in FIG. 5 and analogies can be made, so it will not be repeated here.

In this embodiment, the time difference between time t6_1 and time t6_2 is dead time. The dead time may be, for example, in a range between 2 microseconds and 4 microseconds, so that the rising edge of the second control signal LS_FP is sufficiently offset from the rising edge of the first control signal LS_G.

At time t7_1, the first control signal LS_G switches from a relatively high voltage value to a relatively low voltage value to generate a falling edge of the first control signal LS_G. At this time, the second control signal LS_FP has a relatively high voltage value.

At time t7_2, the second control signal LS_FP switches from a relatively high voltage value to a relatively low voltage value to generate a falling edge of the second control signal LS_FP. At this time, the first field plate electrode of the first switching element 110 stops receiving the second control signal LS_FP, causing the drift layer resistance RD1 to increase from a relatively low resistance value to a relatively high resistance value. Regarding the operation of the power conversion circuit 100 from time t7_1 to time t7_2, reference can be made to the relevant description of the embodiment in FIG. 5 and analogies can be made, so it will not be repeated here.

It should be noted that from time t7_1 to time t7_2, by the falling edge of the second control signal LS_FP being later than the falling edge of the first control signal LS_G, the voltage between the source and the drain of the first switching element 110 can be prevented. If the difference is too large, a ringing phenomenon will occur, so as to avoid the penetration phenomenon caused by mistakenly turning on the first switching element 110 due to the ringing phenomenon.

In this embodiment, from time t6_1 to time t7_2 (ie, the high potential period T_FP of the second control signal LS_FP), the resistance value of the drift layer resistor RD1 is maintained at a relatively low resistance value, which can reduce the voltage of the first switching element 110 conduction losses.

After time t7_2, the resistance value of the drift layer resistor RD1 is maintained at a relatively high resistance value, which can improve the current blocking capability when the first switching element 110 is turned off.

To sum up, the power conversion circuit and its control method according to the embodiment of the present invention can avoid the ringing phenomenon caused when the first switching element is turned off by staggering the falling edge of the second control signal and the falling edge of the first control signal. , to improve the tolerance to ringing phenomena and the voltage value of breakdown voltage. In some embodiments, when the power conversion circuit operates in different operating modes, the configuration of the second control signal can shorten the time for the first switching element to switch between being turned on and turned off to reduce switching losses, and can Avoid shot-through phenomenon caused by ringing phenomenon.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

10:Power conversion device 100:Power conversion circuit 110: First switching element 120: Second switching element 130:Logic circuit 131:Inverter 132:Switching circuit 133: Comparator 140: Level shifter 150:Inverter 200:Controller 360: Sensing circuit 361:Current source BOOT:endpoint C1~C2: capacitor D1: Diode DRC: drive circuit GND: ground terminal voltage HS: high side control signal HS_FP1, HS_FP2: fourth control signal HS_G: Third control signal L1:Inductor LS: low side control signal LS_FP: Second control signal LS_G: first control signal N1: output terminal N2: coupling end PWM: drive voltage RD1~RD2: Drift layer resistance Rth: thermistor S210~S220: steps T_FP, T_G: High potential period t1_1~t7_2: time VBOOST: bootstrap voltage VDD: power supply voltage VFON: working voltage Vin: input voltage VOUT: output terminal VS: comparison results Vsense: sensing signal Vsw: output voltage Vth: default value

FIG. 1 is a schematic diagram of a power conversion device applying an embodiment of the present invention. FIG. 2 is a circuit diagram of a power conversion circuit according to an embodiment of the present invention. FIG. 3 is a flow chart of a control method of a power conversion circuit according to an embodiment of the present invention. FIG. 4A is a circuit block diagram of a sensing circuit according to the embodiment of FIG. 2 of the present invention. FIG. 4B is a circuit block diagram of the sensing circuit according to the embodiment of FIG. 2 of the present invention. FIG. 5 is a control signal and waveform diagram of the power conversion circuit according to the embodiment of FIG. 2 of the present invention. FIG. 6 is a schematic diagram of the operation of the power conversion circuit according to the embodiment of FIG. 2 of the present invention.

100:Power conversion circuit

110: First switching element

120: Second switching element

130:Logic circuit

131:Inverter

132:Switching circuit

133: Comparator

140: Level shifter

150:Inverter

DRC: drive circuit

GND: ground terminal voltage

HS: high side control signal

HS_FP1: Fourth control signal

HS_G: Third control signal

LS: low side control signal

LS_FP: Second control signal

LS_G: first control signal

N1: output terminal

PWM: drive voltage

RD1~RD2: Drift layer resistance

VBOOST: bootstrap voltage

VDD: power supply voltage

VFON: working voltage

Vin: input voltage

VS: comparison results

Vsense: sensing signal

Vsw: output voltage

Vth: default value

Claims (10)

A power conversion circuit including: a first switching element having a first gate and a first field plate electrode, wherein the first gate receives a first control signal, and the first field plate electrode receives a second control signal, Wherein, during a reload period of the power conversion circuit, the rising edge of the high potential period of the second control signal is earlier than the rising edge of the high potential period of the first control signal, and the high potential period of the second control signal is longer than the high potential period of the first control signal. The power conversion circuit of claim 1, wherein during the overload period of the power conversion circuit, the falling edge of the high potential period of the second control signal is later than the falling edge of the high potential period of the first control signal. The power conversion circuit as described in claim 1, further comprising: a second switching element connected in series between an input voltage and the first switching element, the second switching element having a second gate for receiving a third control signal, During the reload period of the power conversion circuit, the second control signal is the inverse signal of the third control signal, and the period between the high potential period of the first control signal and the high potential period of the third control signal There is a dead time. The power conversion circuit of claim 3, wherein the second switching element further has a second field plate electrode for receiving a fourth control signal different from the third control signal. The power conversion circuit of claim 4, wherein the fourth control signal is a DC voltage signal or a synchronization signal of the third control signal. The power conversion circuit of claim 3, wherein the first switching element, the second switching element and a driving circuit are formed in the same chip. The power conversion circuit as described in claim 1, further comprising: a sensing circuit that senses at least one of the current flowing through the first switching element or the temperature of the first switching element, and generates a sensing signal; and a logic circuit, coupled between the sensing circuit and the first field plate electrode, providing the second control signal according to the sensing signal, Wherein, when the sensing signal is lower than a preset value in response to a light load period of the power conversion circuit, the logic circuit maintains the second control signal at a fixed operating voltage. A control method for a power conversion circuit, wherein the power conversion circuit includes a first switching element and has a first gate to receive a first control signal and a first field plate electrode to receive a second control signal, wherein the control Methods include: Determine the load condition of the power conversion circuit; and During a reload period of the power conversion circuit, the rising edge of the high-potential period of the second control signal is earlier than the rising edge of the high-potential period of the first control signal, and the high-potential period of the second control signal is earlier than the rising edge of the high-potential period of the second control signal. The first control signal has a long high potential period. The control method of claim 8, wherein during the overload period of the power conversion circuit, the falling edge of the high-potential period of the second control signal is later than the falling edge of the high-potential period of the first control signal. The control method as described in request item 8 also includes: When a sensing signal related to one of the current flowing through the first switching element or the temperature of the first switching element is lower than a preset value in response to the light load period of the power conversion circuit, the second The control signal is maintained at a fixed operating voltage.

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