TW202407876A - Semiconductor structure and method for forming the same - Google Patents

Abstract

A method for forming a semiconductor structure, including providing a substrate having an opening in or on the substrate. The method further includes conformally forming a barrier layer in the opening and on the substrate and performing an implantation process to implant a dopant into the barrier layer. A cap layer is conformally formed on the barrier layer and performing an annealing process to diffuse the dopant into the grain boundaries of the barrier layer. The cap layer is removed and the opening is filled with a conductive material.

Description

Semiconductor structures and methods of forming them

Embodiments of the present invention relate to semiconductor process technology, and in particular to methods of forming conductive components.

As the critical dimensions of semiconductor devices gradually shrink with development, the resistance of conductive components such as embedded word lines, contacts, or vias gradually increases. Therefore, the industry still needs to improve the resistance of related conductive components to achieve the goal of reducing critical dimensions while maintaining the performance of semiconductor devices. In existing technical methods, the resistance of related conductive components is reduced by reducing the thickness of the barrier layer or reducing the number of nucleation cycles of the conductive material. However, this may lead to risks such as peeling of the barrier layer/conductive material or increasing the threshold voltage (Vth) of the device.

Embodiments of the present invention provide a method for forming a semiconductor structure, which includes providing a substrate with an opening in or on the substrate; compliantly forming a barrier layer in the opening and on the substrate; and performing a implantation process to implant the dopant cloth into the resistor. in the barrier layer; conformably form a capping layer on the barrier layer; perform an annealing process to diffuse dopants into the grain boundaries of the barrier layer; remove the capping layer; and fill the openings with conductive material.

Embodiments of the present invention provide a method for forming a semiconductor structure, which includes providing a substrate with an opening in or on the substrate; conformably forming a barrier layer in the opening and on the substrate; forming a cover layer on the barrier layer, and the cover layer is The thickness above the bottom surface of the opening is less than the thickness of the cap layer above the top surface of the substrate; a implantation process is performed to implant the dopants through the cap layer and into the barrier layer; an annealing process is performed to diffuse the dopants into the barrier layer in the grain boundaries of the barrier layer; remove the capping layer; and fill the opening with conductive material.

Embodiments of the present invention provide a semiconductor structure, including a substrate with an opening in or on the substrate; a barrier layer lining the opening, in which the grain boundary trapping dopant of the barrier layer; and a conductive material filled in the opening .

In existing semiconductor technology, tungsten is usually used as a material for conductive components such as embedded word lines, contact plugs, via holes, etc., and is usually formed using a deposition process with better filling capabilities, such as chemical vapor deposition. process. As the line width decreases, the related conductive components face the problem that the resistance of the conductive material will increase. Embodiments of the present invention provide a method for forming a conductive material with larger grains. The size of the grains will affect the number of grain boundaries (that is, the smaller the grains, the smaller the grain boundaries. (the larger the grains, the fewer the grain boundaries). When electrons pass through a conductive material with larger grains, they will be hindered by less grain boundaries. Therefore, forming a conductive material with larger grains can reduce the damage of related components. resistance, resulting in a semiconductor structure with high conductivity.

FIG. 1 is a schematic cross-sectional view of a semiconductor structure 10 according to a first embodiment of forming contact plugs or via holes according to the present disclosure. According to an embodiment of the present disclosure, a substrate 100 is provided, and the substrate 100 has an opening 120 thereon. The conductor layer 105 and the dielectric layer 110 are sequentially formed on the substrate 100, and the opening 120 is a contact opening provided in the dielectric layer 110, and exposes a portion of the top surface of the conductor layer 105. In some embodiments, the substrate 100 may be an elemental semiconductor substrate, a compound semiconductor substrate, or an alloy semiconductor substrate. In other embodiments, the substrate 100 may be an insulator-on-semiconductor substrate.

Continuing to refer to FIG. 1 , a barrier layer 130 is formed in the opening 120 and on the substrate 100 . The barrier layer 130 can ensure that the subsequently formed conductive material will not diffuse into the substrate 100 or the dielectric layer 110 . Before forming the barrier layer 130, the adhesive layer 124 can be compliantly formed in the opening 120 and on the substrate 100, and the barrier layer 130 is compliantly formed on the adhesive layer 124 to avoid interference between the barrier layer 130 and the substrate 100. Strip. In some embodiments, barrier layer 130 includes a columnar crystal structure with columnar grain boundaries 132 (see Figure 4 below). In some embodiments, the material of the barrier layer 130 may be TiN, TaN, WN, TaSiN, or TiSiN. In the first embodiment, the material of the adhesive layer 124 may be Ti or Ta.

FIG. 2 is a schematic cross-sectional view of the semiconductor structure 10 performing the implantation process 140 according to the first embodiment. According to the embodiment of the present disclosure, an implantation process 140 is performed to implant the dopant 135 into the barrier layer 130 . In some embodiments, the energy range of the implantation process 140 is 100 eV to 10 MeV, and the dose range of the dopant 135 of the implantation process 140 is 1E10 atoms/cm ² to 1E18 atoms/cm ² . In some embodiments, dopant 135 is boron (B).

FIG. 3 is a schematic cross-sectional view of the semiconductor structure 10 after the capping layer 150 is formed according to the first embodiment. After the implantation process 140 is performed, the capping layer 150 is compliantly formed on the barrier layer 130 . The capping layer 150 can prevent the dopants 135 from escaping out of the barrier layer 130 during the subsequent annealing process. In the first embodiment and the second embodiment, the cover layer 150 may have a uniform thickness. In some embodiments, the capping layer 150 having a uniform thickness in the first and second embodiments may be formed using atomic layer deposition (ALD) or other conformal chemical vapor deposition (conformal CVD), including The capping layer 150 with a uniform thickness is formed under conditions of low deposition rate, low gas flow, long mean free path (MFP), low pressure, and low temperature. In some embodiments, the material of the capping layer 150 may be SiN, SiO2, SiCN, SiC, or SiON.

FIG. 4 illustrates a partially enlarged cross-sectional view of the semiconductor structure 10 in FIG. 3 at block A. As shown in FIG. After the capping layer 150 is formed, the implanted dopants 135 are still randomly distributed throughout the grains of the barrier layer 130 . FIG. 5 shows a partially enlarged cross-sectional view of the semiconductor structure 10 in FIG. 3 after performing the annealing process 155 in block A. As shown in FIG. After the capping layer 150 is formed, an annealing process 155 is performed, so that the dopants 135 diffuse from the grains of the barrier layer 130 to the grain boundaries 132 of the barrier layer 130 due to the temperature increase, and the capping layer 150 prevents the dopants 135 from escaping. Diffusion barrier layer 130 . In some embodiments, the dopant 135 may diffuse into the columnar grain boundaries 132 of the barrier layer 130 . After performing the annealing process, the capping layer 150 may then be removed from the top surface of the barrier layer 130 using a process such as a dry etching process or a wet etching process. In some embodiments, the temperature of the annealing process 155 ranges from 200°C to 400°C, and the duration of the annealing process 155 ranges from 10 minutes to 360 minutes.

FIG. 6 is a schematic cross-sectional view after forming the conductive material layer 160 in the semiconductor structure 10 according to the first embodiment of the present disclosure. FIG. 7 illustrates a partially enlarged cross-sectional view of the semiconductor structure 10 in FIG. 6 at block A. As shown in FIG. After removing the cap layer 150 , a conductive material layer 160 is formed on the barrier layer 130 . In some embodiments, because the conductive material layer 160 is formed at a high temperature, at least part of the dopant 135 will diffuse from the grain boundaries 132 of the barrier layer 130 to the surface of the barrier layer 130 that contacts the conductive material layer 160 . In some embodiments, the temperature at which the conductive material layer 160 is formed is greater than or equal to the temperature of the annealing process 155 . In some embodiments, the temperature at which conductive material layer 160 is formed ranges from 300°C to 400°C. In some embodiments, conductive material layer 160 is tungsten (W).

Continuing to refer to FIG. 7 , the formation of the conductive material layer 160 may include a nucleation step. During the formation of the conductive material layer 160, the dopants 135 diffused from the grain boundaries 132 of the barrier layer 130 to the surface of the barrier layer 130 will enable the conductive material layer 160 to form more solid particles when nucleating and growing on the surface of the barrier layer 130. The high concentration of adatoms will enable the conductive material layer 160 to form larger grains after nucleation and improve the resistance of the final semiconductor structure 10 . It is worth noting that after the conductive material layer 160 is formed, part of the dopant 135 is still trapped in the grain boundaries 132 of the barrier layer 130 . In addition, since part of the dopant 135 is still trapped in the grain boundary 132 of the barrier layer 130, the semiconductor structure 10 can measure the content of the dopant 135 in the barrier layer 130 through element distribution analysis.

FIG. 8 is a schematic cross-sectional view of the semiconductor structure 10 after a planarization process according to the first embodiment of the present disclosure. After the conductive material layer 160 is formed, a planarization process is performed to expose the top surface of the dielectric layer 110 , thereby forming the conductive material 165 . Conductive material 165 has grain boundaries 162, which can be used to measure the size of the grains. In some embodiments, after the conductive material 165 is formed, its grain size ranges from about 10 nanometers to about 300 nanometers.

The first embodiment provides a method of forming conductive material 165 with larger grains using dopants 135 . After the planarization process is performed, the semiconductor structure 10 can continue to undergo further processes, such as forming metal interconnect structures to connect various components within the substrate 100 , and the conductive material 165 can serve as contact plugs or vias for the semiconductor device, where No more details.

The following describes the second embodiment of the present disclosure with reference to Figures 9-10. The second embodiment is similar to the first embodiment. The difference is that the first embodiment is used to form contact plugs or via holes in the back end of line (BEOL) process, while the second embodiment is used to form internal Buried character lines. FIG. 9 is a second embodiment of forming buried word lines according to the present disclosure, illustrating a schematic cross-sectional view of the semiconductor structure 20 . The opening 120 is a word line trench provided in the substrate 100. The oxide layer 126 can be formed first in the opening 120 and on the substrate 100 to prevent the subsequently formed barrier layer 130 from peeling off. In the second embodiment, the material of the oxide layer 126 may be SiO ₂ , SiN, or SiON. After the barrier layer 130 is formed, the second embodiment may continue to perform processes such as those described in FIGS. 2 to 8 above, which will not be repeated here. FIG. 10 is a schematic cross-sectional view of the semiconductor structure 20 after a planarization process according to the second embodiment of the present disclosure. After the conductive material layer 160 is formed, a planarization process is performed to expose the top surface of the substrate 100, thereby forming the conductive material 165.

As described above, the second embodiment provides a formation method using the dopant 135 to form the conductive material 165 with larger grains. In the second embodiment, after performing the planarization process, the semiconductor structure 20 can continue to undergo further processes, such as forming transistors and metal interconnect structures, and the conductive material 165 can serve as embedded word lines of the memory device. No further details will be given here.

The third embodiment of the present disclosure will be described below with reference to Figures 11-14B. FIG. 11 is a schematic cross-sectional view of a semiconductor structure 30 according to a third embodiment of forming contact plugs or via holes according to the present disclosure. The third embodiment is similar to the first embodiment, but the difference is that the first embodiment performs the implantation process 140 first and then forms the cap layer 150 , while the third embodiment first forms the cap layer 150 ′ with uneven thickness. , and then perform the implantation process 140. First, the conductor layer 105 and the dielectric layer 110 are sequentially formed on the substrate 100 . Next, the adhesive layer 124 and the barrier layer 130 are conformably formed in the opening 120 and on the substrate 100 , and a cover layer 150 ′ with uneven thickness is formed on the barrier layer 130 , and the cover layer 150 ′ is formed on the bottom surface of the opening 120 The upper thickness T1 will be less than the thickness T2 of the capping layer 150' above the top surface of the dielectric layer 110. In some embodiments, the capping layer 150' with uneven thickness of the third embodiment may use physical vapor deposition (PVD), chemical vapor deposition (CVD), or other processes that can form a film layer with low step coverage. The formation includes forming the capping layer 150' with a non-uniform thickness under conditions of high deposition rate, high gas flow, short mean free path (MFP), high pressure, and high temperature. In some embodiments, the material of the capping layer 150' may be SiN, SiO ₂ , SiCN, SiC, or SiON.

FIG. 12 is a schematic cross-sectional view of the semiconductor structure 30 performing the implantation process 140 according to the third embodiment of the present disclosure. After forming the capping layer 150', a implantation process 140 is performed to implant the dopant 135 through the capping layer 150' and into the barrier layer 130. Due to the difference in thickness of the capping layer 150', the dopant 135 will pass through the capping layer 150' of different thicknesses before reaching the barrier layer 130 during implantation, so that the dopant 135 can have different concentrations in the barrier layer 130. In other words, under the same implantation energy, if the dopant 135 only needs to pass through a smaller thickness (for example, the thickness T1 in Figure 11) to reach the barrier layer 130 (that is, the energy consumption is small) , then more dopants 135 will be implanted in this part of the barrier layer 130. If the dopants 135 need to pass through a larger thickness (for example, thickness T2 in Figure 11) to reach the barrier layer 130 (that is, the energy consumption is large), then less dopant 135 will be implanted in this part of the barrier layer 130 . In the third embodiment, the barrier layer 130 has a first concentration of dopants 135 on the bottom surface of the opening 120 , the barrier layer 130 has a second concentration of dopants 135 on the top surface of the dielectric layer 110 , and the first The concentration is greater than the second concentration.

FIGS. 13A and 13B respectively illustrate partial enlarged cross-sectional views of blocks A and B of the semiconductor structure 30 of FIG. 12 after performing the implantation process 140 . In Figure 13A, the dopant 135 only needs to pass through the thinner cap layer 150', so the barrier layer 130 below the thinner cap layer 150' has more dopants 135, while in Figure 13B In the figure, the dopant 135 needs to pass through the thicker capping layer 150', so the barrier layer 130 located under the thicker capping layer 150' has only a small amount of dopant 135. After the implantation process 140 is performed, the implanted dopants 135 will be randomly distributed throughout the grains of the barrier layer 130 .

FIGS. 14A and 14B respectively illustrate partial enlarged cross-sectional views of blocks A and B of the semiconductor structure 30 of FIG. 12 after performing the annealing process 155 . After the implantation process 140 is performed, an annealing process 155 is performed to allow the dopants 135 to diffuse from the grains of the barrier layer 130 into the grain boundaries 132 of the barrier layer 130 . The grain boundaries of the barrier layer 130 in Figure 14A have more dopants 135, while the grain boundaries of the barrier layer 130 in Figure 14B have less dopants 135. Therefore, the concentration difference of the dopant 135 in the barrier layer 130 will result in that when the conductive material layer 160 is subsequently formed, the portion with a high dopant concentration can have a greater formation rate, while the portion with a low dopant concentration has a smaller formation rate. rate.

After performing the annealing process 155, processes such as those described above in Figures 6 to 8 can continue. According to the embodiment of the present disclosure, the capping layer 150′ is then removed, and a conductive material layer 160 is formed on the barrier layer 130 to fill the opening 120 with the conductive material 165. In the third embodiment, similar to the first embodiment, at least part of the dopant 135 will diffuse from the grain boundary 132 of the barrier layer 130 to the surface where the barrier layer 130 contacts the conductive material layer 160 . However, in the third embodiment, due to the concentration difference of the dopant 135 in the barrier layer 130, there will be a different dopant concentration difference on the surface of the barrier layer 130, and thus change the conductive material layer. 160 formation rate. Because more dopants 135 are diffused from the bottom surface of the opening 120 than its sidewalls and the top surface of the dielectric layer 110 , a higher concentration of adatoms is allowed to form on the bottom surface of the opening 120 , so that the conductive material 165 is formed on the opening 120 The formation rate of the bottom surface may be greater than the formation rate of the conductive material 165 on the sidewalls of the opening 120 and on the top surface of the dielectric layer 110 . In other words, the rate at which the conductive material 165 fills the bottom of the opening 120 is greater than the rate at which the conductive material 165 seals the top of the opening 120 , which effectively improves the filling efficiency of the conductive material 165 and avoids the formation of a seam. The third embodiment provides a method of forming a conductive material with larger grains while avoiding the formation of seams in the openings 120 .

The fourth embodiment of the present disclosure will be described below with reference to Figures 15-16. The fourth embodiment is similar to the third embodiment. The difference is that the third embodiment is used to form contact plugs or via holes in the back-end process, while the fourth embodiment is used to form embedded word lines. FIG. 15 is a schematic cross-sectional view of a semiconductor device 40 according to a fourth embodiment of forming buried word lines according to the present disclosure. The opening 120 is a word line trench provided in the substrate 100 . As described in Figure 11 above, after the capping layer 150' with uneven thickness is first formed, the implantation process 140 is then performed. The thickness T1 of the cap layer 150' above the bottom surface of the opening 120 will be smaller than the thickness T2 of the cap layer 150' above the top surface of the dielectric layer 110.

FIG. 16 is a schematic cross-sectional view of the semiconductor structure 40 performing the implantation process 140 according to the fourth embodiment of the present disclosure. After forming the capping layer 150', a implantation process 140 is performed to implant the dopant 135 through the capping layer 150' and into the barrier layer 130. As described in FIG. 12 above, due to the difference in thickness of the capping layer 150', the dopant 135 will pass through the capping layer 150' of different thicknesses before reaching the barrier layer 130 during implantation, so that the dopant 135 is in the barrier layer 130. Medium energy has different concentrations. After the capping layer 150' is formed, processes such as those described in Figures 13A to 14B and Figures 6 to 8 can be continued, and the description will not be repeated here.

In summary, embodiments of the present invention provide a method for forming a conductive material with larger crystal grains and controlling the formation rate of the conductive material on the barrier layer through a implantation process. When electrons pass through a conductive material with larger grains, they are less hindered by grain boundaries. Therefore, forming a conductive material with larger grains can reduce the resistance of related components, resulting in a semiconductor structure with high conductivity. Controlling the formation rate of conductive material on the barrier layer can effectively avoid the formation of seams in the openings.

Although the present invention is disclosed in the foregoing embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

10: Semiconductor structure 20: Semiconductor structure 30: Semiconductor structure 40: Semiconductor structure 100:Substrate 105: Wire layer 110: Dielectric layer 120:Open your mouth 124:Adhesive layer 126:Oxide layer 130:Barrier layer 132:Grain Boundary 135:Dopant 140: Implantation process 150: cover 150’: cover 155: Annealing process 160: conductive material layer 162:Grain Boundary 165: Conductive materials A:Box B:Box T1:Thickness T2:Thickness

To make the features and advantages of the present invention more obvious and understandable, different embodiments are given below and are described in detail with reference to the accompanying drawings: 1 to 8 are schematic cross-sectional views of a semiconductor structure at different stages according to the first embodiment of the present disclosure. Figures 9 and 10 are schematic cross-sectional views of the semiconductor structure at different stages according to the second embodiment of the present disclosure. Figures 11, 12, 13A, 13B, 14A and Figure 14B are schematic cross-sectional views of a semiconductor structure at different stages according to the third embodiment of the present disclosure. Figures 15 and 16 are schematic cross-sectional views of a semiconductor structure at different stages according to a fourth embodiment of the present disclosure.

10: Semiconductor structure

100:Substrate

105: Wire layer

110: Dielectric layer

124:Adhesive layer

130:Barrier layer

162:Grain Boundary

165: Conductive materials

Claims (14)

A method for forming a semiconductor structure, including: Provide a substrate with an opening in or on the substrate; Compliantly forming a barrier layer in the opening and on the substrate; performing an implantation process to implant a doped cloth into the barrier layer; Compliantly forming a capping layer on the barrier layer; performing an annealing process to diffuse the dopant into the grain boundaries of the barrier layer; remove the covering; and Fill the opening with a conductive material. The method of forming a semiconductor structure as claimed in claim 1, wherein after the step of filling the conductive material, part of the dopant is still trapped in the grain boundary of the barrier layer. The method of forming a semiconductor structure according to claim 1, wherein a dielectric layer is further provided on the substrate, and the opening is a contact opening provided in the dielectric layer. The method of forming a semiconductor structure as claimed in claim 1, wherein the opening is a word line trench provided in the substrate. The method of forming a semiconductor structure as claimed in claim 1, wherein the dopant is boron and the conductive material is tungsten. The method of forming a semiconductor structure as claimed in claim 1, wherein the step of filling the conductive material includes: forming a conductive material layer on the barrier layer; and A planarization process is performed to expose the top surface of the substrate, wherein the temperature at which the conductive material layer is formed is greater than or equal to the temperature of the annealing process. The method of forming a semiconductor structure as claimed in claim 1, wherein in the step of filling the conductive material, at least part of the dopant is diffused from the grain boundary of the barrier layer to a surface of the barrier layer in contact with the conductive material. A method for forming a semiconductor structure, including: Provide a substrate with an opening in or on the substrate; Compliantly forming a barrier layer in the opening and on the substrate; Forming a capping layer on the barrier layer, the thickness of the capping layer above the bottom surface of the opening is less than the thickness of the capping layer above the top surface of the substrate; performing a implantation process to implant a dopant through the capping layer and into the barrier layer; performing an annealing process to diffuse the dopant into the grain boundaries of the barrier layer; remove the covering; and Fill the opening with a conductive material. The method of forming a semiconductor structure as claimed in claim 8, wherein the barrier layer has a first concentration of the dopant on the bottom surface of the opening, and the barrier layer has a second concentration of the dopant on the top surface of the substrate. quality, and the first concentration is greater than the second concentration. A semiconductor structure including: a substrate having an opening in or on the substrate; a barrier layer lining the opening, wherein the grain boundaries of the barrier layer trap a dopant; and A conductive material is filled in the opening. The semiconductor structure of claim 10, wherein a dielectric layer is further provided on the substrate, and the opening is a contact opening provided in the dielectric layer. The semiconductor structure of claim 10, wherein the opening is a word line trench disposed in the substrate. The semiconductor structure of claim 10, wherein the conductive material has a grain size ranging from about 10 nanometers to about 300 nanometers. The semiconductor structure of claim 10, wherein the barrier layer includes a columnar crystal structure.

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