TW202407668A - Pixel unit - Google Patents

Abstract

A pixel unit is provided. The pixel unit includes an amplitude setting circuit, a width setting circuit, an intermediate circuit, and a light source circuit. The amplitude setting circuit generates an amplitude setting signal in response to an amplitude scan signal. The width setting circuit generates an intermediate width setting signal in response to a width scan signal. The intermediate circuit is electrically connected to the width setting circuit, and the intermediate circuit generates a driving transistor enablement signal in response to the intermediate width setting signal. The light source circuit includes a driving transistor and a lighting circuit. The driving transistor is electrically connected to the amplitude setting circuit and the intermediate circuit. The driving transistor selectively generates a driving current according to the driving transistor enablement signal. The driving current is changed with the amplitude setting signal. The lightning circuit is electrically connected to the driving transistor. The driving current flows through the lightning circuit, and brightness of the lightning circuit is changed with the driving current.

Description

pixel unit

The present invention relates to a pixel unit, and in particular to a pixel unit that changes the amplitude and width of the driving current flowing through the light-emitting diode, thereby adjusting the luminous brightness.

Please refer to Figure 1A, which is a schematic diagram of a conventional pixel unit PXL(m, n) using an amplitude setting circuit pamCKT(m, n) and a width setting circuit pwmCKT(m, n) to adjust the brightness of a light emitting diode. The pixel unit PXL(m, n) includes: a light-emitting diode LED, an amplitude setting circuit pamCKT(m, n), an amplitude setting transistor Tamp, a width setting circuit pwmCKT(m, n), and a driving transistor Tdrv. In Figure 1A, the amplitude setting circuit pamCKT(m, n) is electrically connected to the gate of the amplitude setting transistor Tamp, and the width setting circuit pwmCKT(m, n) is electrically connected to the gate of the driving transistor Tdrv. The source and drain of the amplitude setting transistor Tamp are electrically connected to the supply voltage Vdd and the source of the driving transistor Tdrv respectively. The anode of the light-emitting diode LED is electrically connected to the drain of the driving transistor Tdrv, and the cathode is electrically connected to the ground voltage Vss. The purpose of this architecture is to use the amplitude setting circuit pamCKT(m, n) to fix the pulse amplitude of the driving current Idrv of the light-emitting diode LED at the optimal efficiency point, and to use the width setting circuit pwmCKT(m, n) to control the driving The pulse width of the current Idrv is controlled to regulate the brightness (gray scale) of the light-emitting diode LED.

Please refer to Figure 1B, which is a schematic diagram of the pulse wave of the driving current Idrv flowing through the pixel unit PXL(m, n). In Figure 1B, the vertical axis represents the drive current Idrv and the horizontal axis represents time. The driving current Idrv has a pulse waveform. Here, the pulse size of the driving current Idrv is defined as pulse amplitude (pulse amplitude) cAMP; and the pulse period of the driving current Idrv is defined as pulse width (pulse width) cPW. Among them, the brightness of the driving transistor Tdrv changes with the pulse amplitude cAMP and pulse width cPW of the driving current Idrv.

Please also see Figures 1A and 1B. Whether the amplitude setting transistor Tamp is turned on or not is controlled by the amplitude setting circuit pamCKT(m, n), and the pulse amplitude cAMP of the driving current Idrv changes with the degree of conduction of the amplitude setting transistor Tamp. On the other hand, whether the drive transistor Tdrv is turned on or not is controlled by the width setting circuit pwmCKT(m, n), and the pulse width cPW of the drive current Idrv changes according to the conduction state of the drive transistor Tdrv.

Ideally, the amplitude setting circuit pamCKT(m, n) controls the pulse amplitude cAMP of the driving current Idrv, and the width setting circuit pwmCKT(m, n) controls the pulse width cPW of the driving current Idrv, should be independent of each other. However, according to conventional technology, as the amplitude setting circuit pamCKT(m, n) changes the pulse width cPW of the driving current Idrv, the pulse amplitude cAMP of the driving current Idrv is also affected.

Please refer to Figure 2. The pixel unit PXL(m, n) using conventional technology uses the width setting circuit pwdCKT(m, n) to adjust the pulse width cPW. At the same time, the pulse amplitude of the driving current Idrv is also affected. Schematic diagram. Please also see Figures 1A and 2.

In Figure 2, the vertical axis is the drive current Idrv, the horizontal axis is time, and the waveforms WF1a, WF1b, and WF1c respectively correspond to the width setting circuit pwmCKT(m, n). The pulse width cPW of the drive current Idrv is set to cPW_1a, The situation of cPW_1b and cPW_1c. In an ideal situation, no matter the pulse width cPW of the driving current Idrv is set to any value, the pulse amplitude cAMP of the driving current Idrv should remain unchanged.

However, it can be seen from Figure 2 that when the drive current Idrv is set to the widest pulse width cPW_1a, the pulse amplitude cAMP_1a of the drive current Idrv is the highest; when the drive current Idrv is set to the second-widest pulse width cPW_1b, The pulse amplitude cAMP_1b of the driving current is slightly lower; and when the driving current Idrv is set to the narrowest pulse width cPW_1c, the pulse amplitude cAMP_1c of the driving current is the lowest. That is to say, when the pulse width cPW of the driving current Idrv gradually becomes smaller, the pulse amplitude cAMP of the driving current Idrv also gradually becomes smaller.

Therefore, the conventional technology cannot accurately control the pulse amplitude cAMP and pulse width cPW of the driving current Idrv. In conjunction, the light-emitting diode LED will exhibit a wavelength shift phenomenon when emitting light. Therefore, the user's visual experience when viewing the display screen will be affected by the phenomenon of color cast in the screen.

The present invention relates to a pixel unit, and in particular to a pixel unit that changes the amplitude and width of the driving current flowing through the light-emitting diode, thereby adjusting the luminance.

According to one aspect of the present invention, a pixel unit is provided. Includes: amplitude setting circuit, width setting circuit, relay circuit and light source circuit. The amplitude setting circuit generates an amplitude setting signal in response to the amplitude setting column scanning signal. The width setting circuit generates a relay width setting signal in response to the width setting column scan signal. The relay circuit is electrically connected to the width setting circuit, which generates a drive enable signal in response to the relay width setting signal. The light source circuit includes: driving transistor and light-emitting circuit. The driving transistor is electrically connected to the amplitude setting circuit and the relay circuit. The driving transistor selectively generates a driving current according to the driving enable signal. The drive current changes with the amplitude setting signal. The light-emitting circuit is electrically connected to the driving transistor. The driving current flows through the light-emitting circuit, and the brightness of the light-emitting circuit changes with the driving current.

In order to have a better understanding of the above and other aspects of the present invention, examples are given below and are described in detail with reference to the accompanying drawings:

As mentioned above, the conventional technology does not accurately control the driving current Idrv, which affects the brightness of the light-emitting diode. To this end, this disclosure improves the internal structure of the pixel unit PXL(m, n) and designs the pixel unit PXL(m, n) in which the pulse amplitude cAMP is not affected by the pulse width cPW of the driving current Idrv. In the following embodiments, it is assumed that the pixel unit PXL(m, n) uses a PMOS transistor. However, in practical applications, there is no need to limit the type of transistor used to implement the pixel unit PXL(m, n).

Please refer to Figure 3, which is a block diagram of a display device using the present disclosure. The display device 30 according to the concept of the present disclosure includes: a timing controller 31, a source driving circuit 33, a gate control circuit 35 and a display panel 37. The timing controller 31 is electrically connected to the source driving circuit 33 through a plurality of source control lines Sctl_src, and is electrically connected to the gate control circuit 35 through a plurality of gate control lines Sctl_gc. For ease of explanation, the same symbols are used here to represent signal lines and signals transmitted on the signal lines. For example, Sctl_srcw represents both the source control line and the source control signal. The timing controller 31 uses the source control signal Sctl_src to control the source driving circuit 33 to generate a row-direction control signal to the display panel 37 , and uses the gate control signal Sctl_gc to control the gate control circuit 35 to generate a column-direction control signal to the display panel 37 .

The display panel 37 includes pixel units PXL(1, 1)˜PXL(M, N) arranged in M rows and N columns. In this article, the position of the pixel unit PXL in the array is represented in coordinate format. For example, PXL(m, n) represents the pixel unit located in the m-th row and n-th column. Among them, m, n, M, and N are positive integers, and m≦M and n≦N. For the convenience of explanation, the examples in this article take the pixel unit PXL(m, n) as an example. The other pixel units PXL(1~(m-1), 1~(n-1)), PXL((( The structures of m+1)~M, (n+1)~N) are similar to the pixel unit PXL(m, n).

For ease of understanding, in Figure 3, the signals related to the pixel unit PXL(m, n) are marked, including: external compensation signal SSL[m], amplitude data voltage aDAT[m], width data voltage wDAT[m], Amplitude setting column scanning signal ampSCAN[n], width setting column scanning signal wdSCAN[n], light emission control signal EM[n], and sweep signal Sweep[n]. To simplify the diagram, Figure 3 does not depict signals with fixed voltage values (ie, amplitude supply voltage Vdd_a, width supply voltage Vdd_w, set voltage Vset, ground voltage Vss, gate conduction voltage _VGH ). The purpose and function of each signal will be explained in Figures 4A and 4B.

Next, this article will explain the structure of the display panel 37 shown in Figure 3 and the internal circuit of the pixel unit. The following will describe how the pixel unit PXL(m, n) operates with the control signals related to the setting of the amplitude and width with reference to the internal structure of the pixel unit PXL(m, n).

Please refer to Figure 4A, which is a schematic diagram of an embodiment of the pixel unit PXL(m, n) of the present disclosure. The pixel unit PXL(m, n) includes: characteristic compensation transistors Tacmp, Twcmp, light source circuit LT(m, n), amplitude setting circuit amCKT(m, n) and width setting module pwmMDL(m, n). The characteristic compensation transistor Tacmp, the amplitude setting circuit amCKT(m, n) and the light source circuit LT(m, n) are all electrically connected to the end point Ncmp. The width setting module pwmMDL(m, n) is electrically connected to the light source circuit LT(m, n). The characteristic compensation transistor Twcmp is electrically connected to the width setting module pwmMDL(m, n). Among them, the amplitude setting circuit amCKT(m, n) is used to set the size (amplitude) of the driving current Idrv of the light source circuit LT(m, n); the width setting module pwmMDL(m, n) is used to set the light source circuit LT(m , n) period (width) of the drive current Idrv. Next, the internal components and connection relationships of the amplitude setting circuit amCKT(m, n), the width setting module pwmMDL(m, n) and the light source circuit LT(m, n) will be described respectively.

The amplitude setting circuit amCKT(m, n) includes: amplitude setting transistors Ta1, Ta2, Ta3, Tamp and bias capacitor Ca. The source of the amplitude setting transistor Ta1 receives the amplitude data voltage aDAT[m], the gate receives the amplitude setting column scan signal ampSCAN[n], and the drain is electrically connected to the terminal Na2. The source of the amplitude setting transistor Ta2 receives the width supply voltage Vdd_w, the gate receives the amplitude setting column scan signal ampSCAN[n], and the drain is electrically connected to the terminal Na1. The source of the amplitude setting transistor Ta3 receives the amplitude supply voltage Vdd_a, the gate receives the light emission control signal EM[n], and the drain is electrically connected to the terminal Na1. The source of the amplitude setting transistor Tamp is electrically connected to the terminal Na1, the gate is electrically connected to the terminal Na2, and the drain is electrically connected to the terminal Ncmp. Both ends of the bias capacitor Ca are electrically connected to terminals Na1 and Na2 respectively.

The operation of the amplitude setting circuit amCKT(m, n) can be briefly described as follows. The two ends of the bias capacitor Ca form an amplitude setting voltage difference ΔVca as the amplitude setting transistors Ta1, Ta2, and Ta3 are turned on. Among them, the amplitude setting voltage difference ΔVca is equivalent to the difference between the amplitude supply voltage Vdd_a and the amplitude data voltage aDAT[m] (ΔVca=Vdd_a-aDAT[m]). In addition, the amplitude setting voltage difference ΔVca determines whether the amplitude setting transistor Tamp is turned on. When the amplitude setting voltage difference ΔVca is greater than the critical voltage of the amplitude setting transistor Tamp, the amplitude setting transistor Tamp will be turned on. Moreover, the magnitude of the current flowing through the amplitude setting transistor Tamp changes with the amplitude setting voltage difference ΔVca.

The width setting module pwmMDL(m, n) includes: width setting circuit pwmCKT(m, n) and relay circuit imdCKT(m, n). The width setting circuit pwmCKT(m, n) includes: width setting transistors Tw1, Tw2, Tw3, Twd and bias capacitor Cw. The relay circuit imdCKT(m, n) includes: bias capacitor Cm and relay transistors Tm1, Tm2, Tm3, and Tm4.

First, the connection relationship of components in the width setting circuit pwmCKT(m, n) will be explained. Both ends of the width setting transistor Tw1 are electrically connected to the end point Nw1 and the gate conduction voltage V _GH respectively. Among them, the endpoint Nw1 receives the sweep signal Sweep[n]. Both ends of the width setting transistor Tw2 are electrically connected to the terminal point Nw2 and the width data voltage wDAT[m] respectively. Both ends of the width setting transistor Tw3 are electrically connected to the end point Nm1 and the setting voltage Vset respectively. The gates of the width setting transistors Tw1, Tw2, and Tw3 are all controlled by the width setting column scan signal wdSCAN[n]. Both ends of the width setting transistor Twd are electrically connected to the width supply voltage Vdd_w and the terminal Nm1 respectively, and the gate of the width setting transistor Twd is electrically connected to the terminal Nw2. Both ends of the bias capacitor Cw are electrically connected to the terminals Nw1 and Nw2 respectively.

When the width setting transistor Tw1 is turned on, the end point Nw1 is the gate turn-on voltage V _GH . When the width setting transistor Tw2 is turned on, the endpoint Nw2 is the width data voltage wDAT[m]. Whether the width setting transistor Twd is turned on or not depends on the voltage difference between the width supply voltage Vdd_w and the end point Nw2. Among them, the voltage of the terminal Nw2 is related to the voltage difference ΔVcw between the sweep signal Sweep[n] and the bias capacitor Cw. When the width setting transistor Twd is turned on, the voltage of the terminal Nm1 is the width supply voltage Vdd_w.

Next, the connection relationship of the components in the relay circuit imdCKT(m, n) will be explained. Both ends of the bias capacitor Cm are electrically connected to the width supply voltage Vdd_w and the end point Nm1 respectively. The sources of the relay transistors Tm1 and Tm3 are both electrically connected to the width supply voltage Vdd_w, and the gates are both electrically connected to the end point Nm1. The drain electrode of the relay transistor Tm1 is electrically connected to the terminal point Nm2, and the drain electrode of the relay transistor Tm3 is electrically connected to the terminal point Nm3. The source of the relay transistor Tm2 is electrically connected to the end point Nm2, the gate receives the light emission control signal EM[n], and the source is electrically connected to the set voltage Vset. The source of the relay transistor Tm4 is electrically connected to the terminal Nm3, the gate is electrically connected to Nm2, and the source is electrically connected to the set voltage Vset.

The voltage difference ΔVcm across the bias capacitor Cm is equivalent to the voltage difference between the width supply voltage Vdd_w and the end point Nm1 (ie, ΔVcm=Vdd_w-Nm1). Moreover, since both ends of the bias capacitor Cm are electrically connected to the sources and gates of the relay transistors Tm1 and Tm3, the conductive state of the relay transistors Tm1 and Tm3 is affected by the voltage difference between the two ends of the bias capacitor Cm. ΔVcm influence. Since the width supply voltage Vdd_w is a constant value, the voltage difference ΔVcm of the bias capacitor Cm depends on the voltage of the terminal Nm1. Therefore, this article defines the signal of the endpoint Nm1 as the intermediate width setting signal (intermediate width setting signal).

Because the gate of the relay transistor Tm2 receives the light-emitting control signal EM[n], the relay transistor Tm2 is only turned on during the light-emitting period dT_EM, and remains off during the remaining periods. Once the relay transistor Tm2 is turned on, the terminal Nm2 will drop to the set voltage Vset. At the same time, the relay transistor Tm4 is also turned on because the gate is lowered to the set voltage Vset. Furthermore, the terminal Nm3 also decreases to the set voltage Vset as the relay transistor Tm4 is turned on, so that the drive enable signal Son is equal to the set voltage Vset (Son=Vset); and the drive transistor Tdrv is also turned on.

The light source circuit LT(m, n) includes: a driving transistor Tdrv and a light-emitting circuit. The light-emitting circuit may be various types of light-emitting diode LEDs that use current to control brightness. For example, organic light-emitting diode (OLED for short), sub-millimeter light-emitting diode (Mini Light Emitting Diode for short), or micro light-emitting diode (Micro Light Emitting Diode for short) for μLED) etc.

The source of the driving transistor Tdrv is electrically connected to the terminal Ncmp, the gate is electrically connected to the terminal Nm3, and the drain is electrically connected to the anode of the light-emitting diode LED. The cathode of the light emitting diode LED is electrically connected to the ground voltage Vss. When the driving transistor Tdrv is turned on, a driving current Idrv flowing through the light-emitting diode LED is generated. The brightness of the light-emitting diode LED changes with the amplitude and width of the driving current Idrv. Whether the driving transistor Tdrv is turned on or not depends on the driving enable signal Son, and the size of the driving current Idrv depends on the voltage difference (V _SG ) between the source and gate of the amplitude setting transistor Tamp.

According to the different signal attributes, in this article, the signals related to the pixel unit PXL(m, n) can be divided into several categories, as shown in Table 1.

Table 1 Signal properties Signal example Provide pixel units PXL(1, 1)~PXL(M, N) and have signals with fixed voltage values Amplitude supply voltage Vdd_a (for example, 10V), width supply voltage Vdd_w (for example, 10V), set voltage Vset (voltage value close to Vss), ground voltage Vss, gate conduction voltage _VGH Changes with the number of rows (m) where the pixel unit PXL(m, n) is located. External compensation signal SSL[m], amplitude data voltage aDAT[m] (for example, 0~5V), width data voltage wDAT[m] (for example, 0~5V) Changes with the number of columns (n) where the pixel unit PXL(m, n) is located. Amplitude compensation enable signal aCMP_en[n], width compensation enable signal wCMP_en[n], amplitude setting column scanning signal ampSCAN[n], width setting column scanning signal wdSCAN[n], luminescence control signal EM[n], scan SignalSweep[n]

The gate of the characteristic compensation transistor Tacmp receives the amplitude compensation enable signal aCMP_en[n], and the gate of the characteristic compensation transistor Twcmp receives the width compensation enable signal wCMP_en[n]. Moreover, one end of the characteristic compensation transistors Tacmp and Twcmp receives the external compensation signal SSL[m]. The characteristic compensation transistors Tacmp and Twcmp are turned on only during the characteristic compensation period dT_cmp. After the characteristic compensation period dT_cmp ends, the characteristic compensation transistors Tacmp and Twcmp remain off. Therefore, the characteristic compensation transistors Tacmp and Twcmp do not affect the generation of the drive current Idrv. Therefore, the compensation transistors Tacmp and Twcmp will not be repeatedly drawn in Figure 4A with the characteristics of the bottom-line type in Figure 4A.

In short, the timing controller 31 uses the characteristic compensation transistor Tacmp to sense the characteristics of the amplitude setting transistor Tamp in the pixel units PXL(1, 1)~PXL(M, N) during the characteristic compensation period dT_cmp, and utilizes the characteristics The compensation transistor Twcmp senses the characteristics of the width setting transistor Twd in the pixel units PXL(1, 1)~PXL(M, N). Thereafter, the timing controller 31 adjusts the control method of the pixel units PXL(1, 1)~PXL(M, N) according to the sensing result of the characteristic compensation period dT_cmp.

For example, assume that the pixel units PXL(1, 1) and PXL(2, 1) both correspond to the same display brightness. Then, based on the different voltage amplitudes required for compensation, the timing controller 31 subsequently provides the amplitude data voltages aDAT[1], aDAT[2] and the width data voltages wDAT[1], wDAT[2] to the two pixel units. The voltage value of ] may vary depending on the sensing result of dT_cmp during characteristic compensation.

Please refer to Figure 4B, which is generated by the gate control circuit and is used to control the pixel units PXL(1~M, n), PXL(1~M) in the nth column and (n+1)th column of the present disclosure. , n+1) waveform diagram of the control signal in the column direction. In this diagram, the waveforms from top to bottom are: the amplitude setting column scanning signal ampSCAN[n] corresponding to the pixel unit PXL(1~M, n), the width setting column scanning signal wdSCAN[n], and the luminescence Control signal EM[n], sweep signal Sweep[n], as well as amplitude setting column scanning signal ampSCAN[n+1] and width setting column scanning signal wdSCAN corresponding to the pixel unit PXL(1~M, n+1) [n+1], luminescence control signal EM[n+1], sweep signal Sweep[n+1]; the horizontal axis is time.

According to the concept of the present disclosure, the column-direction related control signals generated by the gate control circuit 35 are synchronously transmitted to the pixel units located in the same column. On the other hand, the source driving circuit 33 provides corresponding amplitude data voltages aDAT[1]~aDAT according to the number of rows (m, where m=1~M) of the pixel unit PXL(1~M, n). [M] and the width data voltage wDAT[1]~wDAT[M] to the pixel units PXL(1~M, n) located in the same column but different rows.

Figure 4B defines the period related to the brightness control of the M pixel units PXL(1~M, n) located in the nth column as the pixel setting and display period dT_pxl[n] (time points t1~t10). Moreover, the period related to the brightness control of the M pixel units PXL(1~M, n+1) located in the (n+1)th column is defined as the pixel setting and display period dT_pxl[n+1] (time point t3~ t11).

The pixel setting and display period dT_pxl[n] corresponding to the pixel unit PXL(1~M, n) in the nth column includes: the amplitude setting period dT_amp (time points t1~t2), the width setting period dT_wd (time points t2~t3), The lighting period is dT_EM (time point t4~t8), and the off period is dT_OFF (time point t8~t10). The pixel setting and display period dT_pxl[n+1] corresponding to the pixel unit PXL(1~M, n+1) in the (n+1)th column includes: the amplitude setting period dT_amp (time points t3~t5), the width setting period dT_wd (time point t5~t6), light-emitting period dT_EM (time point t7~t9), off period dT_OFF (time point t9~t11).

The gate control circuit 35 generates control signals corresponding to each column column by column. Therefore, each section of the pixel setting and display period dT_pxl[n] and each section of the pixel setting and display period dT_pxl[n+1] are maintained. Fixed column selection time difference ΔTr. In Figure 4B, a buffer period Δt is drawn between the width setting period dT_wd and the light-emitting period dT_EM. Whether or not Δt is set during the buffering period, as well as the number and location of the settings, do not need to be limited.

To put it further, the amplitude setting column scanning signals ampSCAN [n] and ampSCAN [n+1] respectively corresponding to the pixel units PXL(1~M, n) and PXL(1~M, n+1) are different from each other. The column selection time difference ΔTr; the width setting column scanning signals wdSCAN[n] and wdSCAN[n+1] corresponding to the pixel units PXL(1~M, n) and PXL(1~M, n+1) respectively differ by one period from each other. Column selection time difference ΔTr; the light-emitting control signals EM[n] and EM[n+1] corresponding to the pixel units PXL(1~M, n) and PXL(1~M, n+1) respectively differ from each other by a column selection period The time difference ΔTr; and, the sweep signals Sweep[n] and Sweep[n+1] corresponding to the pixel units PXL(1~M, n) and PXL(1~M, n+1) respectively are different from each other by one column selection. Time difference ΔTr. The column selection time difference ΔTr is equivalent to the sum of the amplitude setting period dT_amp and the width setting period dT_wd. In practical applications, it can be assumed that the lengths of the amplitude setting period dT_amp and the width setting period dT_wd are equal to the period Th of a horizontal synchronization pulse. Accordingly, the column selection time difference ΔTr is equivalent to twice the period Th of the horizontal synchronization pulse wave. That is, ΔTr=2*Th.

Since the control signals generated by the gate control circuit 35 and corresponding to each column differ only in time order, only the control signals related to the pixel unit PXL(1~M, n) located in the nth column will be described below. During the amplitude setting period dT_amp (time point t1~t2), the source driving circuit 33 simultaneously transmits the amplitude data voltages aDAT[1]~aDAT[M] to the M pixel units PXL (1~M, also located in the nth column) respectively. n). Moreover, during the width setting period dT_wd (time point t2~t3), the source driving circuit 33 simultaneously transmits the width data voltages wDAT[1]~wDAT[M] to the M pixel units PXL (1~ M, n). Regarding the amplitude setting column scanning signal ampSCAN[n], the width setting column scanning signal wdSCAN[n], the emission control signal EM[n], and the sweep signal Sweep[n], the amplitude setting period dT_amp, the width setting period dT_wd, and the emission period dT_EM , the changes in dT_OFF during the shutdown period can be found in Table 2.

Table 2 Amplitude setting period dT_amp Width setting period dT_wd Luminescence period dT_EM dT_OFF during shutdown Schema Picture 5 Picture 6 Figure 7A, 7B Picture 8 ampSCAN[n] V _GL V _GH V _GH V _GH wdSCAN[n] V _GH V _GL V _GH V _GH EM[n] V _GH V _GH V _GL V _GH Sweep[n] V _GH V _{GH VGHàVGL ​} V _GH

Please refer to Figure 5, which is a schematic diagram of the internal components of the pixel unit PXL(m, n) disclosed in the present disclosure, and dT_amp operates in response to the control signal in the column direction during the amplitude setting period. Please also see Figures 4B and 5 and Table 2. The following describes the operations of the amplitude setting circuit pamCKT(m, n), the width setting circuit pwdCKT(m, n), and the relay circuit imdCKT(m, n) during the amplitude setting period dT_amp.

In the amplitude setting circuit pamCKT(m, n), the amplitude setting column scan signal ampSCAN[n] received by the amplitude setting transistors Ta1 and Ta2 due to the gate is the gate closing voltage V _GL (ampSCAN[n]=V _GL ) The amplitude setting transistor Ta3 is turned on because the light-emitting control signal EM[n] received by the gate is the gate conduction voltage V _GH (EM[n]=V _GH ). As the amplitude setting transistors Ta1 and Ta2 are turned on, the voltage of the terminal Na1 is the amplitude supply voltage Vdd_a, and the voltage of the terminal Na2 is the amplitude data voltage aDAT[m]. Since both ends of the capacitor Ca are electrically connected to the terminals Na1 and Na2 respectively, the capacitor Ca will accumulate charges according to the voltage difference between the amplitude supply voltage Vdd_a and the amplitude data voltage aDAT[m] (amplitude setting voltage difference ΔVca). Furthermore, since the source and gate of the amplitude setting transistor Tamp are electrically connected to the terminals Na1 and Na2 respectively, the amplitude setting transistor Tamp is turned on due to the voltage difference between the amplitude supply voltage Vdd_a and the amplitude data voltage aDAT[m]. . However, since the amplitude setting transistor Ta3 is turned off during the amplitude setting period dT_amp, no current flows through the amplitude setting transistor Tamp.

In the width setting circuit pwdCKT(m, n), the width setting transistors Tw1, Tw2, and Tw3 receive the width setting column scan signal wdSCAN[n] due to the gate conduction voltage V _GH (wdSCAN[n]=V _GH ) and disconnect. In addition, the width setting transistor Twd is also turned off because the width setting transistor Tw2 is turned off. Therefore, the width setting circuit pwdCKT(m, n) does not operate during the amplitude setting period dT_amp.

In the relay circuit imdCKT(m, n), both the relay transistors Tm1 and Tm3 are turned off due to the turn-off of the width setting transistor Twd. The relay transistor Tm2 is turned off because the light-emitting control signal EM[n] received by the gate is the gate conduction voltage (EM[n]=V _GH ), and the relay transistor Tm4 is turned off as the relay transistor Tm2 Disconnect. Therefore, the relay circuit imdCKT(m, n) does not operate during the amplitude setting period dT_amp. Accordingly, the gate of the driving transistor Tdrv is in a floating state during the amplitude setting period dT_amp and is not turned on, and the light-emitting diode LED does not emit light during the amplitude setting period dT_amp.

Please refer to Figure 6, which is a schematic diagram of the internal components of the pixel unit PXL(m, n) of the present disclosure operating in response to the control signal in the column direction during the width setting period dT_wd. Please also see Figures 4B, 6 and Table 2. The following describes the operations of the amplitude setting circuit pamCKT(m, n), the width setting circuit pwdCKT(m, n), and the relay circuit imdCKT(m, n) during the width setting period dT_wd.

In the amplitude setting circuit pamCKT(m, n), the amplitude setting transistors Ta1 and Ta2 are switched because the amplitude setting column scanning signal ampSCAN[n] received by the gate is the gate conduction voltage V _GH (ampSCAN[n]=V _GH ). Turn off; the amplitude setting transistor Ta3 turns off because the light-emitting control signal EM[n] received by the gate is the gate conduction voltage V _GH (EM[n]=V _GH ). The amplitude setting transistor Tamp is turned on due to the voltage difference across the bias capacitor Ca. However, because the amplitude setting transistor Ta3 is turned off, there is still no current flowing through the amplitude setting transistor Tamp during the width setting period dT_wd.

In the width setting circuit pwdCKT(m, n), the width setting transistors Tw1, Tw2, and Tw3 are turned on because the width setting column scanning signal wdSCAN[n] is the gate closing voltage V _GL (wdSCAN [n]=V _GL ). The voltage at the endpoint Nw1 is the gate conduction voltage V _GH because the width setting transistor Tw1 is turned on; the voltage at the endpoint Nw2 is the width data voltage wDAT[m] because the width setting transistor Tw2 is turned on. Associatedly, the voltage difference between the two ends of the bias capacitor Cw depends on the gate conduction voltage V _GH and the width data voltage wDAT [m]. The relay width setting signal Nm1 becomes the set voltage Vset because the width setting transistor Tw3 is turned on. At the same time, the width setting transistor Twd is turned off because the voltage of the terminal Nw2 is the width data voltage wDAT[m].

In the relay circuit imdCKT(m, n), the gates of relay transistors Tm1 and Tm3 are both at the set voltage Vset. In addition, the relay transistor Tm2 is turned off because the light-emitting control signal EM[n] received by the gate is the gate conduction voltage V _GH (EM[n]=V _GH ). Since the voltage value of the set voltage Vset is quite close to the ground voltage Vss (Vset≈Vss), the relay transistors Tm1 and Tm3 will be turned on. As the relay transistor Tm1 is turned on, the terminal Nm2 will be set to the width supply voltage Vdd_w (Nm2=Vdd_w). Moreover, the relay transistor Tm4 receives the width supply voltage Vdd_w because its gate is connected to the terminal Nm2, so the relay transistor Tm4 is turned off. Therefore, the drive enable signal Son is the width supply voltage Vdd_w (Son=Vdd_w) because the relay transistor Tm3 is turned on. Accordingly, because the gate is at the width supply voltage Vdd_w during the amplitude setting period dT_amp, the driving transistor Tdrv is turned off during the amplitude setting period dT_amp, so the light-emitting diode LED does not emit light during the amplitude setting period dT_amp.

After the width setting period dT_Wd ends, the display panel 37 enters the light-emitting period dT_EM. During the emission period dT_EM, the amplitude setting column scan signal ampSCAN[n], the width setting column scan signal wdSCAN[n] and the emission control signal EM[n] are all set to the gate closing voltage V _GL , and the sweep signal Sweep[n ] Gradually decreases from the gate turn-on voltage V _GH to the gate turn-off voltage V _GL . Please also see Figures 4A, 4B, 7A, and 7B.

In the amplitude setting circuit pamCKT(m, n), the amplitude setting transistors Ta1 and Ta2 are switched because the amplitude setting column scanning signal ampSCAN[n] received by the gate is the gate conduction voltage V _GH (ampSCAN[n]=V _GH ). Off; the amplitude setting transistor Ta3 is turned on because the light-emitting control signal EM received by the gate is the gate closing voltage V _GL (EM[n]=V _GL ). Therefore, the voltage of terminal Na1 is the amplitude supply voltage Vdd_a (Na1=Vdd_a). On the other hand, the amplitude setting voltage difference ΔVca is the voltage difference between the end points Na1 and Na2 (ΔVca=Vdd_a-aDAT[m]).

Based on the relationship between the amplitude setting voltage ΔVca, the amplitude supply voltage Vdd_a and the amplitude data voltage aDAT[m] (ΔVca=Vdd_a-aDAT[m]), and the fact that the amplitude supply voltage Vdd_a is a constant value, the amplitude setting can be inferred The voltage difference ΔVca changes with the change of the amplitude data voltage aDAT[m]. That is, when the amplitude data voltage aDAT[m] is larger, the amplitude setting voltage difference ΔVca is smaller; when the amplitude data voltage aDAT[m] is smaller, the amplitude setting voltage difference ΔVca is larger. Since the source and gate of the amplitude setting transistor Tamp are connected across the two ends of the bias capacitor Ca, the amplitude setting voltage difference ΔVca will determine whether the amplitude setting transistor Tamp is turned on, and the amount of current when the amplitude setting transistor Tamp is turned on. .

Following the above, the amplitude setting voltage difference ΔVca is affected by the amplitude data voltage aDAT[m], and the amplitude setting voltage difference ΔVca further affects the current flowing through the amplitude setting transistor Tamp. Associatedly, the current flowing through the amplitude setting transistor Tamp will depend on the amplitude data voltage aDAT[m] received by the terminal Na2. Furthermore, when both the amplitude setting transistor Tamp and the driving transistor Tdrv are turned on, the current flowing through the amplitude setting transistor Tamp will also flow through the driving transistor Tdrv. In other words, the current value (magnitude) of the driving current Idrv changes with the amplitude data voltage aDAT[m] received by the terminal Na2. Therefore, the signal at the endpoint Na2 is defined as the amplitude setting signal here.

Next, the operation of the width setting circuit pwdCKT(m, n) during the light emission period dT_EM will be described. As can be seen from Figures 7A and 7B, the endpoint Nw1 in the width setting circuit pwdCKT(m, n) receives the sweep signal Sweep[n]. Therefore, the sweep signal Sweep[n] affects the operation of the width setting circuit pwdCKT(m, n). As the voltage of the sweep signal Sweep[n] gradually decreases, the voltage of the terminal Nw2 also gradually decreases. Associatedly, the width setting transistor Twd will switch from the off state to the on state. Therefore, the light-emitting period dT_EM can be further divided into two light-emitting phases STG1 and STG2 according to whether the width setting transistor Twd is turned on or not. In the light-emitting stage STG1, the width setting transistor Twd is in an off state (as shown in Figure 7A); and in the light-emitting stage STG2, the width setting transistor Twd is in an on state (as shown in Figure 7B). The following describes the differences between the width setting circuit pwdCKT(m, n) in the light-emitting phase STG1 and STG2 respectively.

Please refer to Figure 7A, which is a schematic diagram of the internal components of the pixel unit PXL(m, n) disclosed in the present disclosure, and STG1 operates in response to the control signal in the column direction during the light emitting phase. In the width setting circuit pwdCKT(m, n), the width setting column scanning signal wdSCAN[n] is the gate conduction voltage V _GH (wdSCAN[n]=V _GH ), causing the width setting transistors Tw1, Tw2, and Tw3 to turn off . Because one end of the bias capacitor Cw connected to Nw1 receives the decreasing sweep signal Sweep[n], the voltage of the end point Nw2 connected to the other end of the bias capacitor Cw also decreases. In the light-emitting stage STG1, the gate voltage of the width setting transistor Twd is not low enough, so the width setting transistor Twd remains off. Therefore, all transistors in the width setting circuit pwdCKT(m, n) are turned off during the light-emitting phase STG1.

In the relay circuit imdCKT(m, n), the relay transistors Tm1 and Tm3 are turned on due to the bias voltage at both ends of the bias capacitor Cm. Moreover, the relay transistor Tm2 is turned on because the gate is turned on because the light emission control signal EM[n]=gate closing voltage _VGL . The end point Nm2 is located at an intermediate value between the set voltage Vset and the width supply voltage Vdd_w because the relay transistors Tm1 and Tm2 are both turned on. Therefore, the voltage at the terminal Nm2 is not enough to turn on the relay transistor Tm4. In the light-emitting phase STG1, the voltage of the terminal Nm3 is determined by the turned-on relay transistor Tm3, that is, the width supply voltage Vdd_w. Therefore, the driving transistor Tdrv is turned off due to the gate receiving width supply voltage Vdd_w. Therefore, the light-emitting diode LED still does not emit light during the light-emitting stage STG1.

Please refer to Figure 7B, which is a schematic diagram of the internal components of the pixel unit PXL(m, n) of the present disclosure, and STG2 operates in response to the control signal in the column direction during the light emitting phase. In the width setting circuit pwdCKT(m, n), the width setting transistors Tw1, Tw2, and Tw3 receive the width setting column scan signal wdSCAN[n] due to the gate conduction voltage (wdSCAN[n]=V _GH ). And disconnect. Because one end of the bias capacitor Cw connected to the terminal Nw1 receives the decreasing sweep signal Sweep[n], the voltage of the terminal Nw2 connected to the other end of the bias capacitor Cw also decreases. In the light-emitting stage STG2, the gate voltage of the width setting transistor Twd has been reduced to a level sufficient to turn on the width setting transistor Twd. Therefore, the width setting transistors Tw1, Tw2, and Tw3 are turned off in the light-emitting phase STG2, but the width setting transistor Twd is turned on.

In the relay circuit imdCKT(m, n), the relay width setting signal Nm1 is turned on because the width setting transistor Twd is turned on, thereby supplying the width with voltage Vdd_w (Nm1=Vdd_w). Relatedly, the voltage difference between the source and gate of relay transistors Tm1 and Tm3 is both 0V. Therefore, relay transistors Tm1 and Tm3 are turned off. In addition, the relay transistor Tm2 is turned on because the light-emitting control signal EM[n] received by the gate is the gate closing voltage V _GL (EM[n]=V _GL ). The end point Nm2 is the set voltage Vset (Nm2=Vset) because the relay transistor Tm2 is turned on. Therefore, the voltage at the terminal Nm2 is sufficient to turn on the relay transistor Tm4. When the relay transistor Tm4 is turned on, the voltage of the terminal Nm3 gradually decreases to the set voltage Vset (Nm3=Son=Vset). Therefore, the driving transistor Tdrv is turned on because the driving enable signal Son is equal to the set voltage Vset (Son=Vset). Therefore, the driving transistor Tdrv will be turned on during the light-emitting phase STG2, so that the light-emitting diode LED starts to emit light during the light-emitting phase STG2.

Figures 7A and 7B have illustrated the operation mode of the pixel unit PXL(m, n) in the light-emitting phases STG1 and STG2. Next, Table 3 is used to summarize and compare the contents of Figures 7A and 7B.

table 3 period Luminescence period dT_EM stage Glow stage STG1 Glow stage STG2 Schema Figure 7A Figure 7B Amplitude setting circuit pamCKT(m, n) The amplitude setting transistors Ta1 and Ta2 are off, and the amplitude setting transistors Ta3 and Tamp are on. Width setting circuit pwdCKT(m, n) The width setting transistors Tw1, Tw2, Tw3, and Twd are all turned off. The width setting transistors Tw1, Tw2, and Tw3 are off, and the width setting transistor Twd is on. Relay circuit imdCKT(m, n) The relay transistor Tm4 is turned off, and the relay transistors Tm1, Tm2, and Tm3 are turned on. The turned-on relay transistor Tm3 makes the drive enable signal Son equal to the width supply voltage Vdd_w (Son=Vdd_w). The relay transistors Tm1 and Tm3 are turned off, and the relay transistors Tm2 and Tm4 are turned on. The turned-on relay transistor Tm4 makes the drive enable signal Son equal to the set voltage Vset (Son=Vset). Light source circuit LT(m, n) The driving transistor Tdrv is disconnected because Son=Vdd_w, and no driving current Idrv is generated. The drive transistor Tdrv is turned on because Son=Vset, generating a drive current Idrv

Further observation of Figures 7A and 7B shows that the voltage drop speed of the end point Nw2 affects the conduction speed of the width setting transistor Twd and the change speed of the relay width setting signal Nm1. Furthermore, as shown in Figure 6, the voltage of the endpoint Nw2 is determined by the width setting transistor Tw2 conducting the width data voltage wDAT[m] to the endpoint Nw2 during the amplitude setting period dT_amp. Since the gates of the relay transistors Tm1 and Tm3 are controlled by the relay width setting signal Nm1, the time when the relay transistors Tm1 and Tm3 switch from the on state to the off state also changes with the relay width setting signal Nm1. Varies with speed. Furthermore, when the relay transistors Tm1 and Tm3 switch from the on state to the off state, the voltage of the terminal Nm3 will change. Among them, the voltage change of the terminal Nm3 is equivalent to the voltage change of the driving enable signal Son. Therefore, the time point at which the driving transistor Tdrv starts to turn on also changes accordingly.

Please refer to Figure 8, which is a schematic diagram of the internal components of the pixel unit PXL(m, n) of the present disclosure operating in response to the control signal in the column direction during the off period dT_OFF. Please also see Figures 4B, 8 and Table 2. The following describes how the amplitude setting circuit pamCKT(m, n), width setting circuit pwdCKT(m, n), and relay circuit imdCKT(m, n) operate during the off period dT_OFF.

In the amplitude setting circuit pamCKT(m, n), the amplitude setting transistors Ta1 and Ta2 are switched because the amplitude setting column scanning signal ampSCAN[n] received by the gate is the gate conduction voltage V _GH (ampSCAN[n]=V _GH ). Turn off; the amplitude setting transistor Ta3 turns off because the light-emitting control signal EM[n] received by the gate is the gate conduction voltage V _GH (EM[n]=V _GH ). At this time, although the amplitude setting transistor Tamp is turned on due to the voltage difference across the bias capacitor Ca, due to the disconnection of the amplitude setting transistor Ta3, there is still no current flowing through the amplitude setting transistor Tamp during the off period dT_OFF.

In the width setting circuit pwdCKT(m, n), the width setting transistors Tw1, Tw2, and Tw3 are turned off because the width setting column scanning signal wdSCAN[n] is the gate conduction voltage V _GH (wdSCAN[n]=V _GH ). . In addition, the width setting transistor Twd is also turned off because the width setting transistor Tw2 is turned off. Therefore, the width setting circuit pwdCKT(m, n) stops operating during the off period dT_OFF.

In the relay circuit imdCKT(m, n), both the relay transistors Tm1 and Tm3 are turned off due to the turn-off of the width setting transistor Twd. The relay transistor Tm2 is turned off because the light-emitting control signal EM[n] received by the gate is the gate conduction voltage (EM[n]=V _GH ), and the gate of the relay transistor Tm4 is in a floating state. Accordingly, the gate of the driving transistor Tdrv is also in a floating state during the off period dT_OFF, and the light emitting diode LED does not emit light during the off period dT_OFF.

Please refer to Figure 9, which is a schematic diagram of the pixel unit PXL(m, n) unit according to the concept of the present disclosure. The pulse amplitude cAMP of the driving current Idrv is less susceptible to the pulse width setting circuit pwdCKT(m, n). . In Figure 9, the vertical axis is the drive current Idrv, the horizontal axis is time, and the waveforms WF2a, WF2b, and WF2c respectively correspond to the width setting circuit pwmCKT(m, n). The pulse width cPW of the drive current Idrv is set to cPW_2a, The situation of cPW_2b and cPW_2c. As can be seen from Figure 9, the pulse amplitude cAMP_2a corresponding to the widest pulse width cPW_2a, the pulse amplitude cAMP_2b corresponding to the next widest pulse width cPW_2b, and the pulse amplitude cAMP_2b corresponding to the narrowest pulse width cPW_2c The wave amplitudes cAMP_2c are quite close. That is, even if the pulse width cPW of the driving current Idrv is adjusted from the wider pulse amplitude cAMP_2a to the narrower pulse amplitude cAMP_2c, the pulse amplitude cAMP of the driving current Idrv remains substantially unchanged.

Compared with Figure 2, it can be clearly seen that the waveform in Figure 9 proves that when the pixel unit of the present disclosure is used, the pulse amplitude cAMP of the driving current Idrv will not change drastically with the change of the pulse width cPW. In other words, the pulse amplitude cAMP and pulse width cPW of the driving current Idrv can be adjusted independently.

Please refer to Figure 10, which is a schematic diagram of another embodiment of the pixel unit PXL(m, n) of the present disclosure. The structure of the pixel unit PXL(m, n)' shown in Figure 10 is similar to that of the pixel unit PXL(m, n) in Figure 4. The main difference between the two is that the relay circuits imdCKT and imdCKT' contain The number of relay crystals varies.

The relay circuit imdCKT(m, n) in Figure 4A can be regarded as a combination of two-stage source followers. Among them, relay transistors Tm1 and Tm2 are first-stage source followers; relay transistors Tm3 and Tm4 are second-stage source followers. In addition, the relay circuit imdCKT(m, n)’ in Figure 10 only includes a single-stage source follower composed of relay transistors Tm1 and Tm2.

Comparing Figures 4A and 10, it can be seen that in Figure 4A, the gate of the driving transistor Tdrv (the driving enable signal Son) is equivalent to being indirectly affected by the voltage of the terminal Nm2. That is, after the terminal Nm2 changes the conductive state of the relay transistor Tm4, the voltage of the terminal Nm3 is changed. In addition, in Figure 10, the gate of the driving transistor Tdrv (the driving enable signal Son) is directly affected by the terminal Nm2. Since the operation of the pixel unit in Figure 10 can also be matched with the waveform in Figure 4B, the components and operation details of Figure 10 will not be described in detail here. Table 4 summarizes the differences between Figures 4A and 10. Table 4 Figure 4A Picture 10 relay circuit imdCKT(m, n) imdCKT(m, n)' source follower two levels single stage Drive enable signal Son Depends on whether the relay transistor Tm4 is turned on, and the relay transistor Tm4 is affected by the relay transistor Tm2 Depends on whether the relay transistor Tm2 is turned on Turn on/off depending on the voltage at terminal Nm1 Relay transistor Tm1 Turn on/off with the change of the light emission control signal EM[n] Relay transistor Tm2

In summary, this disclosure provides relay circuits imdCKT and imdCKT’ between the width setting circuit pwmCKT(m, n) and the gate of the driving transistor Tdrv. The settings of the relay circuits imdCKT and imdCKT’ can amplify the transition voltage of the relay width setting signal Nm1, thereby accelerating the conduction state of the driving transistor Tdrv. In other words, the settings of the relay circuits imdCKT and imdCKT’ can make the driving transistor Tdrv change more quickly in response to the width data voltage wDAT[m]. Please also note that the design and implementation of the relay circuit are not limited to the embodiments of this article.

In summary, although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

PXL(m,n),PXL(1,1),PXL(M,1),PXL(1,N),PXL(M,N),PXL(m,n)': pixel unit pamCKT(m,n ): Amplitude setting circuit pwmCKT(m,n): Width setting circuit Tamp, Ta1, Ta2, Ta3: Amplitude setting transistor Tdrv: Driving transistor Idrv: Driving current LED: Light emitting diode cPW, cPW_1c, cPW_1b, cPW_1a, cPW_2a, cPW_2b, cPW_2c: pulse width cAMP, cAMP_1a, cAMP_1b, cAMP_1c, cAMP_2a, cAMP_2b, cAMP_2c: pulse amplitude WF1a, WF1b, WF1c, WF2a, WF2b, WF2c: waveform 30: display device 31: timing controller Sctl_gc: Gate control signal (line) Sctl_src: Source control signal (line) 33: Source drive circuit 35: Gate control circuit SSL[m]: External compensation signal aDAT[m]: Amplitude data voltage wDAT[m]: Width Data voltage ampSCAN[n], ampSCAN[n+1]: Amplitude setting column scanning signal wdSCAN[n], wdSCAN[n+1]: Width setting column scanning signal EM[n], EM[n+1]: Lighting control Signal Sweep[n], Sweep[n+1]: Sweep signal 37: Display panel Vdd_w: Width supply voltage Vdd_a: Amplitude supply voltage Na1, Na2, Ncmp, Nm1, Nm2, Nm3, Nw1, Nw2: Endpoint Ca, Cm, Cw: bias capacitance Tacmp, Twcmp: characteristic compensation transistor LT (m, n): light source circuit Vss: ground voltage Son: drive enable signal imdCKT (m, n): relay circuit Tm1, Tm2, Tm3, Tm4: relay transistor Tw1, Tw2, Tw3, Twd: width setting transistor V _GH : gate conduction voltage Vset: setting voltage pwmMDL (m, n): width setting module aCMP_en[n]: amplitude compensation Enable signal wCMP_en[n]: width compensation enable signal t1~t11: time point dT_amp: amplitude setting period dt_wd: width setting period dt_EM: light-emitting period dT_OFF: off period dT_pxl[n], dt_pxl[n+1]: pixel setting and Display period ΔTr: Column selection time difference Δt: Buffering period V _GL : Gate closing voltage

Figure 1A is a schematic diagram of a conventional pixel unit PXL(m, n) using an amplitude setting circuit pamCKT(m, n) and a width setting circuit pwmCKT(m, n) to adjust the brightness of a light emitting diode; Figure 1B is a schematic diagram of the pulse wave of the driving current Idrv flowing through the pixel unit PXL(m, n); Figure 2 is a schematic diagram showing that the pixel unit PXL(m, n) using conventional technology uses the width setting circuit pwdCKT(m, n) to adjust the pulse width cPW, and at the same time, the pulse amplitude of the driving current Idrv is also affected; Figure 3 is a block diagram of a display device using the present disclosure; Figure 4A is a schematic diagram of an embodiment of the pixel unit PXL(m, n) of the present disclosure; Figure 4B, which is generated by the gate control circuit, is used to control the pixel units PXL(1~M, n) and PXL(1~M, n) of the nth column and (n+1)th column of the present disclosure. +1) Waveform diagram of control signal in column direction; Figure 5 is a schematic diagram of the internal components of the pixel unit PXL(m, n) disclosed in the present disclosure, and dT_amp operates in response to the control signal in the column direction during the amplitude setting period; Figure 6 is a schematic diagram of the internal components of the pixel unit PXL(m, n) disclosed in the present disclosure, and how dT_wd operates in response to the control signal in the column direction during the width setting period; Figure 7A is a schematic diagram of the internal components of the pixel unit PXL(m, n) disclosed in the present disclosure, and STG1 operates in response to the control signal in the column direction during the light emitting phase; Figure 7B is a schematic diagram of the internal components of the pixel unit PXL(m, n) disclosed in the present disclosure, and STG2 operates in response to the control signal in the column direction during the light emitting phase; Figure 8 is a schematic diagram showing the operation of the internal components of the pixel unit PXL(m, n) in the present disclosure in response to the control signal in the column direction during the off period dT_OFF; Figure 9 is a schematic diagram of the pixel unit PXL(m, n) unit based on the concept of the present disclosure. The amplitude of the driving current Idrv is less susceptible to the pulse width set by the width setting circuit pwdCKT(m, n); and Figure 10 is a schematic diagram of another embodiment of the pixel unit PXL(m, n) of the present disclosure.

PXL(m,n): pixel unit

pamCKT(m,n): amplitude setting circuit

aDAT[m]: Amplitude data voltage

Vdd_w: width supply voltage

Vdd_a: amplitude supply voltage

Ta1, Ta2, Ta3, Tamp: amplitude setting transistor

Na1,Na2,Ncmp,Nw1,Nw2,Nm1,Nm2,Nm3: endpoints

EM[n]: Luminous control signal

ampSCAN[n]: Amplitude setting column scan signal

Ca, Cw, Cm: bias capacitance

Tacmp, Twcmp: characteristic compensation transistor

SSL[m]: external compensation signal

aCMP_en[n]: Amplitude compensation enable signal

wCMP_en[n]: Width compensation enable signal

Tdrv: drive transistor

LED: light emitting diode

Vss: ground voltage

LT(m,n): light source circuit

Son: drive enable signal

pwmMDL(m,n): width setting module

Sweep[n]: Sweep signal

wdSCAN[n]: Width setting column scan signal

Tw1, Tw2, Tw3, Twd: Width setting transistor

V _GH :gate conduction voltage

wDAT[m]: width data voltage

pwmCKT(m,n): Width setting circuit

Tm1, Tm2, Tm3, Tm4: relay transistor

imdCKT(m,n): relay circuit

Vset: set voltage

Claims (10)

A pixel unit containing: An amplitude setting circuit that generates an amplitude setting signal in response to an amplitude setting column scan signal; a width setting circuit that generates a relay width setting signal in response to a width setting column scan signal; A relay circuit, electrically connected to the width setting circuit, generates a drive enable signal in response to the relay width setting signal; and A light source circuit, including: A driving transistor, electrically connected to the amplitude setting circuit and the relay circuit, selectively generates a driving current according to the driving enable signal, wherein the magnitude of the driving current changes with the amplitude setting signal; as well as A light-emitting circuit is electrically connected to the driving transistor, and its brightness changes with the driving current. The pixel unit as described in claim 1, wherein, The amplitude setting column scan signal switches from a first voltage to a second voltage at the beginning of a first setting period, and switches from the second voltage to the first voltage at the end of the first setting period; and, The width setting column scan signal switches from the first voltage to the second voltage at the beginning of a second setting period, and switches from the second voltage to the first voltage at the end of the second setting period. The pixel unit as claimed in claim 2, wherein The amplitude setting circuit and the relay circuit receive a lighting control signal, and The width setting circuit receives a scan signal. The pixel unit as described in claim 3, wherein, The light-emitting control signal switches from the first voltage to the second voltage at the beginning of a light-emitting period, and switches from the second voltage to the first voltage at the end of the light-emitting period. The pixel unit described in claim 4, wherein, The amplitude setting column scan signal, the width setting column scan signal and the light emitting control signal are all maintained at the first voltage during an off period, and the off period is later than the light emitting period. The pixel unit as claimed in claim 1, wherein the width setting circuit includes: a first bias capacitor that receives a sweep signal, wherein the sweep signal gradually changes from a first voltage to a second voltage during a lighting period; and A first width setting transistor, electrically connected to the relay circuit and the first bias capacitor, is a first light-emitting device in the light-emitting period as the scanning signal changes during the light-emitting period. stage is turned off, and is turned on in a second light-emitting stage in the light-emitting period, wherein the relay width setting signal changes with the conduction state of the first width setting transistor. The pixel unit as claimed in claim 6, wherein the width setting circuit further includes: a second width setting transistor, electrically connected to one end of the first bias capacitor, which receives the first voltage; a third width setting transistor, electrically connected to the other end of the first bias capacitor, which receives a width data voltage, wherein the width data voltage is related to the position of the pixel unit on a display panel; and a fourth width setting transistor electrically connected to the first width setting transistor, The second width setting transistor, the third width setting transistor and the fourth width setting transistor are turned off during a first setting period, and during a second setting period in response to the control of the width setting column scan signal. It is turned on during the lighting period and turned off during the lighting period and an off period. A pixel unit as claimed in claim 7, wherein The second setting period is later than the first setting period, the lighting period is later than the second setting period, and the off period is later than the lighting period, wherein, The second light-emitting stage is later than the first light-emitting stage. A pixel unit as claimed in claim 7, wherein The voltage difference of the first bias capacitor is determined by the second width setting transistor and the third width setting transistor that are turned on during the second setting period, and The fourth width setting transistor sets the relay width setting signal to a setting voltage during the second setting period. The pixel unit as claimed in claim 1, wherein the relay circuit includes: a second bias capacitor electrically connected to the width setting circuit; A first relay transistor, electrically connected to the second bias capacitor and the width setting circuit, is selectively turned on in response to the relay width setting signal; and A second relay transistor, electrically connected to the first relay transistor, is selectively turned on in response to the light emitting control signal, and the driving enable signal changes with the conduction state of the second relay transistor. change.