TW202405653A - Method and computer program product and apparatus for decoding low-density parity-check (ldpc) code - Google Patents

Abstract

The invention is related to a method, a computer program product and an apparatus for decoding low-density parity-check (LDPC) code. The method includes: determining whether a bit flipping algorithm for decoding a codeword goes to a trapping state after an observation period, in which a sequential selection strategy is used; and changing to use a un-sequential selection strategy to perform the bit flipping algorithm on the codeword when the bit flipping algorithm goes to the trapping state. With the usage of un-sequential selection strategy, it would allow the flipping algorithm jump out of the trapping state.

Description

Low-density parity check code decoding method and computer program products and devices

The invention relates to a storage device, and in particular to a low-density parity check code decoding method, computer program product and device.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processor (Host) can provide any address to access the NOR flash memory on the address pin, and obtain the data stored at the address from the data pin of the NOR flash memory in a timely manner. material. On the contrary, NAND flash memory does not have random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processor needs to write a sequence of Bytes values to the NAND flash memory to define the type of request command (Command) (such as , read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data for a write operation in flash memory) or a block (the smallest block of data for an erase operation in flash memory). Improving the efficiency of reading data from flash memory modules has always been an important issue that affects the overall performance of flash memory controllers. therefore. The present invention proposes a low-density parity check code decoding method, computer program product and device to improve the efficiency of reading data.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem that needs to be solved.

This specification relates to a method of decoding a low-density parity check code performed by a processing unit. The method includes the following steps: after an observation period using a sequential selection strategy, determining whether the bit flip algorithm enters a trap state when decoding the codeword; and when the bit flip algorithm enters the trap state, changing to non-sequential The sequential selection strategy is used, and the bit flipping algorithm is performed on the codeword under the non-sequential selection strategy.

This manual also relates to a computer program product, including program code. When the processing unit executes the program code, the decoding method of the low-density parity check code as described above is implemented.

This specification also relates to a low-density parity check code decoding device, which includes: a change node calculation circuit; and a processing unit coupled to the change node calculation circuit. The processing unit is configured to determine whether the bit flip algorithm enters a trap state when decoding the codeword after an observation period using the sequential selection strategy; and when the bit flip algorithm enters the trap state, change to a non-sequential selection strategy , and drives the change node calculation circuit to perform a bit flipping algorithm on the codeword under a non-sequential selection strategy.

The codeword is divided into blocks of the same length. The sequential selection strategy refers to sequentially selecting multiple blocks in the codeword, and driving the change node calculation circuit to execute the bit flip algorithm only for the selected blocks in the codeword each time. A non-sequential selection strategy refers to any sequential combination of blocks in a codeword that is different from a sequential selection strategy.

One of the advantages of the above embodiment is that the bit flipping algorithm can escape from the trap state through the use of the non-sequential selection strategy as mentioned above.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

The following description is a preferred implementation manner for completing the invention, and its purpose is to describe the basic spirit of the invention, but is not intended to limit the invention. For the actual invention, reference must be made to the following claims.

It must be understood that the words "including" and "include" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude the possibility of adding further technical features, values, method steps, processes, components, components, or any combination of the above.

The use of words such as "first", "second" and "third" in the claims is used to modify the elements in the claims, and is not used to indicate that there is a priority, precedence relationship between them, or that they are one element. Prior to another element, or the chronological order in which method steps are performed, it is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements could be interpreted in a similar fashion, such as "between" versus "directly between," "adjacent" versus "directly adjacent," etc.

Refer to Figure 1. The electronic device 10 includes a host side (Host Side) 110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as a device side (Device Side). The electronic device 10 can be implemented in electronic products such as personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, and digital video cameras. The host 110 and the host interface (Host Interface) 131 of the flash memory controller 130 can be connected by a Universal Serial Bus (USB), an advanced technology attachment (ATA), or a serial advanced technology attachment (ATA). attachment, SATA), peripheral component interconnect express (PCI-E), Universal Flash Storage (UFS), embedded multi-media card (Embedded Multi-Media Card, eMMC) and other communication protocols are mutually exclusive communication. The flash interface (Flash Interface) 139 of the NAND Flash Controller (NFC) 137 and the flash memory module 150 can communicate with each other using a Double Data Rate (DDR) communication protocol, for example, open NAND flash (Open NAND Flash Interface, ONFI), double data rate switch (DDR Toggle) or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and When executing software and/or firmware instructions, the functions described later are provided. The processing unit 134 receives host commands through the host interface 131, such as read command (Read Command), write command (Write Command), discard command (Discard Command), erase command (Erase Command), etc., schedules and executes these commands. . The flash memory controller 130 also includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM) or a static random access memory (Static Random Access Memory, SRAM) or a combination of the above two, is used to configure space as a data buffer to store user data (also called host data) read from the host 110 and about to be written to the flash memory module 150, and from the flash memory module. The group 150 reads and outputs the user data to the host 110 . The random access memory 136 can also store data needed during execution, such as variables, data tables, host-to-Flash Address Mapping Table (H2F table for short), flash memory and host addresses. Comparison table (Flash-to-Host Address Mapping Table, referred to as F2H table), etc. The NAND flash memory controller 137 provides functions required for accessing the flash memory module 150, such as a command sequencer (Command Sequencer), low-density parity-check (Low-Density Parity-Check, LDPC), etc.

The flash memory controller 130 can be configured with a shared bus architecture (Shared Bus Architecture) for coupling components to each other to transmit data, addresses, control signals, etc. These components include the host interface 131, the processing unit 134, and the RAM 136 , NAND flash memory controller 137, etc. The bus includes parallel physical lines that connect two or more components in the flash memory controller 130 . A shared bus is a shared transmission medium. At any time, only two devices can use these lines to communicate with each other and transfer data. Data and control signals can propagate in both directions between components along data and control lines respectively, but on the other hand, address signals can only propagate in one direction along address lines. For example, when the processing unit 134 wants to read data at a specific address of the RAM 136, the processing unit 134 transmits the address to the RAM 136 on the address line. Then, the data at this address will be returned to the processing unit 134 on the data line. In order to complete the data reading operation, control signals are transmitted using control lines.

The flash memory module 150 provides a large amount of storage space, usually hundreds of Gigabytes (GB) or even several Terabytes (TB), for storing large amounts of user data. For example, high-resolution pictures, videos, etc. The flash memory module 150 includes a control circuit and a memory array. The memory cells in the memory array can be configured as single-level cells (Single Level Cells, SLCs) and multi-level cells (Multiple Level Cells, MLCs). (Triple Level Cells, TLCs), Quad-Level Cells (QLCs), or any combination of the above. The processing unit 134 can write user data to a specified address (destination address) in the flash memory module 150 through the flash memory interface 139, and read user data from a specified address (source address) in the flash memory module 150. . The flash memory interface 139 uses several electronic signals to coordinate the transmission of data and commands between the flash memory controller 130 and the flash memory module 150, including data lines (Data Line), clock signals (Clock Signal) and control signals (Control Signal). Data lines can be used to transmit commands, addresses, read and write data; control signal lines can be used to transmit chip enable (Chip Enable, CE), address extraction enable (Address Latch Enable, ALE), command extraction enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

Referring to Figure 2, the interface 151 in the flash memory module 150 may include four input/output channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel is connected to four NAND flash memory units, for example, channel CH#0 is connected to NAND flash memory cells 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory cell can be packaged as an independent chip (die). The flash memory interface 139 can send one of the enable signals CE#0 to CE#3 through the interface 151 to enable the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, and 153#8 to 153#11. , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory unit in a parallel manner, or write user data to the enabled NAND flash memory unit. Those skilled in the art can change the design of the flash memory module 150 according to system requirements, configure more or fewer channels in the flash memory module 150, and/or connect each channel to more or fewer NAND flash memory cells. , the present invention is not limited thereby.

The NAND flash memory controller 137 may include a low-density parity check encoder (LDPC Encoder) for generating a low-density parity check code (LDPC Code) based on user data, which is a linear error correction code (Linear Error Correcting Code). For example, the generation of LDPC code can be expressed by the following formula: MSG _1xn ⊙ PCM _{nx (n+m)} = CW _1x(n+m) where MSG _1xn represents a 1-column, n-row matrix of user data, PCM _{nx (n+m)} represents n columns and (n+m) rows Parity Check Matrix, CW _1x(n+m) represents 1 column and (n+m) of the last generated codeword (Codeword) Row matrix, ⊙ represents Modulo 2 Multiplication. The parity check matrix can contain a Quasi-Cyclic (QC) structure, and the value of the first n bits in CW _1x(n+m) is equal to the value of MSG _1xn , while the value of the first n bits in CW _1x(n+m) The value of the last m bits is called the LDPC code. Examples are as follows: Those skilled in the art know that conventional parity check matrices and efficient algorithms can be used to generate LDPC codes, such as two-stage encoding (2-stage Encoding).

The NAND flash memory controller 137 may include an LDPC decoder (LDPC Decoder) 138 for verifying the codeword (including user information and LDPC code) read from the flash memory module 150 through the flash memory interface 139 and determining the codeword. contains error bits. Once an erroneous bit is found in the codeword, the LDPC decoder 138 attempts to recover the correct codeword and obtains user information from the codeword. If the correct codeword cannot be recovered after a predetermined number of attempts, the LDPC decoder 138 determines that the codeword is an uncorrectable codeword. Regarding LDPC decoding, refer to the example (n=3, k=6) LDPC code shown in Figure 3. Blocks 33#0 to 33#5 represent Variable Nodes, and blocks 31#0 to 31#2 represent Check Nodes. The bits in the change nodes 33#0 to 33#5 form a codeword, which is composed of user data and LDPC code. The bits must meet the graphic constraints (Graphical Constrains). Specifically, all lines connected to a change node have the same value, and the sum of all lines connected to a check node must leave a remainder of 0 when divided by two (that is, they add up to an even number, or has an even number of odd values). Check nodes 31#0 to 31#2 can also be called syndromes (Syndrome).

The NAND flash memory controller 137 also includes a static random access memory (Static Random Access Memory, SRAM) 140 for storing data required during the decoding process. The flash memory interface 139 can store the code words (including multiple hard bits) read from the flash memory module 150 and the specified addresses of the soft bits in the SRAM 140 . Each hard bit can correspond to at least one soft bit, and the corresponding soft bit is used to indicate the confidence of the hard bit (Likelihood of Belief). In order to correct the erroneous bits in the hard bits, the SRAM 140 also needs configuration space to store the updated changed nodes and their corresponding soft bits during the decoding process. Similarly, each change node may correspond to at least one soft bit, and the corresponding soft bit is used to indicate the degree of confidence of this change node.

Reference is made to the block diagram of NAND flash memory controller 137 shown in FIG. 4 . In detail, the LDPC Decoder 138 includes two important circuits: a Check-node Calculation Circuit 418 and a Variable-node Calculation Circuit 416 . The check node calculation circuit 418 performs modular square multiplication on the hard bits or change nodes and the parity check matrix to calculate the syndrome. The change node calculation circuit 416 performs a known bit flipping algorithm (Bit Flipping Algorithm) based on the soft bits corresponding to the hard bits or the change node and the syndrome to generate a new change node, and uses a known formula To calculate the soft bits of the new changed node. The configurable area 431 in the SRAM 140 is used to store hard bits and change nodes, and the configuration area 433 is used to store the hard bits and soft bits corresponding to the change nodes. The flash memory interface 139 writes the codeword (including a plurality of hard bits) read from the flash memory module 150 into the area 431 . In some embodiments, the flash memory interface 139 may include a soft-bit calculation circuit for calculating each hard bit in the codeword when reading the codeword from the flash memory module 150 . Soft bits. And write the calculated soft bits into area 433. The change node calculation circuit 416 writes the change node and its soft bits into areas 431 and 433 respectively. LDPC decoder 138 includes a processing unit 412, which may be implemented in a variety of ways, such as using general-purpose hardware (e.g., a single processor, multiple processors with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and When executing software and/or firmware instructions, functions described later are provided, for example, integrating the operations of the check node calculation circuit 418 and the change node calculation circuit 416 during the decoding process. Those skilled in the art can dispose the processing unit 412 outside the LDPC decoder 138, and the present invention is not limited thereby.

The check node calculation circuit 418 is used to calculate the syndrome based on the hard bits or change nodes stored in the area 431 and the parity check matrix. The generation of the syndrome can be expressed by the following formula: PCM _{nx (n+m)} ⊙ CW _{( n+m )x 1} = SYD _mx1 where, PCM _{nx (n+m)} represents n columns and (n+m) row odd and even Check matrix, MSG _(n+m)x1 represents the (n+m) column, 1-row matrix of the codeword, SYD _mx1 represents the m-column, 1-row matrix of the syndrome, ⊙ represents modulo 2 multiplication. Examples are as follows: Since the calculated syndrome is all "0", the codeword does not contain error bits. If the calculated syndrome is not all "0", the codeword contains erroneous bits. The check node calculation circuit 418 may output hard bits or change nodes, and the calculated syndrome to the change node calculation circuit 416 . In some embodiments, the check node calculation circuit 418 can calculate the reliability of the syndrome (Reliability of Syndrome) based on the soft bits corresponding to the hard bits or the change nodes, and combine the syndrome and its reliability. transmitted to the change node calculation circuit 416.

The change node calculation circuit 416 determines whether the codeword needs to be corrected based on the syndrome input from the check node calculation circuit 418. If it is not needed (that is, the syndrome is all “0”), the changed node calculation circuit 416 sends a decoding success message to the processing unit 412 . If necessary (that is, the syndrome is not all "0"), the change node calculation circuit 416 sends a decoding failure message to the processing unit 412, and calculates the decoding failure information based on the syndrome, the hard bit or the change node, corresponding to the hard bit. Or the soft bits of the change node, execute the conventional bit flip algorithm, which is used to change the state of one or more hard bits or change nodes that may be wrong in the codeword (that is, change "0b0" to " 0b1", or change "0b1" to "0b0"). Change nodes can also be collectively called codewords. The change node calculation circuit 416 stores the updated change node into the area 431 in the SRAM 140 . Then, the change node calculation circuit 416 uses a conventional formula to calculate the soft bits corresponding to the updated change node according to the updated change node, and stores the calculated soft bits to the area 433 in the SRAM 140 . The soft bits can be log-likelihood ratio (Log-likelihood Ratio, LLR), quantization value of log-likelihood ratio (Quantization of LLR), etc.

A section of codeword (which may include hard bits read from the flash memory module 150 or include change nodes generated by the change node calculation circuit 416) may be divided into the same length (for example, 16, 32) according to the computing power of the change node calculation circuit 416. , 64, 128, 256, 512, 736 bits, etc.) multiple chunks (Chunks). The codeword includes user information and LDPC code, and the common code rate (Code Rate) is close to 0.9. In other words, user data accounts for close to 90% of the entire codeword. Referring to Figure 5, for example, codeword 50 may be divided into blocks 510, 530, 550, and 570 of equal length, block 570 containing LDPC code 575. Although the following embodiments take 4 blocks as an example, those skilled in the art can divide a codeword into any number of blocks exceeding 1 according to system requirements. In some previous embodiments, the change node calculation circuit 416 repeatedly performs multiple iteration operations. In each iteration, bit flips are sequentially performed for a block in the codeword, and the number of iterations cannot exceed a preset number. threshold. For example, in each iteration, bit flips are performed on blocks 510, 530, 550, and 570 in sequence. However, since the parity check matrix may contain a trap set (Trapping Set), the bit flip algorithm enters the trapping state (Trapping State), so that after executing the maximum allowed number of iterations, the check node is still not found. Calculation circuit 418 produces a result in which the syndrome is all "0"s.

In order to avoid entering a trap state, the embodiment of the present invention implements a new scheduling strategy (Novel Scheduling Strategy) in the LDPC decoding method that is different from the sequential selection of different blocks in the codeword as described above. The LDPC decoding method is performed by the processing unit 412 in the LDPC decoder 138 and includes: after an observation period using the sequential selection strategy, determining whether the bit flip algorithm enters a trap state when decoding the codeword; and when the bit flip algorithm enters a trap state When the method enters the trap state, the scheduling strategy is changed to a non-sequential selection strategy, and a bit flip algorithm is performed on the codeword under the non-sequential selection strategy. The sequential selection strategy refers to sequentially selecting multiple blocks in the codeword, and each process only performs the bit flipping algorithm on the selected blocks in the codeword. The non-sequential selection strategy refers to any sequential combination of multiple blocks in the codeword that is different from the sequential selection strategy.

Specifically, when the check node calculation circuit 418 finds that the codeword read from the flash memory module 150 cannot pass the check, it notifies the processing unit 412 and allows the processing unit 412 to start executing the error correction program. Referring to the flow chart of the error correction method shown in Figure 6, the details are as follows:

Step S610: Initialize variable i to 0. The processing unit 412 uses the variable i to record the number of iterations to control the number of executions of the iterations not to exceed the preset maximum allowed number of times MAX _itr .

Step S621: Set the scheduling strategy to sequentially select multiple blocks in the codeword, and execute the bit flipping algorithm only for the selected blocks in the codeword at a time, which can also be called a sequential selection strategy. For example, referring to Figure 4, the scheduling policy is set to select blocks 510, 530, 550 and 570 in sequence.

Step S623: Execute the bit flipping algorithm of the entire codeword according to the set scheduling strategy (which can be a sequential or non-sequential selection strategy). This step may represent one iteration of bit flipping for the entire codeword. For details, please refer to the description of the method flowchart of FIG. 7 in the following paragraphs. The processing unit 412 can drive the change node calculation circuit 416 to perform bit flipping on specific blocks in the codeword. When the flipped codeword passes the check of the check node calculation circuit 418, the change node calculation circuit 416 will send a decoding success message to the processing unit 412. When the change node calculation circuit 416 performs bit flipping on all required blocks in the codeword but fails to decode successfully, the processing unit 412 knows that the bit flipping of this iteration has failed.

Regarding the technical details of step S623, refer to the flow chart of the bit flipping program shown in Figure 7. The detailed description is as follows:

Step S711: Obtain the scheduling policy (which can be a sequential or non-sequential selection policy). For example, referring to FIG. 4 , the sequential selection strategy can be expressed as {#510, #530, #550, #570}, which represents sequentially selecting blocks 510, 530, 550 and 570 for bit flipping. As another example, the non-sequential selection strategy may be {#530, #550, #570}, which means that block 510 is skipped, and blocks 530, 550, and 570 are selected sequentially for bit flipping. As another example, the non-sequential selection strategy may be {#570, #550, #530, #510}, which represents sequentially selecting blocks 570, 550, 530 and 510 for bit flipping.

Step S713: Initialize variable j to 0. The processing unit 412 uses variable j to record the number of blocks that have been flipped, and is used to control the number of executions of bit flipping not to exceed the total number of blocks that need to be executed MAX _chk . It should be noted that due to different scheduling policies, the MAX _chk set in different iterations may be different.

Step S730: Calculate and store the threshold value (Threshold) of the initial codeword, which is used to indicate the error situation of the initial codeword. The closer to "0", the lower the error level, and the higher the error level, the higher the error level. The processing unit 412 may first calculate a plurality of syndrome weights (Syndrome Weights) using a plurality of preset conventional check equations (Check Equations) for each bit in the codeword. For example, each bit may use The 4 check formulas calculate the 4 check subweights. Each check formula can refer to the soft bit of the specified bit, the specified syndrome associated with the specified bit, and other bits associated with the specified syndrome, and calculate a syndrome weight to represent this Partial error status of bits. The closer to "0", the lower the error level. The higher the error level, the higher the error level. The bits mentioned above may refer to hard bits or change nodes. The processing unit 412 may use a Tanner Graph to derive the specified syndrome associated with the specified bit and other bits associated with the specified syndrome. All calculated syndrome weights are then summed for each bit to represent the overall error condition for that bit. The processing unit 412 finally obtains the maximum value from the sum of the syndrome weights of all bits as the critical value of the initial codeword, and stores the critical value of the initial codeword to a designated address in the SRAM 140 .

Step S751: Execute a bit flipping algorithm for the block indicated by the j-th item of the scheduling policy to generate a flipped codeword. For example, assuming that the scheduling strategy is set to {#510, #530, #550, #570}, and j=2: the processing unit 412 can output the address signal of the block 550 to the change node calculation circuit 416 for driving the change node calculation. Circuitry 416 reads the hard bits or change nodes of block 550 from area 431 and performs a conventional bit flip based on the syndrome, the hard bits or change nodes, and the soft bits corresponding to the hard bits or change nodes. Algorithm used to change the state of one or more hard bits or change nodes that may be in error in block 550.

Step S753: Calculate and store the critical value of the flipped codeword, which is used to indicate the error situation of the flipped codeword. The closer to "0", the lower the error level. The higher the critical value, the higher the error level. The details of the calculation can be derived from step S751, and will not be described again for the sake of simplicity.

Step S755: Calculate the difference between the critical values of the codeword before bit flipping and after bit flipping to represent the error improvement of the codeword after bit flipping, and store the calculated difference into the SRAM 140 Specify the address. A difference of "0" means no improvement, a positive difference means it is getting worse, and a negative difference means it is getting better. The processing unit 412 may use a data table in a specified address of the SRAM 140 to store historical changes of the threshold value of the codeword. Assume that the scheduling strategies of the first three iterations are {#510, #530, #550, #570}: Table 1 shows the data table of the example: Table 1 Iteration number first flip second flip third flip fourth flip Tr0 Tr1 Dif1 Tr2 Dif2 Tr3 Dif3 Tr4 Dif4 1 2 3 +1 2 -1 2 0 2 0 2 2 3 +1 2 -1 2 0 2 0 3 2 3 +1 2 -1 2 0 2 0 The field Tr0 stores the critical value of the initial codeword, the field Tr1 stores the critical value of the codeword after flipping block 510, and the field Dif1 stores the result of Tr1 minus Tr0. Field Tr2 stores the critical value of the codeword after flipping block 520, and field Dif2 stores the result of Tr2 minus Tr1. Field Tr3 stores the critical value of the codeword after flipping block 530, and field Dif3 stores the result of Tr3 minus Tr2. Field Tr4 stores the critical value of the codeword after flipping block 540, and field Dif4 stores the result of Tr4 minus Tr3.

Step S757: Determine whether the flipped codeword passes the check. The change node calculation circuit 416 transmits the flipped codeword to the check node calculation circuit 418, determines whether the flipped codeword passes the check based on the syndrome received from the check node calculation circuit 418, and transmits decoding based on the judgment result. A message of success or decoding failure is sent to the processing unit 412. If the processing unit 412 receives a decoding success message from the changed node calculation circuit 416, it means that the decoding is successful. If the processing unit 412 receives a decoding failure message from the changed node calculation circuit 416, it means that the decoding has failed, and the process continues to the processing of step S758.

Step S758: Add one to the variable j, indicating that the bit flip of this block has been completed.

Step S759: Determine whether variable j is greater than the total number of blocks to be executed MAX _chk . If yes, it means that the bit flip of this iteration is completed, this process is left, and the process of step S625 of FIG. 6 is continued. Otherwise, the flow continues with the processing of step S751.

Step S625: Determine whether the changed node generated by the bit flipping of this iteration passes the check. If the processing unit 412 receives a successful decoding message from the changed node calculation circuit 416 in step S623, it means that the decoding is successful, and the entire error correction process ends. If the processing unit 412 does not receive a successful decoding message from the changed node calculation circuit 416 in step S623, it means that the decoding has failed, and the process continues with the processing of step S627.

Step S627: Add one to the variable i, indicating that the bit flip of this iteration has been completed.

Step S629: Determine whether the variable i is greater than the preset iteration number MAX _obv during the observation period, and MAX _obv is a positive integer. If yes, it means that the observation period using the sequential selection strategy is over, and the process continues to the process of step S630. Otherwise, it means that the observation period using the sequential selection strategy has not ended, and the process continues to step S621. In some embodiments, MAX _obv is set to a value of 3 or greater.

Step S630: Determine whether variable i is greater than the preset maximum allowed number of times MAX _itr . If so, it means that the decoding of this codeword failed and the entire process ends. Otherwise, the flow continues with the processing of step S640.

Step S640: Determine whether the bit flipping algorithm enters a trap state based on historical changes in the critical value of the codeword in previous iterations. If yes, the flow continues to the process of step S650. Otherwise, the flow continues with the processing of step S621. Refer to Figure 8 for a schematic diagram of changes corresponding to the critical value difference in Table 1. For example, the processing unit 412 finds from the records in Table 1 that the bit flipping algorithm is likely to enter a trap state because the same variation pattern (Variation Pattern) appears in the three iterations during the observation period of the sequential selection strategy.

Step S650: Change the scheduling strategy according to the historical changes in the critical values of codewords in previous iterations. The changed scheduling strategy can be called a non-sequential selection strategy. The non-sequential selection strategy refers to any sequential combination of multiple blocks in the codeword that is different from the sequential selection strategy. In some embodiments, processing unit 412 may remove the first corresponding block with a difference greater than 0 in the previous iteration from the codeword without processing. Continuing the example in Table 1, the changed scheduling strategy is {#530, #550, #570}. In other embodiments, the processing unit 412 may arrange the order of the corresponding blocks in the codeword from low to high according to the difference value in the previous iteration. Continuing the example in Table 1, the changed scheduling strategy is {#530, #550, #570, #510}.

All or part of the steps in the method described in the present invention can be implemented by computer instructions, such as drivers for specific hardware, etc. In addition, it can also be implemented in other types of programs. Those with ordinary skill in the art can write the methods of the embodiments of the present invention as computer instructions, which will not be described again for the sake of simplicity. Computer instructions implemented according to the methods of the embodiments of the present invention can be stored in appropriate computer-readable media, such as DVD, CD-ROM, USB disk, hard disk, or can also be placed in a computer that can be accessed through a network (for example, the Internet, or A web server accessible by other appropriate vehicles).

Although Figures 1, 2, and 4 include the above-described elements, it does not rule out the use of more other additional elements to achieve better technical effects without violating the spirit of the invention. In addition, although the flow charts of Figures 6 and 7 are executed in a specified order, those skilled in the art can modify the order of these steps while achieving the same effect without violating the spirit of the invention. Therefore, The present invention is not limited to the use of only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements which will be obvious to one skilled in the art. Therefore, the scope of the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

10: Electronic devices 110: Host side 130:Flash controller 131:Host interface 134: Processing unit 136: Random access memory 137:NAND flash memory controller 138:LDPC decoder 139:Flash memory interface 140: Static random access memory 150:Flash memory module 151:Interface 153#0~153#15: NAND flash memory unit CH#0~CH#3: Channel CE#0~CE#3: enable signal 31#0~31#2: Verification node 33#0~33#5: Change nodes 412: Processing unit 416: Change node calculation circuit 418: Check node calculation circuit 431,433: Area in static random access memory 50: code word 510,530,550,570: blocks 575:LDPC code S610~S650: Method steps S711~S759: Method steps

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of an example LDPC code according to an embodiment of the present invention.

FIG. 4 is a block diagram of a NAND flash memory controller according to an embodiment of the present invention.

Figure 5 is a schematic block diagram of a codeword according to an embodiment of the present invention.

FIG. 6 is a flow chart of an error correction method according to an embodiment of the present invention.

FIG. 7 is a flow chart of a bit flipping procedure according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of changes in threshold differences according to an embodiment of the present invention.

S610~S650: Method steps

Claims (15)

A decoding method of low-density parity check codes, executed by a processing unit in a low-density parity check decoder, the method includes: After an observation period using a sequential selection strategy, it is determined whether the bit flipping algorithm enters a trap state when decoding a codeword divided into blocks of the same length. The sequential selection strategy refers to the sequential selection strategy. selectively selecting a plurality of the blocks in the codeword, and executing the bit flip algorithm only for the selected blocks in the codeword at a time; and When the bit flipping algorithm enters the trap state, it is changed to a non-sequential selection strategy, and the bit flipping algorithm is executed on the codeword under the non-sequential selection strategy, where The non-sequential selection strategy refers to any sequential combination of multiple blocks in the codeword that is different from the sequential selection strategy. The decoding method of low-density parity check codes according to claim 1, wherein the observation period includes at least three iterations of using the sequential selection strategy to execute the bit flipping algorithm for the codeword. The decoding method of low-density parity check code as described in claim 1, wherein each iteration during the observation period includes multiple bit flipping procedures, and each time the bit flipping procedure includes: Obtain the first critical value of the code word before flipping to indicate the error situation of the code word before flipping; Execute the bit flipping algorithm on the selected block to generate a flipped codeword; Calculate a second critical value of the flipped codeword to indicate an error condition of the flipped codeword; and Calculate the difference between the second critical value minus the first critical value to represent the error improvement of the flipped codeword, Wherein, whether the bit flip algorithm enters the trap state when decoding a codeword is determined based on historical changes in the critical value of the codeword in previous iterations. The decoding method of low-density parity check code as described in claim 3, wherein the calculation step of the second critical value in the bit flipping procedure each time includes: Using multiple check formulas to calculate multiple syndrome weights for each bit of the flipped codeword; summing a plurality of the syndrome weights for each bit of the flipped codeword; and The maximum value of the sum of multiple syndrome weights of all the bits of the flipped codeword is obtained as the second critical value of the flipped codeword. The decoding method of low-density parity check code as described in claim 3, wherein when the same change pattern of a plurality of the difference values is found between a plurality of the iterations during the observation period, it is determined that the bit The meta-flip algorithm enters the trap state when decoding a codeword. The decoding method of low-density parity check code as described in claim 3, wherein the non-sequential selection strategy removes the first corresponding block with a difference greater than 0 in the previous iteration from the codeword. Remove without processing. The decoding method of low-density parity check code as described in claim 3, wherein the non-sequential selection strategy arranges the order of the corresponding blocks in the codeword from low to high according to the difference value in the previous iteration. . A computer program product comprising a program code, wherein when a processing unit executes the program code, the decoding method of a low-density parity check code as described in any one of claims 1 to 7 is implemented. A decoding device for low-density parity check codes, including: Change node calculation circuit; and A processing unit coupled to the change node calculation circuit, configured to determine whether the bit flip algorithm enters a trap state when decoding a codeword after an observation period using a sequential selection strategy, wherein the codeword is divided into Multiple blocks of the same length, the sequential selection strategy refers to sequentially selecting multiple blocks in the codeword, and driving the change node calculation circuit to only execute the selected blocks in the codeword each time The bit flip algorithm; and when the bit flip algorithm enters the trap state, it changes to a non-sequential selection strategy, and drives the change node calculation circuit to perform the selection under the non-sequential selection strategy. The codeword performs the bit flipping algorithm, wherein the non-sequential selection strategy refers to any sequential combination of a plurality of blocks in the codeword that is different from the sequential selection strategy. The decoding device of low-density parity check code according to claim 9, wherein the observation period includes at least three iterations of using the sequential selection strategy to execute the bit flipping algorithm for the codeword. The low-density parity check code decoding device as claimed in claim 9, wherein each iteration of the observation period includes multiple bit flipping procedures, and each bit flipping procedure includes: Obtain the first critical value of the code word before flipping to indicate the error situation of the code word before flipping; Driving the changed node calculation circuit to execute the bit flipping algorithm for the selected block to generate a flipped codeword; Calculate a second critical value of the flipped codeword to indicate an error condition of the flipped codeword; and Calculate the difference between the second critical value minus the first critical value to represent the error improvement of the flipped codeword, Wherein, whether the bit flip algorithm enters the trap state when decoding a codeword is determined based on historical changes in the critical value of the codeword in previous iterations. The low-density parity check code decoding device as claimed in claim 11, wherein each calculation operation of the second critical value in the bit flipping procedure includes: Using multiple check formulas to calculate multiple syndrome weights for each bit of the flipped codeword; summing a plurality of the syndrome weights for each bit of the flipped codeword; and The maximum value of the sum of multiple syndrome weights of all the bits of the flipped codeword is obtained as the second critical value of the flipped codeword. The decoding device for low-density parity check codes as claimed in claim 11, wherein when the processing unit finds the same change pattern of multiple difference values between multiple iterations during the observation period, It is determined that the bit flip algorithm enters the trap state when decoding the codeword. The decoding device of low-density parity check code as described in claim 11, wherein the non-sequential selection strategy removes the first corresponding block with the difference greater than 0 in the previous iteration from the codeword. Remove without processing. The decoding device of low-density parity check code as described in claim 11, wherein the non-sequential selection strategy arranges the order of the corresponding blocks in the codeword from low to high according to the difference value in the previous iteration. .

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